drivers/pinctrl/samsung/pinctrl-exynos.c

   1 /*
   2  * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2012 Linaro Ltd
   7  *              http://www.linaro.org
   8  *
   9  * Author: Thomas Abraham <thomas.ab@samsung.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This file contains the Samsung Exynos specific information required by the
  17  * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
  18  * external gpio and wakeup interrupt support.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/device.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irqdomain.h>
  25 #include <linux/irq.h>
  26 #include <linux/irqchip/chained_irq.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/io.h>
  29 #include <linux/slab.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/err.h>
  32
  33 #include "pinctrl-samsung.h"
  34 #include "pinctrl-exynos.h"
  35
  36 struct exynos_irq_chip {
  37         struct irq_chip chip;
  38
  39         u32 eint_con;
  40         u32 eint_mask;
  41         u32 eint_pend;
  42 };
  43
  44 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
  45 {
  46         return container_of(chip, struct exynos_irq_chip, chip);
  47 }
  48
  49 static const struct samsung_pin_bank_type bank_type_off = {
  50         .fld_width = { 4, 1, 2, 2, 2, 2, },
  51         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
  52 };
  53
  54 static const struct samsung_pin_bank_type bank_type_alive = {
  55         .fld_width = { 4, 1, 2, 2, },
  56         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
  57 };
  58
  59 static void exynos_irq_mask(struct irq_data *irqd)
  60 {
  61         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
  62         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
  63         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
  64         unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
  65         unsigned long mask;
  66         unsigned long flags;
  67
  68         spin_lock_irqsave(&bank->slock, flags);
  69
  70         mask = readl(bank->eint_base + reg_mask);
  71         mask |= 1 << irqd->hwirq;
  72         writel(mask, bank->eint_base + reg_mask);
  73
  74         spin_unlock_irqrestore(&bank->slock, flags);
  75 }
  76
  77 static void exynos_irq_ack(struct irq_data *irqd)
  78 {
  79         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
  80         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
  81         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
  82         unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
  83
  84         writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
  85 }
  86
  87 static void exynos_irq_unmask(struct irq_data *irqd)
  88 {
  89         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
  90         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
  91         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
  92         unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
  93         unsigned long mask;
  94         unsigned long flags;
  95
  96         /*
  97          * Ack level interrupts right before unmask
  98          *
  99          * If we don't do this we'll get a double-interrupt.  Level triggered
 100          * interrupts must not fire an interrupt if the level is not
 101          * _currently_ active, even if it was active while the interrupt was
 102          * masked.
 103          */
 104         if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
 105                 exynos_irq_ack(irqd);
 106
 107         spin_lock_irqsave(&bank->slock, flags);
 108
 109         mask = readl(bank->eint_base + reg_mask);
 110         mask &= ~(1 << irqd->hwirq);
 111         writel(mask, bank->eint_base + reg_mask);
 112
 113         spin_unlock_irqrestore(&bank->slock, flags);
 114 }
 115
 116 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
 117 {
 118         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
 119         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
 120         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 121         unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
 122         unsigned int con, trig_type;
 123         unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
 124
 125         switch (type) {
 126         case IRQ_TYPE_EDGE_RISING:
 127                 trig_type = EXYNOS_EINT_EDGE_RISING;
 128                 break;
 129         case IRQ_TYPE_EDGE_FALLING:
 130                 trig_type = EXYNOS_EINT_EDGE_FALLING;
 131                 break;
 132         case IRQ_TYPE_EDGE_BOTH:
 133                 trig_type = EXYNOS_EINT_EDGE_BOTH;
 134                 break;
 135         case IRQ_TYPE_LEVEL_HIGH:
 136                 trig_type = EXYNOS_EINT_LEVEL_HIGH;
 137                 break;
 138         case IRQ_TYPE_LEVEL_LOW:
 139                 trig_type = EXYNOS_EINT_LEVEL_LOW;
 140                 break;
 141         default:
 142                 pr_err("unsupported external interrupt type\n");
 143                 return -EINVAL;
 144         }
 145
 146         if (type & IRQ_TYPE_EDGE_BOTH)
 147                 irq_set_handler_locked(irqd, handle_edge_irq);
 148         else
 149                 irq_set_handler_locked(irqd, handle_level_irq);
 150
 151         con = readl(bank->eint_base + reg_con);
 152         con &= ~(EXYNOS_EINT_CON_MASK << shift);
 153         con |= trig_type << shift;
 154         writel(con, bank->eint_base + reg_con);
 155
 156         return 0;
 157 }
 158
 159 static int exynos_irq_request_resources(struct irq_data *irqd)
 160 {
 161         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
 162         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
 163         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 164         const struct samsung_pin_bank_type *bank_type = bank->type;
 165         unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
 166         unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
 167         unsigned long flags;
 168         unsigned int mask;
 169         unsigned int con;
 170         int ret;
 171
 172         ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
 173         if (ret) {
 174                 dev_err(bank->gpio_chip.parent,
 175                         "unable to lock pin %s-%lu IRQ\n",
 176                         bank->name, irqd->hwirq);
 177                 return ret;
 178         }
 179
 180         reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
 181         shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
 182         mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
 183
 184         spin_lock_irqsave(&bank->slock, flags);
 185
 186         con = readl(bank->eint_base + reg_con);
 187         con &= ~(mask << shift);
 188         con |= EXYNOS_EINT_FUNC << shift;
 189         writel(con, bank->eint_base + reg_con);
 190
 191         spin_unlock_irqrestore(&bank->slock, flags);
 192
 193         exynos_irq_unmask(irqd);
 194
 195         return 0;
 196 }
 197
 198 static void exynos_irq_release_resources(struct irq_data *irqd)
 199 {
 200         struct irq_chip *chip = irq_data_get_irq_chip(irqd);
 201         struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
 202         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 203         const struct samsung_pin_bank_type *bank_type = bank->type;
 204         unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
 205         unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
 206         unsigned long flags;
 207         unsigned int mask;
 208         unsigned int con;
 209
 210         reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
 211         shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
 212         mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
 213
 214         exynos_irq_mask(irqd);
 215
 216         spin_lock_irqsave(&bank->slock, flags);
 217
 218         con = readl(bank->eint_base + reg_con);
 219         con &= ~(mask << shift);
 220         con |= FUNC_INPUT << shift;
 221         writel(con, bank->eint_base + reg_con);
 222
 223         spin_unlock_irqrestore(&bank->slock, flags);
 224
 225         gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
 226 }
 227
 228 /*
 229  * irq_chip for gpio interrupts.
 230  */
 231 static struct exynos_irq_chip exynos_gpio_irq_chip = {
 232         .chip = {
 233                 .name = "exynos_gpio_irq_chip",
 234                 .irq_unmask = exynos_irq_unmask,
 235                 .irq_mask = exynos_irq_mask,
 236                 .irq_ack = exynos_irq_ack,
 237                 .irq_set_type = exynos_irq_set_type,
 238                 .irq_request_resources = exynos_irq_request_resources,
 239                 .irq_release_resources = exynos_irq_release_resources,
 240         },
 241         .eint_con = EXYNOS_GPIO_ECON_OFFSET,
 242         .eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
 243         .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
 244 };
 245
 246 static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
 247                                         irq_hw_number_t hw)
 248 {
 249         struct samsung_pin_bank *b = h->host_data;
 250
 251         irq_set_chip_data(virq, b);
 252         irq_set_chip_and_handler(virq, &b->irq_chip->chip,
 253                                         handle_level_irq);
 254         return 0;
 255 }
 256
 257 /*
 258  * irq domain callbacks for external gpio and wakeup interrupt controllers.
 259  */
 260 static const struct irq_domain_ops exynos_eint_irqd_ops = {
 261         .map    = exynos_eint_irq_map,
 262         .xlate  = irq_domain_xlate_twocell,
 263 };
 264
 265 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
 266 {
 267         struct samsung_pinctrl_drv_data *d = data;
 268         struct samsung_pin_bank *bank = d->pin_banks;
 269         unsigned int svc, group, pin, virq;
 270
 271         svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
 272         group = EXYNOS_SVC_GROUP(svc);
 273         pin = svc & EXYNOS_SVC_NUM_MASK;
 274
 275         if (!group)
 276                 return IRQ_HANDLED;
 277         bank += (group - 1);
 278
 279         virq = irq_linear_revmap(bank->irq_domain, pin);
 280         if (!virq)
 281                 return IRQ_NONE;
 282         generic_handle_irq(virq);
 283         return IRQ_HANDLED;
 284 }
 285
 286 struct exynos_eint_gpio_save {
 287         u32 eint_con;
 288         u32 eint_fltcon0;
 289         u32 eint_fltcon1;
 290 };
 291
 292 /*
 293  * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
 294  * @d: driver data of samsung pinctrl driver.
 295  */
 296 static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 297 {
 298         struct samsung_pin_bank *bank;
 299         struct device *dev = d->dev;
 300         int ret;
 301         int i;
 302
 303         if (!d->irq) {
 304                 dev_err(dev, "irq number not available\n");
 305                 return -EINVAL;
 306         }
 307
 308         ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
 309                                         0, dev_name(dev), d);
 310         if (ret) {
 311                 dev_err(dev, "irq request failed\n");
 312                 return -ENXIO;
 313         }
 314
 315         bank = d->pin_banks;
 316         for (i = 0; i < d->nr_banks; ++i, ++bank) {
 317                 if (bank->eint_type != EINT_TYPE_GPIO)
 318                         continue;
 319                 bank->irq_domain = irq_domain_add_linear(bank->of_node,
 320                                 bank->nr_pins, &exynos_eint_irqd_ops, bank);
 321                 if (!bank->irq_domain) {
 322                         dev_err(dev, "gpio irq domain add failed\n");
 323                         ret = -ENXIO;
 324                         goto err_domains;
 325                 }
 326
 327                 bank->soc_priv = devm_kzalloc(d->dev,
 328                         sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
 329                 if (!bank->soc_priv) {
 330                         irq_domain_remove(bank->irq_domain);
 331                         ret = -ENOMEM;
 332                         goto err_domains;
 333                 }
 334
 335                 bank->irq_chip = &exynos_gpio_irq_chip;
 336         }
 337
 338         return 0;
 339
 340 err_domains:
 341         for (--i, --bank; i >= 0; --i, --bank) {
 342                 if (bank->eint_type != EINT_TYPE_GPIO)
 343                         continue;
 344                 irq_domain_remove(bank->irq_domain);
 345         }
 346
 347         return ret;
 348 }
 349
 350 static u32 exynos_eint_wake_mask = 0xffffffff;
 351
 352 u32 exynos_get_eint_wake_mask(void)
 353 {
 354         return exynos_eint_wake_mask;
 355 }
 356
 357 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
 358 {
 359         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 360         unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
 361
 362         pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
 363
 364         if (!on)
 365                 exynos_eint_wake_mask |= bit;
 366         else
 367                 exynos_eint_wake_mask &= ~bit;
 368
 369         return 0;
 370 }
 371
 372 /*
 373  * irq_chip for wakeup interrupts
 374  */
 375 static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = {
 376         .chip = {
 377                 .name = "exynos4210_wkup_irq_chip",
 378                 .irq_unmask = exynos_irq_unmask,
 379                 .irq_mask = exynos_irq_mask,
 380                 .irq_ack = exynos_irq_ack,
 381                 .irq_set_type = exynos_irq_set_type,
 382                 .irq_set_wake = exynos_wkup_irq_set_wake,
 383                 .irq_request_resources = exynos_irq_request_resources,
 384                 .irq_release_resources = exynos_irq_release_resources,
 385         },
 386         .eint_con = EXYNOS_WKUP_ECON_OFFSET,
 387         .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
 388         .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
 389 };
 390
 391 static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = {
 392         .chip = {
 393                 .name = "exynos7_wkup_irq_chip",
 394                 .irq_unmask = exynos_irq_unmask,
 395                 .irq_mask = exynos_irq_mask,
 396                 .irq_ack = exynos_irq_ack,
 397                 .irq_set_type = exynos_irq_set_type,
 398                 .irq_set_wake = exynos_wkup_irq_set_wake,
 399                 .irq_request_resources = exynos_irq_request_resources,
 400                 .irq_release_resources = exynos_irq_release_resources,
 401         },
 402         .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
 403         .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
 404         .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
 405 };
 406
 407 /* list of external wakeup controllers supported */
 408 static const struct of_device_id exynos_wkup_irq_ids[] = {
 409         { .compatible = "samsung,exynos4210-wakeup-eint",
 410                         .data = &exynos4210_wkup_irq_chip },
 411         { .compatible = "samsung,exynos7-wakeup-eint",
 412                         .data = &exynos7_wkup_irq_chip },
 413         { }
 414 };
 415
 416 /* interrupt handler for wakeup interrupts 0..15 */
 417 static void exynos_irq_eint0_15(struct irq_desc *desc)
 418 {
 419         struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);
 420         struct samsung_pin_bank *bank = eintd->bank;
 421         struct irq_chip *chip = irq_desc_get_chip(desc);
 422         int eint_irq;
 423
 424         chained_irq_enter(chip, desc);
 425
 426         eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
 427         generic_handle_irq(eint_irq);
 428
 429         chained_irq_exit(chip, desc);
 430 }
 431
 432 static inline void exynos_irq_demux_eint(unsigned long pend,
 433                                                 struct irq_domain *domain)
 434 {
 435         unsigned int irq;
 436
 437         while (pend) {
 438                 irq = fls(pend) - 1;
 439                 generic_handle_irq(irq_find_mapping(domain, irq));
 440                 pend &= ~(1 << irq);
 441         }
 442 }
 443
 444 /* interrupt handler for wakeup interrupt 16 */
 445 static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
 446 {
 447         struct irq_chip *chip = irq_desc_get_chip(desc);
 448         struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc);
 449         unsigned long pend;
 450         unsigned long mask;
 451         int i;
 452
 453         chained_irq_enter(chip, desc);
 454
 455         for (i = 0; i < eintd->nr_banks; ++i) {
 456                 struct samsung_pin_bank *b = eintd->banks[i];
 457                 pend = readl(b->eint_base + b->irq_chip->eint_pend
 458                                 + b->eint_offset);
 459                 mask = readl(b->eint_base + b->irq_chip->eint_mask
 460                                 + b->eint_offset);
 461                 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
 462         }
 463
 464         chained_irq_exit(chip, desc);
 465 }
 466
 467 /*
 468  * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
 469  * @d: driver data of samsung pinctrl driver.
 470  */
 471 static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
 472 {
 473         struct device *dev = d->dev;
 474         struct device_node *wkup_np = NULL;
 475         struct device_node *np;
 476         struct samsung_pin_bank *bank;
 477         struct exynos_weint_data *weint_data;
 478         struct exynos_muxed_weint_data *muxed_data;
 479         struct exynos_irq_chip *irq_chip;
 480         unsigned int muxed_banks = 0;
 481         unsigned int i;
 482         int idx, irq;
 483
 484         for_each_child_of_node(dev->of_node, np) {
 485                 const struct of_device_id *match;
 486
 487                 match = of_match_node(exynos_wkup_irq_ids, np);
 488                 if (match) {
 489                         irq_chip = kmemdup(match->data,
 490                                 sizeof(*irq_chip), GFP_KERNEL);
 491                         wkup_np = np;
 492                         break;
 493                 }
 494         }
 495         if (!wkup_np)
 496                 return -ENODEV;
 497
 498         bank = d->pin_banks;
 499         for (i = 0; i < d->nr_banks; ++i, ++bank) {
 500                 if (bank->eint_type != EINT_TYPE_WKUP)
 501                         continue;
 502
 503                 bank->irq_domain = irq_domain_add_linear(bank->of_node,
 504                                 bank->nr_pins, &exynos_eint_irqd_ops, bank);
 505                 if (!bank->irq_domain) {
 506                         dev_err(dev, "wkup irq domain add failed\n");
 507                         return -ENXIO;
 508                 }
 509
 510                 bank->irq_chip = irq_chip;
 511
 512                 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
 513                         bank->eint_type = EINT_TYPE_WKUP_MUX;
 514                         ++muxed_banks;
 515                         continue;
 516                 }
 517
 518                 weint_data = devm_kzalloc(dev, bank->nr_pins
 519                                         * sizeof(*weint_data), GFP_KERNEL);
 520                 if (!weint_data)
 521                         return -ENOMEM;
 522
 523                 for (idx = 0; idx < bank->nr_pins; ++idx) {
 524                         irq = irq_of_parse_and_map(bank->of_node, idx);
 525                         if (!irq) {
 526                                 dev_err(dev, "irq number for eint-%s-%d not found\n",
 527                                                         bank->name, idx);
 528                                 continue;
 529                         }
 530                         weint_data[idx].irq = idx;
 531                         weint_data[idx].bank = bank;
 532                         irq_set_chained_handler_and_data(irq,
 533                                                          exynos_irq_eint0_15,
 534                                                          &weint_data[idx]);
 535                 }
 536         }
 537
 538         if (!muxed_banks)
 539                 return 0;
 540
 541         irq = irq_of_parse_and_map(wkup_np, 0);
 542         if (!irq) {
 543                 dev_err(dev, "irq number for muxed EINTs not found\n");
 544                 return 0;
 545         }
 546
 547         muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
 548                 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
 549         if (!muxed_data)
 550                 return -ENOMEM;
 551
 552         irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31,
 553                                          muxed_data);
 554
 555         bank = d->pin_banks;
 556         idx = 0;
 557         for (i = 0; i < d->nr_banks; ++i, ++bank) {
 558                 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
 559                         continue;
 560
 561                 muxed_data->banks[idx++] = bank;
 562         }
 563         muxed_data->nr_banks = muxed_banks;
 564
 565         return 0;
 566 }
 567
 568 static void exynos_pinctrl_suspend_bank(
 569                                 struct samsung_pinctrl_drv_data *drvdata,
 570                                 struct samsung_pin_bank *bank)
 571 {
 572         struct exynos_eint_gpio_save *save = bank->soc_priv;
 573         void __iomem *regs = bank->eint_base;
 574
 575         save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
 576                                                 + bank->eint_offset);
 577         save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 578                                                 + 2 * bank->eint_offset);
 579         save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 580                                                 + 2 * bank->eint_offset + 4);
 581
 582         pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
 583         pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
 584         pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
 585 }
 586
 587 static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
 588 {
 589         struct samsung_pin_bank *bank = drvdata->pin_banks;
 590         int i;
 591
 592         for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
 593                 if (bank->eint_type == EINT_TYPE_GPIO)
 594                         exynos_pinctrl_suspend_bank(drvdata, bank);
 595 }
 596
 597 static void exynos_pinctrl_resume_bank(
 598                                 struct samsung_pinctrl_drv_data *drvdata,
 599                                 struct samsung_pin_bank *bank)
 600 {
 601         struct exynos_eint_gpio_save *save = bank->soc_priv;
 602         void __iomem *regs = bank->eint_base;
 603
 604         pr_debug("%s:     con %#010x => %#010x\n", bank->name,
 605                         readl(regs + EXYNOS_GPIO_ECON_OFFSET
 606                         + bank->eint_offset), save->eint_con);
 607         pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
 608                         readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 609                         + 2 * bank->eint_offset), save->eint_fltcon0);
 610         pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
 611                         readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 612                         + 2 * bank->eint_offset + 4), save->eint_fltcon1);
 613
 614         writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
 615                                                 + bank->eint_offset);
 616         writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
 617                                                 + 2 * bank->eint_offset);
 618         writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
 619                                                 + 2 * bank->eint_offset + 4);
 620 }
 621
 622 static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
 623 {
 624         struct samsung_pin_bank *bank = drvdata->pin_banks;
 625         int i;
 626
 627         for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
 628                 if (bank->eint_type == EINT_TYPE_GPIO)
 629                         exynos_pinctrl_resume_bank(drvdata, bank);
 630 }
 631
 632 /* pin banks of s5pv210 pin-controller */
 633 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
 634         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 635         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
 636         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
 637         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 638         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 639         EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
 640         EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
 641         EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
 642         EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
 643         EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
 644         EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
 645         EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
 646         EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
 647         EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
 648         EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
 649         EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
 650         EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
 651         EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
 652         EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
 653         EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
 654         EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
 655         EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
 656         EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
 657         EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
 658         EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
 659         EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
 660         EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
 661         EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
 662         EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
 663         EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
 664         EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
 665         EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
 666         EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
 667         EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
 668 };
 669
 670 const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
 671         {
 672                 /* pin-controller instance 0 data */
 673                 .pin_banks      = s5pv210_pin_bank,
 674                 .nr_banks       = ARRAY_SIZE(s5pv210_pin_bank),
 675                 .eint_gpio_init = exynos_eint_gpio_init,
 676                 .eint_wkup_init = exynos_eint_wkup_init,
 677                 .suspend        = exynos_pinctrl_suspend,
 678                 .resume         = exynos_pinctrl_resume,
 679         },
 680 };
 681
 682 /* pin banks of exynos3250 pin-controller 0 */
 683 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
 684         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 685         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 686         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb",  0x08),
 687         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 688         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 689         EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
 690         EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
 691 };
 692
 693 /* pin banks of exynos3250 pin-controller 1 */
 694 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
 695         EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
 696         EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
 697         EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
 698         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
 699         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 700         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 701         EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
 702         EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
 703         EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
 704         EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
 705         EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
 706         EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
 707         EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
 708         EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
 709         EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
 710         EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
 711 };
 712
 713 /*
 714  * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
 715  * two gpio/pin-mux/pinconfig controllers.
 716  */
 717 const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
 718         {
 719                 /* pin-controller instance 0 data */
 720                 .pin_banks      = exynos3250_pin_banks0,
 721                 .nr_banks       = ARRAY_SIZE(exynos3250_pin_banks0),
 722                 .eint_gpio_init = exynos_eint_gpio_init,
 723                 .suspend        = exynos_pinctrl_suspend,
 724                 .resume         = exynos_pinctrl_resume,
 725         }, {
 726                 /* pin-controller instance 1 data */
 727                 .pin_banks      = exynos3250_pin_banks1,
 728                 .nr_banks       = ARRAY_SIZE(exynos3250_pin_banks1),
 729                 .eint_gpio_init = exynos_eint_gpio_init,
 730                 .eint_wkup_init = exynos_eint_wkup_init,
 731                 .suspend        = exynos_pinctrl_suspend,
 732                 .resume         = exynos_pinctrl_resume,
 733         },
 734 };
 735
 736 /* pin banks of exynos4210 pin-controller 0 */
 737 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
 738         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 739         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 740         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
 741         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 742         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 743         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
 744         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
 745         EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
 746         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
 747         EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
 748         EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
 749         EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
 750         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
 751         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
 752         EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
 753         EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
 754 };
 755
 756 /* pin banks of exynos4210 pin-controller 1 */
 757 static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
 758         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
 759         EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
 760         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
 761         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 762         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 763         EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
 764         EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
 765         EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
 766         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
 767         EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
 768         EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
 769         EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
 770         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
 771         EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
 772         EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
 773         EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
 774         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 775         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 776         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 777         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 778 };
 779
 780 /* pin banks of exynos4210 pin-controller 2 */
 781 static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
 782         EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
 783 };
 784
 785 /*
 786  * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
 787  * three gpio/pin-mux/pinconfig controllers.
 788  */
 789 const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
 790         {
 791                 /* pin-controller instance 0 data */
 792                 .pin_banks      = exynos4210_pin_banks0,
 793                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks0),
 794                 .eint_gpio_init = exynos_eint_gpio_init,
 795                 .suspend        = exynos_pinctrl_suspend,
 796                 .resume         = exynos_pinctrl_resume,
 797         }, {
 798                 /* pin-controller instance 1 data */
 799                 .pin_banks      = exynos4210_pin_banks1,
 800                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks1),
 801                 .eint_gpio_init = exynos_eint_gpio_init,
 802                 .eint_wkup_init = exynos_eint_wkup_init,
 803                 .suspend        = exynos_pinctrl_suspend,
 804                 .resume         = exynos_pinctrl_resume,
 805         }, {
 806                 /* pin-controller instance 2 data */
 807                 .pin_banks      = exynos4210_pin_banks2,
 808                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks2),
 809         },
 810 };
 811
 812 /* pin banks of exynos4x12 pin-controller 0 */
 813 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
 814         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 815         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 816         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
 817         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 818         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 819         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
 820         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
 821         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
 822         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
 823         EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
 824         EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
 825         EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
 826         EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
 827 };
 828
 829 /* pin banks of exynos4x12 pin-controller 1 */
 830 static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
 831         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
 832         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 833         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 834         EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
 835         EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
 836         EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
 837         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
 838         EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
 839         EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
 840         EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
 841         EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
 842         EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
 843         EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
 844         EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
 845         EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
 846         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
 847         EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
 848         EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
 849         EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
 850         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 851         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 852         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 853         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 854 };
 855
 856 /* pin banks of exynos4x12 pin-controller 2 */
 857 static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
 858         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 859 };
 860
 861 /* pin banks of exynos4x12 pin-controller 3 */
 862 static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
 863         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
 864         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
 865         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
 866         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
 867         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
 868 };
 869
 870 /*
 871  * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
 872  * four gpio/pin-mux/pinconfig controllers.
 873  */
 874 const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
 875         {
 876                 /* pin-controller instance 0 data */
 877                 .pin_banks      = exynos4x12_pin_banks0,
 878                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks0),
 879                 .eint_gpio_init = exynos_eint_gpio_init,
 880                 .suspend        = exynos_pinctrl_suspend,
 881                 .resume         = exynos_pinctrl_resume,
 882         }, {
 883                 /* pin-controller instance 1 data */
 884                 .pin_banks      = exynos4x12_pin_banks1,
 885                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks1),
 886                 .eint_gpio_init = exynos_eint_gpio_init,
 887                 .eint_wkup_init = exynos_eint_wkup_init,
 888                 .suspend        = exynos_pinctrl_suspend,
 889                 .resume         = exynos_pinctrl_resume,
 890         }, {
 891                 /* pin-controller instance 2 data */
 892                 .pin_banks      = exynos4x12_pin_banks2,
 893                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks2),
 894                 .eint_gpio_init = exynos_eint_gpio_init,
 895                 .suspend        = exynos_pinctrl_suspend,
 896                 .resume         = exynos_pinctrl_resume,
 897         }, {
 898                 /* pin-controller instance 3 data */
 899                 .pin_banks      = exynos4x12_pin_banks3,
 900                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks3),
 901                 .eint_gpio_init = exynos_eint_gpio_init,
 902                 .suspend        = exynos_pinctrl_suspend,
 903                 .resume         = exynos_pinctrl_resume,
 904         },
 905 };
 906
 907 /* pin banks of exynos5250 pin-controller 0 */
 908 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
 909         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 910         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 911         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
 912         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
 913         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
 914         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
 915         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
 916         EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
 917         EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
 918         EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
 919         EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
 920         EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
 921         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
 922         EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
 923         EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
 924         EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
 925         EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
 926         EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
 927         EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
 928         EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
 929         EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
 930         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 931         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 932         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 933         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 934 };
 935
 936 /* pin banks of exynos5250 pin-controller 1 */
 937 static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
 938         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
 939         EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
 940         EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
 941         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
 942         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
 943         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
 944         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
 945         EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
 946         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
 947 };
 948
 949 /* pin banks of exynos5250 pin-controller 2 */
 950 static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
 951         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
 952         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
 953         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
 954         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
 955         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
 956 };
 957
 958 /* pin banks of exynos5250 pin-controller 3 */
 959 static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
 960         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 961 };
 962
 963 /*
 964  * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
 965  * four gpio/pin-mux/pinconfig controllers.
 966  */
 967 const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
 968         {
 969                 /* pin-controller instance 0 data */
 970                 .pin_banks      = exynos5250_pin_banks0,
 971                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks0),
 972                 .eint_gpio_init = exynos_eint_gpio_init,
 973                 .eint_wkup_init = exynos_eint_wkup_init,
 974                 .suspend        = exynos_pinctrl_suspend,
 975                 .resume         = exynos_pinctrl_resume,
 976         }, {
 977                 /* pin-controller instance 1 data */
 978                 .pin_banks      = exynos5250_pin_banks1,
 979                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks1),
 980                 .eint_gpio_init = exynos_eint_gpio_init,
 981                 .suspend        = exynos_pinctrl_suspend,
 982                 .resume         = exynos_pinctrl_resume,
 983         }, {
 984                 /* pin-controller instance 2 data */
 985                 .pin_banks      = exynos5250_pin_banks2,
 986                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks2),
 987                 .eint_gpio_init = exynos_eint_gpio_init,
 988                 .suspend        = exynos_pinctrl_suspend,
 989                 .resume         = exynos_pinctrl_resume,
 990         }, {
 991                 /* pin-controller instance 3 data */
 992                 .pin_banks      = exynos5250_pin_banks3,
 993                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks3),
 994                 .eint_gpio_init = exynos_eint_gpio_init,
 995                 .suspend        = exynos_pinctrl_suspend,
 996                 .resume         = exynos_pinctrl_resume,
 997         },
 998 };
 999
1000 /* pin banks of exynos5260 pin-controller 0 */
1001 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
1002         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
1003         EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
1004         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1005         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1006         EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
1007         EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
1008         EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
1009         EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
1010         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
1011         EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
1012         EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
1013         EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
1014         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
1015         EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
1016         EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
1017         EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
1018         EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
1019         EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
1020         EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
1021         EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
1022         EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
1023 };
1024
1025 /* pin banks of exynos5260 pin-controller 1 */
1026 static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
1027         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
1028         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
1029         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1030         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1031         EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
1032 };
1033
1034 /* pin banks of exynos5260 pin-controller 2 */
1035 static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
1036         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1037         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1038 };
1039
1040 /*
1041  * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
1042  * three gpio/pin-mux/pinconfig controllers.
1043  */
1044 const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
1045         {
1046                 /* pin-controller instance 0 data */
1047                 .pin_banks      = exynos5260_pin_banks0,
1048                 .nr_banks       = ARRAY_SIZE(exynos5260_pin_banks0),
1049                 .eint_gpio_init = exynos_eint_gpio_init,
1050                 .eint_wkup_init = exynos_eint_wkup_init,
1051         }, {
1052                 /* pin-controller instance 1 data */
1053                 .pin_banks      = exynos5260_pin_banks1,
1054                 .nr_banks       = ARRAY_SIZE(exynos5260_pin_banks1),
1055                 .eint_gpio_init = exynos_eint_gpio_init,
1056         }, {
1057                 /* pin-controller instance 2 data */
1058                 .pin_banks      = exynos5260_pin_banks2,
1059                 .nr_banks       = ARRAY_SIZE(exynos5260_pin_banks2),
1060                 .eint_gpio_init = exynos_eint_gpio_init,
1061         },
1062 };
1063
1064 /* pin banks of exynos5410 pin-controller 0 */
1065 static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
1066         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1067         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1068         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1069         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1070         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1071         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1072         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
1073         EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
1074         EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
1075         EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
1076         EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
1077         EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
1078         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
1079         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
1080         EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
1081         EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),
1082         EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),
1083         EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),
1084         EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),
1085         EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
1086         EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
1087         EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
1088         EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
1089         EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
1090         EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
1091         EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),
1092         EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),
1093         EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),
1094         EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),
1095         EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),
1096         EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),
1097         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1098         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1099         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1100         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1101 };
1102
1103 /* pin banks of exynos5410 pin-controller 1 */
1104 static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
1105         EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
1106         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
1107         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
1108         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),
1109         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),
1110         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),
1111         EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),
1112         EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),
1113         EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),
1114 };
1115
1116 /* pin banks of exynos5410 pin-controller 2 */
1117 static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
1118         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
1119         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
1120         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
1121         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
1122         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
1123 };
1124
1125 /* pin banks of exynos5410 pin-controller 3 */
1126 static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
1127         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1128 };
1129
1130 /*
1131  * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
1132  * four gpio/pin-mux/pinconfig controllers.
1133  */
1134 const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
1135         {
1136                 /* pin-controller instance 0 data */
1137                 .pin_banks      = exynos5410_pin_banks0,
1138                 .nr_banks       = ARRAY_SIZE(exynos5410_pin_banks0),
1139                 .eint_gpio_init = exynos_eint_gpio_init,
1140                 .eint_wkup_init = exynos_eint_wkup_init,
1141                 .suspend        = exynos_pinctrl_suspend,
1142                 .resume         = exynos_pinctrl_resume,
1143         }, {
1144                 /* pin-controller instance 1 data */
1145                 .pin_banks      = exynos5410_pin_banks1,
1146                 .nr_banks       = ARRAY_SIZE(exynos5410_pin_banks1),
1147                 .eint_gpio_init = exynos_eint_gpio_init,
1148                 .suspend        = exynos_pinctrl_suspend,
1149                 .resume         = exynos_pinctrl_resume,
1150         }, {
1151                 /* pin-controller instance 2 data */
1152                 .pin_banks      = exynos5410_pin_banks2,
1153                 .nr_banks       = ARRAY_SIZE(exynos5410_pin_banks2),
1154                 .eint_gpio_init = exynos_eint_gpio_init,
1155                 .suspend        = exynos_pinctrl_suspend,
1156                 .resume         = exynos_pinctrl_resume,
1157         }, {
1158                 /* pin-controller instance 3 data */
1159                 .pin_banks      = exynos5410_pin_banks3,
1160                 .nr_banks       = ARRAY_SIZE(exynos5410_pin_banks3),
1161                 .eint_gpio_init = exynos_eint_gpio_init,
1162                 .suspend        = exynos_pinctrl_suspend,
1163                 .resume         = exynos_pinctrl_resume,
1164         },
1165 };
1166
1167 /* pin banks of exynos5420 pin-controller 0 */
1168 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
1169         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
1170         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1171         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1172         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1173         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1174 };
1175
1176 /* pin banks of exynos5420 pin-controller 1 */
1177 static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
1178         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
1179         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
1180         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1181         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1182         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
1183         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
1184         EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
1185         EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
1186         EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
1187         EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
1188         EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
1189         EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
1190         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
1191 };
1192
1193 /* pin banks of exynos5420 pin-controller 2 */
1194 static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
1195         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1196         EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1197         EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
1198         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
1199         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
1200         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
1201         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
1202         EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
1203 };
1204
1205 /* pin banks of exynos5420 pin-controller 3 */
1206 static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
1207         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1208         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1209         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1210         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1211         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1212         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1213         EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
1214         EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
1215         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
1216 };
1217
1218 /* pin banks of exynos5420 pin-controller 4 */
1219 static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
1220         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1221 };
1222
1223 /*
1224  * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
1225  * four gpio/pin-mux/pinconfig controllers.
1226  */
1227 const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
1228         {
1229                 /* pin-controller instance 0 data */
1230                 .pin_banks      = exynos5420_pin_banks0,
1231                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks0),
1232                 .eint_gpio_init = exynos_eint_gpio_init,
1233                 .eint_wkup_init = exynos_eint_wkup_init,
1234         }, {
1235                 /* pin-controller instance 1 data */
1236                 .pin_banks      = exynos5420_pin_banks1,
1237                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks1),
1238                 .eint_gpio_init = exynos_eint_gpio_init,
1239         }, {
1240                 /* pin-controller instance 2 data */
1241                 .pin_banks      = exynos5420_pin_banks2,
1242                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks2),
1243                 .eint_gpio_init = exynos_eint_gpio_init,
1244         }, {
1245                 /* pin-controller instance 3 data */
1246                 .pin_banks      = exynos5420_pin_banks3,
1247                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks3),
1248                 .eint_gpio_init = exynos_eint_gpio_init,
1249         }, {
1250                 /* pin-controller instance 4 data */
1251                 .pin_banks      = exynos5420_pin_banks4,
1252                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks4),
1253                 .eint_gpio_init = exynos_eint_gpio_init,
1254         },
1255 };
1256
1257 /* pin banks of exynos5433 pin-controller - ALIVE */
1258 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = {
1259         EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1260         EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1261         EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1262         EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1263         EXYNOS_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
1264         EXYNOS_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
1265         EXYNOS_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),
1266         EXYNOS_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),
1267         EXYNOS_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),
1268 };
1269
1270 /* pin banks of exynos5433 pin-controller - AUD */
1271 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = {
1272         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1273         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1274 };
1275
1276 /* pin banks of exynos5433 pin-controller - CPIF */
1277 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = {
1278         EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
1279 };
1280
1281 /* pin banks of exynos5433 pin-controller - eSE */
1282 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = {
1283         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
1284 };
1285
1286 /* pin banks of exynos5433 pin-controller - FINGER */
1287 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = {
1288         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
1289 };
1290
1291 /* pin banks of exynos5433 pin-controller - FSYS */
1292 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = {
1293         EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
1294         EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
1295         EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
1296         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
1297         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
1298         EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
1299 };
1300
1301 /* pin banks of exynos5433 pin-controller - IMEM */
1302 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = {
1303         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
1304 };
1305
1306 /* pin banks of exynos5433 pin-controller - NFC */
1307 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = {
1308         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
1309 };
1310
1311 /* pin banks of exynos5433 pin-controller - PERIC */
1312 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = {
1313         EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
1314         EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
1315         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
1316         EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
1317         EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
1318         EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
1319         EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
1320         EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
1321         EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
1322         EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
1323         EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
1324         EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
1325         EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
1326         EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
1327         EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
1328         EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
1329         EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
1330 };
1331
1332 /* pin banks of exynos5433 pin-controller - TOUCH */
1333 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = {
1334         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
1335 };
1336
1337 /*
1338  * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
1339  * ten gpio/pin-mux/pinconfig controllers.
1340  */
1341 const struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
1342         {
1343                 /* pin-controller instance 0 data */
1344                 .pin_banks      = exynos5433_pin_banks0,
1345                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks0),
1346                 .eint_wkup_init = exynos_eint_wkup_init,
1347                 .suspend        = exynos_pinctrl_suspend,
1348                 .resume         = exynos_pinctrl_resume,
1349                 .nr_ext_resources = 1,
1350         }, {
1351                 /* pin-controller instance 1 data */
1352                 .pin_banks      = exynos5433_pin_banks1,
1353                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks1),
1354                 .eint_gpio_init = exynos_eint_gpio_init,
1355                 .suspend        = exynos_pinctrl_suspend,
1356                 .resume         = exynos_pinctrl_resume,
1357         }, {
1358                 /* pin-controller instance 2 data */
1359                 .pin_banks      = exynos5433_pin_banks2,
1360                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks2),
1361                 .eint_gpio_init = exynos_eint_gpio_init,
1362                 .suspend        = exynos_pinctrl_suspend,
1363                 .resume         = exynos_pinctrl_resume,
1364         }, {
1365                 /* pin-controller instance 3 data */
1366                 .pin_banks      = exynos5433_pin_banks3,
1367                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks3),
1368                 .eint_gpio_init = exynos_eint_gpio_init,
1369                 .suspend        = exynos_pinctrl_suspend,
1370                 .resume         = exynos_pinctrl_resume,
1371         }, {
1372                 /* pin-controller instance 4 data */
1373                 .pin_banks      = exynos5433_pin_banks4,
1374                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks4),
1375                 .eint_gpio_init = exynos_eint_gpio_init,
1376                 .suspend        = exynos_pinctrl_suspend,
1377                 .resume         = exynos_pinctrl_resume,
1378         }, {
1379                 /* pin-controller instance 5 data */
1380                 .pin_banks      = exynos5433_pin_banks5,
1381                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks5),
1382                 .eint_gpio_init = exynos_eint_gpio_init,
1383                 .suspend        = exynos_pinctrl_suspend,
1384                 .resume         = exynos_pinctrl_resume,
1385         }, {
1386                 /* pin-controller instance 6 data */
1387                 .pin_banks      = exynos5433_pin_banks6,
1388                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks6),
1389                 .eint_gpio_init = exynos_eint_gpio_init,
1390                 .suspend        = exynos_pinctrl_suspend,
1391                 .resume         = exynos_pinctrl_resume,
1392         }, {
1393                 /* pin-controller instance 7 data */
1394                 .pin_banks      = exynos5433_pin_banks7,
1395                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks7),
1396                 .eint_gpio_init = exynos_eint_gpio_init,
1397                 .suspend        = exynos_pinctrl_suspend,
1398                 .resume         = exynos_pinctrl_resume,
1399         }, {
1400                 /* pin-controller instance 8 data */
1401                 .pin_banks      = exynos5433_pin_banks8,
1402                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks8),
1403                 .eint_gpio_init = exynos_eint_gpio_init,
1404                 .suspend        = exynos_pinctrl_suspend,
1405                 .resume         = exynos_pinctrl_resume,
1406         }, {
1407                 /* pin-controller instance 9 data */
1408                 .pin_banks      = exynos5433_pin_banks9,
1409                 .nr_banks       = ARRAY_SIZE(exynos5433_pin_banks9),
1410                 .eint_gpio_init = exynos_eint_gpio_init,
1411                 .suspend        = exynos_pinctrl_suspend,
1412                 .resume         = exynos_pinctrl_resume,
1413         },
1414 };
1415
1416 /* pin banks of exynos7 pin-controller - ALIVE */
1417 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
1418         EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1419         EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1420         EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1421         EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1422 };
1423
1424 /* pin banks of exynos7 pin-controller - BUS0 */
1425 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
1426         EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
1427         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
1428         EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
1429         EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
1430         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
1431         EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
1432         EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
1433         EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
1434         EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
1435         EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
1436         EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
1437         EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
1438         EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
1439         EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
1440         EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
1441 };
1442
1443 /* pin banks of exynos7 pin-controller - NFC */
1444 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
1445         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
1446 };
1447
1448 /* pin banks of exynos7 pin-controller - TOUCH */
1449 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
1450         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
1451 };
1452
1453 /* pin banks of exynos7 pin-controller - FF */
1454 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
1455         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
1456 };
1457
1458 /* pin banks of exynos7 pin-controller - ESE */
1459 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
1460         EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
1461 };
1462
1463 /* pin banks of exynos7 pin-controller - FSYS0 */
1464 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
1465         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
1466 };
1467
1468 /* pin banks of exynos7 pin-controller - FSYS1 */
1469 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
1470         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
1471         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
1472         EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
1473         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
1474 };
1475
1476 /* pin banks of exynos7 pin-controller - BUS1 */
1477 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
1478         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
1479         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
1480         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
1481         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
1482         EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
1483         EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
1484         EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
1485         EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
1486         EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
1487         EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
1488 };
1489
1490 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {
1491         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1492         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1493 };
1494
1495 const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
1496         {
1497                 /* pin-controller instance 0 Alive data */
1498                 .pin_banks      = exynos7_pin_banks0,
1499                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks0),
1500                 .eint_wkup_init = exynos_eint_wkup_init,
1501         }, {
1502                 /* pin-controller instance 1 BUS0 data */
1503                 .pin_banks      = exynos7_pin_banks1,
1504                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks1),
1505                 .eint_gpio_init = exynos_eint_gpio_init,
1506         }, {
1507                 /* pin-controller instance 2 NFC data */
1508                 .pin_banks      = exynos7_pin_banks2,
1509                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks2),
1510                 .eint_gpio_init = exynos_eint_gpio_init,
1511         }, {
1512                 /* pin-controller instance 3 TOUCH data */
1513                 .pin_banks      = exynos7_pin_banks3,
1514                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks3),
1515                 .eint_gpio_init = exynos_eint_gpio_init,
1516         }, {
1517                 /* pin-controller instance 4 FF data */
1518                 .pin_banks      = exynos7_pin_banks4,
1519                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks4),
1520                 .eint_gpio_init = exynos_eint_gpio_init,
1521         }, {
1522                 /* pin-controller instance 5 ESE data */
1523                 .pin_banks      = exynos7_pin_banks5,
1524                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks5),
1525                 .eint_gpio_init = exynos_eint_gpio_init,
1526         }, {
1527                 /* pin-controller instance 6 FSYS0 data */
1528                 .pin_banks      = exynos7_pin_banks6,
1529                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks6),
1530                 .eint_gpio_init = exynos_eint_gpio_init,
1531         }, {
1532                 /* pin-controller instance 7 FSYS1 data */
1533                 .pin_banks      = exynos7_pin_banks7,
1534                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks7),
1535                 .eint_gpio_init = exynos_eint_gpio_init,
1536         }, {
1537                 /* pin-controller instance 8 BUS1 data */
1538                 .pin_banks      = exynos7_pin_banks8,
1539                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks8),
1540                 .eint_gpio_init = exynos_eint_gpio_init,
1541         }, {
1542                 /* pin-controller instance 9 AUD data */
1543                 .pin_banks      = exynos7_pin_banks9,
1544                 .nr_banks       = ARRAY_SIZE(exynos7_pin_banks9),
1545                 .eint_gpio_init = exynos_eint_gpio_init,
1546         },
1547 };