drivers/pinctrl/samsung/pinctrl-samsung.h

   1 /*
   2  * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2012 Linaro Ltd
   7  *              http://www.linaro.org
   8  *
   9  * Author: Thomas Abraham <thomas.ab@samsung.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #ifndef __PINCTRL_SAMSUNG_H
  18 #define __PINCTRL_SAMSUNG_H
  19
  20 #include <linux/pinctrl/pinctrl.h>
  21 #include <linux/pinctrl/pinmux.h>
  22 #include <linux/pinctrl/pinconf.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/pinctrl/machine.h>
  25
  26 #include <linux/gpio.h>
  27
  28 /**
  29  * enum pincfg_type - possible pin configuration types supported.
  30  * @PINCFG_TYPE_FUNC: Function configuration.
  31  * @PINCFG_TYPE_DAT: Pin value configuration.
  32  * @PINCFG_TYPE_PUD: Pull up/down configuration.
  33  * @PINCFG_TYPE_DRV: Drive strength configuration.
  34  * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
  35  * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
  36  */
  37 enum pincfg_type {
  38         PINCFG_TYPE_FUNC,
  39         PINCFG_TYPE_DAT,
  40         PINCFG_TYPE_PUD,
  41         PINCFG_TYPE_DRV,
  42         PINCFG_TYPE_CON_PDN,
  43         PINCFG_TYPE_PUD_PDN,
  44
  45         PINCFG_TYPE_NUM
  46 };
  47
  48 /*
  49  * pin configuration (pull up/down and drive strength) type and its value are
  50  * packed together into a 16-bits. The upper 8-bits represent the configuration
  51  * type and the lower 8-bits hold the value of the configuration type.
  52  */
  53 #define PINCFG_TYPE_MASK                0xFF
  54 #define PINCFG_VALUE_SHIFT              8
  55 #define PINCFG_VALUE_MASK               (0xFF << PINCFG_VALUE_SHIFT)
  56 #define PINCFG_PACK(type, value)        (((value) << PINCFG_VALUE_SHIFT) | type)
  57 #define PINCFG_UNPACK_TYPE(cfg)         ((cfg) & PINCFG_TYPE_MASK)
  58 #define PINCFG_UNPACK_VALUE(cfg)        (((cfg) & PINCFG_VALUE_MASK) >> \
  59                                                 PINCFG_VALUE_SHIFT)
  60 /**
  61  * enum eint_type - possible external interrupt types.
  62  * @EINT_TYPE_NONE: bank does not support external interrupts
  63  * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
  64  * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
  65  * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
  66  *
  67  * Samsung GPIO controller groups all the available pins into banks. The pins
  68  * in a pin bank can support external gpio interrupts or external wakeup
  69  * interrupts or no interrupts at all. From a software perspective, the only
  70  * difference between external gpio and external wakeup interrupts is that
  71  * the wakeup interrupts can additionally wakeup the system if it is in
  72  * suspended state.
  73  */
  74 enum eint_type {
  75         EINT_TYPE_NONE,
  76         EINT_TYPE_GPIO,
  77         EINT_TYPE_WKUP,
  78         EINT_TYPE_WKUP_MUX,
  79 };
  80
  81 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
  82 #define PIN_NAME_LENGTH 10
  83
  84 #define PIN_GROUP(n, p, f)                              \
  85         {                                               \
  86                 .name           = n,                    \
  87                 .pins           = p,                    \
  88                 .num_pins       = ARRAY_SIZE(p),        \
  89                 .func           = f                     \
  90         }
  91
  92 #define PMX_FUNC(n, g)                                  \
  93         {                                               \
  94                 .name           = n,                    \
  95                 .groups         = g,                    \
  96                 .num_groups     = ARRAY_SIZE(g),        \
  97         }
  98
  99 struct samsung_pinctrl_drv_data;
 100
 101 /**
 102  * struct samsung_pin_bank_type: pin bank type description
 103  * @fld_width: widths of configuration bitfields (0 if unavailable)
 104  * @reg_offset: offsets of configuration registers (don't care of width is 0)
 105  */
 106 struct samsung_pin_bank_type {
 107         u8 fld_width[PINCFG_TYPE_NUM];
 108         u8 reg_offset[PINCFG_TYPE_NUM];
 109 };
 110
 111 /**
 112  * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
 113  * @type: type of the bank (register offsets and bitfield widths)
 114  * @pctl_offset: starting offset of the pin-bank registers.
 115  * @pctl_res_idx: index of base address for pin-bank registers.
 116  * @nr_pins: number of pins included in this bank.
 117  * @eint_func: function to set in CON register to configure pin as EINT.
 118  * @eint_type: type of the external interrupt supported by the bank.
 119  * @eint_mask: bit mask of pins which support EINT function.
 120  * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
 121  * @name: name to be prefixed for each pin in this pin bank.
 122  */
 123 struct samsung_pin_bank_data {
 124         const struct samsung_pin_bank_type *type;
 125         u32             pctl_offset;
 126         u8              pctl_res_idx;
 127         u8              nr_pins;
 128         u8              eint_func;
 129         enum eint_type  eint_type;
 130         u32             eint_mask;
 131         u32             eint_offset;
 132         const char      *name;
 133 };
 134
 135 /**
 136  * struct samsung_pin_bank: represent a controller pin-bank.
 137  * @type: type of the bank (register offsets and bitfield widths)
 138  * @pctl_base: base address of the pin-bank registers
 139  * @pctl_offset: starting offset of the pin-bank registers.
 140  * @nr_pins: number of pins included in this bank.
 141  * @eint_base: base address of the pin-bank EINT registers.
 142  * @eint_func: function to set in CON register to configure pin as EINT.
 143  * @eint_type: type of the external interrupt supported by the bank.
 144  * @eint_mask: bit mask of pins which support EINT function.
 145  * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
 146  * @name: name to be prefixed for each pin in this pin bank.
 147  * @pin_base: starting pin number of the bank.
 148  * @soc_priv: per-bank private data for SoC-specific code.
 149  * @of_node: OF node of the bank.
 150  * @drvdata: link to controller driver data
 151  * @irq_domain: IRQ domain of the bank.
 152  * @gpio_chip: GPIO chip of the bank.
 153  * @grange: linux gpio pin range supported by this bank.
 154  * @irq_chip: link to irq chip for external gpio and wakeup interrupts.
 155  * @slock: spinlock protecting bank registers
 156  * @pm_save: saved register values during suspend
 157  */
 158 struct samsung_pin_bank {
 159         const struct samsung_pin_bank_type *type;
 160         void __iomem    *pctl_base;
 161         u32             pctl_offset;
 162         u8              nr_pins;
 163         void __iomem    *eint_base;
 164         u8              eint_func;
 165         enum eint_type  eint_type;
 166         u32             eint_mask;
 167         u32             eint_offset;
 168         const char      *name;
 169
 170         u32             pin_base;
 171         void            *soc_priv;
 172         struct device_node *of_node;
 173         struct samsung_pinctrl_drv_data *drvdata;
 174         struct irq_domain *irq_domain;
 175         struct gpio_chip gpio_chip;
 176         struct pinctrl_gpio_range grange;
 177         struct exynos_irq_chip *irq_chip;
 178         spinlock_t slock;
 179
 180         u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
 181 };
 182
 183 /**
 184  * struct samsung_retention_data: runtime pin-bank retention control data.
 185  * @regs: array of PMU registers to control pad retention.
 186  * @nr_regs: number of registers in @regs array.
 187  * @value: value to store to registers to turn off retention.
 188  * @refcnt: atomic counter if retention control affects more than one bank.
 189  * @priv: retention control code private data
 190  * @enable: platform specific callback to enter retention mode.
 191  * @disable: platform specific callback to exit retention mode.
 192  **/
 193 struct samsung_retention_ctrl {
 194         const u32       *regs;
 195         int             nr_regs;
 196         u32             value;
 197         atomic_t        *refcnt;
 198         void            *priv;
 199         void            (*enable)(struct samsung_pinctrl_drv_data *);
 200         void            (*disable)(struct samsung_pinctrl_drv_data *);
 201 };
 202
 203 /**
 204  * struct samsung_retention_data: represent a pin-bank retention control data.
 205  * @regs: array of PMU registers to control pad retention.
 206  * @nr_regs: number of registers in @regs array.
 207  * @value: value to store to registers to turn off retention.
 208  * @refcnt: atomic counter if retention control affects more than one bank.
 209  * @init: platform specific callback to initialize retention control.
 210  **/
 211 struct samsung_retention_data {
 212         const u32       *regs;
 213         int             nr_regs;
 214         u32             value;
 215         atomic_t        *refcnt;
 216         struct samsung_retention_ctrl *(*init)(struct samsung_pinctrl_drv_data *,
 217                                         const struct samsung_retention_data *);
 218 };
 219
 220 /**
 221  * struct samsung_pin_ctrl: represent a pin controller.
 222  * @pin_banks: list of pin banks included in this controller.
 223  * @nr_banks: number of pin banks.
 224  * @nr_ext_resources: number of the extra base address for pin banks.
 225  * @retention_data: configuration data for retention control.
 226  * @eint_gpio_init: platform specific callback to setup the external gpio
 227  *      interrupts for the controller.
 228  * @eint_wkup_init: platform specific callback to setup the external wakeup
 229  *      interrupts for the controller.
 230  */
 231 struct samsung_pin_ctrl {
 232         const struct samsung_pin_bank_data *pin_banks;
 233         unsigned int    nr_banks;
 234         unsigned int    nr_ext_resources;
 235         const struct samsung_retention_data *retention_data;
 236
 237         int             (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
 238         int             (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
 239         void            (*suspend)(struct samsung_pinctrl_drv_data *);
 240         void            (*resume)(struct samsung_pinctrl_drv_data *);
 241 };
 242
 243 /**
 244  * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
 245  * @node: global list node
 246  * @virt_base: register base address of the controller; this will be equal
 247  *             to each bank samsung_pin_bank->pctl_base and used on legacy
 248  *             platforms (like S3C24XX or S3C64XX) which has to access the base
 249  *             through samsung_pinctrl_drv_data, not samsung_pin_bank).
 250  * @dev: device instance representing the controller.
 251  * @irq: interrpt number used by the controller to notify gpio interrupts.
 252  * @ctrl: pin controller instance managed by the driver.
 253  * @pctl: pin controller descriptor registered with the pinctrl subsystem.
 254  * @pctl_dev: cookie representing pinctrl device instance.
 255  * @pin_groups: list of pin groups available to the driver.
 256  * @nr_groups: number of such pin groups.
 257  * @pmx_functions: list of pin functions available to the driver.
 258  * @nr_function: number of such pin functions.
 259  * @pin_base: starting system wide pin number.
 260  * @nr_pins: number of pins supported by the controller.
 261  * @retention_ctrl: retention control runtime data.
 262  */
 263 struct samsung_pinctrl_drv_data {
 264         struct list_head                node;
 265         void __iomem                    *virt_base;
 266         struct device                   *dev;
 267         int                             irq;
 268
 269         struct pinctrl_desc             pctl;
 270         struct pinctrl_dev              *pctl_dev;
 271
 272         const struct samsung_pin_group  *pin_groups;
 273         unsigned int                    nr_groups;
 274         const struct samsung_pmx_func   *pmx_functions;
 275         unsigned int                    nr_functions;
 276
 277         struct samsung_pin_bank         *pin_banks;
 278         unsigned int                    nr_banks;
 279         unsigned int                    pin_base;
 280         unsigned int                    nr_pins;
 281
 282         struct samsung_retention_ctrl   *retention_ctrl;
 283
 284         void (*suspend)(struct samsung_pinctrl_drv_data *);
 285         void (*resume)(struct samsung_pinctrl_drv_data *);
 286 };
 287
 288 /**
 289  * struct samsung_pin_group: represent group of pins of a pinmux function.
 290  * @name: name of the pin group, used to lookup the group.
 291  * @pins: the pins included in this group.
 292  * @num_pins: number of pins included in this group.
 293  * @func: the function number to be programmed when selected.
 294  */
 295 struct samsung_pin_group {
 296         const char              *name;
 297         const unsigned int      *pins;
 298         u8                      num_pins;
 299         u8                      func;
 300 };
 301
 302 /**
 303  * struct samsung_pmx_func: represent a pin function.
 304  * @name: name of the pin function, used to lookup the function.
 305  * @groups: one or more names of pin groups that provide this function.
 306  * @num_groups: number of groups included in @groups.
 307  */
 308 struct samsung_pmx_func {
 309         const char              *name;
 310         const char              **groups;
 311         u8                      num_groups;
 312         u32                     val;
 313 };
 314
 315 /* list of all exported SoC specific data */
 316 extern const struct samsung_pin_ctrl exynos3250_pin_ctrl[];
 317 extern const struct samsung_pin_ctrl exynos4210_pin_ctrl[];
 318 extern const struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
 319 extern const struct samsung_pin_ctrl exynos5250_pin_ctrl[];
 320 extern const struct samsung_pin_ctrl exynos5260_pin_ctrl[];
 321 extern const struct samsung_pin_ctrl exynos5410_pin_ctrl[];
 322 extern const struct samsung_pin_ctrl exynos5420_pin_ctrl[];
 323 extern const struct samsung_pin_ctrl exynos5433_pin_ctrl[];
 324 extern const struct samsung_pin_ctrl exynos7_pin_ctrl[];
 325 extern const struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
 326 extern const struct samsung_pin_ctrl s3c2412_pin_ctrl[];
 327 extern const struct samsung_pin_ctrl s3c2416_pin_ctrl[];
 328 extern const struct samsung_pin_ctrl s3c2440_pin_ctrl[];
 329 extern const struct samsung_pin_ctrl s3c2450_pin_ctrl[];
 330 extern const struct samsung_pin_ctrl s5pv210_pin_ctrl[];
 331
 332 #endif /* __PINCTRL_SAMSUNG_H */