drivers/pinctrl/sh-pfc/gpio.c

   1 /*
   2  * SuperH Pin Function Controller GPIO driver.
   3  *
   4  * Copyright (C) 2008 Magnus Damm
   5  * Copyright (C) 2009 - 2012 Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11
  12 #include <linux/device.h>
  13 #include <linux/gpio.h>
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/slab.h>
  18 #include <linux/spinlock.h>
  19
  20 #include "core.h"
  21
  22 struct sh_pfc_gpio_data_reg {
  23         const struct pinmux_data_reg *info;
  24         u32 shadow;
  25 };
  26
  27 struct sh_pfc_gpio_pin {
  28         u8 dbit;
  29         u8 dreg;
  30 };
  31
  32 struct sh_pfc_chip {
  33         struct sh_pfc                   *pfc;
  34         struct gpio_chip                gpio_chip;
  35
  36         struct sh_pfc_window            *mem;
  37         struct sh_pfc_gpio_data_reg     *regs;
  38         struct sh_pfc_gpio_pin          *pins;
  39 };
  40
  41 static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
  42 {
  43         struct sh_pfc_chip *chip = gpiochip_get_data(gc);
  44         return chip->pfc;
  45 }
  46
  47 static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
  48                               struct sh_pfc_gpio_data_reg **reg,
  49                               unsigned int *bit)
  50 {
  51         int idx = sh_pfc_get_pin_index(chip->pfc, offset);
  52         struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
  53
  54         *reg = &chip->regs[gpio_pin->dreg];
  55         *bit = gpio_pin->dbit;
  56 }
  57
  58 static u32 gpio_read_data_reg(struct sh_pfc_chip *chip,
  59                               const struct pinmux_data_reg *dreg)
  60 {
  61         phys_addr_t address = dreg->reg;
  62         void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
  63
  64         return sh_pfc_read_raw_reg(mem, dreg->reg_width);
  65 }
  66
  67 static void gpio_write_data_reg(struct sh_pfc_chip *chip,
  68                                 const struct pinmux_data_reg *dreg, u32 value)
  69 {
  70         phys_addr_t address = dreg->reg;
  71         void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
  72
  73         sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
  74 }
  75
  76 static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
  77 {
  78         struct sh_pfc *pfc = chip->pfc;
  79         struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
  80         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
  81         const struct pinmux_data_reg *dreg;
  82         unsigned int bit;
  83         unsigned int i;
  84
  85         for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
  86                 for (bit = 0; bit < dreg->reg_width; bit++) {
  87                         if (dreg->enum_ids[bit] == pin->enum_id) {
  88                                 gpio_pin->dreg = i;
  89                                 gpio_pin->dbit = bit;
  90                                 return;
  91                         }
  92                 }
  93         }
  94
  95         BUG();
  96 }
  97
  98 static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
  99 {
 100         struct sh_pfc *pfc = chip->pfc;
 101         const struct pinmux_data_reg *dreg;
 102         unsigned int i;
 103
 104         /* Count the number of data registers, allocate memory and initialize
 105          * them.
 106          */
 107         for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
 108                 ;
 109
 110         chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs),
 111                                   GFP_KERNEL);
 112         if (chip->regs == NULL)
 113                 return -ENOMEM;
 114
 115         for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
 116                 chip->regs[i].info = dreg;
 117                 chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
 118         }
 119
 120         for (i = 0; i < pfc->info->nr_pins; i++) {
 121                 if (pfc->info->pins[i].enum_id == 0)
 122                         continue;
 123
 124                 gpio_setup_data_reg(chip, i);
 125         }
 126
 127         return 0;
 128 }
 129
 130 /* -----------------------------------------------------------------------------
 131  * Pin GPIOs
 132  */
 133
 134 static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
 135 {
 136         struct sh_pfc *pfc = gpio_to_pfc(gc);
 137         int idx = sh_pfc_get_pin_index(pfc, offset);
 138
 139         if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
 140                 return -EINVAL;
 141
 142         return pinctrl_gpio_request(offset);
 143 }
 144
 145 static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
 146 {
 147         return pinctrl_gpio_free(offset);
 148 }
 149
 150 static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
 151                                int value)
 152 {
 153         struct sh_pfc_gpio_data_reg *reg;
 154         unsigned int bit;
 155         unsigned int pos;
 156
 157         gpio_get_data_reg(chip, offset, &reg, &bit);
 158
 159         pos = reg->info->reg_width - (bit + 1);
 160
 161         if (value)
 162                 reg->shadow |= BIT(pos);
 163         else
 164                 reg->shadow &= ~BIT(pos);
 165
 166         gpio_write_data_reg(chip, reg->info, reg->shadow);
 167 }
 168
 169 static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
 170 {
 171         return pinctrl_gpio_direction_input(offset);
 172 }
 173
 174 static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
 175                                     int value)
 176 {
 177         gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
 178
 179         return pinctrl_gpio_direction_output(offset);
 180 }
 181
 182 static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
 183 {
 184         struct sh_pfc_chip *chip = gpiochip_get_data(gc);
 185         struct sh_pfc_gpio_data_reg *reg;
 186         unsigned int bit;
 187         unsigned int pos;
 188
 189         gpio_get_data_reg(chip, offset, &reg, &bit);
 190
 191         pos = reg->info->reg_width - (bit + 1);
 192
 193         return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
 194 }
 195
 196 static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
 197 {
 198         gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
 199 }
 200
 201 static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
 202 {
 203         struct sh_pfc *pfc = gpio_to_pfc(gc);
 204         unsigned int i, k;
 205
 206         for (i = 0; i < pfc->info->gpio_irq_size; i++) {
 207                 const short *gpios = pfc->info->gpio_irq[i].gpios;
 208
 209                 for (k = 0; gpios[k] >= 0; k++) {
 210                         if (gpios[k] == offset)
 211                                 goto found;
 212                 }
 213         }
 214
 215         return 0;
 216
 217 found:
 218         return pfc->irqs[i];
 219 }
 220
 221 static int gpio_pin_setup(struct sh_pfc_chip *chip)
 222 {
 223         struct sh_pfc *pfc = chip->pfc;
 224         struct gpio_chip *gc = &chip->gpio_chip;
 225         int ret;
 226
 227         chip->pins = devm_kzalloc(pfc->dev, pfc->info->nr_pins *
 228                                   sizeof(*chip->pins), GFP_KERNEL);
 229         if (chip->pins == NULL)
 230                 return -ENOMEM;
 231
 232         ret = gpio_setup_data_regs(chip);
 233         if (ret < 0)
 234                 return ret;
 235
 236         gc->request = gpio_pin_request;
 237         gc->free = gpio_pin_free;
 238         gc->direction_input = gpio_pin_direction_input;
 239         gc->get = gpio_pin_get;
 240         gc->direction_output = gpio_pin_direction_output;
 241         gc->set = gpio_pin_set;
 242         gc->to_irq = gpio_pin_to_irq;
 243
 244         gc->label = pfc->info->name;
 245         gc->parent = pfc->dev;
 246         gc->owner = THIS_MODULE;
 247         gc->base = 0;
 248         gc->ngpio = pfc->nr_gpio_pins;
 249
 250         return 0;
 251 }
 252
 253 /* -----------------------------------------------------------------------------
 254  * Function GPIOs
 255  */
 256
 257 #ifdef CONFIG_SUPERH
 258 static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
 259 {
 260         static bool __print_once;
 261         struct sh_pfc *pfc = gpio_to_pfc(gc);
 262         unsigned int mark = pfc->info->func_gpios[offset].enum_id;
 263         unsigned long flags;
 264         int ret;
 265
 266         if (!__print_once) {
 267                 dev_notice(pfc->dev,
 268                            "Use of GPIO API for function requests is deprecated."
 269                            " Convert to pinctrl\n");
 270                 __print_once = true;
 271         }
 272
 273         if (mark == 0)
 274                 return -EINVAL;
 275
 276         spin_lock_irqsave(&pfc->lock, flags);
 277         ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
 278         spin_unlock_irqrestore(&pfc->lock, flags);
 279
 280         return ret;
 281 }
 282
 283 static int gpio_function_setup(struct sh_pfc_chip *chip)
 284 {
 285         struct sh_pfc *pfc = chip->pfc;
 286         struct gpio_chip *gc = &chip->gpio_chip;
 287
 288         gc->request = gpio_function_request;
 289
 290         gc->label = pfc->info->name;
 291         gc->owner = THIS_MODULE;
 292         gc->base = pfc->nr_gpio_pins;
 293         gc->ngpio = pfc->info->nr_func_gpios;
 294
 295         return 0;
 296 }
 297 #endif
 298
 299 /* -----------------------------------------------------------------------------
 300  * Register/unregister
 301  */
 302
 303 static struct sh_pfc_chip *
 304 sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
 305                     struct sh_pfc_window *mem)
 306 {
 307         struct sh_pfc_chip *chip;
 308         int ret;
 309
 310         chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
 311         if (unlikely(!chip))
 312                 return ERR_PTR(-ENOMEM);
 313
 314         chip->mem = mem;
 315         chip->pfc = pfc;
 316
 317         ret = setup(chip);
 318         if (ret < 0)
 319                 return ERR_PTR(ret);
 320
 321         ret = devm_gpiochip_add_data(pfc->dev, &chip->gpio_chip, chip);
 322         if (unlikely(ret < 0))
 323                 return ERR_PTR(ret);
 324
 325         dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
 326                  chip->gpio_chip.label, chip->gpio_chip.base,
 327                  chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
 328
 329         return chip;
 330 }
 331
 332 int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
 333 {
 334         struct sh_pfc_chip *chip;
 335         phys_addr_t address;
 336         unsigned int i;
 337
 338         if (pfc->info->data_regs == NULL)
 339                 return 0;
 340
 341         /* Find the memory window that contain the GPIO registers. Boards that
 342          * register a separate GPIO device will not supply a memory resource
 343          * that covers the data registers. In that case don't try to handle
 344          * GPIOs.
 345          */
 346         address = pfc->info->data_regs[0].reg;
 347         for (i = 0; i < pfc->num_windows; ++i) {
 348                 struct sh_pfc_window *window = &pfc->windows[i];
 349
 350                 if (address >= window->phys &&
 351                     address < window->phys + window->size)
 352                         break;
 353         }
 354
 355         if (i == pfc->num_windows)
 356                 return 0;
 357
 358         /* If we have IRQ resources make sure their number is correct. */
 359         if (pfc->num_irqs != pfc->info->gpio_irq_size) {
 360                 dev_err(pfc->dev, "invalid number of IRQ resources\n");
 361                 return -EINVAL;
 362         }
 363
 364         /* Register the real GPIOs chip. */
 365         chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]);
 366         if (IS_ERR(chip))
 367                 return PTR_ERR(chip);
 368
 369         pfc->gpio = chip;
 370
 371         if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
 372                 return 0;
 373
 374 #ifdef CONFIG_SUPERH
 375         /*
 376          * Register the GPIO to pin mappings. As pins with GPIO ports
 377          * must come first in the ranges, skip the pins without GPIO
 378          * ports by stopping at the first range that contains such a
 379          * pin.
 380          */
 381         for (i = 0; i < pfc->nr_ranges; ++i) {
 382                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
 383                 int ret;
 384
 385                 if (range->start >= pfc->nr_gpio_pins)
 386                         break;
 387
 388                 ret = gpiochip_add_pin_range(&chip->gpio_chip,
 389                         dev_name(pfc->dev), range->start, range->start,
 390                         range->end - range->start + 1);
 391                 if (ret < 0)
 392                         return ret;
 393         }
 394
 395         /* Register the function GPIOs chip. */
 396         if (pfc->info->nr_func_gpios == 0)
 397                 return 0;
 398
 399         chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
 400         if (IS_ERR(chip))
 401                 return PTR_ERR(chip);
 402 #endif /* CONFIG_SUPERH */
 403
 404         return 0;
 405 }