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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / sh-pfc / pfc-r8a7740.c
1 /*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24
25 #include "core.h"
26 #include "sh_pfc.h"
27
28 #define CPU_ALL_PORT(fn, pfx, sfx) \
29 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
30 PORT_10(100, fn, pfx##10, sfx), PORT_90(100, fn, pfx##1, sfx), \
31 PORT_10(200, fn, pfx##20, sfx), \
32 PORT_1(210, fn, pfx##210, sfx), PORT_1(211, fn, pfx##211, sfx)
33
34 #define IRQC_PIN_MUX(irq, pin) \
35 static const unsigned int intc_irq##irq##_pins[] = { \
36 pin, \
37 }; \
38 static const unsigned int intc_irq##irq##_mux[] = { \
39 IRQ##irq##_MARK, \
40 }
41
42 #define IRQC_PINS_MUX(irq, idx, pin) \
43 static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
44 pin, \
45 }; \
46 static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
47 IRQ##irq##_PORT##pin##_MARK, \
48 }
49
50 enum {
51 PINMUX_RESERVED = 0,
52
53 /* PORT0_DATA -> PORT211_DATA */
54 PINMUX_DATA_BEGIN,
55 PORT_ALL(DATA),
56 PINMUX_DATA_END,
57
58 /* PORT0_IN -> PORT211_IN */
59 PINMUX_INPUT_BEGIN,
60 PORT_ALL(IN),
61 PINMUX_INPUT_END,
62
63 /* PORT0_OUT -> PORT211_OUT */
64 PINMUX_OUTPUT_BEGIN,
65 PORT_ALL(OUT),
66 PINMUX_OUTPUT_END,
67
68 PINMUX_FUNCTION_BEGIN,
69 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
70 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
71 PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
72 PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
73 PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
74 PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
75 PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
76 PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
77 PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
78 PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
79
80 MSEL1CR_31_0, MSEL1CR_31_1,
81 MSEL1CR_30_0, MSEL1CR_30_1,
82 MSEL1CR_29_0, MSEL1CR_29_1,
83 MSEL1CR_28_0, MSEL1CR_28_1,
84 MSEL1CR_27_0, MSEL1CR_27_1,
85 MSEL1CR_26_0, MSEL1CR_26_1,
86 MSEL1CR_16_0, MSEL1CR_16_1,
87 MSEL1CR_15_0, MSEL1CR_15_1,
88 MSEL1CR_14_0, MSEL1CR_14_1,
89 MSEL1CR_13_0, MSEL1CR_13_1,
90 MSEL1CR_12_0, MSEL1CR_12_1,
91 MSEL1CR_9_0, MSEL1CR_9_1,
92 MSEL1CR_7_0, MSEL1CR_7_1,
93 MSEL1CR_6_0, MSEL1CR_6_1,
94 MSEL1CR_5_0, MSEL1CR_5_1,
95 MSEL1CR_4_0, MSEL1CR_4_1,
96 MSEL1CR_3_0, MSEL1CR_3_1,
97 MSEL1CR_2_0, MSEL1CR_2_1,
98 MSEL1CR_0_0, MSEL1CR_0_1,
99
100 MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
101 MSEL3CR_6_0, MSEL3CR_6_1,
102
103 MSEL4CR_19_0, MSEL4CR_19_1,
104 MSEL4CR_18_0, MSEL4CR_18_1,
105 MSEL4CR_15_0, MSEL4CR_15_1,
106 MSEL4CR_10_0, MSEL4CR_10_1,
107 MSEL4CR_6_0, MSEL4CR_6_1,
108 MSEL4CR_4_0, MSEL4CR_4_1,
109 MSEL4CR_1_0, MSEL4CR_1_1,
110
111 MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
112 MSEL5CR_30_0, MSEL5CR_30_1,
113 MSEL5CR_29_0, MSEL5CR_29_1,
114 MSEL5CR_27_0, MSEL5CR_27_1,
115 MSEL5CR_25_0, MSEL5CR_25_1,
116 MSEL5CR_23_0, MSEL5CR_23_1,
117 MSEL5CR_21_0, MSEL5CR_21_1,
118 MSEL5CR_19_0, MSEL5CR_19_1,
119 MSEL5CR_17_0, MSEL5CR_17_1,
120 MSEL5CR_15_0, MSEL5CR_15_1,
121 MSEL5CR_14_0, MSEL5CR_14_1,
122 MSEL5CR_13_0, MSEL5CR_13_1,
123 MSEL5CR_12_0, MSEL5CR_12_1,
124 MSEL5CR_11_0, MSEL5CR_11_1,
125 MSEL5CR_10_0, MSEL5CR_10_1,
126 MSEL5CR_8_0, MSEL5CR_8_1,
127 MSEL5CR_7_0, MSEL5CR_7_1,
128 MSEL5CR_6_0, MSEL5CR_6_1,
129 MSEL5CR_5_0, MSEL5CR_5_1,
130 MSEL5CR_4_0, MSEL5CR_4_1,
131 MSEL5CR_3_0, MSEL5CR_3_1,
132 MSEL5CR_2_0, MSEL5CR_2_1,
133 MSEL5CR_0_0, MSEL5CR_0_1,
134 PINMUX_FUNCTION_END,
135
136 PINMUX_MARK_BEGIN,
137
138 /* IRQ */
139 IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
140 IRQ1_MARK,
141 IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
142 IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
143 IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
144 IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
145 IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
146 IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
147 IRQ8_MARK,
148 IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
149 IRQ10_MARK,
150 IRQ11_MARK,
151 IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
152 IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
153 IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
154 IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
155 IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
156 IRQ17_MARK,
157 IRQ18_MARK,
158 IRQ19_MARK,
159 IRQ20_MARK,
160 IRQ21_MARK,
161 IRQ22_MARK,
162 IRQ23_MARK,
163 IRQ24_MARK,
164 IRQ25_MARK,
165 IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
166 IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
167 IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
168 IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
169 IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
170 IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
171
172 /* Function */
173
174 /* DBGT */
175 DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
176 DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
177 DBGMD21_MARK,
178
179 /* FSI-A */
180 FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
181 FSIAISLD_PORT5_MARK,
182 FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
183 FSIASPDIF_PORT18_MARK,
184 FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
185 FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
186 FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
187
188 /* FSI-B */
189 FSIBCK_MARK,
190
191 /* FMSI */
192 FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
193 FMSISLD_PORT6_MARK,
194 FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
195 FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
196 FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
197
198 /* SCIFA0 */
199 SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
200 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
201
202 /* SCIFA1 */
203 SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
204 SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
205
206 /* SCIFA2 */
207 SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
208 SCIFA2_SCK_PORT199_MARK,
209 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
210 SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
211
212 /* SCIFA3 */
213 SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
214 SCIFA3_SCK_PORT116_MARK,
215 SCIFA3_CTS_PORT117_MARK,
216 SCIFA3_RXD_PORT174_MARK,
217 SCIFA3_TXD_PORT175_MARK,
218
219 SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
220 SCIFA3_SCK_PORT158_MARK,
221 SCIFA3_CTS_PORT162_MARK,
222 SCIFA3_RXD_PORT159_MARK,
223 SCIFA3_TXD_PORT160_MARK,
224
225 /* SCIFA4 */
226 SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
227 SCIFA4_TXD_PORT13_MARK,
228
229 SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
230 SCIFA4_TXD_PORT203_MARK,
231
232 SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
233 SCIFA4_TXD_PORT93_MARK,
234
235 SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
236 SCIFA4_SCK_PORT205_MARK,
237
238 /* SCIFA5 */
239 SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
240 SCIFA5_RXD_PORT10_MARK,
241
242 SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
243 SCIFA5_TXD_PORT208_MARK,
244
245 SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
246 SCIFA5_RXD_PORT92_MARK,
247
248 SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
249 SCIFA5_SCK_PORT206_MARK,
250
251 /* SCIFA6 */
252 SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
253
254 /* SCIFA7 */
255 SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
256
257 /* SCIFB */
258 SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
259 SCIFB_RXD_PORT191_MARK,
260 SCIFB_TXD_PORT192_MARK,
261 SCIFB_RTS_PORT186_MARK,
262 SCIFB_CTS_PORT187_MARK,
263
264 SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
265 SCIFB_RXD_PORT3_MARK,
266 SCIFB_TXD_PORT4_MARK,
267 SCIFB_RTS_PORT172_MARK,
268 SCIFB_CTS_PORT173_MARK,
269
270 /* LCD0 */
271 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
272 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
273 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
274 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
275 LCD0_D16_MARK, LCD0_D17_MARK,
276 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
277 LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
278 LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
279 LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
280 LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
281
282 LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
283 LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
284 LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
285 LCD0_LCLK_PORT165_MARK,
286
287 LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
288 LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
289 LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
290 LCD0_LCLK_PORT102_MARK,
291
292 /* LCD1 */
293 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
294 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
295 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
296 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
297 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
298 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
299 LCD1_DON_MARK, LCD1_VCPWC_MARK,
300 LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
301
302 LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
303 LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
304 LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
305 LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
306
307 /* RSPI */
308 RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
309 RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
310 RSPI_MISO_A_MARK,
311
312 /* VIO CKO */
313 VIO_CKO1_MARK, /* needs fixup */
314 VIO_CKO2_MARK,
315 VIO_CKO_1_MARK,
316 VIO_CKO_MARK,
317
318 /* VIO0 */
319 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
320 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
321 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
322 VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
323 VIO0_FIELD_MARK,
324
325 VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
326 VIO0_D14_PORT25_MARK,
327 VIO0_D15_PORT24_MARK,
328
329 VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
330 VIO0_D14_PORT95_MARK,
331 VIO0_D15_PORT96_MARK,
332
333 /* VIO1 */
334 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
335 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
336 VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
337
338 /* TPU0 */
339 TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
340 TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
341 TPU0TO2_PORT202_MARK,
342
343 /* SSP1 0 */
344 STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
345 STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
346 STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
347
348 /* SSP1 1 */
349 STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
350 STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
351 STP1_IPSYNC_MARK,
352
353 STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
354 STP1_IPEN_PORT187_MARK,
355
356 STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
357 STP1_IPEN_PORT193_MARK,
358
359 /* SIM */
360 SIM_RST_MARK, SIM_CLK_MARK,
361 SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
362 SIM_D_PORT199_MARK,
363
364 /* SDHI0 */
365 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
366 SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
367
368 /* SDHI1 */
369 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
370 SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
371
372 /* SDHI2 */
373 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
374 SDHI2_CLK_MARK, SDHI2_CMD_MARK,
375
376 SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
377 SDHI2_WP_PORT25_MARK,
378
379 SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
380 SDHI2_CD_PORT202_MARK,
381
382 /* MSIOF2 */
383 MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
384 MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
385 MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
386 MSIOF2_RSCK_MARK,
387
388 /* KEYSC */
389 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
390 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
391 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
392
393 KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
394 KEYIN1_PORT44_MARK,
395 KEYIN2_PORT45_MARK,
396 KEYIN3_PORT46_MARK,
397
398 KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
399 KEYIN1_PORT57_MARK,
400 KEYIN2_PORT56_MARK,
401 KEYIN3_PORT55_MARK,
402
403 /* VOU */
404 DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
405 DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
406 DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
407 DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
408 DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
409
410 /* MEMC */
411 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
412 MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
413 MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
414 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
415 MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
416
417 MEMC_CS1_MARK, /* MSEL4CR_6_0 */
418 MEMC_ADV_MARK,
419 MEMC_WAIT_MARK,
420 MEMC_BUSCLK_MARK,
421
422 MEMC_A1_MARK, /* MSEL4CR_6_1 */
423 MEMC_DREQ0_MARK,
424 MEMC_DREQ1_MARK,
425 MEMC_A0_MARK,
426
427 /* MMC */
428 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
429 MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
430 MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
431 MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
432
433 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
434 MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
435 MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
436 MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
437
438 /* MSIOF0 */
439 MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
440 MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
441 MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
442 MSIOF0_TSYNC_MARK,
443
444 /* MSIOF1 */
445 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
446 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
447
448 MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
449 MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
450 MSIOF1_TSYNC_PORT120_MARK,
451 MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
452
453 MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
454 MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
455 MSIOF1_RXD_PORT75_MARK,
456 MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
457
458 /* GPIO */
459 GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
460
461 /* USB0 */
462 USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
463
464 /* USB1 */
465 USB1_OCI_MARK, USB1_PPON_MARK,
466
467 /* BBIF1 */
468 BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
469 BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
470 BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
471
472 /* BBIF2 */
473 BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
474 BBIF2_RXD2_PORT60_MARK,
475 BBIF2_TSYNC2_PORT6_MARK,
476 BBIF2_TSCK2_PORT59_MARK,
477
478 BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
479 BBIF2_TXD2_PORT183_MARK,
480 BBIF2_TSCK2_PORT89_MARK,
481 BBIF2_TSYNC2_PORT184_MARK,
482
483 /* BSC / FLCTL / PCMCIA */
484 CS0_MARK, CS2_MARK, CS4_MARK,
485 CS5B_MARK, CS6A_MARK,
486 CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
487 CS5A_PORT19_MARK,
488 IOIS16_MARK, /* ? */
489
490 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
491 A4_FOE_MARK, /* share with FLCTL */
492 A5_FCDE_MARK, /* share with FLCTL */
493 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
494 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
495 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
496 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
497 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
498 A26_MARK,
499
500 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
501 D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
502 D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
503 D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
504 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
505 D15_NAF15_MARK, /* share with FLCTL */
506 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
507 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
508 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
509 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
510
511 WE0_FWE_MARK, /* share with FLCTL */
512 WE1_MARK,
513 WE2_ICIORD_MARK, /* share with PCMCIA */
514 WE3_ICIOWR_MARK, /* share with PCMCIA */
515 CKO_MARK, BS_MARK, RDWR_MARK,
516 RD_FSC_MARK, /* share with FLCTL */
517 WAIT_PORT177_MARK, /* WAIT Port 90/177 */
518 WAIT_PORT90_MARK,
519
520 FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
521
522 /* IRDA */
523 IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
524
525 /* ATAPI */
526 IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
527 IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
528 IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
529 IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
530 IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
531 IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
532 IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
533 IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
534
535 /* RMII */
536 RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
537 RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
538 RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
539 RMII_REF50CK_MARK, /* for RMII */
540 RMII_REF125CK_MARK, /* for GMII */
541
542 /* GEther */
543 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
544 ET_ETXD2_MARK, ET_ETXD3_MARK,
545 ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
546 ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
547 ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
548 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
549 ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
550 ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
551 ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
552 ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
553
554 /* DMA0 */
555 DREQ0_MARK, DACK0_MARK,
556
557 /* DMA1 */
558 DREQ1_MARK, DACK1_MARK,
559
560 /* SYSC */
561 RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
562
563 /* IRREM */
564 IROUT_MARK,
565
566 /* SDENC */
567 SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
568
569 /* HDMI */
570 HDMI_HPD_MARK, HDMI_CEC_MARK,
571
572 /* DEBUG */
573 EDEBGREQ_PULLUP_MARK, /* for JTAG */
574 EDEBGREQ_PULLDOWN_MARK,
575
576 TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
577 TRACEAUD_FROM_LCDC0_MARK,
578 TRACEAUD_FROM_MEMC_MARK,
579
580 PINMUX_MARK_END,
581 };
582
583 static const u16 pinmux_data[] = {
584 PINMUX_DATA_ALL(),
585
586 /* Port0 */
587 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
588 PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
589 PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
590 PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
591 PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
592 PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
593 PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
594
595 /* Port1 */
596 PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
597 PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
598 PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
599 PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
600 PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
601 PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
602 PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
603
604 /* Port2 */
605 PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
606 PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
607 PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
608 PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
609 PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
610
611 /* Port3 */
612 PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
613 PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
614 PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
615 PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
616
617 /* Port4 */
618 PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
619 PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
620 PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
621 PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
622
623 /* Port5 */
624 PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
625 PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
626 PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
627 PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
628 PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
629
630 /* Port6 */
631 PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
632 PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
633 PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
634 PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
635 PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
636
637 /* Port7 */
638 PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
639
640 /* Port8 */
641 PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
642
643 /* Port9 */
644 PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
645 PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
646
647 /* Port10 */
648 PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
649 PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
650 PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
651
652 /* Port11 */
653 PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
654 PINMUX_DATA(FSIBCK_MARK, PORT11_FN2),
655 PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
656
657 /* Port12 */
658 PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
659 PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
660 PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
661 PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
662 PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
663
664 /* Port13 */
665 PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
666 PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
667 PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
668 PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
669
670 /* Port14 */
671 PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
672 PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
673 PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
674 PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
675 PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
676
677 /* Port15 */
678 PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
679 PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
680 PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
681 PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
682 PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
683
684 /* Port16 */
685 PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
686 PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
687
688 /* Port17 */
689 PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
690 PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
691
692 /* Port18 */
693 PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
694 PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
695
696 /* Port19 */
697 PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
698 PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
699 PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
700
701 /* Port20 */
702 PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
703 PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
704 PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
705
706 /* Port21 */
707 PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
708 PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
709 PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
710 PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
711 PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
712 PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
713
714 /* Port22 */
715 PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
716 PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
717 PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
718
719 /* Port23 */
720 PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
721 PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
722 PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
723 PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
724 PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
725 PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
726
727 /* Port24 */
728 PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
729 PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
730 PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
731 PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
732
733 /* Port25 */
734 PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
735 PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
736 PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
737 PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
738
739 /* Port26 */
740 PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
741 PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
742 PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
743
744 /* Port27 - Port39 Function */
745 PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
746 PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
747 PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
748 PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
749 PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
750 PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
751 PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
752 PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
753 PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
754 PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
755 PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
756 PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
757 PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
758
759 /* Port38 IRQ */
760 PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
761
762 /* Port40 */
763 PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
764 PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
765 PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
766
767 /* Port41 */
768 PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
769 PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
770 PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
771
772 /* Port42 */
773 PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
774 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
775 PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
776
777 /* Port43 */
778 PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
779 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
780 PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
781 PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
782
783 /* Port44 */
784 PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
785 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
786 PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
787 PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
788
789 /* Port45 */
790 PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
791 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
792 PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
793 PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
794
795 /* Port46 */
796 PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
797 PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
798 PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
799
800 /* Port47 */
801 PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
802 PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
803 PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
804
805 /* Port48 */
806 PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
807 PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
808 PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
809
810 /* Port49 */
811 PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
812 PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
813 PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
814 PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
815
816 /* Port50 */
817 PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
818 PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
819 PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
820 PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
821
822 /* Port51 */
823 PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
824 PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
825 PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
826
827 /* Port52 */
828 PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
829 PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
830 PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
831
832 /* Port53 */
833 PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
834 PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
835 PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
836
837 /* Port54 */
838 PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
839 PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
840 PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
841
842 /* Port55 */
843 PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
844 PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
845 PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
846 PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
847
848 /* Port56 */
849 PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
850 PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
851 PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
852 PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
853 PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
854
855 /* Port57 */
856 PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
857 PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
858 PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
859 PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
860 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
861
862 /* Port58 */
863 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0),
864 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
865 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
866 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
867 PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
868
869 /* Port59 */
870 PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
871 PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
872 PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
873
874 /* Port60 */
875 PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
876 PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
877 PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
878
879 /* Port61 */
880 PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
881 PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
882
883 /* Port62 */
884 PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
885 PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
886 PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
887 PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
888
889 /* Port63 */
890 PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
891 PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
892 PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
893
894 /* Port64 */
895 PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
896 PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
897 PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
898 PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
899
900 /* Port65 */
901 PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
902 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
903 PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
904
905 /* Port66 */
906 PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
907 PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
908 PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
909 PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
910
911 /* Port67 - Port73 Function1 */
912 PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
913 PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
914 PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
915 PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
916 PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
917 PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
918 PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
919
920 /* Port67 - Port73 Function2 */
921 PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
922 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
923 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
924 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
925 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
926 PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
927 PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
928
929 /* Port67 - Port73 Function4 */
930 PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
931 PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
932 PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
933 PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
934 PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
935 PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
936 PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
937
938 /* Port67 - Port73 Function6 */
939 PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
940 PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
941 PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
942 PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
943 PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
944 PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
945 PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
946
947 /* Port67 - Port71 IRQ */
948 PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
949 PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
950 PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
951 PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
952 PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
953
954 /* Port74 */
955 PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
956 PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
957 PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
958 PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
959 PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
960
961 /* Port75 */
962 PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
963 PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
964 PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
965 PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
966 PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
967
968 /* Port76 - Port80 Function */
969 PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
970 PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
971 PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
972 PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
973 PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
974
975 /* Port81 */
976 PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
977 PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
978
979 /* Port82 - Port88 Function */
980 PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
981 PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
982 PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
983 PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
984 PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
985 PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
986 PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
987
988 /* Port89 */
989 PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
990 PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
991 PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
992
993 /* Port90 */
994 PINMUX_DATA(DACK0_MARK, PORT90_FN1),
995 PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
996 PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
997 PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
998
999 /* Port91 */
1000 PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
1001 PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
1002 PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1003 PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
1004
1005 /* Port92 */
1006 PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
1007 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
1008 PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1009 PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
1010 PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
1011
1012 /* Port93 */
1013 PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
1014 PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
1015 PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1016 PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
1017 PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
1018
1019 /* Port94 */
1020 PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
1021 PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
1022 PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1023 PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
1024 PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
1025
1026 /* Port95 */
1027 PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
1028 PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
1029
1030 PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
1031 PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
1032 PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
1033 PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
1034
1035 /* Port96 */
1036 PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
1037 PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
1038
1039 PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
1040 PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
1041 PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
1042 PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
1043
1044 /* Port97 */
1045 PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
1046 PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
1047 PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
1048 PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
1049 PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
1050
1051 /* Port98 */
1052 PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
1053 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
1054 PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
1055 PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
1056
1057 /* Port99 */
1058 PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
1059 PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
1060 PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
1061 PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
1062 PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
1063
1064 /* Port100 */
1065 PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
1066 PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
1067 PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
1068 PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
1069
1070 /* Port101 */
1071 PINMUX_DATA(FCE0_MARK, PORT101_FN1),
1072
1073 /* Port102 */
1074 PINMUX_DATA(FRB_MARK, PORT102_FN1),
1075 PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
1076
1077 /* Port103 */
1078 PINMUX_DATA(CS5B_MARK, PORT103_FN1),
1079 PINMUX_DATA(FCE1_MARK, PORT103_FN2),
1080 PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
1081
1082 /* Port104 */
1083 PINMUX_DATA(CS6A_MARK, PORT104_FN1),
1084 PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
1085 PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
1086
1087 /* Port105 */
1088 PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
1089 PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
1090
1091 /* Port106 */
1092 PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
1093 PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
1094
1095 /* Port107 - Port115 Function */
1096 PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
1097 PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
1098 PINMUX_DATA(CS0_MARK, PORT109_FN1),
1099 PINMUX_DATA(CS2_MARK, PORT110_FN1),
1100 PINMUX_DATA(CS4_MARK, PORT111_FN1),
1101 PINMUX_DATA(WE1_MARK, PORT112_FN1),
1102 PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
1103 PINMUX_DATA(RDWR_MARK, PORT114_FN1),
1104 PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
1105
1106 /* Port116 */
1107 PINMUX_DATA(A25_MARK, PORT116_FN1),
1108 PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
1109 PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
1110 PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
1111 PINMUX_DATA(GPO1_MARK, PORT116_FN5),
1112
1113 /* Port117 */
1114 PINMUX_DATA(A24_MARK, PORT117_FN1),
1115 PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
1116 PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
1117 PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
1118 PINMUX_DATA(GPO0_MARK, PORT117_FN5),
1119
1120 /* Port118 */
1121 PINMUX_DATA(A23_MARK, PORT118_FN1),
1122 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
1123 PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
1124 PINMUX_DATA(GPI1_MARK, PORT118_FN5),
1125 PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
1126
1127 /* Port119 */
1128 PINMUX_DATA(A22_MARK, PORT119_FN1),
1129 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
1130 PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
1131 PINMUX_DATA(GPI0_MARK, PORT119_FN5),
1132 PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
1133
1134 /* Port120 */
1135 PINMUX_DATA(A21_MARK, PORT120_FN1),
1136 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1137 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1138 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
1139
1140 /* Port121 */
1141 PINMUX_DATA(A20_MARK, PORT121_FN1),
1142 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
1143 PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
1144 PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
1145
1146 /* Port122 */
1147 PINMUX_DATA(A19_MARK, PORT122_FN1),
1148 PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
1149
1150 /* Port123 */
1151 PINMUX_DATA(A18_MARK, PORT123_FN1),
1152 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
1153
1154 /* Port124 */
1155 PINMUX_DATA(A17_MARK, PORT124_FN1),
1156 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
1157
1158 /* Port125 - Port141 Function */
1159 PINMUX_DATA(A16_MARK, PORT125_FN1),
1160 PINMUX_DATA(A15_MARK, PORT126_FN1),
1161 PINMUX_DATA(A14_MARK, PORT127_FN1),
1162 PINMUX_DATA(A13_MARK, PORT128_FN1),
1163 PINMUX_DATA(A12_MARK, PORT129_FN1),
1164 PINMUX_DATA(A11_MARK, PORT130_FN1),
1165 PINMUX_DATA(A10_MARK, PORT131_FN1),
1166 PINMUX_DATA(A9_MARK, PORT132_FN1),
1167 PINMUX_DATA(A8_MARK, PORT133_FN1),
1168 PINMUX_DATA(A7_MARK, PORT134_FN1),
1169 PINMUX_DATA(A6_MARK, PORT135_FN1),
1170 PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
1171 PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
1172 PINMUX_DATA(A3_MARK, PORT138_FN1),
1173 PINMUX_DATA(A2_MARK, PORT139_FN1),
1174 PINMUX_DATA(A1_MARK, PORT140_FN1),
1175 PINMUX_DATA(CKO_MARK, PORT141_FN1),
1176
1177 /* Port142 - Port157 Function1 */
1178 PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
1179 PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
1180 PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
1181 PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
1182 PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
1183 PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
1184 PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
1185 PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
1186 PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
1187 PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
1188 PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
1189 PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
1190 PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
1191 PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
1192 PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
1193 PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
1194
1195 /* Port142 - Port149 Function3 */
1196 PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
1197 PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
1198 PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
1199 PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
1200 PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
1201 PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
1202 PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
1203 PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
1204
1205 /* Port158 */
1206 PINMUX_DATA(D31_MARK, PORT158_FN1),
1207 PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
1208 PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
1209 PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
1210 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
1211 PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
1212
1213 /* Port159 */
1214 PINMUX_DATA(D30_MARK, PORT159_FN1),
1215 PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
1216 PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
1217 PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
1218 PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
1219
1220 /* Port160 */
1221 PINMUX_DATA(D29_MARK, PORT160_FN1),
1222 PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
1223 PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
1224 PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
1225 PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
1226
1227 /* Port161 */
1228 PINMUX_DATA(D28_MARK, PORT161_FN1),
1229 PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
1230 PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
1231 PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
1232 PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
1233 PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
1234
1235 /* Port162 */
1236 PINMUX_DATA(D27_MARK, PORT162_FN1),
1237 PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
1238 PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
1239 PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
1240 PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
1241
1242 /* Port163 */
1243 PINMUX_DATA(D26_MARK, PORT163_FN1),
1244 PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
1245 PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
1246 PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
1247 PINMUX_DATA(IROUT_MARK, PORT163_FN5),
1248 PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
1249
1250 /* Port164 */
1251 PINMUX_DATA(D25_MARK, PORT164_FN1),
1252 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
1253 PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
1254 PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
1255 PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
1256
1257 /* Port165 */
1258 PINMUX_DATA(D24_MARK, PORT165_FN1),
1259 PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
1260 PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
1261 PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
1262
1263 /* Port166 - Port171 Function1 */
1264 PINMUX_DATA(D21_MARK, PORT166_FN1),
1265 PINMUX_DATA(D20_MARK, PORT167_FN1),
1266 PINMUX_DATA(D19_MARK, PORT168_FN1),
1267 PINMUX_DATA(D18_MARK, PORT169_FN1),
1268 PINMUX_DATA(D17_MARK, PORT170_FN1),
1269 PINMUX_DATA(D16_MARK, PORT171_FN1),
1270
1271 /* Port166 - Port171 Function3 */
1272 PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
1273 PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
1274 PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
1275 PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
1276 PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
1277 PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
1278
1279 /* Port166 - Port171 Function6 */
1280 PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
1281 PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
1282 PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
1283 PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
1284 PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
1285 PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
1286
1287 /* Port167 - Port171 IRQ */
1288 PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
1289 PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
1290 PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
1291 PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
1292 PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
1293
1294 /* Port172 */
1295 PINMUX_DATA(D23_MARK, PORT172_FN1),
1296 PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
1297 PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
1298 PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
1299 PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
1300
1301 /* Port173 */
1302 PINMUX_DATA(D22_MARK, PORT173_FN1),
1303 PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
1304 PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
1305 PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
1306 PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
1307
1308 /* Port174 */
1309 PINMUX_DATA(A26_MARK, PORT174_FN1),
1310 PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
1311 PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
1312 PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
1313
1314 /* Port175 */
1315 PINMUX_DATA(A0_MARK, PORT175_FN1),
1316 PINMUX_DATA(BS_MARK, PORT175_FN2),
1317 PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
1318 PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
1319
1320 /* Port176 */
1321 PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
1322
1323 /* Port177 */
1324 PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
1325 PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
1326 PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
1327 PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
1328
1329 /* Port178 */
1330 PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
1331 PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
1332 PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
1333
1334 /* Port179 */
1335 PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
1336 PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
1337 PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
1338
1339 /* Port180 */
1340 PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
1341 PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
1342 PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
1343 PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
1344 PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
1345
1346 /* Port181 */
1347 PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
1348 PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
1349 PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
1350
1351 /* Port182 */
1352 PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
1353 PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
1354 PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
1355
1356 /* Port183 */
1357 PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
1358 PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
1359 PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
1360
1361 /* Port184 */
1362 PINMUX_DATA(DACK1_MARK, PORT184_FN1),
1363 PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
1364 PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
1365
1366 /* Port185 - Port192 Function1 */
1367 PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
1368 PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
1369 PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
1370 PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
1371 PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
1372 PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
1373 PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
1374
1375 /* Port185 - Port192 Function3 */
1376 PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
1377 PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
1378 PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
1379 PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
1380 PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
1381 PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
1382 PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
1383 PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
1384
1385 /* Port185 - Port192 Function6 */
1386 PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
1387 PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
1388 PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
1389 PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
1390 PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
1391 PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
1392 PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
1393 PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
1394
1395 /* Port193 */
1396 PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
1397 PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
1398 PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
1399 PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
1400
1401 /* Port194 */
1402 PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
1403 PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
1404 PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
1405 PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
1406
1407 /* Port195 */
1408 PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
1409 PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
1410 PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
1411 PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
1412
1413 /* Port196 */
1414 PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
1415 PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
1416 PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
1417 PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
1418
1419 /* Port197 */
1420 PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
1421 PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
1422 PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
1423 PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
1424
1425 /* Port198 */
1426 PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
1427 PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
1428 PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
1429 PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
1430
1431 /* Port199 */
1432 PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
1433 PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
1434 PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
1435 PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
1436 PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
1437 PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
1438
1439 /* Port200 */
1440 PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
1441 PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
1442 PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
1443 PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
1444 PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
1445
1446 /* Port201 */
1447 PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
1448 PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
1449
1450 PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
1451 PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
1452 PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
1453 PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
1454
1455 /* Port202 */
1456 PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
1457 PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
1458
1459 PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
1460 PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
1461 PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
1462 PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
1463 PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
1464 PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
1465
1466 /* Port203 - Port208 Function1 */
1467 PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
1468 PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
1469 PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
1470 PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
1471 PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
1472 PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
1473
1474 /* Port203 - Port208 Function3 */
1475 PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
1476 PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
1477 PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
1478 PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
1479 PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
1480 PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
1481
1482 /* Port203 - Port208 Function6 */
1483 PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
1484 PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
1485 PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
1486 PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
1487 PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
1488 PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
1489
1490 /* Port203 - Port208 Function7 */
1491 PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1492 PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1493 PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
1494 PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
1495 PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1496 PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1497
1498 /* Port209 */
1499 PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1500 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
1501
1502 /* Port210 */
1503 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
1504 PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1),
1505
1506 /* Port211 */
1507 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1508 PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
1509
1510 /* SDENC */
1511 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1512 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
1513
1514 /* SYSC */
1515 PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
1516 PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
1517
1518 /* DEBUG */
1519 PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
1520 PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
1521
1522 PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
1523 PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
1524 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1525 };
1526
1527 #define __I (SH_PFC_PIN_CFG_INPUT)
1528 #define __O (SH_PFC_PIN_CFG_OUTPUT)
1529 #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1530 #define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
1531 #define __PU (SH_PFC_PIN_CFG_PULL_UP)
1532 #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1533
1534 #define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
1535 #define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
1536 #define R8A7740_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
1537 #define R8A7740_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
1538 #define R8A7740_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
1539 #define R8A7740_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
1540 #define R8A7740_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
1541 #define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
1542 #define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
1543
1544 static const struct sh_pfc_pin pinmux_pins[] = {
1545 /* Table 56-1 (I/O and Pull U/D) */
1546 R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1),
1547 R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3),
1548 R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5),
1549 R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7),
1550 R8A7740_PIN_IO(8), R8A7740_PIN_IO(9),
1551 R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11),
1552 R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13),
1553 R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15),
1554 R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17),
1555 R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19),
1556 R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21),
1557 R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23),
1558 R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25),
1559 R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27),
1560 R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29),
1561 R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31),
1562 R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33),
1563 R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35),
1564 R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37),
1565 R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39),
1566 R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41),
1567 R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43),
1568 R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45),
1569 R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47),
1570 R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49),
1571 R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51),
1572 R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53),
1573 R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55),
1574 R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57),
1575 R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59),
1576 R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61),
1577 R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63),
1578 R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65),
1579 R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67),
1580 R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69),
1581 R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71),
1582 R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73),
1583 R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75),
1584 R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77),
1585 R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79),
1586 R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81),
1587 R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83),
1588 R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85),
1589 R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87),
1590 R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89),
1591 R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91),
1592 R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93),
1593 R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95),
1594 R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97),
1595 R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99),
1596 R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101),
1597 R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103),
1598 R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105),
1599 R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107),
1600 R8A7740_PIN_IO(108), R8A7740_PIN_IO(109),
1601 R8A7740_PIN_IO(110), R8A7740_PIN_IO(111),
1602 R8A7740_PIN_IO(112), R8A7740_PIN_IO(113),
1603 R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115),
1604 R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117),
1605 R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119),
1606 R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121),
1607 R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123),
1608 R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125),
1609 R8A7740_PIN_IO(126), R8A7740_PIN_IO(127),
1610 R8A7740_PIN_IO(128), R8A7740_PIN_IO(129),
1611 R8A7740_PIN_IO(130), R8A7740_PIN_IO(131),
1612 R8A7740_PIN_IO(132), R8A7740_PIN_IO(133),
1613 R8A7740_PIN_IO(134), R8A7740_PIN_IO(135),
1614 R8A7740_PIN_IO(136), R8A7740_PIN_IO(137),
1615 R8A7740_PIN_IO(138), R8A7740_PIN_IO(139),
1616 R8A7740_PIN_IO(140), R8A7740_PIN_IO(141),
1617 R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143),
1618 R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145),
1619 R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147),
1620 R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149),
1621 R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151),
1622 R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153),
1623 R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155),
1624 R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157),
1625 R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159),
1626 R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161),
1627 R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163),
1628 R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165),
1629 R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167),
1630 R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169),
1631 R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171),
1632 R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173),
1633 R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175),
1634 R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177),
1635 R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179),
1636 R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181),
1637 R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183),
1638 R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185),
1639 R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187),
1640 R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189),
1641 R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191),
1642 R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193),
1643 R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195),
1644 R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197),
1645 R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199),
1646 R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201),
1647 R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203),
1648 R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205),
1649 R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207),
1650 R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209),
1651 R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211),
1652 };
1653
1654 /* - BSC -------------------------------------------------------------------- */
1655 static const unsigned int bsc_data8_pins[] = {
1656 /* D[0:7] */
1657 157, 156, 155, 154, 153, 152, 151, 150,
1658 };
1659 static const unsigned int bsc_data8_mux[] = {
1660 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1661 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1662 };
1663 static const unsigned int bsc_data16_pins[] = {
1664 /* D[0:15] */
1665 157, 156, 155, 154, 153, 152, 151, 150,
1666 149, 148, 147, 146, 145, 144, 143, 142,
1667 };
1668 static const unsigned int bsc_data16_mux[] = {
1669 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1670 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1671 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1672 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1673 };
1674 static const unsigned int bsc_data32_pins[] = {
1675 /* D[0:31] */
1676 157, 156, 155, 154, 153, 152, 151, 150,
1677 149, 148, 147, 146, 145, 144, 143, 142,
1678 171, 170, 169, 168, 167, 166, 173, 172,
1679 165, 164, 163, 162, 161, 160, 159, 158,
1680 };
1681 static const unsigned int bsc_data32_mux[] = {
1682 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1683 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1684 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1685 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1686 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
1687 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
1688 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
1689 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
1690 };
1691 static const unsigned int bsc_cs0_pins[] = {
1692 /* CS */
1693 109,
1694 };
1695 static const unsigned int bsc_cs0_mux[] = {
1696 CS0_MARK,
1697 };
1698 static const unsigned int bsc_cs2_pins[] = {
1699 /* CS */
1700 110,
1701 };
1702 static const unsigned int bsc_cs2_mux[] = {
1703 CS2_MARK,
1704 };
1705 static const unsigned int bsc_cs4_pins[] = {
1706 /* CS */
1707 111,
1708 };
1709 static const unsigned int bsc_cs4_mux[] = {
1710 CS4_MARK,
1711 };
1712 static const unsigned int bsc_cs5a_0_pins[] = {
1713 /* CS */
1714 105,
1715 };
1716 static const unsigned int bsc_cs5a_0_mux[] = {
1717 CS5A_PORT105_MARK,
1718 };
1719 static const unsigned int bsc_cs5a_1_pins[] = {
1720 /* CS */
1721 19,
1722 };
1723 static const unsigned int bsc_cs5a_1_mux[] = {
1724 CS5A_PORT19_MARK,
1725 };
1726 static const unsigned int bsc_cs5b_pins[] = {
1727 /* CS */
1728 103,
1729 };
1730 static const unsigned int bsc_cs5b_mux[] = {
1731 CS5B_MARK,
1732 };
1733 static const unsigned int bsc_cs6a_pins[] = {
1734 /* CS */
1735 104,
1736 };
1737 static const unsigned int bsc_cs6a_mux[] = {
1738 CS6A_MARK,
1739 };
1740 static const unsigned int bsc_rd_we8_pins[] = {
1741 /* RD, WE[0] */
1742 115, 113,
1743 };
1744 static const unsigned int bsc_rd_we8_mux[] = {
1745 RD_FSC_MARK, WE0_FWE_MARK,
1746 };
1747 static const unsigned int bsc_rd_we16_pins[] = {
1748 /* RD, WE[0:1] */
1749 115, 113, 112,
1750 };
1751 static const unsigned int bsc_rd_we16_mux[] = {
1752 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1753 };
1754 static const unsigned int bsc_rd_we32_pins[] = {
1755 /* RD, WE[0:3] */
1756 115, 113, 112, 108, 107,
1757 };
1758 static const unsigned int bsc_rd_we32_mux[] = {
1759 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
1760 };
1761 static const unsigned int bsc_bs_pins[] = {
1762 /* BS */
1763 175,
1764 };
1765 static const unsigned int bsc_bs_mux[] = {
1766 BS_MARK,
1767 };
1768 static const unsigned int bsc_rdwr_pins[] = {
1769 /* RDWR */
1770 114,
1771 };
1772 static const unsigned int bsc_rdwr_mux[] = {
1773 RDWR_MARK,
1774 };
1775 /* - CEU0 ------------------------------------------------------------------- */
1776 static const unsigned int ceu0_data_0_7_pins[] = {
1777 /* D[0:7] */
1778 34, 33, 32, 31, 30, 29, 28, 27,
1779 };
1780 static const unsigned int ceu0_data_0_7_mux[] = {
1781 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
1782 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
1783 };
1784 static const unsigned int ceu0_data_8_15_0_pins[] = {
1785 /* D[8:15] */
1786 182, 181, 180, 179, 178, 26, 25, 24,
1787 };
1788 static const unsigned int ceu0_data_8_15_0_mux[] = {
1789 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1790 VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
1791 VIO0_D15_PORT24_MARK,
1792 };
1793 static const unsigned int ceu0_data_8_15_1_pins[] = {
1794 /* D[8:15] */
1795 182, 181, 180, 179, 178, 22, 95, 96,
1796 };
1797 static const unsigned int ceu0_data_8_15_1_mux[] = {
1798 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1799 VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
1800 VIO0_D15_PORT96_MARK,
1801 };
1802 static const unsigned int ceu0_clk_0_pins[] = {
1803 /* CKO */
1804 36,
1805 };
1806 static const unsigned int ceu0_clk_0_mux[] = {
1807 VIO_CKO_MARK,
1808 };
1809 static const unsigned int ceu0_clk_1_pins[] = {
1810 /* CKO */
1811 14,
1812 };
1813 static const unsigned int ceu0_clk_1_mux[] = {
1814 VIO_CKO1_MARK,
1815 };
1816 static const unsigned int ceu0_clk_2_pins[] = {
1817 /* CKO */
1818 15,
1819 };
1820 static const unsigned int ceu0_clk_2_mux[] = {
1821 VIO_CKO2_MARK,
1822 };
1823 static const unsigned int ceu0_sync_pins[] = {
1824 /* CLK, VD, HD */
1825 35, 39, 37,
1826 };
1827 static const unsigned int ceu0_sync_mux[] = {
1828 VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
1829 };
1830 static const unsigned int ceu0_field_pins[] = {
1831 /* FIELD */
1832 38,
1833 };
1834 static const unsigned int ceu0_field_mux[] = {
1835 VIO0_FIELD_MARK,
1836 };
1837 /* - CEU1 ------------------------------------------------------------------- */
1838 static const unsigned int ceu1_data_pins[] = {
1839 /* D[0:7] */
1840 182, 181, 180, 179, 178, 26, 25, 24,
1841 };
1842 static const unsigned int ceu1_data_mux[] = {
1843 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
1844 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
1845 };
1846 static const unsigned int ceu1_clk_pins[] = {
1847 /* CKO */
1848 23,
1849 };
1850 static const unsigned int ceu1_clk_mux[] = {
1851 VIO_CKO_1_MARK,
1852 };
1853 static const unsigned int ceu1_sync_pins[] = {
1854 /* CLK, VD, HD */
1855 197, 198, 160,
1856 };
1857 static const unsigned int ceu1_sync_mux[] = {
1858 VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
1859 };
1860 static const unsigned int ceu1_field_pins[] = {
1861 /* FIELD */
1862 21,
1863 };
1864 static const unsigned int ceu1_field_mux[] = {
1865 VIO1_FIELD_MARK,
1866 };
1867 /* - FSIA ------------------------------------------------------------------- */
1868 static const unsigned int fsia_mclk_in_pins[] = {
1869 /* CK */
1870 11,
1871 };
1872 static const unsigned int fsia_mclk_in_mux[] = {
1873 FSIACK_MARK,
1874 };
1875 static const unsigned int fsia_mclk_out_pins[] = {
1876 /* OMC */
1877 10,
1878 };
1879 static const unsigned int fsia_mclk_out_mux[] = {
1880 FSIAOMC_MARK,
1881 };
1882 static const unsigned int fsia_sclk_in_pins[] = {
1883 /* ILR, IBT */
1884 12, 13,
1885 };
1886 static const unsigned int fsia_sclk_in_mux[] = {
1887 FSIAILR_MARK, FSIAIBT_MARK,
1888 };
1889 static const unsigned int fsia_sclk_out_pins[] = {
1890 /* OLR, OBT */
1891 7, 8,
1892 };
1893 static const unsigned int fsia_sclk_out_mux[] = {
1894 FSIAOLR_MARK, FSIAOBT_MARK,
1895 };
1896 static const unsigned int fsia_data_in_0_pins[] = {
1897 /* ISLD */
1898 0,
1899 };
1900 static const unsigned int fsia_data_in_0_mux[] = {
1901 FSIAISLD_PORT0_MARK,
1902 };
1903 static const unsigned int fsia_data_in_1_pins[] = {
1904 /* ISLD */
1905 5,
1906 };
1907 static const unsigned int fsia_data_in_1_mux[] = {
1908 FSIAISLD_PORT5_MARK,
1909 };
1910 static const unsigned int fsia_data_out_0_pins[] = {
1911 /* OSLD */
1912 9,
1913 };
1914 static const unsigned int fsia_data_out_0_mux[] = {
1915 FSIAOSLD_MARK,
1916 };
1917 static const unsigned int fsia_data_out_1_pins[] = {
1918 /* OSLD */
1919 0,
1920 };
1921 static const unsigned int fsia_data_out_1_mux[] = {
1922 FSIAOSLD1_MARK,
1923 };
1924 static const unsigned int fsia_data_out_2_pins[] = {
1925 /* OSLD */
1926 1,
1927 };
1928 static const unsigned int fsia_data_out_2_mux[] = {
1929 FSIAOSLD2_MARK,
1930 };
1931 static const unsigned int fsia_spdif_0_pins[] = {
1932 /* SPDIF */
1933 9,
1934 };
1935 static const unsigned int fsia_spdif_0_mux[] = {
1936 FSIASPDIF_PORT9_MARK,
1937 };
1938 static const unsigned int fsia_spdif_1_pins[] = {
1939 /* SPDIF */
1940 18,
1941 };
1942 static const unsigned int fsia_spdif_1_mux[] = {
1943 FSIASPDIF_PORT18_MARK,
1944 };
1945 /* - FSIB ------------------------------------------------------------------- */
1946 static const unsigned int fsib_mclk_in_pins[] = {
1947 /* CK */
1948 11,
1949 };
1950 static const unsigned int fsib_mclk_in_mux[] = {
1951 FSIBCK_MARK,
1952 };
1953 /* - GETHER ----------------------------------------------------------------- */
1954 static const unsigned int gether_rmii_pins[] = {
1955 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
1956 195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
1957 };
1958 static const unsigned int gether_rmii_mux[] = {
1959 RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
1960 RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
1961 RMII_MDC_MARK, RMII_MDIO_MARK,
1962 };
1963 static const unsigned int gether_mii_pins[] = {
1964 /* RXD[0:3], RX_CLK, RX_DV, RX_ER
1965 * TXD[0:3], TX_CLK, TX_EN, TX_ER
1966 * CRS, COL, MDC, MDIO,
1967 */
1968 185, 186, 187, 188, 174, 161, 204,
1969 171, 170, 169, 168, 184, 183, 203,
1970 205, 163, 206, 207,
1971 };
1972 static const unsigned int gether_mii_mux[] = {
1973 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1974 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1975 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1976 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1977 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1978 };
1979 static const unsigned int gether_gmii_pins[] = {
1980 /* RXD[0:7], RX_CLK, RX_DV, RX_ER
1981 * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
1982 * CRS, COL, MDC, MDIO, REF125CK_MARK,
1983 */
1984 185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
1985 171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
1986 205, 163, 206, 207,
1987 };
1988 static const unsigned int gether_gmii_mux[] = {
1989 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1990 ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
1991 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1992 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1993 ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
1994 ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1995 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1996 RMII_REF125CK_MARK,
1997 };
1998 static const unsigned int gether_int_pins[] = {
1999 /* PHY_INT */
2000 164,
2001 };
2002 static const unsigned int gether_int_mux[] = {
2003 ET_PHY_INT_MARK,
2004 };
2005 static const unsigned int gether_link_pins[] = {
2006 /* LINK */
2007 177,
2008 };
2009 static const unsigned int gether_link_mux[] = {
2010 ET_LINK_MARK,
2011 };
2012 static const unsigned int gether_wol_pins[] = {
2013 /* WOL */
2014 175,
2015 };
2016 static const unsigned int gether_wol_mux[] = {
2017 ET_WOL_MARK,
2018 };
2019 /* - HDMI ------------------------------------------------------------------- */
2020 static const unsigned int hdmi_pins[] = {
2021 /* HPD, CEC */
2022 210, 211,
2023 };
2024 static const unsigned int hdmi_mux[] = {
2025 HDMI_HPD_MARK, HDMI_CEC_MARK,
2026 };
2027 /* - INTC ------------------------------------------------------------------- */
2028 IRQC_PINS_MUX(0, 0, 2);
2029 IRQC_PINS_MUX(0, 1, 13);
2030 IRQC_PIN_MUX(1, 20);
2031 IRQC_PINS_MUX(2, 0, 11);
2032 IRQC_PINS_MUX(2, 1, 12);
2033 IRQC_PINS_MUX(3, 0, 10);
2034 IRQC_PINS_MUX(3, 1, 14);
2035 IRQC_PINS_MUX(4, 0, 15);
2036 IRQC_PINS_MUX(4, 1, 172);
2037 IRQC_PINS_MUX(5, 0, 0);
2038 IRQC_PINS_MUX(5, 1, 1);
2039 IRQC_PINS_MUX(6, 0, 121);
2040 IRQC_PINS_MUX(6, 1, 173);
2041 IRQC_PINS_MUX(7, 0, 120);
2042 IRQC_PINS_MUX(7, 1, 209);
2043 IRQC_PIN_MUX(8, 119);
2044 IRQC_PINS_MUX(9, 0, 118);
2045 IRQC_PINS_MUX(9, 1, 210);
2046 IRQC_PIN_MUX(10, 19);
2047 IRQC_PIN_MUX(11, 104);
2048 IRQC_PINS_MUX(12, 0, 42);
2049 IRQC_PINS_MUX(12, 1, 97);
2050 IRQC_PINS_MUX(13, 0, 64);
2051 IRQC_PINS_MUX(13, 1, 98);
2052 IRQC_PINS_MUX(14, 0, 63);
2053 IRQC_PINS_MUX(14, 1, 99);
2054 IRQC_PINS_MUX(15, 0, 62);
2055 IRQC_PINS_MUX(15, 1, 100);
2056 IRQC_PINS_MUX(16, 0, 68);
2057 IRQC_PINS_MUX(16, 1, 211);
2058 IRQC_PIN_MUX(17, 69);
2059 IRQC_PIN_MUX(18, 70);
2060 IRQC_PIN_MUX(19, 71);
2061 IRQC_PIN_MUX(20, 67);
2062 IRQC_PIN_MUX(21, 202);
2063 IRQC_PIN_MUX(22, 95);
2064 IRQC_PIN_MUX(23, 96);
2065 IRQC_PIN_MUX(24, 180);
2066 IRQC_PIN_MUX(25, 38);
2067 IRQC_PINS_MUX(26, 0, 58);
2068 IRQC_PINS_MUX(26, 1, 81);
2069 IRQC_PINS_MUX(27, 0, 57);
2070 IRQC_PINS_MUX(27, 1, 168);
2071 IRQC_PINS_MUX(28, 0, 56);
2072 IRQC_PINS_MUX(28, 1, 169);
2073 IRQC_PINS_MUX(29, 0, 50);
2074 IRQC_PINS_MUX(29, 1, 170);
2075 IRQC_PINS_MUX(30, 0, 49);
2076 IRQC_PINS_MUX(30, 1, 171);
2077 IRQC_PINS_MUX(31, 0, 41);
2078 IRQC_PINS_MUX(31, 1, 167);
2079
2080 /* - LCD0 ------------------------------------------------------------------- */
2081 static const unsigned int lcd0_data8_pins[] = {
2082 /* D[0:7] */
2083 58, 57, 56, 55, 54, 53, 52, 51,
2084 };
2085 static const unsigned int lcd0_data8_mux[] = {
2086 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2087 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2088 };
2089 static const unsigned int lcd0_data9_pins[] = {
2090 /* D[0:8] */
2091 58, 57, 56, 55, 54, 53, 52, 51,
2092 50,
2093 };
2094 static const unsigned int lcd0_data9_mux[] = {
2095 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2096 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2097 LCD0_D8_MARK,
2098 };
2099 static const unsigned int lcd0_data12_pins[] = {
2100 /* D[0:11] */
2101 58, 57, 56, 55, 54, 53, 52, 51,
2102 50, 49, 48, 47,
2103 };
2104 static const unsigned int lcd0_data12_mux[] = {
2105 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2106 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2107 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2108 };
2109 static const unsigned int lcd0_data16_pins[] = {
2110 /* D[0:15] */
2111 58, 57, 56, 55, 54, 53, 52, 51,
2112 50, 49, 48, 47, 46, 45, 44, 43,
2113 };
2114 static const unsigned int lcd0_data16_mux[] = {
2115 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2116 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2117 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2118 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2119 };
2120 static const unsigned int lcd0_data18_pins[] = {
2121 /* D[0:17] */
2122 58, 57, 56, 55, 54, 53, 52, 51,
2123 50, 49, 48, 47, 46, 45, 44, 43,
2124 42, 41,
2125 };
2126 static const unsigned int lcd0_data18_mux[] = {
2127 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2128 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2129 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2130 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2131 LCD0_D16_MARK, LCD0_D17_MARK,
2132 };
2133 static const unsigned int lcd0_data24_0_pins[] = {
2134 /* D[0:23] */
2135 58, 57, 56, 55, 54, 53, 52, 51,
2136 50, 49, 48, 47, 46, 45, 44, 43,
2137 42, 41, 40, 4, 3, 2, 0, 1,
2138 };
2139 static const unsigned int lcd0_data24_0_mux[] = {
2140 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2141 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2142 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2143 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2144 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
2145 LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
2146 LCD0_D23_PORT1_MARK,
2147 };
2148 static const unsigned int lcd0_data24_1_pins[] = {
2149 /* D[0:23] */
2150 58, 57, 56, 55, 54, 53, 52, 51,
2151 50, 49, 48, 47, 46, 45, 44, 43,
2152 42, 41, 163, 162, 161, 158, 160, 159,
2153 };
2154 static const unsigned int lcd0_data24_1_mux[] = {
2155 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2156 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2157 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2158 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
2159 LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
2160 LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
2161 };
2162 static const unsigned int lcd0_display_pins[] = {
2163 /* DON, VCPWC, VEPWC */
2164 61, 59, 60,
2165 };
2166 static const unsigned int lcd0_display_mux[] = {
2167 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
2168 };
2169 static const unsigned int lcd0_lclk_0_pins[] = {
2170 /* LCLK */
2171 102,
2172 };
2173 static const unsigned int lcd0_lclk_0_mux[] = {
2174 LCD0_LCLK_PORT102_MARK,
2175 };
2176 static const unsigned int lcd0_lclk_1_pins[] = {
2177 /* LCLK */
2178 165,
2179 };
2180 static const unsigned int lcd0_lclk_1_mux[] = {
2181 LCD0_LCLK_PORT165_MARK,
2182 };
2183 static const unsigned int lcd0_sync_pins[] = {
2184 /* VSYN, HSYN, DCK, DISP */
2185 63, 64, 62, 65,
2186 };
2187 static const unsigned int lcd0_sync_mux[] = {
2188 LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
2189 };
2190 static const unsigned int lcd0_sys_pins[] = {
2191 /* CS, WR, RD, RS */
2192 64, 62, 164, 65,
2193 };
2194 static const unsigned int lcd0_sys_mux[] = {
2195 LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
2196 };
2197 /* - LCD1 ------------------------------------------------------------------- */
2198 static const unsigned int lcd1_data8_pins[] = {
2199 /* D[0:7] */
2200 4, 3, 2, 1, 0, 91, 92, 23,
2201 };
2202 static const unsigned int lcd1_data8_mux[] = {
2203 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2204 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2205 };
2206 static const unsigned int lcd1_data9_pins[] = {
2207 /* D[0:8] */
2208 4, 3, 2, 1, 0, 91, 92, 23,
2209 93,
2210 };
2211 static const unsigned int lcd1_data9_mux[] = {
2212 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2213 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2214 LCD1_D8_MARK,
2215 };
2216 static const unsigned int lcd1_data12_pins[] = {
2217 /* D[0:11] */
2218 4, 3, 2, 1, 0, 91, 92, 23,
2219 93, 94, 21, 201,
2220 };
2221 static const unsigned int lcd1_data12_mux[] = {
2222 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2223 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2224 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2225 };
2226 static const unsigned int lcd1_data16_pins[] = {
2227 /* D[0:15] */
2228 4, 3, 2, 1, 0, 91, 92, 23,
2229 93, 94, 21, 201, 200, 199, 196, 195,
2230 };
2231 static const unsigned int lcd1_data16_mux[] = {
2232 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2233 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2234 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2235 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2236 };
2237 static const unsigned int lcd1_data18_pins[] = {
2238 /* D[0:17] */
2239 4, 3, 2, 1, 0, 91, 92, 23,
2240 93, 94, 21, 201, 200, 199, 196, 195,
2241 194, 193,
2242 };
2243 static const unsigned int lcd1_data18_mux[] = {
2244 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2245 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2246 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2247 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2248 LCD1_D16_MARK, LCD1_D17_MARK,
2249 };
2250 static const unsigned int lcd1_data24_pins[] = {
2251 /* D[0:23] */
2252 4, 3, 2, 1, 0, 91, 92, 23,
2253 93, 94, 21, 201, 200, 199, 196, 195,
2254 194, 193, 198, 197, 75, 74, 15, 14,
2255 };
2256 static const unsigned int lcd1_data24_mux[] = {
2257 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2258 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2259 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2260 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2261 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
2262 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
2263 };
2264 static const unsigned int lcd1_display_pins[] = {
2265 /* DON, VCPWC, VEPWC */
2266 100, 5, 6,
2267 };
2268 static const unsigned int lcd1_display_mux[] = {
2269 LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
2270 };
2271 static const unsigned int lcd1_lclk_pins[] = {
2272 /* LCLK */
2273 40,
2274 };
2275 static const unsigned int lcd1_lclk_mux[] = {
2276 LCD1_LCLK_MARK,
2277 };
2278 static const unsigned int lcd1_sync_pins[] = {
2279 /* VSYN, HSYN, DCK, DISP */
2280 98, 97, 99, 12,
2281 };
2282 static const unsigned int lcd1_sync_mux[] = {
2283 LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
2284 };
2285 static const unsigned int lcd1_sys_pins[] = {
2286 /* CS, WR, RD, RS */
2287 97, 99, 13, 12,
2288 };
2289 static const unsigned int lcd1_sys_mux[] = {
2290 LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
2291 };
2292 /* - MMCIF ------------------------------------------------------------------ */
2293 static const unsigned int mmc0_data1_0_pins[] = {
2294 /* D[0] */
2295 68,
2296 };
2297 static const unsigned int mmc0_data1_0_mux[] = {
2298 MMC0_D0_PORT68_MARK,
2299 };
2300 static const unsigned int mmc0_data4_0_pins[] = {
2301 /* D[0:3] */
2302 68, 69, 70, 71,
2303 };
2304 static const unsigned int mmc0_data4_0_mux[] = {
2305 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2306 };
2307 static const unsigned int mmc0_data8_0_pins[] = {
2308 /* D[0:7] */
2309 68, 69, 70, 71, 72, 73, 74, 75,
2310 };
2311 static const unsigned int mmc0_data8_0_mux[] = {
2312 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2313 MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
2314 };
2315 static const unsigned int mmc0_ctrl_0_pins[] = {
2316 /* CMD, CLK */
2317 67, 66,
2318 };
2319 static const unsigned int mmc0_ctrl_0_mux[] = {
2320 MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
2321 };
2322
2323 static const unsigned int mmc0_data1_1_pins[] = {
2324 /* D[0] */
2325 149,
2326 };
2327 static const unsigned int mmc0_data1_1_mux[] = {
2328 MMC1_D0_PORT149_MARK,
2329 };
2330 static const unsigned int mmc0_data4_1_pins[] = {
2331 /* D[0:3] */
2332 149, 148, 147, 146,
2333 };
2334 static const unsigned int mmc0_data4_1_mux[] = {
2335 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2336 };
2337 static const unsigned int mmc0_data8_1_pins[] = {
2338 /* D[0:7] */
2339 149, 148, 147, 146, 145, 144, 143, 142,
2340 };
2341 static const unsigned int mmc0_data8_1_mux[] = {
2342 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2343 MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
2344 };
2345 static const unsigned int mmc0_ctrl_1_pins[] = {
2346 /* CMD, CLK */
2347 104, 103,
2348 };
2349 static const unsigned int mmc0_ctrl_1_mux[] = {
2350 MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
2351 };
2352 /* - SCIFA0 ----------------------------------------------------------------- */
2353 static const unsigned int scifa0_data_pins[] = {
2354 /* RXD, TXD */
2355 197, 198,
2356 };
2357 static const unsigned int scifa0_data_mux[] = {
2358 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2359 };
2360 static const unsigned int scifa0_clk_pins[] = {
2361 /* SCK */
2362 188,
2363 };
2364 static const unsigned int scifa0_clk_mux[] = {
2365 SCIFA0_SCK_MARK,
2366 };
2367 static const unsigned int scifa0_ctrl_pins[] = {
2368 /* RTS, CTS */
2369 194, 193,
2370 };
2371 static const unsigned int scifa0_ctrl_mux[] = {
2372 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
2373 };
2374 /* - SCIFA1 ----------------------------------------------------------------- */
2375 static const unsigned int scifa1_data_pins[] = {
2376 /* RXD, TXD */
2377 195, 196,
2378 };
2379 static const unsigned int scifa1_data_mux[] = {
2380 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2381 };
2382 static const unsigned int scifa1_clk_pins[] = {
2383 /* SCK */
2384 185,
2385 };
2386 static const unsigned int scifa1_clk_mux[] = {
2387 SCIFA1_SCK_MARK,
2388 };
2389 static const unsigned int scifa1_ctrl_pins[] = {
2390 /* RTS, CTS */
2391 23, 21,
2392 };
2393 static const unsigned int scifa1_ctrl_mux[] = {
2394 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
2395 };
2396 /* - SCIFA2 ----------------------------------------------------------------- */
2397 static const unsigned int scifa2_data_pins[] = {
2398 /* RXD, TXD */
2399 200, 201,
2400 };
2401 static const unsigned int scifa2_data_mux[] = {
2402 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2403 };
2404 static const unsigned int scifa2_clk_0_pins[] = {
2405 /* SCK */
2406 22,
2407 };
2408 static const unsigned int scifa2_clk_0_mux[] = {
2409 SCIFA2_SCK_PORT22_MARK,
2410 };
2411 static const unsigned int scifa2_clk_1_pins[] = {
2412 /* SCK */
2413 199,
2414 };
2415 static const unsigned int scifa2_clk_1_mux[] = {
2416 SCIFA2_SCK_PORT199_MARK,
2417 };
2418 static const unsigned int scifa2_ctrl_pins[] = {
2419 /* RTS, CTS */
2420 96, 95,
2421 };
2422 static const unsigned int scifa2_ctrl_mux[] = {
2423 SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
2424 };
2425 /* - SCIFA3 ----------------------------------------------------------------- */
2426 static const unsigned int scifa3_data_0_pins[] = {
2427 /* RXD, TXD */
2428 174, 175,
2429 };
2430 static const unsigned int scifa3_data_0_mux[] = {
2431 SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
2432 };
2433 static const unsigned int scifa3_clk_0_pins[] = {
2434 /* SCK */
2435 116,
2436 };
2437 static const unsigned int scifa3_clk_0_mux[] = {
2438 SCIFA3_SCK_PORT116_MARK,
2439 };
2440 static const unsigned int scifa3_ctrl_0_pins[] = {
2441 /* RTS, CTS */
2442 105, 117,
2443 };
2444 static const unsigned int scifa3_ctrl_0_mux[] = {
2445 SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
2446 };
2447 static const unsigned int scifa3_data_1_pins[] = {
2448 /* RXD, TXD */
2449 159, 160,
2450 };
2451 static const unsigned int scifa3_data_1_mux[] = {
2452 SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
2453 };
2454 static const unsigned int scifa3_clk_1_pins[] = {
2455 /* SCK */
2456 158,
2457 };
2458 static const unsigned int scifa3_clk_1_mux[] = {
2459 SCIFA3_SCK_PORT158_MARK,
2460 };
2461 static const unsigned int scifa3_ctrl_1_pins[] = {
2462 /* RTS, CTS */
2463 161, 162,
2464 };
2465 static const unsigned int scifa3_ctrl_1_mux[] = {
2466 SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
2467 };
2468 /* - SCIFA4 ----------------------------------------------------------------- */
2469 static const unsigned int scifa4_data_0_pins[] = {
2470 /* RXD, TXD */
2471 12, 13,
2472 };
2473 static const unsigned int scifa4_data_0_mux[] = {
2474 SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
2475 };
2476 static const unsigned int scifa4_data_1_pins[] = {
2477 /* RXD, TXD */
2478 204, 203,
2479 };
2480 static const unsigned int scifa4_data_1_mux[] = {
2481 SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
2482 };
2483 static const unsigned int scifa4_data_2_pins[] = {
2484 /* RXD, TXD */
2485 94, 93,
2486 };
2487 static const unsigned int scifa4_data_2_mux[] = {
2488 SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
2489 };
2490 static const unsigned int scifa4_clk_0_pins[] = {
2491 /* SCK */
2492 21,
2493 };
2494 static const unsigned int scifa4_clk_0_mux[] = {
2495 SCIFA4_SCK_PORT21_MARK,
2496 };
2497 static const unsigned int scifa4_clk_1_pins[] = {
2498 /* SCK */
2499 205,
2500 };
2501 static const unsigned int scifa4_clk_1_mux[] = {
2502 SCIFA4_SCK_PORT205_MARK,
2503 };
2504 /* - SCIFA5 ----------------------------------------------------------------- */
2505 static const unsigned int scifa5_data_0_pins[] = {
2506 /* RXD, TXD */
2507 10, 20,
2508 };
2509 static const unsigned int scifa5_data_0_mux[] = {
2510 SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
2511 };
2512 static const unsigned int scifa5_data_1_pins[] = {
2513 /* RXD, TXD */
2514 207, 208,
2515 };
2516 static const unsigned int scifa5_data_1_mux[] = {
2517 SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
2518 };
2519 static const unsigned int scifa5_data_2_pins[] = {
2520 /* RXD, TXD */
2521 92, 91,
2522 };
2523 static const unsigned int scifa5_data_2_mux[] = {
2524 SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
2525 };
2526 static const unsigned int scifa5_clk_0_pins[] = {
2527 /* SCK */
2528 23,
2529 };
2530 static const unsigned int scifa5_clk_0_mux[] = {
2531 SCIFA5_SCK_PORT23_MARK,
2532 };
2533 static const unsigned int scifa5_clk_1_pins[] = {
2534 /* SCK */
2535 206,
2536 };
2537 static const unsigned int scifa5_clk_1_mux[] = {
2538 SCIFA5_SCK_PORT206_MARK,
2539 };
2540 /* - SCIFA6 ----------------------------------------------------------------- */
2541 static const unsigned int scifa6_data_pins[] = {
2542 /* RXD, TXD */
2543 25, 26,
2544 };
2545 static const unsigned int scifa6_data_mux[] = {
2546 SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
2547 };
2548 static const unsigned int scifa6_clk_pins[] = {
2549 /* SCK */
2550 24,
2551 };
2552 static const unsigned int scifa6_clk_mux[] = {
2553 SCIFA6_SCK_MARK,
2554 };
2555 /* - SCIFA7 ----------------------------------------------------------------- */
2556 static const unsigned int scifa7_data_pins[] = {
2557 /* RXD, TXD */
2558 0, 1,
2559 };
2560 static const unsigned int scifa7_data_mux[] = {
2561 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2562 };
2563 /* - SCIFB ------------------------------------------------------------------ */
2564 static const unsigned int scifb_data_0_pins[] = {
2565 /* RXD, TXD */
2566 191, 192,
2567 };
2568 static const unsigned int scifb_data_0_mux[] = {
2569 SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
2570 };
2571 static const unsigned int scifb_clk_0_pins[] = {
2572 /* SCK */
2573 190,
2574 };
2575 static const unsigned int scifb_clk_0_mux[] = {
2576 SCIFB_SCK_PORT190_MARK,
2577 };
2578 static const unsigned int scifb_ctrl_0_pins[] = {
2579 /* RTS, CTS */
2580 186, 187,
2581 };
2582 static const unsigned int scifb_ctrl_0_mux[] = {
2583 SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
2584 };
2585 static const unsigned int scifb_data_1_pins[] = {
2586 /* RXD, TXD */
2587 3, 4,
2588 };
2589 static const unsigned int scifb_data_1_mux[] = {
2590 SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
2591 };
2592 static const unsigned int scifb_clk_1_pins[] = {
2593 /* SCK */
2594 2,
2595 };
2596 static const unsigned int scifb_clk_1_mux[] = {
2597 SCIFB_SCK_PORT2_MARK,
2598 };
2599 static const unsigned int scifb_ctrl_1_pins[] = {
2600 /* RTS, CTS */
2601 172, 173,
2602 };
2603 static const unsigned int scifb_ctrl_1_mux[] = {
2604 SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
2605 };
2606 /* - SDHI0 ------------------------------------------------------------------ */
2607 static const unsigned int sdhi0_data1_pins[] = {
2608 /* D0 */
2609 77,
2610 };
2611 static const unsigned int sdhi0_data1_mux[] = {
2612 SDHI0_D0_MARK,
2613 };
2614 static const unsigned int sdhi0_data4_pins[] = {
2615 /* D[0:3] */
2616 77, 78, 79, 80,
2617 };
2618 static const unsigned int sdhi0_data4_mux[] = {
2619 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
2620 };
2621 static const unsigned int sdhi0_ctrl_pins[] = {
2622 /* CMD, CLK */
2623 76, 82,
2624 };
2625 static const unsigned int sdhi0_ctrl_mux[] = {
2626 SDHI0_CMD_MARK, SDHI0_CLK_MARK,
2627 };
2628 static const unsigned int sdhi0_cd_pins[] = {
2629 /* CD */
2630 81,
2631 };
2632 static const unsigned int sdhi0_cd_mux[] = {
2633 SDHI0_CD_MARK,
2634 };
2635 static const unsigned int sdhi0_wp_pins[] = {
2636 /* WP */
2637 83,
2638 };
2639 static const unsigned int sdhi0_wp_mux[] = {
2640 SDHI0_WP_MARK,
2641 };
2642 /* - SDHI1 ------------------------------------------------------------------ */
2643 static const unsigned int sdhi1_data1_pins[] = {
2644 /* D0 */
2645 68,
2646 };
2647 static const unsigned int sdhi1_data1_mux[] = {
2648 SDHI1_D0_MARK,
2649 };
2650 static const unsigned int sdhi1_data4_pins[] = {
2651 /* D[0:3] */
2652 68, 69, 70, 71,
2653 };
2654 static const unsigned int sdhi1_data4_mux[] = {
2655 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
2656 };
2657 static const unsigned int sdhi1_ctrl_pins[] = {
2658 /* CMD, CLK */
2659 67, 66,
2660 };
2661 static const unsigned int sdhi1_ctrl_mux[] = {
2662 SDHI1_CMD_MARK, SDHI1_CLK_MARK,
2663 };
2664 static const unsigned int sdhi1_cd_pins[] = {
2665 /* CD */
2666 72,
2667 };
2668 static const unsigned int sdhi1_cd_mux[] = {
2669 SDHI1_CD_MARK,
2670 };
2671 static const unsigned int sdhi1_wp_pins[] = {
2672 /* WP */
2673 73,
2674 };
2675 static const unsigned int sdhi1_wp_mux[] = {
2676 SDHI1_WP_MARK,
2677 };
2678 /* - SDHI2 ------------------------------------------------------------------ */
2679 static const unsigned int sdhi2_data1_pins[] = {
2680 /* D0 */
2681 205,
2682 };
2683 static const unsigned int sdhi2_data1_mux[] = {
2684 SDHI2_D0_MARK,
2685 };
2686 static const unsigned int sdhi2_data4_pins[] = {
2687 /* D[0:3] */
2688 205, 206, 207, 208,
2689 };
2690 static const unsigned int sdhi2_data4_mux[] = {
2691 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
2692 };
2693 static const unsigned int sdhi2_ctrl_pins[] = {
2694 /* CMD, CLK */
2695 204, 203,
2696 };
2697 static const unsigned int sdhi2_ctrl_mux[] = {
2698 SDHI2_CMD_MARK, SDHI2_CLK_MARK,
2699 };
2700 static const unsigned int sdhi2_cd_0_pins[] = {
2701 /* CD */
2702 202,
2703 };
2704 static const unsigned int sdhi2_cd_0_mux[] = {
2705 SDHI2_CD_PORT202_MARK,
2706 };
2707 static const unsigned int sdhi2_wp_0_pins[] = {
2708 /* WP */
2709 177,
2710 };
2711 static const unsigned int sdhi2_wp_0_mux[] = {
2712 SDHI2_WP_PORT177_MARK,
2713 };
2714 static const unsigned int sdhi2_cd_1_pins[] = {
2715 /* CD */
2716 24,
2717 };
2718 static const unsigned int sdhi2_cd_1_mux[] = {
2719 SDHI2_CD_PORT24_MARK,
2720 };
2721 static const unsigned int sdhi2_wp_1_pins[] = {
2722 /* WP */
2723 25,
2724 };
2725 static const unsigned int sdhi2_wp_1_mux[] = {
2726 SDHI2_WP_PORT25_MARK,
2727 };
2728 /* - TPU0 ------------------------------------------------------------------- */
2729 static const unsigned int tpu0_to0_pins[] = {
2730 /* TO */
2731 23,
2732 };
2733 static const unsigned int tpu0_to0_mux[] = {
2734 TPU0TO0_MARK,
2735 };
2736 static const unsigned int tpu0_to1_pins[] = {
2737 /* TO */
2738 21,
2739 };
2740 static const unsigned int tpu0_to1_mux[] = {
2741 TPU0TO1_MARK,
2742 };
2743 static const unsigned int tpu0_to2_0_pins[] = {
2744 /* TO */
2745 66,
2746 };
2747 static const unsigned int tpu0_to2_0_mux[] = {
2748 TPU0TO2_PORT66_MARK,
2749 };
2750 static const unsigned int tpu0_to2_1_pins[] = {
2751 /* TO */
2752 202,
2753 };
2754 static const unsigned int tpu0_to2_1_mux[] = {
2755 TPU0TO2_PORT202_MARK,
2756 };
2757 static const unsigned int tpu0_to3_pins[] = {
2758 /* TO */
2759 180,
2760 };
2761 static const unsigned int tpu0_to3_mux[] = {
2762 TPU0TO3_MARK,
2763 };
2764
2765 static const struct sh_pfc_pin_group pinmux_groups[] = {
2766 SH_PFC_PIN_GROUP(bsc_data8),
2767 SH_PFC_PIN_GROUP(bsc_data16),
2768 SH_PFC_PIN_GROUP(bsc_data32),
2769 SH_PFC_PIN_GROUP(bsc_cs0),
2770 SH_PFC_PIN_GROUP(bsc_cs2),
2771 SH_PFC_PIN_GROUP(bsc_cs4),
2772 SH_PFC_PIN_GROUP(bsc_cs5a_0),
2773 SH_PFC_PIN_GROUP(bsc_cs5a_1),
2774 SH_PFC_PIN_GROUP(bsc_cs5b),
2775 SH_PFC_PIN_GROUP(bsc_cs6a),
2776 SH_PFC_PIN_GROUP(bsc_rd_we8),
2777 SH_PFC_PIN_GROUP(bsc_rd_we16),
2778 SH_PFC_PIN_GROUP(bsc_rd_we32),
2779 SH_PFC_PIN_GROUP(bsc_bs),
2780 SH_PFC_PIN_GROUP(bsc_rdwr),
2781 SH_PFC_PIN_GROUP(ceu0_data_0_7),
2782 SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
2783 SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
2784 SH_PFC_PIN_GROUP(ceu0_clk_0),
2785 SH_PFC_PIN_GROUP(ceu0_clk_1),
2786 SH_PFC_PIN_GROUP(ceu0_clk_2),
2787 SH_PFC_PIN_GROUP(ceu0_sync),
2788 SH_PFC_PIN_GROUP(ceu0_field),
2789 SH_PFC_PIN_GROUP(ceu1_data),
2790 SH_PFC_PIN_GROUP(ceu1_clk),
2791 SH_PFC_PIN_GROUP(ceu1_sync),
2792 SH_PFC_PIN_GROUP(ceu1_field),
2793 SH_PFC_PIN_GROUP(fsia_mclk_in),
2794 SH_PFC_PIN_GROUP(fsia_mclk_out),
2795 SH_PFC_PIN_GROUP(fsia_sclk_in),
2796 SH_PFC_PIN_GROUP(fsia_sclk_out),
2797 SH_PFC_PIN_GROUP(fsia_data_in_0),
2798 SH_PFC_PIN_GROUP(fsia_data_in_1),
2799 SH_PFC_PIN_GROUP(fsia_data_out_0),
2800 SH_PFC_PIN_GROUP(fsia_data_out_1),
2801 SH_PFC_PIN_GROUP(fsia_data_out_2),
2802 SH_PFC_PIN_GROUP(fsia_spdif_0),
2803 SH_PFC_PIN_GROUP(fsia_spdif_1),
2804 SH_PFC_PIN_GROUP(fsib_mclk_in),
2805 SH_PFC_PIN_GROUP(gether_rmii),
2806 SH_PFC_PIN_GROUP(gether_mii),
2807 SH_PFC_PIN_GROUP(gether_gmii),
2808 SH_PFC_PIN_GROUP(gether_int),
2809 SH_PFC_PIN_GROUP(gether_link),
2810 SH_PFC_PIN_GROUP(gether_wol),
2811 SH_PFC_PIN_GROUP(hdmi),
2812 SH_PFC_PIN_GROUP(intc_irq0_0),
2813 SH_PFC_PIN_GROUP(intc_irq0_1),
2814 SH_PFC_PIN_GROUP(intc_irq1),
2815 SH_PFC_PIN_GROUP(intc_irq2_0),
2816 SH_PFC_PIN_GROUP(intc_irq2_1),
2817 SH_PFC_PIN_GROUP(intc_irq3_0),
2818 SH_PFC_PIN_GROUP(intc_irq3_1),
2819 SH_PFC_PIN_GROUP(intc_irq4_0),
2820 SH_PFC_PIN_GROUP(intc_irq4_1),
2821 SH_PFC_PIN_GROUP(intc_irq5_0),
2822 SH_PFC_PIN_GROUP(intc_irq5_1),
2823 SH_PFC_PIN_GROUP(intc_irq6_0),
2824 SH_PFC_PIN_GROUP(intc_irq6_1),
2825 SH_PFC_PIN_GROUP(intc_irq7_0),
2826 SH_PFC_PIN_GROUP(intc_irq7_1),
2827 SH_PFC_PIN_GROUP(intc_irq8),
2828 SH_PFC_PIN_GROUP(intc_irq9_0),
2829 SH_PFC_PIN_GROUP(intc_irq9_1),
2830 SH_PFC_PIN_GROUP(intc_irq10),
2831 SH_PFC_PIN_GROUP(intc_irq11),
2832 SH_PFC_PIN_GROUP(intc_irq12_0),
2833 SH_PFC_PIN_GROUP(intc_irq12_1),
2834 SH_PFC_PIN_GROUP(intc_irq13_0),
2835 SH_PFC_PIN_GROUP(intc_irq13_1),
2836 SH_PFC_PIN_GROUP(intc_irq14_0),
2837 SH_PFC_PIN_GROUP(intc_irq14_1),
2838 SH_PFC_PIN_GROUP(intc_irq15_0),
2839 SH_PFC_PIN_GROUP(intc_irq15_1),
2840 SH_PFC_PIN_GROUP(intc_irq16_0),
2841 SH_PFC_PIN_GROUP(intc_irq16_1),
2842 SH_PFC_PIN_GROUP(intc_irq17),
2843 SH_PFC_PIN_GROUP(intc_irq18),
2844 SH_PFC_PIN_GROUP(intc_irq19),
2845 SH_PFC_PIN_GROUP(intc_irq20),
2846 SH_PFC_PIN_GROUP(intc_irq21),
2847 SH_PFC_PIN_GROUP(intc_irq22),
2848 SH_PFC_PIN_GROUP(intc_irq23),
2849 SH_PFC_PIN_GROUP(intc_irq24),
2850 SH_PFC_PIN_GROUP(intc_irq25),
2851 SH_PFC_PIN_GROUP(intc_irq26_0),
2852 SH_PFC_PIN_GROUP(intc_irq26_1),
2853 SH_PFC_PIN_GROUP(intc_irq27_0),
2854 SH_PFC_PIN_GROUP(intc_irq27_1),
2855 SH_PFC_PIN_GROUP(intc_irq28_0),
2856 SH_PFC_PIN_GROUP(intc_irq28_1),
2857 SH_PFC_PIN_GROUP(intc_irq29_0),
2858 SH_PFC_PIN_GROUP(intc_irq29_1),
2859 SH_PFC_PIN_GROUP(intc_irq30_0),
2860 SH_PFC_PIN_GROUP(intc_irq30_1),
2861 SH_PFC_PIN_GROUP(intc_irq31_0),
2862 SH_PFC_PIN_GROUP(intc_irq31_1),
2863 SH_PFC_PIN_GROUP(lcd0_data8),
2864 SH_PFC_PIN_GROUP(lcd0_data9),
2865 SH_PFC_PIN_GROUP(lcd0_data12),
2866 SH_PFC_PIN_GROUP(lcd0_data16),
2867 SH_PFC_PIN_GROUP(lcd0_data18),
2868 SH_PFC_PIN_GROUP(lcd0_data24_0),
2869 SH_PFC_PIN_GROUP(lcd0_data24_1),
2870 SH_PFC_PIN_GROUP(lcd0_display),
2871 SH_PFC_PIN_GROUP(lcd0_lclk_0),
2872 SH_PFC_PIN_GROUP(lcd0_lclk_1),
2873 SH_PFC_PIN_GROUP(lcd0_sync),
2874 SH_PFC_PIN_GROUP(lcd0_sys),
2875 SH_PFC_PIN_GROUP(lcd1_data8),
2876 SH_PFC_PIN_GROUP(lcd1_data9),
2877 SH_PFC_PIN_GROUP(lcd1_data12),
2878 SH_PFC_PIN_GROUP(lcd1_data16),
2879 SH_PFC_PIN_GROUP(lcd1_data18),
2880 SH_PFC_PIN_GROUP(lcd1_data24),
2881 SH_PFC_PIN_GROUP(lcd1_display),
2882 SH_PFC_PIN_GROUP(lcd1_lclk),
2883 SH_PFC_PIN_GROUP(lcd1_sync),
2884 SH_PFC_PIN_GROUP(lcd1_sys),
2885 SH_PFC_PIN_GROUP(mmc0_data1_0),
2886 SH_PFC_PIN_GROUP(mmc0_data4_0),
2887 SH_PFC_PIN_GROUP(mmc0_data8_0),
2888 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2889 SH_PFC_PIN_GROUP(mmc0_data1_1),
2890 SH_PFC_PIN_GROUP(mmc0_data4_1),
2891 SH_PFC_PIN_GROUP(mmc0_data8_1),
2892 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2893 SH_PFC_PIN_GROUP(scifa0_data),
2894 SH_PFC_PIN_GROUP(scifa0_clk),
2895 SH_PFC_PIN_GROUP(scifa0_ctrl),
2896 SH_PFC_PIN_GROUP(scifa1_data),
2897 SH_PFC_PIN_GROUP(scifa1_clk),
2898 SH_PFC_PIN_GROUP(scifa1_ctrl),
2899 SH_PFC_PIN_GROUP(scifa2_data),
2900 SH_PFC_PIN_GROUP(scifa2_clk_0),
2901 SH_PFC_PIN_GROUP(scifa2_clk_1),
2902 SH_PFC_PIN_GROUP(scifa2_ctrl),
2903 SH_PFC_PIN_GROUP(scifa3_data_0),
2904 SH_PFC_PIN_GROUP(scifa3_clk_0),
2905 SH_PFC_PIN_GROUP(scifa3_ctrl_0),
2906 SH_PFC_PIN_GROUP(scifa3_data_1),
2907 SH_PFC_PIN_GROUP(scifa3_clk_1),
2908 SH_PFC_PIN_GROUP(scifa3_ctrl_1),
2909 SH_PFC_PIN_GROUP(scifa4_data_0),
2910 SH_PFC_PIN_GROUP(scifa4_data_1),
2911 SH_PFC_PIN_GROUP(scifa4_data_2),
2912 SH_PFC_PIN_GROUP(scifa4_clk_0),
2913 SH_PFC_PIN_GROUP(scifa4_clk_1),
2914 SH_PFC_PIN_GROUP(scifa5_data_0),
2915 SH_PFC_PIN_GROUP(scifa5_data_1),
2916 SH_PFC_PIN_GROUP(scifa5_data_2),
2917 SH_PFC_PIN_GROUP(scifa5_clk_0),
2918 SH_PFC_PIN_GROUP(scifa5_clk_1),
2919 SH_PFC_PIN_GROUP(scifa6_data),
2920 SH_PFC_PIN_GROUP(scifa6_clk),
2921 SH_PFC_PIN_GROUP(scifa7_data),
2922 SH_PFC_PIN_GROUP(scifb_data_0),
2923 SH_PFC_PIN_GROUP(scifb_clk_0),
2924 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2925 SH_PFC_PIN_GROUP(scifb_data_1),
2926 SH_PFC_PIN_GROUP(scifb_clk_1),
2927 SH_PFC_PIN_GROUP(scifb_ctrl_1),
2928 SH_PFC_PIN_GROUP(sdhi0_data1),
2929 SH_PFC_PIN_GROUP(sdhi0_data4),
2930 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2931 SH_PFC_PIN_GROUP(sdhi0_cd),
2932 SH_PFC_PIN_GROUP(sdhi0_wp),
2933 SH_PFC_PIN_GROUP(sdhi1_data1),
2934 SH_PFC_PIN_GROUP(sdhi1_data4),
2935 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2936 SH_PFC_PIN_GROUP(sdhi1_cd),
2937 SH_PFC_PIN_GROUP(sdhi1_wp),
2938 SH_PFC_PIN_GROUP(sdhi2_data1),
2939 SH_PFC_PIN_GROUP(sdhi2_data4),
2940 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2941 SH_PFC_PIN_GROUP(sdhi2_cd_0),
2942 SH_PFC_PIN_GROUP(sdhi2_wp_0),
2943 SH_PFC_PIN_GROUP(sdhi2_cd_1),
2944 SH_PFC_PIN_GROUP(sdhi2_wp_1),
2945 SH_PFC_PIN_GROUP(tpu0_to0),
2946 SH_PFC_PIN_GROUP(tpu0_to1),
2947 SH_PFC_PIN_GROUP(tpu0_to2_0),
2948 SH_PFC_PIN_GROUP(tpu0_to2_1),
2949 SH_PFC_PIN_GROUP(tpu0_to3),
2950 };
2951
2952 static const char * const bsc_groups[] = {
2953 "bsc_data8",
2954 "bsc_data16",
2955 "bsc_data32",
2956 "bsc_cs0",
2957 "bsc_cs2",
2958 "bsc_cs4",
2959 "bsc_cs5a_0",
2960 "bsc_cs5a_1",
2961 "bsc_cs5b",
2962 "bsc_cs6a",
2963 "bsc_rd_we8",
2964 "bsc_rd_we16",
2965 "bsc_rd_we32",
2966 "bsc_bs",
2967 "bsc_rdwr",
2968 };
2969
2970 static const char * const ceu0_groups[] = {
2971 "ceu0_data_0_7",
2972 "ceu0_data_8_15_0",
2973 "ceu0_data_8_15_1",
2974 "ceu0_clk_0",
2975 "ceu0_clk_1",
2976 "ceu0_clk_2",
2977 "ceu0_sync",
2978 "ceu0_field",
2979 };
2980
2981 static const char * const ceu1_groups[] = {
2982 "ceu1_data",
2983 "ceu1_clk",
2984 "ceu1_sync",
2985 "ceu1_field",
2986 };
2987
2988 static const char * const fsia_groups[] = {
2989 "fsia_mclk_in",
2990 "fsia_mclk_out",
2991 "fsia_sclk_in",
2992 "fsia_sclk_out",
2993 "fsia_data_in_0",
2994 "fsia_data_in_1",
2995 "fsia_data_out_0",
2996 "fsia_data_out_1",
2997 "fsia_data_out_2",
2998 "fsia_spdif_0",
2999 "fsia_spdif_1",
3000 };
3001
3002 static const char * const fsib_groups[] = {
3003 "fsib_mclk_in",
3004 };
3005
3006 static const char * const gether_groups[] = {
3007 "gether_rmii",
3008 "gether_mii",
3009 "gether_gmii",
3010 "gether_int",
3011 "gether_link",
3012 "gether_wol",
3013 };
3014
3015 static const char * const hdmi_groups[] = {
3016 "hdmi",
3017 };
3018
3019 static const char * const intc_groups[] = {
3020 "intc_irq0_0",
3021 "intc_irq0_1",
3022 "intc_irq1",
3023 "intc_irq2_0",
3024 "intc_irq2_1",
3025 "intc_irq3_0",
3026 "intc_irq3_1",
3027 "intc_irq4_0",
3028 "intc_irq4_1",
3029 "intc_irq5_0",
3030 "intc_irq5_1",
3031 "intc_irq6_0",
3032 "intc_irq6_1",
3033 "intc_irq7_0",
3034 "intc_irq7_1",
3035 "intc_irq8",
3036 "intc_irq9_0",
3037 "intc_irq9_1",
3038 "intc_irq10",
3039 "intc_irq11",
3040 "intc_irq12_0",
3041 "intc_irq12_1",
3042 "intc_irq13_0",
3043 "intc_irq13_1",
3044 "intc_irq14_0",
3045 "intc_irq14_1",
3046 "intc_irq15_0",
3047 "intc_irq15_1",
3048 "intc_irq16_0",
3049 "intc_irq16_1",
3050 "intc_irq17",
3051 "intc_irq18",
3052 "intc_irq19",
3053 "intc_irq20",
3054 "intc_irq21",
3055 "intc_irq22",
3056 "intc_irq23",
3057 "intc_irq24",
3058 "intc_irq25",
3059 "intc_irq26_0",
3060 "intc_irq26_1",
3061 "intc_irq27_0",
3062 "intc_irq27_1",
3063 "intc_irq28_0",
3064 "intc_irq28_1",
3065 "intc_irq29_0",
3066 "intc_irq29_1",
3067 "intc_irq30_0",
3068 "intc_irq30_1",
3069 "intc_irq31_0",
3070 "intc_irq31_1",
3071 };
3072
3073 static const char * const lcd0_groups[] = {
3074 "lcd0_data8",
3075 "lcd0_data9",
3076 "lcd0_data12",
3077 "lcd0_data16",
3078 "lcd0_data18",
3079 "lcd0_data24_0",
3080 "lcd0_data24_1",
3081 "lcd0_display",
3082 "lcd0_lclk_0",
3083 "lcd0_lclk_1",
3084 "lcd0_sync",
3085 "lcd0_sys",
3086 };
3087
3088 static const char * const lcd1_groups[] = {
3089 "lcd1_data8",
3090 "lcd1_data9",
3091 "lcd1_data12",
3092 "lcd1_data16",
3093 "lcd1_data18",
3094 "lcd1_data24",
3095 "lcd1_display",
3096 "lcd1_lclk",
3097 "lcd1_sync",
3098 "lcd1_sys",
3099 };
3100
3101 static const char * const mmc0_groups[] = {
3102 "mmc0_data1_0",
3103 "mmc0_data4_0",
3104 "mmc0_data8_0",
3105 "mmc0_ctrl_0",
3106 "mmc0_data1_1",
3107 "mmc0_data4_1",
3108 "mmc0_data8_1",
3109 "mmc0_ctrl_1",
3110 };
3111
3112 static const char * const scifa0_groups[] = {
3113 "scifa0_data",
3114 "scifa0_clk",
3115 "scifa0_ctrl",
3116 };
3117
3118 static const char * const scifa1_groups[] = {
3119 "scifa1_data",
3120 "scifa1_clk",
3121 "scifa1_ctrl",
3122 };
3123
3124 static const char * const scifa2_groups[] = {
3125 "scifa2_data",
3126 "scifa2_clk_0",
3127 "scifa2_clk_1",
3128 "scifa2_ctrl",
3129 };
3130
3131 static const char * const scifa3_groups[] = {
3132 "scifa3_data_0",
3133 "scifa3_clk_0",
3134 "scifa3_ctrl_0",
3135 "scifa3_data_1",
3136 "scifa3_clk_1",
3137 "scifa3_ctrl_1",
3138 };
3139
3140 static const char * const scifa4_groups[] = {
3141 "scifa4_data_0",
3142 "scifa4_data_1",
3143 "scifa4_data_2",
3144 "scifa4_clk_0",
3145 "scifa4_clk_1",
3146 };
3147
3148 static const char * const scifa5_groups[] = {
3149 "scifa5_data_0",
3150 "scifa5_data_1",
3151 "scifa5_data_2",
3152 "scifa5_clk_0",
3153 "scifa5_clk_1",
3154 };
3155
3156 static const char * const scifa6_groups[] = {
3157 "scifa6_data",
3158 "scifa6_clk",
3159 };
3160
3161 static const char * const scifa7_groups[] = {
3162 "scifa7_data",
3163 };
3164
3165 static const char * const scifb_groups[] = {
3166 "scifb_data_0",
3167 "scifb_clk_0",
3168 "scifb_ctrl_0",
3169 "scifb_data_1",
3170 "scifb_clk_1",
3171 "scifb_ctrl_1",
3172 };
3173
3174 static const char * const sdhi0_groups[] = {
3175 "sdhi0_data1",
3176 "sdhi0_data4",
3177 "sdhi0_ctrl",
3178 "sdhi0_cd",
3179 "sdhi0_wp",
3180 };
3181
3182 static const char * const sdhi1_groups[] = {
3183 "sdhi1_data1",
3184 "sdhi1_data4",
3185 "sdhi1_ctrl",
3186 "sdhi1_cd",
3187 "sdhi1_wp",
3188 };
3189
3190 static const char * const sdhi2_groups[] = {
3191 "sdhi2_data1",
3192 "sdhi2_data4",
3193 "sdhi2_ctrl",
3194 "sdhi2_cd_0",
3195 "sdhi2_wp_0",
3196 "sdhi2_cd_1",
3197 "sdhi2_wp_1",
3198 };
3199
3200 static const char * const tpu0_groups[] = {
3201 "tpu0_to0",
3202 "tpu0_to1",
3203 "tpu0_to2_0",
3204 "tpu0_to2_1",
3205 "tpu0_to3",
3206 };
3207
3208 static const struct sh_pfc_function pinmux_functions[] = {
3209 SH_PFC_FUNCTION(bsc),
3210 SH_PFC_FUNCTION(ceu0),
3211 SH_PFC_FUNCTION(ceu1),
3212 SH_PFC_FUNCTION(fsia),
3213 SH_PFC_FUNCTION(fsib),
3214 SH_PFC_FUNCTION(gether),
3215 SH_PFC_FUNCTION(hdmi),
3216 SH_PFC_FUNCTION(intc),
3217 SH_PFC_FUNCTION(lcd0),
3218 SH_PFC_FUNCTION(lcd1),
3219 SH_PFC_FUNCTION(mmc0),
3220 SH_PFC_FUNCTION(scifa0),
3221 SH_PFC_FUNCTION(scifa1),
3222 SH_PFC_FUNCTION(scifa2),
3223 SH_PFC_FUNCTION(scifa3),
3224 SH_PFC_FUNCTION(scifa4),
3225 SH_PFC_FUNCTION(scifa5),
3226 SH_PFC_FUNCTION(scifa6),
3227 SH_PFC_FUNCTION(scifa7),
3228 SH_PFC_FUNCTION(scifb),
3229 SH_PFC_FUNCTION(sdhi0),
3230 SH_PFC_FUNCTION(sdhi1),
3231 SH_PFC_FUNCTION(sdhi2),
3232 SH_PFC_FUNCTION(tpu0),
3233 };
3234
3235 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3236 PORTCR(0, 0xe6050000), /* PORT0CR */
3237 PORTCR(1, 0xe6050001), /* PORT1CR */
3238 PORTCR(2, 0xe6050002), /* PORT2CR */
3239 PORTCR(3, 0xe6050003), /* PORT3CR */
3240 PORTCR(4, 0xe6050004), /* PORT4CR */
3241 PORTCR(5, 0xe6050005), /* PORT5CR */
3242 PORTCR(6, 0xe6050006), /* PORT6CR */
3243 PORTCR(7, 0xe6050007), /* PORT7CR */
3244 PORTCR(8, 0xe6050008), /* PORT8CR */
3245 PORTCR(9, 0xe6050009), /* PORT9CR */
3246 PORTCR(10, 0xe605000a), /* PORT10CR */
3247 PORTCR(11, 0xe605000b), /* PORT11CR */
3248 PORTCR(12, 0xe605000c), /* PORT12CR */
3249 PORTCR(13, 0xe605000d), /* PORT13CR */
3250 PORTCR(14, 0xe605000e), /* PORT14CR */
3251 PORTCR(15, 0xe605000f), /* PORT15CR */
3252 PORTCR(16, 0xe6050010), /* PORT16CR */
3253 PORTCR(17, 0xe6050011), /* PORT17CR */
3254 PORTCR(18, 0xe6050012), /* PORT18CR */
3255 PORTCR(19, 0xe6050013), /* PORT19CR */
3256 PORTCR(20, 0xe6050014), /* PORT20CR */
3257 PORTCR(21, 0xe6050015), /* PORT21CR */
3258 PORTCR(22, 0xe6050016), /* PORT22CR */
3259 PORTCR(23, 0xe6050017), /* PORT23CR */
3260 PORTCR(24, 0xe6050018), /* PORT24CR */
3261 PORTCR(25, 0xe6050019), /* PORT25CR */
3262 PORTCR(26, 0xe605001a), /* PORT26CR */
3263 PORTCR(27, 0xe605001b), /* PORT27CR */
3264 PORTCR(28, 0xe605001c), /* PORT28CR */
3265 PORTCR(29, 0xe605001d), /* PORT29CR */
3266 PORTCR(30, 0xe605001e), /* PORT30CR */
3267 PORTCR(31, 0xe605001f), /* PORT31CR */
3268 PORTCR(32, 0xe6050020), /* PORT32CR */
3269 PORTCR(33, 0xe6050021), /* PORT33CR */
3270 PORTCR(34, 0xe6050022), /* PORT34CR */
3271 PORTCR(35, 0xe6050023), /* PORT35CR */
3272 PORTCR(36, 0xe6050024), /* PORT36CR */
3273 PORTCR(37, 0xe6050025), /* PORT37CR */
3274 PORTCR(38, 0xe6050026), /* PORT38CR */
3275 PORTCR(39, 0xe6050027), /* PORT39CR */
3276 PORTCR(40, 0xe6050028), /* PORT40CR */
3277 PORTCR(41, 0xe6050029), /* PORT41CR */
3278 PORTCR(42, 0xe605002a), /* PORT42CR */
3279 PORTCR(43, 0xe605002b), /* PORT43CR */
3280 PORTCR(44, 0xe605002c), /* PORT44CR */
3281 PORTCR(45, 0xe605002d), /* PORT45CR */
3282 PORTCR(46, 0xe605002e), /* PORT46CR */
3283 PORTCR(47, 0xe605002f), /* PORT47CR */
3284 PORTCR(48, 0xe6050030), /* PORT48CR */
3285 PORTCR(49, 0xe6050031), /* PORT49CR */
3286 PORTCR(50, 0xe6050032), /* PORT50CR */
3287 PORTCR(51, 0xe6050033), /* PORT51CR */
3288 PORTCR(52, 0xe6050034), /* PORT52CR */
3289 PORTCR(53, 0xe6050035), /* PORT53CR */
3290 PORTCR(54, 0xe6050036), /* PORT54CR */
3291 PORTCR(55, 0xe6050037), /* PORT55CR */
3292 PORTCR(56, 0xe6050038), /* PORT56CR */
3293 PORTCR(57, 0xe6050039), /* PORT57CR */
3294 PORTCR(58, 0xe605003a), /* PORT58CR */
3295 PORTCR(59, 0xe605003b), /* PORT59CR */
3296 PORTCR(60, 0xe605003c), /* PORT60CR */
3297 PORTCR(61, 0xe605003d), /* PORT61CR */
3298 PORTCR(62, 0xe605003e), /* PORT62CR */
3299 PORTCR(63, 0xe605003f), /* PORT63CR */
3300 PORTCR(64, 0xe6050040), /* PORT64CR */
3301 PORTCR(65, 0xe6050041), /* PORT65CR */
3302 PORTCR(66, 0xe6050042), /* PORT66CR */
3303 PORTCR(67, 0xe6050043), /* PORT67CR */
3304 PORTCR(68, 0xe6050044), /* PORT68CR */
3305 PORTCR(69, 0xe6050045), /* PORT69CR */
3306 PORTCR(70, 0xe6050046), /* PORT70CR */
3307 PORTCR(71, 0xe6050047), /* PORT71CR */
3308 PORTCR(72, 0xe6050048), /* PORT72CR */
3309 PORTCR(73, 0xe6050049), /* PORT73CR */
3310 PORTCR(74, 0xe605004a), /* PORT74CR */
3311 PORTCR(75, 0xe605004b), /* PORT75CR */
3312 PORTCR(76, 0xe605004c), /* PORT76CR */
3313 PORTCR(77, 0xe605004d), /* PORT77CR */
3314 PORTCR(78, 0xe605004e), /* PORT78CR */
3315 PORTCR(79, 0xe605004f), /* PORT79CR */
3316 PORTCR(80, 0xe6050050), /* PORT80CR */
3317 PORTCR(81, 0xe6050051), /* PORT81CR */
3318 PORTCR(82, 0xe6050052), /* PORT82CR */
3319 PORTCR(83, 0xe6050053), /* PORT83CR */
3320
3321 PORTCR(84, 0xe6051054), /* PORT84CR */
3322 PORTCR(85, 0xe6051055), /* PORT85CR */
3323 PORTCR(86, 0xe6051056), /* PORT86CR */
3324 PORTCR(87, 0xe6051057), /* PORT87CR */
3325 PORTCR(88, 0xe6051058), /* PORT88CR */
3326 PORTCR(89, 0xe6051059), /* PORT89CR */
3327 PORTCR(90, 0xe605105a), /* PORT90CR */
3328 PORTCR(91, 0xe605105b), /* PORT91CR */
3329 PORTCR(92, 0xe605105c), /* PORT92CR */
3330 PORTCR(93, 0xe605105d), /* PORT93CR */
3331 PORTCR(94, 0xe605105e), /* PORT94CR */
3332 PORTCR(95, 0xe605105f), /* PORT95CR */
3333 PORTCR(96, 0xe6051060), /* PORT96CR */
3334 PORTCR(97, 0xe6051061), /* PORT97CR */
3335 PORTCR(98, 0xe6051062), /* PORT98CR */
3336 PORTCR(99, 0xe6051063), /* PORT99CR */
3337 PORTCR(100, 0xe6051064), /* PORT100CR */
3338 PORTCR(101, 0xe6051065), /* PORT101CR */
3339 PORTCR(102, 0xe6051066), /* PORT102CR */
3340 PORTCR(103, 0xe6051067), /* PORT103CR */
3341 PORTCR(104, 0xe6051068), /* PORT104CR */
3342 PORTCR(105, 0xe6051069), /* PORT105CR */
3343 PORTCR(106, 0xe605106a), /* PORT106CR */
3344 PORTCR(107, 0xe605106b), /* PORT107CR */
3345 PORTCR(108, 0xe605106c), /* PORT108CR */
3346 PORTCR(109, 0xe605106d), /* PORT109CR */
3347 PORTCR(110, 0xe605106e), /* PORT110CR */
3348 PORTCR(111, 0xe605106f), /* PORT111CR */
3349 PORTCR(112, 0xe6051070), /* PORT112CR */
3350 PORTCR(113, 0xe6051071), /* PORT113CR */
3351 PORTCR(114, 0xe6051072), /* PORT114CR */
3352
3353 PORTCR(115, 0xe6052073), /* PORT115CR */
3354 PORTCR(116, 0xe6052074), /* PORT116CR */
3355 PORTCR(117, 0xe6052075), /* PORT117CR */
3356 PORTCR(118, 0xe6052076), /* PORT118CR */
3357 PORTCR(119, 0xe6052077), /* PORT119CR */
3358 PORTCR(120, 0xe6052078), /* PORT120CR */
3359 PORTCR(121, 0xe6052079), /* PORT121CR */
3360 PORTCR(122, 0xe605207a), /* PORT122CR */
3361 PORTCR(123, 0xe605207b), /* PORT123CR */
3362 PORTCR(124, 0xe605207c), /* PORT124CR */
3363 PORTCR(125, 0xe605207d), /* PORT125CR */
3364 PORTCR(126, 0xe605207e), /* PORT126CR */
3365 PORTCR(127, 0xe605207f), /* PORT127CR */
3366 PORTCR(128, 0xe6052080), /* PORT128CR */
3367 PORTCR(129, 0xe6052081), /* PORT129CR */
3368 PORTCR(130, 0xe6052082), /* PORT130CR */
3369 PORTCR(131, 0xe6052083), /* PORT131CR */
3370 PORTCR(132, 0xe6052084), /* PORT132CR */
3371 PORTCR(133, 0xe6052085), /* PORT133CR */
3372 PORTCR(134, 0xe6052086), /* PORT134CR */
3373 PORTCR(135, 0xe6052087), /* PORT135CR */
3374 PORTCR(136, 0xe6052088), /* PORT136CR */
3375 PORTCR(137, 0xe6052089), /* PORT137CR */
3376 PORTCR(138, 0xe605208a), /* PORT138CR */
3377 PORTCR(139, 0xe605208b), /* PORT139CR */
3378 PORTCR(140, 0xe605208c), /* PORT140CR */
3379 PORTCR(141, 0xe605208d), /* PORT141CR */
3380 PORTCR(142, 0xe605208e), /* PORT142CR */
3381 PORTCR(143, 0xe605208f), /* PORT143CR */
3382 PORTCR(144, 0xe6052090), /* PORT144CR */
3383 PORTCR(145, 0xe6052091), /* PORT145CR */
3384 PORTCR(146, 0xe6052092), /* PORT146CR */
3385 PORTCR(147, 0xe6052093), /* PORT147CR */
3386 PORTCR(148, 0xe6052094), /* PORT148CR */
3387 PORTCR(149, 0xe6052095), /* PORT149CR */
3388 PORTCR(150, 0xe6052096), /* PORT150CR */
3389 PORTCR(151, 0xe6052097), /* PORT151CR */
3390 PORTCR(152, 0xe6052098), /* PORT152CR */
3391 PORTCR(153, 0xe6052099), /* PORT153CR */
3392 PORTCR(154, 0xe605209a), /* PORT154CR */
3393 PORTCR(155, 0xe605209b), /* PORT155CR */
3394 PORTCR(156, 0xe605209c), /* PORT156CR */
3395 PORTCR(157, 0xe605209d), /* PORT157CR */
3396 PORTCR(158, 0xe605209e), /* PORT158CR */
3397 PORTCR(159, 0xe605209f), /* PORT159CR */
3398 PORTCR(160, 0xe60520a0), /* PORT160CR */
3399 PORTCR(161, 0xe60520a1), /* PORT161CR */
3400 PORTCR(162, 0xe60520a2), /* PORT162CR */
3401 PORTCR(163, 0xe60520a3), /* PORT163CR */
3402 PORTCR(164, 0xe60520a4), /* PORT164CR */
3403 PORTCR(165, 0xe60520a5), /* PORT165CR */
3404 PORTCR(166, 0xe60520a6), /* PORT166CR */
3405 PORTCR(167, 0xe60520a7), /* PORT167CR */
3406 PORTCR(168, 0xe60520a8), /* PORT168CR */
3407 PORTCR(169, 0xe60520a9), /* PORT169CR */
3408 PORTCR(170, 0xe60520aa), /* PORT170CR */
3409 PORTCR(171, 0xe60520ab), /* PORT171CR */
3410 PORTCR(172, 0xe60520ac), /* PORT172CR */
3411 PORTCR(173, 0xe60520ad), /* PORT173CR */
3412 PORTCR(174, 0xe60520ae), /* PORT174CR */
3413 PORTCR(175, 0xe60520af), /* PORT175CR */
3414 PORTCR(176, 0xe60520b0), /* PORT176CR */
3415 PORTCR(177, 0xe60520b1), /* PORT177CR */
3416 PORTCR(178, 0xe60520b2), /* PORT178CR */
3417 PORTCR(179, 0xe60520b3), /* PORT179CR */
3418 PORTCR(180, 0xe60520b4), /* PORT180CR */
3419 PORTCR(181, 0xe60520b5), /* PORT181CR */
3420 PORTCR(182, 0xe60520b6), /* PORT182CR */
3421 PORTCR(183, 0xe60520b7), /* PORT183CR */
3422 PORTCR(184, 0xe60520b8), /* PORT184CR */
3423 PORTCR(185, 0xe60520b9), /* PORT185CR */
3424 PORTCR(186, 0xe60520ba), /* PORT186CR */
3425 PORTCR(187, 0xe60520bb), /* PORT187CR */
3426 PORTCR(188, 0xe60520bc), /* PORT188CR */
3427 PORTCR(189, 0xe60520bd), /* PORT189CR */
3428 PORTCR(190, 0xe60520be), /* PORT190CR */
3429 PORTCR(191, 0xe60520bf), /* PORT191CR */
3430 PORTCR(192, 0xe60520c0), /* PORT192CR */
3431 PORTCR(193, 0xe60520c1), /* PORT193CR */
3432 PORTCR(194, 0xe60520c2), /* PORT194CR */
3433 PORTCR(195, 0xe60520c3), /* PORT195CR */
3434 PORTCR(196, 0xe60520c4), /* PORT196CR */
3435 PORTCR(197, 0xe60520c5), /* PORT197CR */
3436 PORTCR(198, 0xe60520c6), /* PORT198CR */
3437 PORTCR(199, 0xe60520c7), /* PORT199CR */
3438 PORTCR(200, 0xe60520c8), /* PORT200CR */
3439 PORTCR(201, 0xe60520c9), /* PORT201CR */
3440 PORTCR(202, 0xe60520ca), /* PORT202CR */
3441 PORTCR(203, 0xe60520cb), /* PORT203CR */
3442 PORTCR(204, 0xe60520cc), /* PORT204CR */
3443 PORTCR(205, 0xe60520cd), /* PORT205CR */
3444 PORTCR(206, 0xe60520ce), /* PORT206CR */
3445 PORTCR(207, 0xe60520cf), /* PORT207CR */
3446 PORTCR(208, 0xe60520d0), /* PORT208CR */
3447 PORTCR(209, 0xe60520d1), /* PORT209CR */
3448
3449 PORTCR(210, 0xe60530d2), /* PORT210CR */
3450 PORTCR(211, 0xe60530d3), /* PORT211CR */
3451
3452 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
3453 MSEL1CR_31_0, MSEL1CR_31_1,
3454 MSEL1CR_30_0, MSEL1CR_30_1,
3455 MSEL1CR_29_0, MSEL1CR_29_1,
3456 MSEL1CR_28_0, MSEL1CR_28_1,
3457 MSEL1CR_27_0, MSEL1CR_27_1,
3458 MSEL1CR_26_0, MSEL1CR_26_1,
3459 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3460 0, 0, 0, 0, 0, 0, 0, 0,
3461 MSEL1CR_16_0, MSEL1CR_16_1,
3462 MSEL1CR_15_0, MSEL1CR_15_1,
3463 MSEL1CR_14_0, MSEL1CR_14_1,
3464 MSEL1CR_13_0, MSEL1CR_13_1,
3465 MSEL1CR_12_0, MSEL1CR_12_1,
3466 0, 0, 0, 0,
3467 MSEL1CR_9_0, MSEL1CR_9_1,
3468 0, 0,
3469 MSEL1CR_7_0, MSEL1CR_7_1,
3470 MSEL1CR_6_0, MSEL1CR_6_1,
3471 MSEL1CR_5_0, MSEL1CR_5_1,
3472 MSEL1CR_4_0, MSEL1CR_4_1,
3473 MSEL1CR_3_0, MSEL1CR_3_1,
3474 MSEL1CR_2_0, MSEL1CR_2_1,
3475 0, 0,
3476 MSEL1CR_0_0, MSEL1CR_0_1,
3477 }
3478 },
3479 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
3480 0, 0, 0, 0, 0, 0, 0, 0,
3481 0, 0, 0, 0, 0, 0, 0, 0,
3482 0, 0, 0, 0, 0, 0, 0, 0,
3483 0, 0, 0, 0, 0, 0, 0, 0,
3484 MSEL3CR_15_0, MSEL3CR_15_1,
3485 0, 0, 0, 0, 0, 0, 0, 0,
3486 0, 0, 0, 0, 0, 0, 0, 0,
3487 MSEL3CR_6_0, MSEL3CR_6_1,
3488 0, 0, 0, 0, 0, 0, 0, 0,
3489 0, 0, 0, 0,
3490 }
3491 },
3492 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
3493 0, 0, 0, 0, 0, 0, 0, 0,
3494 0, 0, 0, 0, 0, 0, 0, 0,
3495 0, 0, 0, 0, 0, 0, 0, 0,
3496 MSEL4CR_19_0, MSEL4CR_19_1,
3497 MSEL4CR_18_0, MSEL4CR_18_1,
3498 0, 0, 0, 0,
3499 MSEL4CR_15_0, MSEL4CR_15_1,
3500 0, 0, 0, 0, 0, 0, 0, 0,
3501 MSEL4CR_10_0, MSEL4CR_10_1,
3502 0, 0, 0, 0, 0, 0,
3503 MSEL4CR_6_0, MSEL4CR_6_1,
3504 0, 0,
3505 MSEL4CR_4_0, MSEL4CR_4_1,
3506 0, 0, 0, 0,
3507 MSEL4CR_1_0, MSEL4CR_1_1,
3508 0, 0,
3509 }
3510 },
3511 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
3512 MSEL5CR_31_0, MSEL5CR_31_1,
3513 MSEL5CR_30_0, MSEL5CR_30_1,
3514 MSEL5CR_29_0, MSEL5CR_29_1,
3515 0, 0,
3516 MSEL5CR_27_0, MSEL5CR_27_1,
3517 0, 0,
3518 MSEL5CR_25_0, MSEL5CR_25_1,
3519 0, 0,
3520 MSEL5CR_23_0, MSEL5CR_23_1,
3521 0, 0,
3522 MSEL5CR_21_0, MSEL5CR_21_1,
3523 0, 0,
3524 MSEL5CR_19_0, MSEL5CR_19_1,
3525 0, 0,
3526 MSEL5CR_17_0, MSEL5CR_17_1,
3527 0, 0,
3528 MSEL5CR_15_0, MSEL5CR_15_1,
3529 MSEL5CR_14_0, MSEL5CR_14_1,
3530 MSEL5CR_13_0, MSEL5CR_13_1,
3531 MSEL5CR_12_0, MSEL5CR_12_1,
3532 MSEL5CR_11_0, MSEL5CR_11_1,
3533 MSEL5CR_10_0, MSEL5CR_10_1,
3534 0, 0,
3535 MSEL5CR_8_0, MSEL5CR_8_1,
3536 MSEL5CR_7_0, MSEL5CR_7_1,
3537 MSEL5CR_6_0, MSEL5CR_6_1,
3538 MSEL5CR_5_0, MSEL5CR_5_1,
3539 MSEL5CR_4_0, MSEL5CR_4_1,
3540 MSEL5CR_3_0, MSEL5CR_3_1,
3541 MSEL5CR_2_0, MSEL5CR_2_1,
3542 0, 0,
3543 MSEL5CR_0_0, MSEL5CR_0_1,
3544 }
3545 },
3546 { },
3547 };
3548
3549 static const struct pinmux_data_reg pinmux_data_regs[] = {
3550 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
3551 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3552 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3553 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3554 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3555 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3556 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3557 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3558 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
3559 },
3560 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
3561 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3562 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3563 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
3564 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
3565 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3566 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3567 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3568 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
3569 },
3570 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
3571 0, 0, 0, 0,
3572 0, 0, 0, 0,
3573 0, 0, 0, 0,
3574 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3575 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3576 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3577 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3578 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
3579 },
3580 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
3581 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3582 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3583 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
3584 0, 0, 0, 0,
3585 0, 0, 0, 0,
3586 0, 0, 0, 0,
3587 0, 0, 0, 0,
3588 0, 0, 0, 0 }
3589 },
3590 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
3591 0, 0, 0, 0,
3592 0, 0, 0, 0,
3593 0, 0, 0, 0,
3594 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3595 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3596 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3597 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3598 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
3599 },
3600 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
3601 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
3602 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
3603 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3604 PORT115_DATA, 0, 0, 0,
3605 0, 0, 0, 0,
3606 0, 0, 0, 0,
3607 0, 0, 0, 0,
3608 0, 0, 0, 0 }
3609 },
3610 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
3611 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
3612 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
3613 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
3614 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
3615 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
3616 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
3617 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3618 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
3619 },
3620 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
3621 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
3622 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
3623 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
3624 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
3625 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
3626 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
3627 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
3628 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
3629 },
3630 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
3631 0, 0, 0, 0,
3632 0, 0, 0, 0,
3633 0, 0, 0, 0,
3634 0, 0, PORT209_DATA, PORT208_DATA,
3635 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3636 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3637 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3638 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
3639 },
3640 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
3641 0, 0, 0, 0,
3642 0, 0, 0, 0,
3643 0, 0, 0, 0,
3644 PORT211_DATA, PORT210_DATA, 0, 0,
3645 0, 0, 0, 0,
3646 0, 0, 0, 0,
3647 0, 0, 0, 0,
3648 0, 0, 0, 0 }
3649 },
3650 { },
3651 };
3652
3653 static const struct pinmux_irq pinmux_irqs[] = {
3654 PINMUX_IRQ(2, 13), /* IRQ0A */
3655 PINMUX_IRQ(20), /* IRQ1A */
3656 PINMUX_IRQ(11, 12), /* IRQ2A */
3657 PINMUX_IRQ(10, 14), /* IRQ3A */
3658 PINMUX_IRQ(15, 172), /* IRQ4A */
3659 PINMUX_IRQ(0, 1), /* IRQ5A */
3660 PINMUX_IRQ(121, 173), /* IRQ6A */
3661 PINMUX_IRQ(120, 209), /* IRQ7A */
3662 PINMUX_IRQ(119), /* IRQ8A */
3663 PINMUX_IRQ(118, 210), /* IRQ9A */
3664 PINMUX_IRQ(19), /* IRQ10A */
3665 PINMUX_IRQ(104), /* IRQ11A */
3666 PINMUX_IRQ(42, 97), /* IRQ12A */
3667 PINMUX_IRQ(64, 98), /* IRQ13A */
3668 PINMUX_IRQ(63, 99), /* IRQ14A */
3669 PINMUX_IRQ(62, 100), /* IRQ15A */
3670 PINMUX_IRQ(68, 211), /* IRQ16A */
3671 PINMUX_IRQ(69), /* IRQ17A */
3672 PINMUX_IRQ(70), /* IRQ18A */
3673 PINMUX_IRQ(71), /* IRQ19A */
3674 PINMUX_IRQ(67), /* IRQ20A */
3675 PINMUX_IRQ(202), /* IRQ21A */
3676 PINMUX_IRQ(95), /* IRQ22A */
3677 PINMUX_IRQ(96), /* IRQ23A */
3678 PINMUX_IRQ(180), /* IRQ24A */
3679 PINMUX_IRQ(38), /* IRQ25A */
3680 PINMUX_IRQ(58, 81), /* IRQ26A */
3681 PINMUX_IRQ(57, 168), /* IRQ27A */
3682 PINMUX_IRQ(56, 169), /* IRQ28A */
3683 PINMUX_IRQ(50, 170), /* IRQ29A */
3684 PINMUX_IRQ(49, 171), /* IRQ30A */
3685 PINMUX_IRQ(41, 167), /* IRQ31A */
3686 };
3687
3688 #define PORTnCR_PULMD_OFF (0 << 6)
3689 #define PORTnCR_PULMD_DOWN (2 << 6)
3690 #define PORTnCR_PULMD_UP (3 << 6)
3691 #define PORTnCR_PULMD_MASK (3 << 6)
3692
3693 struct r8a7740_portcr_group {
3694 unsigned int end_pin;
3695 unsigned int offset;
3696 };
3697
3698 static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
3699 { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
3700 };
3701
3702 static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
3703 {
3704 unsigned int i;
3705
3706 for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
3707 const struct r8a7740_portcr_group *group =
3708 &r8a7740_portcr_offsets[i];
3709
3710 if (pin <= group->end_pin)
3711 return pfc->windows->virt + group->offset + pin;
3712 }
3713
3714 return NULL;
3715 }
3716
3717 static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3718 {
3719 void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3720 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3721
3722 switch (value) {
3723 case PORTnCR_PULMD_UP:
3724 return PIN_CONFIG_BIAS_PULL_UP;
3725 case PORTnCR_PULMD_DOWN:
3726 return PIN_CONFIG_BIAS_PULL_DOWN;
3727 case PORTnCR_PULMD_OFF:
3728 default:
3729 return PIN_CONFIG_BIAS_DISABLE;
3730 }
3731 }
3732
3733 static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3734 unsigned int bias)
3735 {
3736 void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3737 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3738
3739 switch (bias) {
3740 case PIN_CONFIG_BIAS_PULL_UP:
3741 value |= PORTnCR_PULMD_UP;
3742 break;
3743 case PIN_CONFIG_BIAS_PULL_DOWN:
3744 value |= PORTnCR_PULMD_DOWN;
3745 break;
3746 }
3747
3748 iowrite8(value, addr);
3749 }
3750
3751 static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
3752 .get_bias = r8a7740_pinmux_get_bias,
3753 .set_bias = r8a7740_pinmux_set_bias,
3754 };
3755
3756 const struct sh_pfc_soc_info r8a7740_pinmux_info = {
3757 .name = "r8a7740_pfc",
3758 .ops = &r8a7740_pfc_ops,
3759
3760 .input = { PINMUX_INPUT_BEGIN,
3761 PINMUX_INPUT_END },
3762 .output = { PINMUX_OUTPUT_BEGIN,
3763 PINMUX_OUTPUT_END },
3764 .function = { PINMUX_FUNCTION_BEGIN,
3765 PINMUX_FUNCTION_END },
3766
3767 .pins = pinmux_pins,
3768 .nr_pins = ARRAY_SIZE(pinmux_pins),
3769 .groups = pinmux_groups,
3770 .nr_groups = ARRAY_SIZE(pinmux_groups),
3771 .functions = pinmux_functions,
3772 .nr_functions = ARRAY_SIZE(pinmux_functions),
3773
3774 .cfg_regs = pinmux_config_regs,
3775 .data_regs = pinmux_data_regs,
3776
3777 .pinmux_data = pinmux_data,
3778 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3779
3780 .gpio_irq = pinmux_irqs,
3781 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
3782 };
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