1 // SPDX-License-Identifier: GPL-2.0
3 * R8A7790 processor support
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2013 Magnus Damm
7 * Copyright (C) 2012 Renesas Solutions Corp.
8 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
12 #include <linux/kernel.h>
13 #include <linux/sys_soc.h>
19 * All pins assigned to GPIO bank 3 can be used for SD interfaces in
20 * which case they support both 3.3V and 1.8V signalling.
22 #define CPU_ALL_PORT(fn, sfx) \
23 PORT_GP_32(0, fn, sfx), \
24 PORT_GP_30(1, fn, sfx), \
25 PORT_GP_30(2, fn, sfx), \
26 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_32(4, fn, sfx), \
28 PORT_GP_32(5, fn, sfx)
37 PINMUX_FUNCTION_BEGIN
,
41 FN_IP0_2_0
, FN_IP0_5_3
, FN_IP0_8_6
, FN_IP0_11_9
, FN_IP0_15_12
,
42 FN_IP0_19_16
, FN_IP0_22_20
, FN_IP0_26_23
, FN_IP0_30_27
,
43 FN_IP1_3_0
, FN_IP1_7_4
, FN_IP1_11_8
, FN_IP1_14_12
,
44 FN_IP1_17_15
, FN_IP1_21_18
, FN_IP1_25_22
, FN_IP1_27_26
,
45 FN_IP1_29_28
, FN_IP2_2_0
, FN_IP2_5_3
, FN_IP2_8_6
, FN_IP2_11_9
,
46 FN_IP2_14_12
, FN_IP2_17_15
, FN_IP2_21_18
, FN_IP2_25_22
,
47 FN_IP2_28_26
, FN_IP3_3_0
, FN_IP3_7_4
, FN_IP3_11_8
,
48 FN_IP3_14_12
, FN_IP3_17_15
,
51 FN_IP3_19_18
, FN_IP3_22_20
, FN_IP3_25_23
, FN_IP3_28_26
,
52 FN_IP3_31_29
, FN_IP4_2_0
, FN_IP4_5_3
, FN_IP4_8_6
, FN_IP4_11_9
,
53 FN_IP4_14_12
, FN_IP4_17_15
, FN_IP4_20_18
, FN_IP4_23_21
,
54 FN_IP4_26_24
, FN_IP4_29_27
, FN_IP5_2_0
, FN_IP5_5_3
, FN_IP5_9_6
,
55 FN_IP5_12_10
, FN_IP5_14_13
, FN_IP5_17_15
, FN_IP5_20_18
,
56 FN_IP5_23_21
, FN_IP5_26_24
, FN_IP5_29_27
, FN_IP6_2_0
,
57 FN_IP6_5_3
, FN_IP6_8_6
, FN_IP6_10_9
, FN_IP6_13_11
,
60 FN_IP7_28_27
, FN_IP7_30_29
, FN_IP8_1_0
, FN_IP8_3_2
, FN_IP8_5_4
,
61 FN_IP8_7_6
, FN_IP8_9_8
, FN_IP8_11_10
, FN_IP8_13_12
, FN_IP8_15_14
,
62 FN_IP8_17_16
, FN_IP8_19_18
, FN_IP8_21_20
, FN_IP8_23_22
,
63 FN_IP8_25_24
, FN_IP8_26
, FN_IP8_27
, FN_VI1_DATA7_VI1_B7
,
64 FN_IP6_16_14
, FN_IP6_19_17
, FN_IP6_22_20
, FN_IP6_25_23
,
65 FN_IP6_28_26
, FN_IP6_31_29
, FN_IP7_2_0
, FN_IP7_5_3
, FN_IP7_7_6
,
66 FN_IP7_9_8
, FN_IP7_12_10
, FN_IP7_15_13
,
69 FN_IP8_28
, FN_IP8_30_29
, FN_IP9_1_0
, FN_IP9_3_2
, FN_IP9_5_4
,
70 FN_IP9_7_6
, FN_IP9_11_8
, FN_IP9_15_12
, FN_IP9_17_16
, FN_IP9_19_18
,
71 FN_IP9_21_20
, FN_IP9_23_22
, FN_IP9_25_24
, FN_IP9_27_26
,
72 FN_IP9_31_28
, FN_IP10_3_0
, FN_IP10_6_4
, FN_IP10_10_7
, FN_IP10_14_11
,
73 FN_IP10_18_15
, FN_IP10_22_19
, FN_IP10_25_23
, FN_IP10_29_26
,
74 FN_IP11_3_0
, FN_IP11_4
, FN_IP11_6_5
, FN_IP11_8_7
, FN_IP11_10_9
,
75 FN_IP11_12_11
, FN_IP11_14_13
, FN_IP11_17_15
, FN_IP11_21_18
,
78 FN_IP11_23_22
, FN_IP11_26_24
, FN_IP11_29_27
, FN_IP11_31_30
,
79 FN_IP12_1_0
, FN_IP12_3_2
, FN_IP12_5_4
, FN_IP12_7_6
, FN_IP12_10_8
,
80 FN_IP12_13_11
, FN_IP12_16_14
, FN_IP12_19_17
, FN_IP12_22_20
,
81 FN_IP12_24_23
, FN_IP12_27_25
, FN_IP12_30_28
, FN_IP13_2_0
,
82 FN_IP13_6_3
, FN_IP13_9_7
, FN_IP13_12_10
, FN_IP13_15_13
,
83 FN_IP13_18_16
, FN_IP13_22_19
, FN_IP13_25_23
, FN_IP13_28_26
,
84 FN_IP13_30_29
, FN_IP14_2_0
, FN_IP14_5_3
, FN_IP14_8_6
, FN_IP14_11_9
,
85 FN_IP14_15_12
, FN_IP14_18_16
,
88 FN_IP14_21_19
, FN_IP14_24_22
, FN_IP14_27_25
, FN_IP14_30_28
,
89 FN_IP15_2_0
, FN_IP15_5_3
, FN_IP15_8_6
, FN_IP15_11_9
, FN_IP15_13_12
,
90 FN_IP15_15_14
, FN_IP15_17_16
, FN_IP15_19_18
, FN_IP15_22_20
,
91 FN_IP15_25_23
, FN_IP15_27_26
, FN_IP15_29_28
, FN_IP16_2_0
,
92 FN_IP16_5_3
, FN_USB0_PWEN
, FN_USB0_OVC_VBUS
, FN_IP16_6
, FN_IP16_7
,
93 FN_USB2_PWEN
, FN_USB2_OVC
, FN_AVS1
, FN_AVS2
, FN_DU_DOTCLKIN0
,
94 FN_IP7_26_25
, FN_DU_DOTCLKIN2
, FN_IP7_18_16
, FN_IP7_21_19
, FN_IP7_24_22
,
97 FN_D0
, FN_MSIOF3_SCK_B
, FN_VI3_DATA0
, FN_VI0_G4
, FN_VI0_G4_B
,
98 FN_D1
, FN_MSIOF3_SYNC_B
, FN_VI3_DATA1
, FN_VI0_G5
,
99 FN_VI0_G5_B
, FN_D2
, FN_MSIOF3_RXD_B
, FN_VI3_DATA2
,
100 FN_VI0_G6
, FN_VI0_G6_B
, FN_D3
, FN_MSIOF3_TXD_B
,
101 FN_VI3_DATA3
, FN_VI0_G7
, FN_VI0_G7_B
, FN_D4
,
102 FN_SCIFB1_RXD_F
, FN_SCIFB0_RXD_C
, FN_VI3_DATA4
,
103 FN_VI0_R0
, FN_VI0_R0_B
, FN_RX0_B
, FN_D5
,
104 FN_SCIFB1_TXD_F
, FN_SCIFB0_TXD_C
, FN_VI3_DATA5
,
105 FN_VI0_R1
, FN_VI0_R1_B
, FN_TX0_B
, FN_D6
,
106 FN_IIC2_SCL_C
, FN_VI3_DATA6
, FN_VI0_R2
, FN_VI0_R2_B
,
107 FN_I2C2_SCL_C
, FN_D7
, FN_AD_DI_B
, FN_IIC2_SDA_C
,
108 FN_VI3_DATA7
, FN_VI0_R3
, FN_VI0_R3_B
, FN_I2C2_SDA_C
, FN_TCLK1
,
109 FN_D8
, FN_SCIFA1_SCK_C
, FN_AVB_TXD0
,
110 FN_VI0_G0
, FN_VI0_G0_B
, FN_VI2_DATA0_VI2_B0
,
113 FN_D9
, FN_SCIFA1_RXD_C
, FN_AVB_TXD1
,
114 FN_VI0_G1
, FN_VI0_G1_B
, FN_VI2_DATA1_VI2_B1
, FN_D10
,
115 FN_SCIFA1_TXD_C
, FN_AVB_TXD2
,
116 FN_VI0_G2
, FN_VI0_G2_B
, FN_VI2_DATA2_VI2_B2
, FN_D11
,
117 FN_SCIFA1_CTS_N_C
, FN_AVB_TXD3
,
118 FN_VI0_G3
, FN_VI0_G3_B
, FN_VI2_DATA3_VI2_B3
,
119 FN_D12
, FN_SCIFA1_RTS_N_C
, FN_AVB_TXD4
,
120 FN_VI0_HSYNC_N
, FN_VI0_HSYNC_N_B
, FN_VI2_DATA4_VI2_B4
,
121 FN_D13
, FN_AVB_TXD5
, FN_VI0_VSYNC_N
,
122 FN_VI0_VSYNC_N_B
, FN_VI2_DATA5_VI2_B5
, FN_D14
,
123 FN_SCIFB1_RXD_C
, FN_AVB_TXD6
, FN_RX1_B
,
124 FN_VI0_CLKENB
, FN_VI0_CLKENB_B
, FN_VI2_DATA6_VI2_B6
,
125 FN_D15
, FN_SCIFB1_TXD_C
, FN_AVB_TXD7
, FN_TX1_B
,
126 FN_VI0_FIELD
, FN_VI0_FIELD_B
, FN_VI2_DATA7_VI2_B7
,
127 FN_A0
, FN_PWM3
, FN_A1
, FN_PWM4
,
130 FN_A2
, FN_PWM5
, FN_MSIOF1_SS1_B
, FN_A3
,
131 FN_PWM6
, FN_MSIOF1_SS2_B
, FN_A4
, FN_MSIOF1_TXD_B
,
132 FN_TPU0TO0
, FN_A5
, FN_SCIFA1_TXD_B
, FN_TPU0TO1
,
133 FN_A6
, FN_SCIFA1_RTS_N_B
, FN_TPU0TO2
, FN_A7
,
134 FN_SCIFA1_SCK_B
, FN_AUDIO_CLKOUT_B
, FN_TPU0TO3
,
135 FN_A8
, FN_SCIFA1_RXD_B
, FN_SSI_SCK5_B
, FN_VI0_R4
,
136 FN_VI0_R4_B
, FN_SCIFB2_RXD_C
, FN_RX2_B
, FN_VI2_DATA0_VI2_B0_B
,
137 FN_A9
, FN_SCIFA1_CTS_N_B
, FN_SSI_WS5_B
, FN_VI0_R5
,
138 FN_VI0_R5_B
, FN_SCIFB2_TXD_C
, FN_TX2_B
, FN_VI2_DATA1_VI2_B1_B
,
139 FN_A10
, FN_SSI_SDATA5_B
, FN_MSIOF2_SYNC
, FN_VI0_R6
,
140 FN_VI0_R6_B
, FN_VI2_DATA2_VI2_B2_B
,
143 FN_A11
, FN_SCIFB2_CTS_N_B
, FN_MSIOF2_SCK
, FN_VI1_R0
,
144 FN_VI1_R0_B
, FN_VI2_G0
, FN_VI2_DATA3_VI2_B3_B
,
145 FN_A12
, FN_SCIFB2_RXD_B
, FN_MSIOF2_TXD
, FN_VI1_R1
,
146 FN_VI1_R1_B
, FN_VI2_G1
, FN_VI2_DATA4_VI2_B4_B
,
147 FN_A13
, FN_SCIFB2_RTS_N_B
, FN_EX_WAIT2
,
148 FN_MSIOF2_RXD
, FN_VI1_R2
, FN_VI1_R2_B
, FN_VI2_G2
,
149 FN_VI2_DATA5_VI2_B5_B
, FN_A14
, FN_SCIFB2_TXD_B
,
150 FN_ATACS11_N
, FN_MSIOF2_SS1
, FN_A15
, FN_SCIFB2_SCK_B
,
151 FN_ATARD1_N
, FN_MSIOF2_SS2
, FN_A16
, FN_ATAWR1_N
,
152 FN_A17
, FN_AD_DO_B
, FN_ATADIR1_N
, FN_A18
,
153 FN_AD_CLK_B
, FN_ATAG1_N
, FN_A19
, FN_AD_NCS_N_B
,
154 FN_ATACS01_N
, FN_EX_WAIT0_B
, FN_A20
, FN_SPCLK
,
155 FN_VI1_R3
, FN_VI1_R3_B
, FN_VI2_G4
,
158 FN_A21
, FN_MOSI_IO0
, FN_VI1_R4
, FN_VI1_R4_B
, FN_VI2_G5
,
159 FN_A22
, FN_MISO_IO1
, FN_VI1_R5
, FN_VI1_R5_B
,
160 FN_VI2_G6
, FN_A23
, FN_IO2
, FN_VI1_G7
,
161 FN_VI1_G7_B
, FN_VI2_G7
, FN_A24
, FN_IO3
,
162 FN_VI1_R7
, FN_VI1_R7_B
, FN_VI2_CLKENB
,
163 FN_VI2_CLKENB_B
, FN_A25
, FN_SSL
, FN_VI1_G6
,
164 FN_VI1_G6_B
, FN_VI2_FIELD
, FN_VI2_FIELD_B
, FN_CS0_N
,
165 FN_VI1_R6
, FN_VI1_R6_B
, FN_VI2_G3
, FN_MSIOF0_SS2_B
,
166 FN_CS1_N_A26
, FN_SPEEDIN
, FN_VI0_R7
, FN_VI0_R7_B
,
167 FN_VI2_CLK
, FN_VI2_CLK_B
, FN_EX_CS0_N
, FN_HRX1_B
,
168 FN_VI1_G5
, FN_VI1_G5_B
, FN_VI2_R0
, FN_HTX0_B
,
169 FN_MSIOF0_SS1_B
, FN_EX_CS1_N
, FN_GPS_CLK
,
170 FN_HCTS1_N_B
, FN_VI1_FIELD
, FN_VI1_FIELD_B
,
171 FN_VI2_R1
, FN_EX_CS2_N
, FN_GPS_SIGN
, FN_HRTS1_N_B
,
172 FN_VI3_CLKENB
, FN_VI1_G0
, FN_VI1_G0_B
, FN_VI2_R2
,
175 FN_EX_CS3_N
, FN_GPS_MAG
, FN_VI3_FIELD
, FN_VI1_G1
, FN_VI1_G1_B
,
176 FN_VI2_R3
, FN_EX_CS4_N
, FN_MSIOF1_SCK_B
, FN_VI3_HSYNC_N
,
177 FN_VI2_HSYNC_N
, FN_IIC1_SCL
, FN_VI2_HSYNC_N_B
,
178 FN_INTC_EN0_N
, FN_I2C1_SCL
, FN_EX_CS5_N
, FN_CAN0_RX
,
179 FN_MSIOF1_RXD_B
, FN_VI3_VSYNC_N
, FN_VI1_G2
,
180 FN_VI1_G2_B
, FN_VI2_R4
, FN_IIC1_SDA
, FN_INTC_EN1_N
,
181 FN_I2C1_SDA
, FN_BS_N
, FN_IETX
, FN_HTX1_B
,
182 FN_CAN1_TX
, FN_DRACK0
, FN_IETX_C
, FN_RD_N
,
183 FN_CAN0_TX
, FN_SCIFA0_SCK_B
, FN_RD_WR_N
, FN_VI1_G3
,
184 FN_VI1_G3_B
, FN_VI2_R5
, FN_SCIFA0_RXD_B
,
185 FN_INTC_IRQ4_N
, FN_WE0_N
, FN_IECLK
, FN_CAN_CLK
,
186 FN_VI2_VSYNC_N
, FN_SCIFA0_TXD_B
, FN_VI2_VSYNC_N_B
,
187 FN_WE1_N
, FN_IERX
, FN_CAN1_RX
, FN_VI1_G4
,
188 FN_VI1_G4_B
, FN_VI2_R6
, FN_SCIFA0_CTS_N_B
,
189 FN_IERX_C
, FN_EX_WAIT0
, FN_IRQ3
, FN_INTC_IRQ3_N
,
190 FN_VI3_CLK
, FN_SCIFA0_RTS_N_B
, FN_HRX0_B
,
191 FN_MSIOF0_SCK_B
, FN_DREQ0_N
, FN_VI1_HSYNC_N
,
192 FN_VI1_HSYNC_N_B
, FN_VI2_R7
, FN_SSI_SCK78_C
,
196 FN_DACK0
, FN_IRQ0
, FN_INTC_IRQ0_N
, FN_SSI_SCK6_B
,
197 FN_VI1_VSYNC_N
, FN_VI1_VSYNC_N_B
, FN_SSI_WS78_C
,
198 FN_DREQ1_N
, FN_VI1_CLKENB
, FN_VI1_CLKENB_B
,
199 FN_SSI_SDATA7_C
, FN_SSI_SCK78_B
, FN_DACK1
, FN_IRQ1
,
200 FN_INTC_IRQ1_N
, FN_SSI_WS6_B
, FN_SSI_SDATA8_C
,
201 FN_DREQ2_N
, FN_HSCK1_B
, FN_HCTS0_N_B
,
202 FN_MSIOF0_TXD_B
, FN_DACK2
, FN_IRQ2
, FN_INTC_IRQ2_N
,
203 FN_SSI_SDATA6_B
, FN_HRTS0_N_B
, FN_MSIOF0_RXD_B
,
204 FN_ETH_CRS_DV
, FN_STP_ISCLK_0_B
,
205 FN_TS_SDEN0_D
, FN_GLO_Q0_C
, FN_IIC2_SCL_E
,
206 FN_I2C2_SCL_E
, FN_ETH_RX_ER
,
207 FN_STP_ISD_0_B
, FN_TS_SPSYNC0_D
, FN_GLO_Q1_C
,
208 FN_IIC2_SDA_E
, FN_I2C2_SDA_E
, FN_ETH_RXD0
,
209 FN_STP_ISEN_0_B
, FN_TS_SDAT0_D
, FN_GLO_I0_C
,
210 FN_SCIFB1_SCK_G
, FN_SCK1_E
, FN_ETH_RXD1
,
211 FN_HRX0_E
, FN_STP_ISSYNC_0_B
,
212 FN_TS_SCK0_D
, FN_GLO_I1_C
, FN_SCIFB1_RXD_G
,
213 FN_RX1_E
, FN_ETH_LINK
, FN_HTX0_E
,
214 FN_STP_IVCXO27_0_B
, FN_SCIFB1_TXD_G
, FN_TX1_E
,
215 FN_ETH_REF_CLK
, FN_HCTS0_N_E
,
216 FN_STP_IVCXO27_1_B
, FN_HRX0_F
,
219 FN_ETH_MDIO
, FN_HRTS0_N_E
,
220 FN_SIM0_D_C
, FN_HCTS0_N_F
, FN_ETH_TXD1
,
221 FN_HTX0_F
, FN_BPFCLK_G
,
222 FN_ETH_TX_EN
, FN_SIM0_CLK_C
,
223 FN_HRTS0_N_F
, FN_ETH_MAGIC
,
224 FN_SIM0_RST_C
, FN_ETH_TXD0
,
225 FN_STP_ISCLK_1_B
, FN_TS_SDEN1_C
, FN_GLO_SCLK_C
,
226 FN_ETH_MDC
, FN_STP_ISD_1_B
,
227 FN_TS_SPSYNC1_C
, FN_GLO_SDATA_C
, FN_PWM0
,
228 FN_SCIFA2_SCK_C
, FN_STP_ISEN_1_B
, FN_TS_SDAT1_C
,
229 FN_GLO_SS_C
, FN_PWM1
, FN_SCIFA2_TXD_C
,
230 FN_STP_ISSYNC_1_B
, FN_TS_SCK1_C
, FN_GLO_RFON_C
,
231 FN_PCMOE_N
, FN_PWM2
, FN_PWMFSW0
, FN_SCIFA2_RXD_C
,
232 FN_PCMWE_N
, FN_IECLK_C
, FN_DU_DOTCLKIN1
,
233 FN_AUDIO_CLKC
, FN_AUDIO_CLKOUT_C
, FN_VI0_CLK
,
234 FN_ATACS00_N
, FN_AVB_RXD1
,
235 FN_VI0_DATA0_VI0_B0
, FN_ATACS10_N
, FN_AVB_RXD2
,
238 FN_VI0_DATA1_VI0_B1
, FN_ATARD0_N
, FN_AVB_RXD3
,
239 FN_VI0_DATA2_VI0_B2
, FN_ATAWR0_N
,
240 FN_AVB_RXD4
, FN_VI0_DATA3_VI0_B3
, FN_ATADIR0_N
,
241 FN_AVB_RXD5
, FN_VI0_DATA4_VI0_B4
, FN_ATAG0_N
,
242 FN_AVB_RXD6
, FN_VI0_DATA5_VI0_B5
, FN_EX_WAIT1
,
243 FN_AVB_RXD7
, FN_VI0_DATA6_VI0_B6
, FN_AVB_RX_ER
,
244 FN_VI0_DATA7_VI0_B7
, FN_AVB_RX_CLK
,
245 FN_VI1_CLK
, FN_AVB_RX_DV
,
246 FN_VI1_DATA0_VI1_B0
, FN_SCIFA1_SCK_D
,
247 FN_AVB_CRS
, FN_VI1_DATA1_VI1_B1
,
248 FN_SCIFA1_RXD_D
, FN_AVB_MDC
,
249 FN_VI1_DATA2_VI1_B2
, FN_SCIFA1_TXD_D
, FN_AVB_MDIO
,
250 FN_VI1_DATA3_VI1_B3
, FN_SCIFA1_CTS_N_D
,
251 FN_AVB_GTX_CLK
, FN_VI1_DATA4_VI1_B4
, FN_SCIFA1_RTS_N_D
,
252 FN_AVB_MAGIC
, FN_VI1_DATA5_VI1_B5
,
253 FN_AVB_PHY_INT
, FN_VI1_DATA6_VI1_B6
, FN_AVB_GTXREFCLK
,
254 FN_SD0_CLK
, FN_VI1_DATA0_VI1_B0_B
, FN_SD0_CMD
,
255 FN_SCIFB1_SCK_B
, FN_VI1_DATA1_VI1_B1_B
,
258 FN_SD0_DAT0
, FN_SCIFB1_RXD_B
, FN_VI1_DATA2_VI1_B2_B
,
259 FN_SD0_DAT1
, FN_SCIFB1_TXD_B
, FN_VI1_DATA3_VI1_B3_B
,
260 FN_SD0_DAT2
, FN_SCIFB1_CTS_N_B
, FN_VI1_DATA4_VI1_B4_B
,
261 FN_SD0_DAT3
, FN_SCIFB1_RTS_N_B
, FN_VI1_DATA5_VI1_B5_B
,
262 FN_SD0_CD
, FN_MMC0_D6
, FN_TS_SDEN0_B
, FN_USB0_EXTP
,
263 FN_GLO_SCLK
, FN_VI1_DATA6_VI1_B6_B
, FN_IIC1_SCL_B
,
264 FN_I2C1_SCL_B
, FN_VI2_DATA6_VI2_B6_B
, FN_SD0_WP
,
265 FN_MMC0_D7
, FN_TS_SPSYNC0_B
, FN_USB0_IDIN
,
266 FN_GLO_SDATA
, FN_VI1_DATA7_VI1_B7_B
, FN_IIC1_SDA_B
,
267 FN_I2C1_SDA_B
, FN_VI2_DATA7_VI2_B7_B
, FN_SD1_CLK
,
268 FN_AVB_TX_EN
, FN_SD1_CMD
,
269 FN_AVB_TX_ER
, FN_SCIFB0_SCK_B
,
270 FN_SD1_DAT0
, FN_AVB_TX_CLK
,
271 FN_SCIFB0_RXD_B
, FN_SD1_DAT1
, FN_AVB_LINK
,
272 FN_SCIFB0_TXD_B
, FN_SD1_DAT2
,
273 FN_AVB_COL
, FN_SCIFB0_CTS_N_B
,
274 FN_SD1_DAT3
, FN_AVB_RXD0
,
275 FN_SCIFB0_RTS_N_B
, FN_SD1_CD
, FN_MMC1_D6
,
276 FN_TS_SDEN1
, FN_USB1_EXTP
, FN_GLO_SS
, FN_VI0_CLK_B
,
277 FN_IIC2_SCL_D
, FN_I2C2_SCL_D
, FN_SIM0_CLK_B
,
281 FN_SD1_WP
, FN_MMC1_D7
, FN_TS_SPSYNC1
, FN_USB1_IDIN
,
282 FN_GLO_RFON
, FN_VI1_CLK_B
, FN_IIC2_SDA_D
, FN_I2C2_SDA_D
,
283 FN_SIM0_D_B
, FN_SD2_CLK
, FN_MMC0_CLK
, FN_SIM0_CLK
,
284 FN_VI0_DATA0_VI0_B0_B
, FN_TS_SDEN0_C
, FN_GLO_SCLK_B
,
285 FN_VI3_DATA0_B
, FN_SD2_CMD
, FN_MMC0_CMD
, FN_SIM0_D
,
286 FN_VI0_DATA1_VI0_B1_B
, FN_SCIFB1_SCK_E
, FN_SCK1_D
,
287 FN_TS_SPSYNC0_C
, FN_GLO_SDATA_B
, FN_VI3_DATA1_B
,
288 FN_SD2_DAT0
, FN_MMC0_D0
, FN_FMCLK_B
,
289 FN_VI0_DATA2_VI0_B2_B
, FN_SCIFB1_RXD_E
, FN_RX1_D
,
290 FN_TS_SDAT0_C
, FN_GLO_SS_B
, FN_VI3_DATA2_B
,
291 FN_SD2_DAT1
, FN_MMC0_D1
, FN_FMIN_B
,
292 FN_VI0_DATA3_VI0_B3_B
, FN_SCIFB1_TXD_E
, FN_TX1_D
,
293 FN_TS_SCK0_C
, FN_GLO_RFON_B
, FN_VI3_DATA3_B
,
294 FN_SD2_DAT2
, FN_MMC0_D2
, FN_BPFCLK_B
,
295 FN_VI0_DATA4_VI0_B4_B
, FN_HRX0_D
, FN_TS_SDEN1_B
,
296 FN_GLO_Q0_B
, FN_VI3_DATA4_B
, FN_SD2_DAT3
,
297 FN_MMC0_D3
, FN_SIM0_RST
, FN_VI0_DATA5_VI0_B5_B
,
298 FN_HTX0_D
, FN_TS_SPSYNC1_B
, FN_GLO_Q1_B
,
299 FN_VI3_DATA5_B
, FN_SD2_CD
, FN_MMC0_D4
,
300 FN_TS_SDAT0_B
, FN_USB2_EXTP
, FN_GLO_I0
,
301 FN_VI0_DATA6_VI0_B6_B
, FN_HCTS0_N_D
, FN_TS_SDAT1_B
,
302 FN_GLO_I0_B
, FN_VI3_DATA6_B
,
305 FN_SD2_WP
, FN_MMC0_D5
, FN_TS_SCK0_B
, FN_USB2_IDIN
,
306 FN_GLO_I1
, FN_VI0_DATA7_VI0_B7_B
, FN_HRTS0_N_D
,
307 FN_TS_SCK1_B
, FN_GLO_I1_B
, FN_VI3_DATA7_B
,
308 FN_SD3_CLK
, FN_MMC1_CLK
, FN_SD3_CMD
, FN_MMC1_CMD
,
309 FN_MTS_N
, FN_SD3_DAT0
, FN_MMC1_D0
, FN_STM_N
,
310 FN_SD3_DAT1
, FN_MMC1_D1
, FN_MDATA
, FN_SD3_DAT2
,
311 FN_MMC1_D2
, FN_SDATA
, FN_SD3_DAT3
, FN_MMC1_D3
,
312 FN_SCKZ
, FN_SD3_CD
, FN_MMC1_D4
, FN_TS_SDAT1
,
313 FN_VSP
, FN_GLO_Q0
, FN_SIM0_RST_B
, FN_SD3_WP
,
314 FN_MMC1_D5
, FN_TS_SCK1
, FN_GLO_Q1
, FN_FMIN_C
,
315 FN_FMIN_E
, FN_FMIN_F
,
316 FN_MLB_CLK
, FN_IIC2_SCL_B
, FN_I2C2_SCL_B
,
317 FN_MLB_SIG
, FN_SCIFB1_RXD_D
, FN_RX1_C
, FN_IIC2_SDA_B
,
318 FN_I2C2_SDA_B
, FN_MLB_DAT
,
319 FN_SCIFB1_TXD_D
, FN_TX1_C
, FN_BPFCLK_C
,
320 FN_SSI_SCK0129
, FN_CAN_CLK_B
,
324 FN_SSI_WS0129
, FN_CAN0_TX_B
, FN_MOUT1
,
325 FN_SSI_SDATA0
, FN_CAN0_RX_B
, FN_MOUT2
,
326 FN_SSI_SDATA1
, FN_CAN1_TX_B
, FN_MOUT5
,
327 FN_SSI_SDATA2
, FN_CAN1_RX_B
, FN_SSI_SCK1
, FN_MOUT6
,
328 FN_SSI_SCK34
, FN_STP_OPWM_0
, FN_SCIFB0_SCK
,
329 FN_MSIOF1_SCK
, FN_CAN_DEBUG_HW_TRIGGER
, FN_SSI_WS34
,
330 FN_STP_IVCXO27_0
, FN_SCIFB0_RXD
, FN_MSIOF1_SYNC
,
331 FN_CAN_STEP0
, FN_SSI_SDATA3
, FN_STP_ISCLK_0
,
332 FN_SCIFB0_TXD
, FN_MSIOF1_SS1
, FN_CAN_TXCLK
,
333 FN_SSI_SCK4
, FN_STP_ISD_0
, FN_SCIFB0_CTS_N
,
334 FN_MSIOF1_SS2
, FN_SSI_SCK5_C
, FN_CAN_DEBUGOUT0
,
335 FN_SSI_WS4
, FN_STP_ISEN_0
, FN_SCIFB0_RTS_N
,
336 FN_MSIOF1_TXD
, FN_SSI_WS5_C
, FN_CAN_DEBUGOUT1
,
337 FN_SSI_SDATA4
, FN_STP_ISSYNC_0
, FN_MSIOF1_RXD
,
338 FN_CAN_DEBUGOUT2
, FN_SSI_SCK5
, FN_SCIFB1_SCK
,
339 FN_IERX_B
, FN_DU2_EXHSYNC_DU2_HSYNC
, FN_QSTH_QHS
,
340 FN_CAN_DEBUGOUT3
, FN_SSI_WS5
, FN_SCIFB1_RXD
,
341 FN_IECLK_B
, FN_DU2_EXVSYNC_DU2_VSYNC
, FN_QSTB_QHE
,
345 FN_SSI_SDATA5
, FN_SCIFB1_TXD
, FN_IETX_B
, FN_DU2_DR2
,
346 FN_LCDOUT2
, FN_CAN_DEBUGOUT5
, FN_SSI_SCK6
,
347 FN_SCIFB1_CTS_N
, FN_BPFCLK_D
,
348 FN_DU2_DR3
, FN_LCDOUT3
, FN_CAN_DEBUGOUT6
,
349 FN_BPFCLK_F
, FN_SSI_WS6
,
350 FN_SCIFB1_RTS_N
, FN_CAN0_TX_D
, FN_DU2_DR4
,
351 FN_LCDOUT4
, FN_CAN_DEBUGOUT7
, FN_SSI_SDATA6
,
352 FN_FMIN_D
, FN_DU2_DR5
, FN_LCDOUT5
,
353 FN_CAN_DEBUGOUT8
, FN_SSI_SCK78
, FN_STP_IVCXO27_1
,
354 FN_SCK1
, FN_SCIFA1_SCK
, FN_DU2_DR6
, FN_LCDOUT6
,
355 FN_CAN_DEBUGOUT9
, FN_SSI_WS78
, FN_STP_ISCLK_1
,
356 FN_SCIFB2_SCK
, FN_SCIFA2_CTS_N
, FN_DU2_DR7
,
357 FN_LCDOUT7
, FN_CAN_DEBUGOUT10
, FN_SSI_SDATA7
,
358 FN_STP_ISD_1
, FN_SCIFB2_RXD
, FN_SCIFA2_RTS_N
,
359 FN_TCLK2
, FN_QSTVA_QVS
, FN_CAN_DEBUGOUT11
,
360 FN_BPFCLK_E
, FN_SSI_SDATA7_B
,
361 FN_FMIN_G
, FN_SSI_SDATA8
,
362 FN_STP_ISEN_1
, FN_SCIFB2_TXD
, FN_CAN0_TX_C
,
363 FN_CAN_DEBUGOUT12
, FN_SSI_SDATA8_B
, FN_SSI_SDATA9
,
364 FN_STP_ISSYNC_1
, FN_SCIFB2_CTS_N
, FN_SSI_WS1
,
365 FN_SSI_SDATA5_C
, FN_CAN_DEBUGOUT13
, FN_AUDIO_CLKA
,
366 FN_SCIFB2_RTS_N
, FN_CAN_DEBUGOUT14
,
369 FN_AUDIO_CLKB
, FN_SCIF_CLK
, FN_CAN0_RX_D
,
370 FN_DVC_MUTE
, FN_CAN0_RX_C
, FN_CAN_DEBUGOUT15
,
371 FN_REMOCON
, FN_SCIFA0_SCK
, FN_HSCK1
, FN_SCK0
,
372 FN_MSIOF3_SS2
, FN_DU2_DG2
, FN_LCDOUT10
, FN_IIC1_SDA_C
,
373 FN_I2C1_SDA_C
, FN_SCIFA0_RXD
, FN_HRX1
, FN_RX0
,
374 FN_DU2_DR0
, FN_LCDOUT0
, FN_SCIFA0_TXD
, FN_HTX1
,
375 FN_TX0
, FN_DU2_DR1
, FN_LCDOUT1
, FN_SCIFA0_CTS_N
,
376 FN_HCTS1_N
, FN_CTS0_N
, FN_MSIOF3_SYNC
, FN_DU2_DG3
,
377 FN_LCDOUT11
, FN_PWM0_B
, FN_IIC1_SCL_C
, FN_I2C1_SCL_C
,
378 FN_SCIFA0_RTS_N
, FN_HRTS1_N
, FN_RTS0_N
,
379 FN_MSIOF3_SS1
, FN_DU2_DG0
, FN_LCDOUT8
, FN_PWM1_B
,
380 FN_SCIFA1_RXD
, FN_AD_DI
, FN_RX1
,
381 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE
, FN_QCPV_QDE
,
382 FN_SCIFA1_TXD
, FN_AD_DO
, FN_TX1
, FN_DU2_DG1
,
383 FN_LCDOUT9
, FN_SCIFA1_CTS_N
, FN_AD_CLK
,
384 FN_CTS1_N
, FN_MSIOF3_RXD
, FN_DU0_DOTCLKOUT
, FN_QCLK
,
385 FN_SCIFA1_RTS_N
, FN_AD_NCS_N
, FN_RTS1_N
,
386 FN_MSIOF3_TXD
, FN_DU1_DOTCLKOUT
, FN_QSTVB_QVE
,
390 FN_SCIFA2_SCK
, FN_FMCLK
, FN_SCK2
, FN_MSIOF3_SCK
, FN_DU2_DG7
,
391 FN_LCDOUT15
, FN_SCIF_CLK_B
, FN_SCIFA2_RXD
, FN_FMIN
,
392 FN_TX2
, FN_DU2_DB0
, FN_LCDOUT16
, FN_IIC2_SCL
, FN_I2C2_SCL
,
393 FN_SCIFA2_TXD
, FN_BPFCLK
, FN_RX2
, FN_DU2_DB1
, FN_LCDOUT17
,
394 FN_IIC2_SDA
, FN_I2C2_SDA
, FN_HSCK0
, FN_TS_SDEN0
,
395 FN_DU2_DG4
, FN_LCDOUT12
, FN_HCTS0_N_C
, FN_HRX0
,
396 FN_DU2_DB2
, FN_LCDOUT18
, FN_HTX0
, FN_DU2_DB3
,
397 FN_LCDOUT19
, FN_HCTS0_N
, FN_SSI_SCK9
, FN_DU2_DB4
,
398 FN_LCDOUT20
, FN_HRTS0_N
, FN_SSI_WS9
, FN_DU2_DB5
,
399 FN_LCDOUT21
, FN_MSIOF0_SCK
, FN_TS_SDAT0
, FN_ADICLK
,
400 FN_DU2_DB6
, FN_LCDOUT22
, FN_MSIOF0_SYNC
, FN_TS_SCK0
,
401 FN_SSI_SCK2
, FN_ADIDATA
, FN_DU2_DB7
, FN_LCDOUT23
,
402 FN_HRX0_C
, FN_MSIOF0_SS1
, FN_ADICHS0
,
403 FN_DU2_DG5
, FN_LCDOUT13
, FN_MSIOF0_TXD
, FN_ADICHS1
,
404 FN_DU2_DG6
, FN_LCDOUT14
,
407 FN_MSIOF0_SS2
, FN_AUDIO_CLKOUT
, FN_ADICHS2
,
408 FN_DU2_DISP
, FN_QPOLA
, FN_HTX0_C
, FN_SCIFA2_TXD_B
,
409 FN_MSIOF0_RXD
, FN_TS_SPSYNC0
, FN_SSI_WS2
,
410 FN_ADICS_SAMP
, FN_DU2_CDE
, FN_QPOLB
, FN_SCIFA2_RXD_B
,
411 FN_USB1_PWEN
, FN_AUDIO_CLKOUT_D
, FN_USB1_OVC
,
414 FN_SEL_SCIF1_0
, FN_SEL_SCIF1_1
, FN_SEL_SCIF1_2
, FN_SEL_SCIF1_3
,
416 FN_SEL_SCIFB_0
, FN_SEL_SCIFB_1
, FN_SEL_SCIFB_2
,
417 FN_SEL_SCIFB2_0
, FN_SEL_SCIFB2_1
, FN_SEL_SCIFB2_2
,
418 FN_SEL_SCIFB1_0
, FN_SEL_SCIFB1_1
, FN_SEL_SCIFB1_2
, FN_SEL_SCIFB1_3
,
420 FN_SEL_SCIFB1_5
, FN_SEL_SCIFB1_6
,
421 FN_SEL_SCIFA1_0
, FN_SEL_SCIFA1_1
, FN_SEL_SCIFA1_2
, FN_SEL_SCIFA1_3
,
422 FN_SEL_SCIF0_0
, FN_SEL_SCIF0_1
,
423 FN_SEL_SCFA_0
, FN_SEL_SCFA_1
,
424 FN_SEL_SOF1_0
, FN_SEL_SOF1_1
,
425 FN_SEL_SSI7_0
, FN_SEL_SSI7_1
, FN_SEL_SSI7_2
,
426 FN_SEL_SSI6_0
, FN_SEL_SSI6_1
,
427 FN_SEL_SSI5_0
, FN_SEL_SSI5_1
, FN_SEL_SSI5_2
,
428 FN_SEL_VI3_0
, FN_SEL_VI3_1
,
429 FN_SEL_VI2_0
, FN_SEL_VI2_1
,
430 FN_SEL_VI1_0
, FN_SEL_VI1_1
,
431 FN_SEL_VI0_0
, FN_SEL_VI0_1
,
432 FN_SEL_TSIF1_0
, FN_SEL_TSIF1_1
, FN_SEL_TSIF1_2
,
433 FN_SEL_LBS_0
, FN_SEL_LBS_1
,
434 FN_SEL_TSIF0_0
, FN_SEL_TSIF0_1
, FN_SEL_TSIF0_2
, FN_SEL_TSIF0_3
,
435 FN_SEL_SOF3_0
, FN_SEL_SOF3_1
,
436 FN_SEL_SOF0_0
, FN_SEL_SOF0_1
,
438 FN_SEL_TMU1_0
, FN_SEL_TMU1_1
,
439 FN_SEL_HSCIF1_0
, FN_SEL_HSCIF1_1
,
440 FN_SEL_SCIFCLK_0
, FN_SEL_SCIFCLK_1
,
441 FN_SEL_CAN0_0
, FN_SEL_CAN0_1
, FN_SEL_CAN0_2
, FN_SEL_CAN0_3
,
442 FN_SEL_CANCLK_0
, FN_SEL_CANCLK_1
,
443 FN_SEL_SCIFA2_0
, FN_SEL_SCIFA2_1
, FN_SEL_SCIFA2_2
,
444 FN_SEL_CAN1_0
, FN_SEL_CAN1_1
,
445 FN_SEL_SCIF2_0
, FN_SEL_SCIF2_1
,
446 FN_SEL_ADI_0
, FN_SEL_ADI_1
,
447 FN_SEL_SSP_0
, FN_SEL_SSP_1
,
448 FN_SEL_FM_0
, FN_SEL_FM_1
, FN_SEL_FM_2
, FN_SEL_FM_3
,
449 FN_SEL_FM_4
, FN_SEL_FM_5
, FN_SEL_FM_6
,
450 FN_SEL_HSCIF0_0
, FN_SEL_HSCIF0_1
, FN_SEL_HSCIF0_2
, FN_SEL_HSCIF0_3
,
451 FN_SEL_HSCIF0_4
, FN_SEL_HSCIF0_5
,
452 FN_SEL_GPS_0
, FN_SEL_GPS_1
, FN_SEL_GPS_2
,
453 FN_SEL_SIM_0
, FN_SEL_SIM_1
, FN_SEL_SIM_2
,
454 FN_SEL_SSI8_0
, FN_SEL_SSI8_1
, FN_SEL_SSI8_2
,
456 FN_SEL_IICDVFS_0
, FN_SEL_IICDVFS_1
,
457 FN_SEL_IIC0_0
, FN_SEL_IIC0_1
,
458 FN_SEL_IEB_0
, FN_SEL_IEB_1
, FN_SEL_IEB_2
,
459 FN_SEL_IIC2_0
, FN_SEL_IIC2_1
, FN_SEL_IIC2_2
, FN_SEL_IIC2_3
,
461 FN_SEL_IIC1_0
, FN_SEL_IIC1_1
, FN_SEL_IIC1_2
,
462 FN_SEL_I2C2_0
, FN_SEL_I2C2_1
, FN_SEL_I2C2_2
, FN_SEL_I2C2_3
,
464 FN_SEL_I2C1_0
, FN_SEL_I2C1_1
, FN_SEL_I2C1_2
,
469 VI1_DATA7_VI1_B7_MARK
,
471 USB0_PWEN_MARK
, USB0_OVC_VBUS_MARK
,
472 USB2_PWEN_MARK
, USB2_OVC_MARK
, AVS1_MARK
, AVS2_MARK
,
473 DU_DOTCLKIN0_MARK
, DU_DOTCLKIN2_MARK
,
475 D0_MARK
, MSIOF3_SCK_B_MARK
, VI3_DATA0_MARK
, VI0_G4_MARK
, VI0_G4_B_MARK
,
476 D1_MARK
, MSIOF3_SYNC_B_MARK
, VI3_DATA1_MARK
, VI0_G5_MARK
,
477 VI0_G5_B_MARK
, D2_MARK
, MSIOF3_RXD_B_MARK
, VI3_DATA2_MARK
,
478 VI0_G6_MARK
, VI0_G6_B_MARK
, D3_MARK
, MSIOF3_TXD_B_MARK
,
479 VI3_DATA3_MARK
, VI0_G7_MARK
, VI0_G7_B_MARK
, D4_MARK
,
480 SCIFB1_RXD_F_MARK
, SCIFB0_RXD_C_MARK
, VI3_DATA4_MARK
,
481 VI0_R0_MARK
, VI0_R0_B_MARK
, RX0_B_MARK
, D5_MARK
,
482 SCIFB1_TXD_F_MARK
, SCIFB0_TXD_C_MARK
, VI3_DATA5_MARK
,
483 VI0_R1_MARK
, VI0_R1_B_MARK
, TX0_B_MARK
, D6_MARK
,
484 IIC2_SCL_C_MARK
, VI3_DATA6_MARK
, VI0_R2_MARK
, VI0_R2_B_MARK
,
485 I2C2_SCL_C_MARK
, D7_MARK
, AD_DI_B_MARK
, IIC2_SDA_C_MARK
,
486 VI3_DATA7_MARK
, VI0_R3_MARK
, VI0_R3_B_MARK
, I2C2_SDA_C_MARK
, TCLK1_MARK
,
487 D8_MARK
, SCIFA1_SCK_C_MARK
, AVB_TXD0_MARK
,
488 VI0_G0_MARK
, VI0_G0_B_MARK
, VI2_DATA0_VI2_B0_MARK
,
490 D9_MARK
, SCIFA1_RXD_C_MARK
, AVB_TXD1_MARK
,
491 VI0_G1_MARK
, VI0_G1_B_MARK
, VI2_DATA1_VI2_B1_MARK
, D10_MARK
,
492 SCIFA1_TXD_C_MARK
, AVB_TXD2_MARK
,
493 VI0_G2_MARK
, VI0_G2_B_MARK
, VI2_DATA2_VI2_B2_MARK
, D11_MARK
,
494 SCIFA1_CTS_N_C_MARK
, AVB_TXD3_MARK
,
495 VI0_G3_MARK
, VI0_G3_B_MARK
, VI2_DATA3_VI2_B3_MARK
,
496 D12_MARK
, SCIFA1_RTS_N_C_MARK
, AVB_TXD4_MARK
,
497 VI0_HSYNC_N_MARK
, VI0_HSYNC_N_B_MARK
, VI2_DATA4_VI2_B4_MARK
,
498 D13_MARK
, AVB_TXD5_MARK
, VI0_VSYNC_N_MARK
,
499 VI0_VSYNC_N_B_MARK
, VI2_DATA5_VI2_B5_MARK
, D14_MARK
,
500 SCIFB1_RXD_C_MARK
, AVB_TXD6_MARK
, RX1_B_MARK
,
501 VI0_CLKENB_MARK
, VI0_CLKENB_B_MARK
, VI2_DATA6_VI2_B6_MARK
,
502 D15_MARK
, SCIFB1_TXD_C_MARK
, AVB_TXD7_MARK
, TX1_B_MARK
,
503 VI0_FIELD_MARK
, VI0_FIELD_B_MARK
, VI2_DATA7_VI2_B7_MARK
,
504 A0_MARK
, PWM3_MARK
, A1_MARK
, PWM4_MARK
,
506 A2_MARK
, PWM5_MARK
, MSIOF1_SS1_B_MARK
, A3_MARK
,
507 PWM6_MARK
, MSIOF1_SS2_B_MARK
, A4_MARK
, MSIOF1_TXD_B_MARK
,
508 TPU0TO0_MARK
, A5_MARK
, SCIFA1_TXD_B_MARK
, TPU0TO1_MARK
,
509 A6_MARK
, SCIFA1_RTS_N_B_MARK
, TPU0TO2_MARK
, A7_MARK
,
510 SCIFA1_SCK_B_MARK
, AUDIO_CLKOUT_B_MARK
, TPU0TO3_MARK
,
511 A8_MARK
, SCIFA1_RXD_B_MARK
, SSI_SCK5_B_MARK
, VI0_R4_MARK
,
512 VI0_R4_B_MARK
, SCIFB2_RXD_C_MARK
, RX2_B_MARK
, VI2_DATA0_VI2_B0_B_MARK
,
513 A9_MARK
, SCIFA1_CTS_N_B_MARK
, SSI_WS5_B_MARK
, VI0_R5_MARK
,
514 VI0_R5_B_MARK
, SCIFB2_TXD_C_MARK
, TX2_B_MARK
, VI2_DATA1_VI2_B1_B_MARK
,
515 A10_MARK
, SSI_SDATA5_B_MARK
, MSIOF2_SYNC_MARK
, VI0_R6_MARK
,
516 VI0_R6_B_MARK
, VI2_DATA2_VI2_B2_B_MARK
,
518 A11_MARK
, SCIFB2_CTS_N_B_MARK
, MSIOF2_SCK_MARK
, VI1_R0_MARK
,
519 VI1_R0_B_MARK
, VI2_G0_MARK
, VI2_DATA3_VI2_B3_B_MARK
,
520 A12_MARK
, SCIFB2_RXD_B_MARK
, MSIOF2_TXD_MARK
, VI1_R1_MARK
,
521 VI1_R1_B_MARK
, VI2_G1_MARK
, VI2_DATA4_VI2_B4_B_MARK
,
522 A13_MARK
, SCIFB2_RTS_N_B_MARK
, EX_WAIT2_MARK
,
523 MSIOF2_RXD_MARK
, VI1_R2_MARK
, VI1_R2_B_MARK
, VI2_G2_MARK
,
524 VI2_DATA5_VI2_B5_B_MARK
, A14_MARK
, SCIFB2_TXD_B_MARK
,
525 ATACS11_N_MARK
, MSIOF2_SS1_MARK
, A15_MARK
, SCIFB2_SCK_B_MARK
,
526 ATARD1_N_MARK
, MSIOF2_SS2_MARK
, A16_MARK
, ATAWR1_N_MARK
,
527 A17_MARK
, AD_DO_B_MARK
, ATADIR1_N_MARK
, A18_MARK
,
528 AD_CLK_B_MARK
, ATAG1_N_MARK
, A19_MARK
, AD_NCS_N_B_MARK
,
529 ATACS01_N_MARK
, EX_WAIT0_B_MARK
, A20_MARK
, SPCLK_MARK
,
530 VI1_R3_MARK
, VI1_R3_B_MARK
, VI2_G4_MARK
,
532 A21_MARK
, MOSI_IO0_MARK
, VI1_R4_MARK
, VI1_R4_B_MARK
, VI2_G5_MARK
,
533 A22_MARK
, MISO_IO1_MARK
, VI1_R5_MARK
, VI1_R5_B_MARK
,
534 VI2_G6_MARK
, A23_MARK
, IO2_MARK
, VI1_G7_MARK
,
535 VI1_G7_B_MARK
, VI2_G7_MARK
, A24_MARK
, IO3_MARK
,
536 VI1_R7_MARK
, VI1_R7_B_MARK
, VI2_CLKENB_MARK
,
537 VI2_CLKENB_B_MARK
, A25_MARK
, SSL_MARK
, VI1_G6_MARK
,
538 VI1_G6_B_MARK
, VI2_FIELD_MARK
, VI2_FIELD_B_MARK
, CS0_N_MARK
,
539 VI1_R6_MARK
, VI1_R6_B_MARK
, VI2_G3_MARK
, MSIOF0_SS2_B_MARK
,
540 CS1_N_A26_MARK
, SPEEDIN_MARK
, VI0_R7_MARK
, VI0_R7_B_MARK
,
541 VI2_CLK_MARK
, VI2_CLK_B_MARK
, EX_CS0_N_MARK
, HRX1_B_MARK
,
542 VI1_G5_MARK
, VI1_G5_B_MARK
, VI2_R0_MARK
, HTX0_B_MARK
,
543 MSIOF0_SS1_B_MARK
, EX_CS1_N_MARK
, GPS_CLK_MARK
,
544 HCTS1_N_B_MARK
, VI1_FIELD_MARK
, VI1_FIELD_B_MARK
,
545 VI2_R1_MARK
, EX_CS2_N_MARK
, GPS_SIGN_MARK
, HRTS1_N_B_MARK
,
546 VI3_CLKENB_MARK
, VI1_G0_MARK
, VI1_G0_B_MARK
, VI2_R2_MARK
,
548 EX_CS3_N_MARK
, GPS_MAG_MARK
, VI3_FIELD_MARK
,
549 VI1_G1_MARK
, VI1_G1_B_MARK
, VI2_R3_MARK
,
550 EX_CS4_N_MARK
, MSIOF1_SCK_B_MARK
, VI3_HSYNC_N_MARK
,
551 VI2_HSYNC_N_MARK
, IIC1_SCL_MARK
, VI2_HSYNC_N_B_MARK
,
552 INTC_EN0_N_MARK
, I2C1_SCL_MARK
, EX_CS5_N_MARK
, CAN0_RX_MARK
,
553 MSIOF1_RXD_B_MARK
, VI3_VSYNC_N_MARK
, VI1_G2_MARK
,
554 VI1_G2_B_MARK
, VI2_R4_MARK
, IIC1_SDA_MARK
, INTC_EN1_N_MARK
,
555 I2C1_SDA_MARK
, BS_N_MARK
, IETX_MARK
, HTX1_B_MARK
,
556 CAN1_TX_MARK
, DRACK0_MARK
, IETX_C_MARK
, RD_N_MARK
,
557 CAN0_TX_MARK
, SCIFA0_SCK_B_MARK
, RD_WR_N_MARK
, VI1_G3_MARK
,
558 VI1_G3_B_MARK
, VI2_R5_MARK
, SCIFA0_RXD_B_MARK
,
559 INTC_IRQ4_N_MARK
, WE0_N_MARK
, IECLK_MARK
, CAN_CLK_MARK
,
560 VI2_VSYNC_N_MARK
, SCIFA0_TXD_B_MARK
, VI2_VSYNC_N_B_MARK
,
561 WE1_N_MARK
, IERX_MARK
, CAN1_RX_MARK
, VI1_G4_MARK
,
562 VI1_G4_B_MARK
, VI2_R6_MARK
, SCIFA0_CTS_N_B_MARK
,
563 IERX_C_MARK
, EX_WAIT0_MARK
, IRQ3_MARK
, INTC_IRQ3_N_MARK
,
564 VI3_CLK_MARK
, SCIFA0_RTS_N_B_MARK
, HRX0_B_MARK
,
565 MSIOF0_SCK_B_MARK
, DREQ0_N_MARK
, VI1_HSYNC_N_MARK
,
566 VI1_HSYNC_N_B_MARK
, VI2_R7_MARK
, SSI_SCK78_C_MARK
,
569 DACK0_MARK
, IRQ0_MARK
, INTC_IRQ0_N_MARK
, SSI_SCK6_B_MARK
,
570 VI1_VSYNC_N_MARK
, VI1_VSYNC_N_B_MARK
, SSI_WS78_C_MARK
,
571 DREQ1_N_MARK
, VI1_CLKENB_MARK
, VI1_CLKENB_B_MARK
,
572 SSI_SDATA7_C_MARK
, SSI_SCK78_B_MARK
, DACK1_MARK
, IRQ1_MARK
,
573 INTC_IRQ1_N_MARK
, SSI_WS6_B_MARK
, SSI_SDATA8_C_MARK
,
574 DREQ2_N_MARK
, HSCK1_B_MARK
, HCTS0_N_B_MARK
,
575 MSIOF0_TXD_B_MARK
, DACK2_MARK
, IRQ2_MARK
, INTC_IRQ2_N_MARK
,
576 SSI_SDATA6_B_MARK
, HRTS0_N_B_MARK
, MSIOF0_RXD_B_MARK
,
577 ETH_CRS_DV_MARK
, STP_ISCLK_0_B_MARK
,
578 TS_SDEN0_D_MARK
, GLO_Q0_C_MARK
, IIC2_SCL_E_MARK
,
579 I2C2_SCL_E_MARK
, ETH_RX_ER_MARK
,
580 STP_ISD_0_B_MARK
, TS_SPSYNC0_D_MARK
, GLO_Q1_C_MARK
,
581 IIC2_SDA_E_MARK
, I2C2_SDA_E_MARK
, ETH_RXD0_MARK
,
582 STP_ISEN_0_B_MARK
, TS_SDAT0_D_MARK
, GLO_I0_C_MARK
,
583 SCIFB1_SCK_G_MARK
, SCK1_E_MARK
, ETH_RXD1_MARK
,
584 HRX0_E_MARK
, STP_ISSYNC_0_B_MARK
,
585 TS_SCK0_D_MARK
, GLO_I1_C_MARK
, SCIFB1_RXD_G_MARK
,
586 RX1_E_MARK
, ETH_LINK_MARK
, HTX0_E_MARK
,
587 STP_IVCXO27_0_B_MARK
, SCIFB1_TXD_G_MARK
, TX1_E_MARK
,
588 ETH_REF_CLK_MARK
, HCTS0_N_E_MARK
,
589 STP_IVCXO27_1_B_MARK
, HRX0_F_MARK
,
591 ETH_MDIO_MARK
, HRTS0_N_E_MARK
,
592 SIM0_D_C_MARK
, HCTS0_N_F_MARK
, ETH_TXD1_MARK
,
593 HTX0_F_MARK
, BPFCLK_G_MARK
,
594 ETH_TX_EN_MARK
, SIM0_CLK_C_MARK
,
595 HRTS0_N_F_MARK
, ETH_MAGIC_MARK
,
596 SIM0_RST_C_MARK
, ETH_TXD0_MARK
,
597 STP_ISCLK_1_B_MARK
, TS_SDEN1_C_MARK
, GLO_SCLK_C_MARK
,
598 ETH_MDC_MARK
, STP_ISD_1_B_MARK
,
599 TS_SPSYNC1_C_MARK
, GLO_SDATA_C_MARK
, PWM0_MARK
,
600 SCIFA2_SCK_C_MARK
, STP_ISEN_1_B_MARK
, TS_SDAT1_C_MARK
,
601 GLO_SS_C_MARK
, PWM1_MARK
, SCIFA2_TXD_C_MARK
,
602 STP_ISSYNC_1_B_MARK
, TS_SCK1_C_MARK
, GLO_RFON_C_MARK
,
603 PCMOE_N_MARK
, PWM2_MARK
, PWMFSW0_MARK
, SCIFA2_RXD_C_MARK
,
604 PCMWE_N_MARK
, IECLK_C_MARK
, DU_DOTCLKIN1_MARK
,
605 AUDIO_CLKC_MARK
, AUDIO_CLKOUT_C_MARK
, VI0_CLK_MARK
,
606 ATACS00_N_MARK
, AVB_RXD1_MARK
,
607 VI0_DATA0_VI0_B0_MARK
, ATACS10_N_MARK
, AVB_RXD2_MARK
,
609 VI0_DATA1_VI0_B1_MARK
, ATARD0_N_MARK
, AVB_RXD3_MARK
,
610 VI0_DATA2_VI0_B2_MARK
, ATAWR0_N_MARK
,
611 AVB_RXD4_MARK
, VI0_DATA3_VI0_B3_MARK
, ATADIR0_N_MARK
,
612 AVB_RXD5_MARK
, VI0_DATA4_VI0_B4_MARK
, ATAG0_N_MARK
,
613 AVB_RXD6_MARK
, VI0_DATA5_VI0_B5_MARK
, EX_WAIT1_MARK
,
614 AVB_RXD7_MARK
, VI0_DATA6_VI0_B6_MARK
, AVB_RX_ER_MARK
,
615 VI0_DATA7_VI0_B7_MARK
, AVB_RX_CLK_MARK
,
616 VI1_CLK_MARK
, AVB_RX_DV_MARK
,
617 VI1_DATA0_VI1_B0_MARK
, SCIFA1_SCK_D_MARK
,
618 AVB_CRS_MARK
, VI1_DATA1_VI1_B1_MARK
,
619 SCIFA1_RXD_D_MARK
, AVB_MDC_MARK
,
620 VI1_DATA2_VI1_B2_MARK
, SCIFA1_TXD_D_MARK
, AVB_MDIO_MARK
,
621 VI1_DATA3_VI1_B3_MARK
, SCIFA1_CTS_N_D_MARK
,
622 AVB_GTX_CLK_MARK
, VI1_DATA4_VI1_B4_MARK
, SCIFA1_RTS_N_D_MARK
,
623 AVB_MAGIC_MARK
, VI1_DATA5_VI1_B5_MARK
,
624 AVB_PHY_INT_MARK
, VI1_DATA6_VI1_B6_MARK
, AVB_GTXREFCLK_MARK
,
625 SD0_CLK_MARK
, VI1_DATA0_VI1_B0_B_MARK
, SD0_CMD_MARK
,
626 SCIFB1_SCK_B_MARK
, VI1_DATA1_VI1_B1_B_MARK
,
628 SD0_DAT0_MARK
, SCIFB1_RXD_B_MARK
, VI1_DATA2_VI1_B2_B_MARK
,
629 SD0_DAT1_MARK
, SCIFB1_TXD_B_MARK
, VI1_DATA3_VI1_B3_B_MARK
,
630 SD0_DAT2_MARK
, SCIFB1_CTS_N_B_MARK
, VI1_DATA4_VI1_B4_B_MARK
,
631 SD0_DAT3_MARK
, SCIFB1_RTS_N_B_MARK
, VI1_DATA5_VI1_B5_B_MARK
,
632 SD0_CD_MARK
, MMC0_D6_MARK
, TS_SDEN0_B_MARK
, USB0_EXTP_MARK
,
633 GLO_SCLK_MARK
, VI1_DATA6_VI1_B6_B_MARK
, IIC1_SCL_B_MARK
,
634 I2C1_SCL_B_MARK
, VI2_DATA6_VI2_B6_B_MARK
, SD0_WP_MARK
,
635 MMC0_D7_MARK
, TS_SPSYNC0_B_MARK
, USB0_IDIN_MARK
,
636 GLO_SDATA_MARK
, VI1_DATA7_VI1_B7_B_MARK
, IIC1_SDA_B_MARK
,
637 I2C1_SDA_B_MARK
, VI2_DATA7_VI2_B7_B_MARK
, SD1_CLK_MARK
,
638 AVB_TX_EN_MARK
, SD1_CMD_MARK
,
639 AVB_TX_ER_MARK
, SCIFB0_SCK_B_MARK
,
640 SD1_DAT0_MARK
, AVB_TX_CLK_MARK
,
641 SCIFB0_RXD_B_MARK
, SD1_DAT1_MARK
, AVB_LINK_MARK
,
642 SCIFB0_TXD_B_MARK
, SD1_DAT2_MARK
,
643 AVB_COL_MARK
, SCIFB0_CTS_N_B_MARK
,
644 SD1_DAT3_MARK
, AVB_RXD0_MARK
,
645 SCIFB0_RTS_N_B_MARK
, SD1_CD_MARK
, MMC1_D6_MARK
,
646 TS_SDEN1_MARK
, USB1_EXTP_MARK
, GLO_SS_MARK
, VI0_CLK_B_MARK
,
647 IIC2_SCL_D_MARK
, I2C2_SCL_D_MARK
, SIM0_CLK_B_MARK
,
650 SD1_WP_MARK
, MMC1_D7_MARK
, TS_SPSYNC1_MARK
, USB1_IDIN_MARK
,
651 GLO_RFON_MARK
, VI1_CLK_B_MARK
, IIC2_SDA_D_MARK
, I2C2_SDA_D_MARK
,
652 SIM0_D_B_MARK
, SD2_CLK_MARK
, MMC0_CLK_MARK
, SIM0_CLK_MARK
,
653 VI0_DATA0_VI0_B0_B_MARK
, TS_SDEN0_C_MARK
, GLO_SCLK_B_MARK
,
654 VI3_DATA0_B_MARK
, SD2_CMD_MARK
, MMC0_CMD_MARK
, SIM0_D_MARK
,
655 VI0_DATA1_VI0_B1_B_MARK
, SCIFB1_SCK_E_MARK
, SCK1_D_MARK
,
656 TS_SPSYNC0_C_MARK
, GLO_SDATA_B_MARK
, VI3_DATA1_B_MARK
,
657 SD2_DAT0_MARK
, MMC0_D0_MARK
, FMCLK_B_MARK
,
658 VI0_DATA2_VI0_B2_B_MARK
, SCIFB1_RXD_E_MARK
, RX1_D_MARK
,
659 TS_SDAT0_C_MARK
, GLO_SS_B_MARK
, VI3_DATA2_B_MARK
,
660 SD2_DAT1_MARK
, MMC0_D1_MARK
, FMIN_B_MARK
,
661 VI0_DATA3_VI0_B3_B_MARK
, SCIFB1_TXD_E_MARK
, TX1_D_MARK
,
662 TS_SCK0_C_MARK
, GLO_RFON_B_MARK
, VI3_DATA3_B_MARK
,
663 SD2_DAT2_MARK
, MMC0_D2_MARK
, BPFCLK_B_MARK
,
664 VI0_DATA4_VI0_B4_B_MARK
, HRX0_D_MARK
, TS_SDEN1_B_MARK
,
665 GLO_Q0_B_MARK
, VI3_DATA4_B_MARK
, SD2_DAT3_MARK
,
666 MMC0_D3_MARK
, SIM0_RST_MARK
, VI0_DATA5_VI0_B5_B_MARK
,
667 HTX0_D_MARK
, TS_SPSYNC1_B_MARK
, GLO_Q1_B_MARK
,
668 VI3_DATA5_B_MARK
, SD2_CD_MARK
, MMC0_D4_MARK
,
669 TS_SDAT0_B_MARK
, USB2_EXTP_MARK
, GLO_I0_MARK
,
670 VI0_DATA6_VI0_B6_B_MARK
, HCTS0_N_D_MARK
, TS_SDAT1_B_MARK
,
671 GLO_I0_B_MARK
, VI3_DATA6_B_MARK
,
673 SD2_WP_MARK
, MMC0_D5_MARK
, TS_SCK0_B_MARK
, USB2_IDIN_MARK
,
674 GLO_I1_MARK
, VI0_DATA7_VI0_B7_B_MARK
, HRTS0_N_D_MARK
,
675 TS_SCK1_B_MARK
, GLO_I1_B_MARK
, VI3_DATA7_B_MARK
,
676 SD3_CLK_MARK
, MMC1_CLK_MARK
, SD3_CMD_MARK
, MMC1_CMD_MARK
,
677 MTS_N_MARK
, SD3_DAT0_MARK
, MMC1_D0_MARK
, STM_N_MARK
,
678 SD3_DAT1_MARK
, MMC1_D1_MARK
, MDATA_MARK
, SD3_DAT2_MARK
,
679 MMC1_D2_MARK
, SDATA_MARK
, SD3_DAT3_MARK
, MMC1_D3_MARK
,
680 SCKZ_MARK
, SD3_CD_MARK
, MMC1_D4_MARK
, TS_SDAT1_MARK
,
681 VSP_MARK
, GLO_Q0_MARK
, SIM0_RST_B_MARK
, SD3_WP_MARK
,
682 MMC1_D5_MARK
, TS_SCK1_MARK
, GLO_Q1_MARK
, FMIN_C_MARK
,
683 FMIN_E_MARK
, FMIN_F_MARK
,
684 MLB_CLK_MARK
, IIC2_SCL_B_MARK
, I2C2_SCL_B_MARK
,
685 MLB_SIG_MARK
, SCIFB1_RXD_D_MARK
, RX1_C_MARK
, IIC2_SDA_B_MARK
,
686 I2C2_SDA_B_MARK
, MLB_DAT_MARK
,
687 SCIFB1_TXD_D_MARK
, TX1_C_MARK
, BPFCLK_C_MARK
,
688 SSI_SCK0129_MARK
, CAN_CLK_B_MARK
,
691 SSI_WS0129_MARK
, CAN0_TX_B_MARK
, MOUT1_MARK
,
692 SSI_SDATA0_MARK
, CAN0_RX_B_MARK
, MOUT2_MARK
,
693 SSI_SDATA1_MARK
, CAN1_TX_B_MARK
, MOUT5_MARK
,
694 SSI_SDATA2_MARK
, CAN1_RX_B_MARK
, SSI_SCK1_MARK
, MOUT6_MARK
,
695 SSI_SCK34_MARK
, STP_OPWM_0_MARK
, SCIFB0_SCK_MARK
,
696 MSIOF1_SCK_MARK
, CAN_DEBUG_HW_TRIGGER_MARK
, SSI_WS34_MARK
,
697 STP_IVCXO27_0_MARK
, SCIFB0_RXD_MARK
, MSIOF1_SYNC_MARK
,
698 CAN_STEP0_MARK
, SSI_SDATA3_MARK
, STP_ISCLK_0_MARK
,
699 SCIFB0_TXD_MARK
, MSIOF1_SS1_MARK
, CAN_TXCLK_MARK
,
700 SSI_SCK4_MARK
, STP_ISD_0_MARK
, SCIFB0_CTS_N_MARK
,
701 MSIOF1_SS2_MARK
, SSI_SCK5_C_MARK
, CAN_DEBUGOUT0_MARK
,
702 SSI_WS4_MARK
, STP_ISEN_0_MARK
, SCIFB0_RTS_N_MARK
,
703 MSIOF1_TXD_MARK
, SSI_WS5_C_MARK
, CAN_DEBUGOUT1_MARK
,
704 SSI_SDATA4_MARK
, STP_ISSYNC_0_MARK
, MSIOF1_RXD_MARK
,
705 CAN_DEBUGOUT2_MARK
, SSI_SCK5_MARK
, SCIFB1_SCK_MARK
,
706 IERX_B_MARK
, DU2_EXHSYNC_DU2_HSYNC_MARK
, QSTH_QHS_MARK
,
707 CAN_DEBUGOUT3_MARK
, SSI_WS5_MARK
, SCIFB1_RXD_MARK
,
708 IECLK_B_MARK
, DU2_EXVSYNC_DU2_VSYNC_MARK
, QSTB_QHE_MARK
,
711 SSI_SDATA5_MARK
, SCIFB1_TXD_MARK
, IETX_B_MARK
, DU2_DR2_MARK
,
712 LCDOUT2_MARK
, CAN_DEBUGOUT5_MARK
, SSI_SCK6_MARK
,
713 SCIFB1_CTS_N_MARK
, BPFCLK_D_MARK
,
714 DU2_DR3_MARK
, LCDOUT3_MARK
, CAN_DEBUGOUT6_MARK
,
715 BPFCLK_F_MARK
, SSI_WS6_MARK
,
716 SCIFB1_RTS_N_MARK
, CAN0_TX_D_MARK
, DU2_DR4_MARK
,
717 LCDOUT4_MARK
, CAN_DEBUGOUT7_MARK
, SSI_SDATA6_MARK
,
718 FMIN_D_MARK
, DU2_DR5_MARK
, LCDOUT5_MARK
,
719 CAN_DEBUGOUT8_MARK
, SSI_SCK78_MARK
, STP_IVCXO27_1_MARK
,
720 SCK1_MARK
, SCIFA1_SCK_MARK
, DU2_DR6_MARK
, LCDOUT6_MARK
,
721 CAN_DEBUGOUT9_MARK
, SSI_WS78_MARK
, STP_ISCLK_1_MARK
,
722 SCIFB2_SCK_MARK
, SCIFA2_CTS_N_MARK
, DU2_DR7_MARK
,
723 LCDOUT7_MARK
, CAN_DEBUGOUT10_MARK
, SSI_SDATA7_MARK
,
724 STP_ISD_1_MARK
, SCIFB2_RXD_MARK
, SCIFA2_RTS_N_MARK
,
725 TCLK2_MARK
, QSTVA_QVS_MARK
, CAN_DEBUGOUT11_MARK
,
726 BPFCLK_E_MARK
, SSI_SDATA7_B_MARK
,
727 FMIN_G_MARK
, SSI_SDATA8_MARK
,
728 STP_ISEN_1_MARK
, SCIFB2_TXD_MARK
, CAN0_TX_C_MARK
,
729 CAN_DEBUGOUT12_MARK
, SSI_SDATA8_B_MARK
, SSI_SDATA9_MARK
,
730 STP_ISSYNC_1_MARK
, SCIFB2_CTS_N_MARK
, SSI_WS1_MARK
,
731 SSI_SDATA5_C_MARK
, CAN_DEBUGOUT13_MARK
, AUDIO_CLKA_MARK
,
732 SCIFB2_RTS_N_MARK
, CAN_DEBUGOUT14_MARK
,
734 AUDIO_CLKB_MARK
, SCIF_CLK_MARK
, CAN0_RX_D_MARK
,
735 DVC_MUTE_MARK
, CAN0_RX_C_MARK
, CAN_DEBUGOUT15_MARK
,
736 REMOCON_MARK
, SCIFA0_SCK_MARK
, HSCK1_MARK
, SCK0_MARK
,
737 MSIOF3_SS2_MARK
, DU2_DG2_MARK
, LCDOUT10_MARK
, IIC1_SDA_C_MARK
,
738 I2C1_SDA_C_MARK
, SCIFA0_RXD_MARK
, HRX1_MARK
, RX0_MARK
,
739 DU2_DR0_MARK
, LCDOUT0_MARK
, SCIFA0_TXD_MARK
, HTX1_MARK
,
740 TX0_MARK
, DU2_DR1_MARK
, LCDOUT1_MARK
, SCIFA0_CTS_N_MARK
,
741 HCTS1_N_MARK
, CTS0_N_MARK
, MSIOF3_SYNC_MARK
, DU2_DG3_MARK
,
742 LCDOUT11_MARK
, PWM0_B_MARK
, IIC1_SCL_C_MARK
, I2C1_SCL_C_MARK
,
743 SCIFA0_RTS_N_MARK
, HRTS1_N_MARK
, RTS0_N_MARK
,
744 MSIOF3_SS1_MARK
, DU2_DG0_MARK
, LCDOUT8_MARK
, PWM1_B_MARK
,
745 SCIFA1_RXD_MARK
, AD_DI_MARK
, RX1_MARK
,
746 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
, QCPV_QDE_MARK
,
747 SCIFA1_TXD_MARK
, AD_DO_MARK
, TX1_MARK
, DU2_DG1_MARK
,
748 LCDOUT9_MARK
, SCIFA1_CTS_N_MARK
, AD_CLK_MARK
,
749 CTS1_N_MARK
, MSIOF3_RXD_MARK
, DU0_DOTCLKOUT_MARK
, QCLK_MARK
,
750 SCIFA1_RTS_N_MARK
, AD_NCS_N_MARK
, RTS1_N_MARK
,
751 MSIOF3_TXD_MARK
, DU1_DOTCLKOUT_MARK
, QSTVB_QVE_MARK
,
754 SCIFA2_SCK_MARK
, FMCLK_MARK
, SCK2_MARK
, MSIOF3_SCK_MARK
, DU2_DG7_MARK
,
755 LCDOUT15_MARK
, SCIF_CLK_B_MARK
, SCIFA2_RXD_MARK
, FMIN_MARK
,
756 TX2_MARK
, DU2_DB0_MARK
, LCDOUT16_MARK
, IIC2_SCL_MARK
, I2C2_SCL_MARK
,
757 SCIFA2_TXD_MARK
, BPFCLK_MARK
, RX2_MARK
, DU2_DB1_MARK
, LCDOUT17_MARK
,
758 IIC2_SDA_MARK
, I2C2_SDA_MARK
, HSCK0_MARK
, TS_SDEN0_MARK
,
759 DU2_DG4_MARK
, LCDOUT12_MARK
, HCTS0_N_C_MARK
, HRX0_MARK
,
760 DU2_DB2_MARK
, LCDOUT18_MARK
, HTX0_MARK
, DU2_DB3_MARK
,
761 LCDOUT19_MARK
, HCTS0_N_MARK
, SSI_SCK9_MARK
, DU2_DB4_MARK
,
762 LCDOUT20_MARK
, HRTS0_N_MARK
, SSI_WS9_MARK
, DU2_DB5_MARK
,
763 LCDOUT21_MARK
, MSIOF0_SCK_MARK
, TS_SDAT0_MARK
, ADICLK_MARK
,
764 DU2_DB6_MARK
, LCDOUT22_MARK
, MSIOF0_SYNC_MARK
, TS_SCK0_MARK
,
765 SSI_SCK2_MARK
, ADIDATA_MARK
, DU2_DB7_MARK
, LCDOUT23_MARK
,
766 HRX0_C_MARK
, MSIOF0_SS1_MARK
, ADICHS0_MARK
,
767 DU2_DG5_MARK
, LCDOUT13_MARK
, MSIOF0_TXD_MARK
, ADICHS1_MARK
,
768 DU2_DG6_MARK
, LCDOUT14_MARK
,
770 MSIOF0_SS2_MARK
, AUDIO_CLKOUT_MARK
, ADICHS2_MARK
,
771 DU2_DISP_MARK
, QPOLA_MARK
, HTX0_C_MARK
, SCIFA2_TXD_B_MARK
,
772 MSIOF0_RXD_MARK
, TS_SPSYNC0_MARK
, SSI_WS2_MARK
,
773 ADICS_SAMP_MARK
, DU2_CDE_MARK
, QPOLB_MARK
, SCIFA2_RXD_B_MARK
,
774 USB1_PWEN_MARK
, AUDIO_CLKOUT_D_MARK
, USB1_OVC_MARK
,
777 IIC0_SCL_MARK
, IIC0_SDA_MARK
, I2C0_SCL_MARK
, I2C0_SDA_MARK
,
778 IIC3_SCL_MARK
, IIC3_SDA_MARK
, I2C3_SCL_MARK
, I2C3_SDA_MARK
,
782 static const u16 pinmux_data
[] = {
783 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
785 PINMUX_SINGLE(VI1_DATA7_VI1_B7
),
786 PINMUX_SINGLE(USB0_PWEN
),
787 PINMUX_SINGLE(USB0_OVC_VBUS
),
788 PINMUX_SINGLE(USB2_PWEN
),
789 PINMUX_SINGLE(USB2_OVC
),
792 PINMUX_SINGLE(DU_DOTCLKIN0
),
793 PINMUX_SINGLE(DU_DOTCLKIN2
),
795 PINMUX_IPSR_GPSR(IP0_2_0
, D0
),
796 PINMUX_IPSR_MSEL(IP0_2_0
, MSIOF3_SCK_B
, SEL_SOF3_1
),
797 PINMUX_IPSR_MSEL(IP0_2_0
, VI3_DATA0
, SEL_VI3_0
),
798 PINMUX_IPSR_MSEL(IP0_2_0
, VI0_G4
, SEL_VI0_0
),
799 PINMUX_IPSR_MSEL(IP0_2_0
, VI0_G4_B
, SEL_VI0_1
),
800 PINMUX_IPSR_GPSR(IP0_5_3
, D1
),
801 PINMUX_IPSR_MSEL(IP0_5_3
, MSIOF3_SYNC_B
, SEL_SOF3_1
),
802 PINMUX_IPSR_MSEL(IP0_5_3
, VI3_DATA1
, SEL_VI3_0
),
803 PINMUX_IPSR_MSEL(IP0_5_3
, VI0_G5
, SEL_VI0_0
),
804 PINMUX_IPSR_MSEL(IP0_5_3
, VI0_G5_B
, SEL_VI0_1
),
805 PINMUX_IPSR_GPSR(IP0_8_6
, D2
),
806 PINMUX_IPSR_MSEL(IP0_8_6
, MSIOF3_RXD_B
, SEL_SOF3_1
),
807 PINMUX_IPSR_MSEL(IP0_8_6
, VI3_DATA2
, SEL_VI3_0
),
808 PINMUX_IPSR_MSEL(IP0_8_6
, VI0_G6
, SEL_VI0_0
),
809 PINMUX_IPSR_MSEL(IP0_8_6
, VI0_G6_B
, SEL_VI0_1
),
810 PINMUX_IPSR_GPSR(IP0_11_9
, D3
),
811 PINMUX_IPSR_MSEL(IP0_11_9
, MSIOF3_TXD_B
, SEL_SOF3_1
),
812 PINMUX_IPSR_MSEL(IP0_11_9
, VI3_DATA3
, SEL_VI3_0
),
813 PINMUX_IPSR_MSEL(IP0_11_9
, VI0_G7
, SEL_VI0_0
),
814 PINMUX_IPSR_MSEL(IP0_11_9
, VI0_G7_B
, SEL_VI0_1
),
815 PINMUX_IPSR_GPSR(IP0_15_12
, D4
),
816 PINMUX_IPSR_MSEL(IP0_15_12
, SCIFB1_RXD_F
, SEL_SCIFB1_5
),
817 PINMUX_IPSR_MSEL(IP0_15_12
, SCIFB0_RXD_C
, SEL_SCIFB_2
),
818 PINMUX_IPSR_MSEL(IP0_15_12
, VI3_DATA4
, SEL_VI3_0
),
819 PINMUX_IPSR_MSEL(IP0_15_12
, VI0_R0
, SEL_VI0_0
),
820 PINMUX_IPSR_MSEL(IP0_15_12
, VI0_R0_B
, SEL_VI0_1
),
821 PINMUX_IPSR_MSEL(IP0_15_12
, RX0_B
, SEL_SCIF0_1
),
822 PINMUX_IPSR_GPSR(IP0_19_16
, D5
),
823 PINMUX_IPSR_MSEL(IP0_19_16
, SCIFB1_TXD_F
, SEL_SCIFB1_5
),
824 PINMUX_IPSR_MSEL(IP0_19_16
, SCIFB0_TXD_C
, SEL_SCIFB_2
),
825 PINMUX_IPSR_MSEL(IP0_19_16
, VI3_DATA5
, SEL_VI3_0
),
826 PINMUX_IPSR_MSEL(IP0_19_16
, VI0_R1
, SEL_VI0_0
),
827 PINMUX_IPSR_MSEL(IP0_19_16
, VI0_R1_B
, SEL_VI0_1
),
828 PINMUX_IPSR_MSEL(IP0_19_16
, TX0_B
, SEL_SCIF0_1
),
829 PINMUX_IPSR_GPSR(IP0_22_20
, D6
),
830 PINMUX_IPSR_MSEL(IP0_22_20
, IIC2_SCL_C
, SEL_IIC2_2
),
831 PINMUX_IPSR_MSEL(IP0_22_20
, VI3_DATA6
, SEL_VI3_0
),
832 PINMUX_IPSR_MSEL(IP0_22_20
, VI0_R2
, SEL_VI0_0
),
833 PINMUX_IPSR_MSEL(IP0_22_20
, VI0_R2_B
, SEL_VI0_1
),
834 PINMUX_IPSR_MSEL(IP0_22_20
, I2C2_SCL_C
, SEL_I2C2_2
),
835 PINMUX_IPSR_GPSR(IP0_26_23
, D7
),
836 PINMUX_IPSR_MSEL(IP0_26_23
, AD_DI_B
, SEL_ADI_1
),
837 PINMUX_IPSR_MSEL(IP0_26_23
, IIC2_SDA_C
, SEL_IIC2_2
),
838 PINMUX_IPSR_MSEL(IP0_26_23
, VI3_DATA7
, SEL_VI3_0
),
839 PINMUX_IPSR_MSEL(IP0_26_23
, VI0_R3
, SEL_VI0_0
),
840 PINMUX_IPSR_MSEL(IP0_26_23
, VI0_R3_B
, SEL_VI0_1
),
841 PINMUX_IPSR_MSEL(IP0_26_23
, I2C2_SDA_C
, SEL_I2C2_2
),
842 PINMUX_IPSR_MSEL(IP0_26_23
, TCLK1
, SEL_TMU1_0
),
843 PINMUX_IPSR_GPSR(IP0_30_27
, D8
),
844 PINMUX_IPSR_MSEL(IP0_30_27
, SCIFA1_SCK_C
, SEL_SCIFA1_2
),
845 PINMUX_IPSR_GPSR(IP0_30_27
, AVB_TXD0
),
846 PINMUX_IPSR_MSEL(IP0_30_27
, VI0_G0
, SEL_VI0_0
),
847 PINMUX_IPSR_MSEL(IP0_30_27
, VI0_G0_B
, SEL_VI0_1
),
848 PINMUX_IPSR_MSEL(IP0_30_27
, VI2_DATA0_VI2_B0
, SEL_VI2_0
),
850 PINMUX_IPSR_GPSR(IP1_3_0
, D9
),
851 PINMUX_IPSR_MSEL(IP1_3_0
, SCIFA1_RXD_C
, SEL_SCIFA1_2
),
852 PINMUX_IPSR_GPSR(IP1_3_0
, AVB_TXD1
),
853 PINMUX_IPSR_MSEL(IP1_3_0
, VI0_G1
, SEL_VI0_0
),
854 PINMUX_IPSR_MSEL(IP1_3_0
, VI0_G1_B
, SEL_VI0_1
),
855 PINMUX_IPSR_MSEL(IP1_3_0
, VI2_DATA1_VI2_B1
, SEL_VI2_0
),
856 PINMUX_IPSR_GPSR(IP1_7_4
, D10
),
857 PINMUX_IPSR_MSEL(IP1_7_4
, SCIFA1_TXD_C
, SEL_SCIFA1_2
),
858 PINMUX_IPSR_GPSR(IP1_7_4
, AVB_TXD2
),
859 PINMUX_IPSR_MSEL(IP1_7_4
, VI0_G2
, SEL_VI0_0
),
860 PINMUX_IPSR_MSEL(IP1_7_4
, VI0_G2_B
, SEL_VI0_1
),
861 PINMUX_IPSR_MSEL(IP1_7_4
, VI2_DATA2_VI2_B2
, SEL_VI2_0
),
862 PINMUX_IPSR_GPSR(IP1_11_8
, D11
),
863 PINMUX_IPSR_MSEL(IP1_11_8
, SCIFA1_CTS_N_C
, SEL_SCIFA1_2
),
864 PINMUX_IPSR_GPSR(IP1_11_8
, AVB_TXD3
),
865 PINMUX_IPSR_MSEL(IP1_11_8
, VI0_G3
, SEL_VI0_0
),
866 PINMUX_IPSR_MSEL(IP1_11_8
, VI0_G3_B
, SEL_VI0_1
),
867 PINMUX_IPSR_MSEL(IP1_11_8
, VI2_DATA3_VI2_B3
, SEL_VI2_0
),
868 PINMUX_IPSR_GPSR(IP1_14_12
, D12
),
869 PINMUX_IPSR_MSEL(IP1_14_12
, SCIFA1_RTS_N_C
, SEL_SCIFA1_2
),
870 PINMUX_IPSR_GPSR(IP1_14_12
, AVB_TXD4
),
871 PINMUX_IPSR_MSEL(IP1_14_12
, VI0_HSYNC_N
, SEL_VI0_0
),
872 PINMUX_IPSR_MSEL(IP1_14_12
, VI0_HSYNC_N_B
, SEL_VI0_1
),
873 PINMUX_IPSR_MSEL(IP1_14_12
, VI2_DATA4_VI2_B4
, SEL_VI2_0
),
874 PINMUX_IPSR_GPSR(IP1_17_15
, D13
),
875 PINMUX_IPSR_GPSR(IP1_17_15
, AVB_TXD5
),
876 PINMUX_IPSR_MSEL(IP1_17_15
, VI0_VSYNC_N
, SEL_VI0_0
),
877 PINMUX_IPSR_MSEL(IP1_17_15
, VI0_VSYNC_N_B
, SEL_VI0_1
),
878 PINMUX_IPSR_MSEL(IP1_17_15
, VI2_DATA5_VI2_B5
, SEL_VI2_0
),
879 PINMUX_IPSR_GPSR(IP1_21_18
, D14
),
880 PINMUX_IPSR_MSEL(IP1_21_18
, SCIFB1_RXD_C
, SEL_SCIFB1_2
),
881 PINMUX_IPSR_GPSR(IP1_21_18
, AVB_TXD6
),
882 PINMUX_IPSR_MSEL(IP1_21_18
, RX1_B
, SEL_SCIF1_1
),
883 PINMUX_IPSR_MSEL(IP1_21_18
, VI0_CLKENB
, SEL_VI0_0
),
884 PINMUX_IPSR_MSEL(IP1_21_18
, VI0_CLKENB_B
, SEL_VI0_1
),
885 PINMUX_IPSR_MSEL(IP1_21_18
, VI2_DATA6_VI2_B6
, SEL_VI2_0
),
886 PINMUX_IPSR_GPSR(IP1_25_22
, D15
),
887 PINMUX_IPSR_MSEL(IP1_25_22
, SCIFB1_TXD_C
, SEL_SCIFB1_2
),
888 PINMUX_IPSR_GPSR(IP1_25_22
, AVB_TXD7
),
889 PINMUX_IPSR_MSEL(IP1_25_22
, TX1_B
, SEL_SCIF1_1
),
890 PINMUX_IPSR_MSEL(IP1_25_22
, VI0_FIELD
, SEL_VI0_0
),
891 PINMUX_IPSR_MSEL(IP1_25_22
, VI0_FIELD_B
, SEL_VI0_1
),
892 PINMUX_IPSR_MSEL(IP1_25_22
, VI2_DATA7_VI2_B7
, SEL_VI2_0
),
893 PINMUX_IPSR_GPSR(IP1_27_26
, A0
),
894 PINMUX_IPSR_GPSR(IP1_27_26
, PWM3
),
895 PINMUX_IPSR_GPSR(IP1_29_28
, A1
),
896 PINMUX_IPSR_GPSR(IP1_29_28
, PWM4
),
898 PINMUX_IPSR_GPSR(IP2_2_0
, A2
),
899 PINMUX_IPSR_GPSR(IP2_2_0
, PWM5
),
900 PINMUX_IPSR_MSEL(IP2_2_0
, MSIOF1_SS1_B
, SEL_SOF1_1
),
901 PINMUX_IPSR_GPSR(IP2_5_3
, A3
),
902 PINMUX_IPSR_GPSR(IP2_5_3
, PWM6
),
903 PINMUX_IPSR_MSEL(IP2_5_3
, MSIOF1_SS2_B
, SEL_SOF1_1
),
904 PINMUX_IPSR_GPSR(IP2_8_6
, A4
),
905 PINMUX_IPSR_MSEL(IP2_8_6
, MSIOF1_TXD_B
, SEL_SOF1_1
),
906 PINMUX_IPSR_GPSR(IP2_8_6
, TPU0TO0
),
907 PINMUX_IPSR_GPSR(IP2_11_9
, A5
),
908 PINMUX_IPSR_MSEL(IP2_11_9
, SCIFA1_TXD_B
, SEL_SCIFA1_1
),
909 PINMUX_IPSR_GPSR(IP2_11_9
, TPU0TO1
),
910 PINMUX_IPSR_GPSR(IP2_14_12
, A6
),
911 PINMUX_IPSR_MSEL(IP2_14_12
, SCIFA1_RTS_N_B
, SEL_SCIFA1_1
),
912 PINMUX_IPSR_GPSR(IP2_14_12
, TPU0TO2
),
913 PINMUX_IPSR_GPSR(IP2_17_15
, A7
),
914 PINMUX_IPSR_MSEL(IP2_17_15
, SCIFA1_SCK_B
, SEL_SCIFA1_1
),
915 PINMUX_IPSR_GPSR(IP2_17_15
, AUDIO_CLKOUT_B
),
916 PINMUX_IPSR_GPSR(IP2_17_15
, TPU0TO3
),
917 PINMUX_IPSR_GPSR(IP2_21_18
, A8
),
918 PINMUX_IPSR_MSEL(IP2_21_18
, SCIFA1_RXD_B
, SEL_SCIFA1_1
),
919 PINMUX_IPSR_MSEL(IP2_21_18
, SSI_SCK5_B
, SEL_SSI5_1
),
920 PINMUX_IPSR_MSEL(IP2_21_18
, VI0_R4
, SEL_VI0_0
),
921 PINMUX_IPSR_MSEL(IP2_21_18
, VI0_R4_B
, SEL_VI0_1
),
922 PINMUX_IPSR_MSEL(IP2_21_18
, SCIFB2_RXD_C
, SEL_SCIFB2_2
),
923 PINMUX_IPSR_MSEL(IP2_21_18
, RX2_B
, SEL_SCIF2_1
),
924 PINMUX_IPSR_MSEL(IP2_21_18
, VI2_DATA0_VI2_B0_B
, SEL_VI2_1
),
925 PINMUX_IPSR_GPSR(IP2_25_22
, A9
),
926 PINMUX_IPSR_MSEL(IP2_25_22
, SCIFA1_CTS_N_B
, SEL_SCIFA1_1
),
927 PINMUX_IPSR_MSEL(IP2_25_22
, SSI_WS5_B
, SEL_SSI5_1
),
928 PINMUX_IPSR_MSEL(IP2_25_22
, VI0_R5
, SEL_VI0_0
),
929 PINMUX_IPSR_MSEL(IP2_25_22
, VI0_R5_B
, SEL_VI0_1
),
930 PINMUX_IPSR_MSEL(IP2_25_22
, SCIFB2_TXD_C
, SEL_SCIFB2_2
),
931 PINMUX_IPSR_MSEL(IP2_25_22
, TX2_B
, SEL_SCIF2_1
),
932 PINMUX_IPSR_MSEL(IP2_25_22
, VI2_DATA1_VI2_B1_B
, SEL_VI2_1
),
933 PINMUX_IPSR_GPSR(IP2_28_26
, A10
),
934 PINMUX_IPSR_MSEL(IP2_28_26
, SSI_SDATA5_B
, SEL_SSI5_1
),
935 PINMUX_IPSR_GPSR(IP2_28_26
, MSIOF2_SYNC
),
936 PINMUX_IPSR_MSEL(IP2_28_26
, VI0_R6
, SEL_VI0_0
),
937 PINMUX_IPSR_MSEL(IP2_28_26
, VI0_R6_B
, SEL_VI0_1
),
938 PINMUX_IPSR_MSEL(IP2_28_26
, VI2_DATA2_VI2_B2_B
, SEL_VI2_1
),
940 PINMUX_IPSR_GPSR(IP3_3_0
, A11
),
941 PINMUX_IPSR_MSEL(IP3_3_0
, SCIFB2_CTS_N_B
, SEL_SCIFB2_1
),
942 PINMUX_IPSR_GPSR(IP3_3_0
, MSIOF2_SCK
),
943 PINMUX_IPSR_MSEL(IP3_3_0
, VI1_R0
, SEL_VI1_0
),
944 PINMUX_IPSR_MSEL(IP3_3_0
, VI1_R0_B
, SEL_VI1_1
),
945 PINMUX_IPSR_GPSR(IP3_3_0
, VI2_G0
),
946 PINMUX_IPSR_MSEL(IP3_3_0
, VI2_DATA3_VI2_B3_B
, SEL_VI2_1
),
947 PINMUX_IPSR_GPSR(IP3_7_4
, A12
),
948 PINMUX_IPSR_MSEL(IP3_7_4
, SCIFB2_RXD_B
, SEL_SCIFB2_1
),
949 PINMUX_IPSR_GPSR(IP3_7_4
, MSIOF2_TXD
),
950 PINMUX_IPSR_MSEL(IP3_7_4
, VI1_R1
, SEL_VI1_0
),
951 PINMUX_IPSR_MSEL(IP3_7_4
, VI1_R1_B
, SEL_VI1_1
),
952 PINMUX_IPSR_GPSR(IP3_7_4
, VI2_G1
),
953 PINMUX_IPSR_MSEL(IP3_7_4
, VI2_DATA4_VI2_B4_B
, SEL_VI2_1
),
954 PINMUX_IPSR_GPSR(IP3_11_8
, A13
),
955 PINMUX_IPSR_MSEL(IP3_11_8
, SCIFB2_RTS_N_B
, SEL_SCIFB2_1
),
956 PINMUX_IPSR_GPSR(IP3_11_8
, EX_WAIT2
),
957 PINMUX_IPSR_GPSR(IP3_11_8
, MSIOF2_RXD
),
958 PINMUX_IPSR_MSEL(IP3_11_8
, VI1_R2
, SEL_VI1_0
),
959 PINMUX_IPSR_MSEL(IP3_11_8
, VI1_R2_B
, SEL_VI1_1
),
960 PINMUX_IPSR_GPSR(IP3_11_8
, VI2_G2
),
961 PINMUX_IPSR_MSEL(IP3_11_8
, VI2_DATA5_VI2_B5_B
, SEL_VI2_1
),
962 PINMUX_IPSR_GPSR(IP3_14_12
, A14
),
963 PINMUX_IPSR_MSEL(IP3_14_12
, SCIFB2_TXD_B
, SEL_SCIFB2_1
),
964 PINMUX_IPSR_GPSR(IP3_14_12
, ATACS11_N
),
965 PINMUX_IPSR_GPSR(IP3_14_12
, MSIOF2_SS1
),
966 PINMUX_IPSR_GPSR(IP3_17_15
, A15
),
967 PINMUX_IPSR_MSEL(IP3_17_15
, SCIFB2_SCK_B
, SEL_SCIFB2_1
),
968 PINMUX_IPSR_GPSR(IP3_17_15
, ATARD1_N
),
969 PINMUX_IPSR_GPSR(IP3_17_15
, MSIOF2_SS2
),
970 PINMUX_IPSR_GPSR(IP3_19_18
, A16
),
971 PINMUX_IPSR_GPSR(IP3_19_18
, ATAWR1_N
),
972 PINMUX_IPSR_GPSR(IP3_22_20
, A17
),
973 PINMUX_IPSR_MSEL(IP3_22_20
, AD_DO_B
, SEL_ADI_1
),
974 PINMUX_IPSR_GPSR(IP3_22_20
, ATADIR1_N
),
975 PINMUX_IPSR_GPSR(IP3_25_23
, A18
),
976 PINMUX_IPSR_MSEL(IP3_25_23
, AD_CLK_B
, SEL_ADI_1
),
977 PINMUX_IPSR_GPSR(IP3_25_23
, ATAG1_N
),
978 PINMUX_IPSR_GPSR(IP3_28_26
, A19
),
979 PINMUX_IPSR_MSEL(IP3_28_26
, AD_NCS_N_B
, SEL_ADI_1
),
980 PINMUX_IPSR_GPSR(IP3_28_26
, ATACS01_N
),
981 PINMUX_IPSR_MSEL(IP3_28_26
, EX_WAIT0_B
, SEL_LBS_1
),
982 PINMUX_IPSR_GPSR(IP3_31_29
, A20
),
983 PINMUX_IPSR_GPSR(IP3_31_29
, SPCLK
),
984 PINMUX_IPSR_MSEL(IP3_31_29
, VI1_R3
, SEL_VI1_0
),
985 PINMUX_IPSR_MSEL(IP3_31_29
, VI1_R3_B
, SEL_VI1_1
),
986 PINMUX_IPSR_GPSR(IP3_31_29
, VI2_G4
),
988 PINMUX_IPSR_GPSR(IP4_2_0
, A21
),
989 PINMUX_IPSR_GPSR(IP4_2_0
, MOSI_IO0
),
990 PINMUX_IPSR_MSEL(IP4_2_0
, VI1_R4
, SEL_VI1_0
),
991 PINMUX_IPSR_MSEL(IP4_2_0
, VI1_R4_B
, SEL_VI1_1
),
992 PINMUX_IPSR_GPSR(IP4_2_0
, VI2_G5
),
993 PINMUX_IPSR_GPSR(IP4_5_3
, A22
),
994 PINMUX_IPSR_GPSR(IP4_5_3
, MISO_IO1
),
995 PINMUX_IPSR_MSEL(IP4_5_3
, VI1_R5
, SEL_VI1_0
),
996 PINMUX_IPSR_MSEL(IP4_5_3
, VI1_R5_B
, SEL_VI1_1
),
997 PINMUX_IPSR_GPSR(IP4_5_3
, VI2_G6
),
998 PINMUX_IPSR_GPSR(IP4_8_6
, A23
),
999 PINMUX_IPSR_GPSR(IP4_8_6
, IO2
),
1000 PINMUX_IPSR_MSEL(IP4_8_6
, VI1_G7
, SEL_VI1_0
),
1001 PINMUX_IPSR_MSEL(IP4_8_6
, VI1_G7_B
, SEL_VI1_1
),
1002 PINMUX_IPSR_GPSR(IP4_8_6
, VI2_G7
),
1003 PINMUX_IPSR_GPSR(IP4_11_9
, A24
),
1004 PINMUX_IPSR_GPSR(IP4_11_9
, IO3
),
1005 PINMUX_IPSR_MSEL(IP4_11_9
, VI1_R7
, SEL_VI1_0
),
1006 PINMUX_IPSR_MSEL(IP4_11_9
, VI1_R7_B
, SEL_VI1_1
),
1007 PINMUX_IPSR_MSEL(IP4_11_9
, VI2_CLKENB
, SEL_VI2_0
),
1008 PINMUX_IPSR_MSEL(IP4_11_9
, VI2_CLKENB_B
, SEL_VI2_1
),
1009 PINMUX_IPSR_GPSR(IP4_14_12
, A25
),
1010 PINMUX_IPSR_GPSR(IP4_14_12
, SSL
),
1011 PINMUX_IPSR_MSEL(IP4_14_12
, VI1_G6
, SEL_VI1_0
),
1012 PINMUX_IPSR_MSEL(IP4_14_12
, VI1_G6_B
, SEL_VI1_1
),
1013 PINMUX_IPSR_MSEL(IP4_14_12
, VI2_FIELD
, SEL_VI2_0
),
1014 PINMUX_IPSR_MSEL(IP4_14_12
, VI2_FIELD_B
, SEL_VI2_1
),
1015 PINMUX_IPSR_GPSR(IP4_17_15
, CS0_N
),
1016 PINMUX_IPSR_MSEL(IP4_17_15
, VI1_R6
, SEL_VI1_0
),
1017 PINMUX_IPSR_MSEL(IP4_17_15
, VI1_R6_B
, SEL_VI1_1
),
1018 PINMUX_IPSR_GPSR(IP4_17_15
, VI2_G3
),
1019 PINMUX_IPSR_MSEL(IP4_17_15
, MSIOF0_SS2_B
, SEL_SOF0_1
),
1020 PINMUX_IPSR_GPSR(IP4_20_18
, CS1_N_A26
),
1021 PINMUX_IPSR_GPSR(IP4_20_18
, SPEEDIN
),
1022 PINMUX_IPSR_MSEL(IP4_20_18
, VI0_R7
, SEL_VI0_0
),
1023 PINMUX_IPSR_MSEL(IP4_20_18
, VI0_R7_B
, SEL_VI0_1
),
1024 PINMUX_IPSR_MSEL(IP4_20_18
, VI2_CLK
, SEL_VI2_0
),
1025 PINMUX_IPSR_MSEL(IP4_20_18
, VI2_CLK_B
, SEL_VI2_1
),
1026 PINMUX_IPSR_GPSR(IP4_23_21
, EX_CS0_N
),
1027 PINMUX_IPSR_MSEL(IP4_23_21
, HRX1_B
, SEL_HSCIF1_1
),
1028 PINMUX_IPSR_MSEL(IP4_23_21
, VI1_G5
, SEL_VI1_0
),
1029 PINMUX_IPSR_MSEL(IP4_23_21
, VI1_G5_B
, SEL_VI1_1
),
1030 PINMUX_IPSR_GPSR(IP4_23_21
, VI2_R0
),
1031 PINMUX_IPSR_MSEL(IP4_23_21
, HTX0_B
, SEL_HSCIF0_1
),
1032 PINMUX_IPSR_MSEL(IP4_23_21
, MSIOF0_SS1_B
, SEL_SOF0_1
),
1033 PINMUX_IPSR_GPSR(IP4_26_24
, EX_CS1_N
),
1034 PINMUX_IPSR_GPSR(IP4_26_24
, GPS_CLK
),
1035 PINMUX_IPSR_MSEL(IP4_26_24
, HCTS1_N_B
, SEL_HSCIF1_1
),
1036 PINMUX_IPSR_MSEL(IP4_26_24
, VI1_FIELD
, SEL_VI1_0
),
1037 PINMUX_IPSR_MSEL(IP4_26_24
, VI1_FIELD_B
, SEL_VI1_1
),
1038 PINMUX_IPSR_GPSR(IP4_26_24
, VI2_R1
),
1039 PINMUX_IPSR_GPSR(IP4_29_27
, EX_CS2_N
),
1040 PINMUX_IPSR_GPSR(IP4_29_27
, GPS_SIGN
),
1041 PINMUX_IPSR_MSEL(IP4_29_27
, HRTS1_N_B
, SEL_HSCIF1_1
),
1042 PINMUX_IPSR_GPSR(IP4_29_27
, VI3_CLKENB
),
1043 PINMUX_IPSR_MSEL(IP4_29_27
, VI1_G0
, SEL_VI1_0
),
1044 PINMUX_IPSR_MSEL(IP4_29_27
, VI1_G0_B
, SEL_VI1_1
),
1045 PINMUX_IPSR_GPSR(IP4_29_27
, VI2_R2
),
1047 PINMUX_IPSR_GPSR(IP5_2_0
, EX_CS3_N
),
1048 PINMUX_IPSR_GPSR(IP5_2_0
, GPS_MAG
),
1049 PINMUX_IPSR_GPSR(IP5_2_0
, VI3_FIELD
),
1050 PINMUX_IPSR_MSEL(IP5_2_0
, VI1_G1
, SEL_VI1_0
),
1051 PINMUX_IPSR_MSEL(IP5_2_0
, VI1_G1_B
, SEL_VI1_1
),
1052 PINMUX_IPSR_GPSR(IP5_2_0
, VI2_R3
),
1053 PINMUX_IPSR_GPSR(IP5_5_3
, EX_CS4_N
),
1054 PINMUX_IPSR_MSEL(IP5_5_3
, MSIOF1_SCK_B
, SEL_SOF1_1
),
1055 PINMUX_IPSR_GPSR(IP5_5_3
, VI3_HSYNC_N
),
1056 PINMUX_IPSR_MSEL(IP5_5_3
, VI2_HSYNC_N
, SEL_VI2_0
),
1057 PINMUX_IPSR_MSEL(IP5_5_3
, IIC1_SCL
, SEL_IIC1_0
),
1058 PINMUX_IPSR_MSEL(IP5_5_3
, VI2_HSYNC_N_B
, SEL_VI2_1
),
1059 PINMUX_IPSR_GPSR(IP5_5_3
, INTC_EN0_N
),
1060 PINMUX_IPSR_MSEL(IP5_5_3
, I2C1_SCL
, SEL_I2C1_0
),
1061 PINMUX_IPSR_GPSR(IP5_9_6
, EX_CS5_N
),
1062 PINMUX_IPSR_MSEL(IP5_9_6
, CAN0_RX
, SEL_CAN0_0
),
1063 PINMUX_IPSR_MSEL(IP5_9_6
, MSIOF1_RXD_B
, SEL_SOF1_1
),
1064 PINMUX_IPSR_GPSR(IP5_9_6
, VI3_VSYNC_N
),
1065 PINMUX_IPSR_MSEL(IP5_9_6
, VI1_G2
, SEL_VI1_0
),
1066 PINMUX_IPSR_MSEL(IP5_9_6
, VI1_G2_B
, SEL_VI1_1
),
1067 PINMUX_IPSR_GPSR(IP5_9_6
, VI2_R4
),
1068 PINMUX_IPSR_MSEL(IP5_9_6
, IIC1_SDA
, SEL_IIC1_0
),
1069 PINMUX_IPSR_GPSR(IP5_9_6
, INTC_EN1_N
),
1070 PINMUX_IPSR_MSEL(IP5_9_6
, I2C1_SDA
, SEL_I2C1_0
),
1071 PINMUX_IPSR_GPSR(IP5_12_10
, BS_N
),
1072 PINMUX_IPSR_MSEL(IP5_12_10
, IETX
, SEL_IEB_0
),
1073 PINMUX_IPSR_MSEL(IP5_12_10
, HTX1_B
, SEL_HSCIF1_1
),
1074 PINMUX_IPSR_MSEL(IP5_12_10
, CAN1_TX
, SEL_CAN1_0
),
1075 PINMUX_IPSR_GPSR(IP5_12_10
, DRACK0
),
1076 PINMUX_IPSR_MSEL(IP5_12_10
, IETX_C
, SEL_IEB_2
),
1077 PINMUX_IPSR_GPSR(IP5_14_13
, RD_N
),
1078 PINMUX_IPSR_MSEL(IP5_14_13
, CAN0_TX
, SEL_CAN0_0
),
1079 PINMUX_IPSR_MSEL(IP5_14_13
, SCIFA0_SCK_B
, SEL_SCFA_1
),
1080 PINMUX_IPSR_GPSR(IP5_17_15
, RD_WR_N
),
1081 PINMUX_IPSR_MSEL(IP5_17_15
, VI1_G3
, SEL_VI1_0
),
1082 PINMUX_IPSR_MSEL(IP5_17_15
, VI1_G3_B
, SEL_VI1_1
),
1083 PINMUX_IPSR_GPSR(IP5_17_15
, VI2_R5
),
1084 PINMUX_IPSR_MSEL(IP5_17_15
, SCIFA0_RXD_B
, SEL_SCFA_1
),
1085 PINMUX_IPSR_GPSR(IP5_17_15
, INTC_IRQ4_N
),
1086 PINMUX_IPSR_GPSR(IP5_20_18
, WE0_N
),
1087 PINMUX_IPSR_MSEL(IP5_20_18
, IECLK
, SEL_IEB_0
),
1088 PINMUX_IPSR_MSEL(IP5_20_18
, CAN_CLK
, SEL_CANCLK_0
),
1089 PINMUX_IPSR_MSEL(IP5_20_18
, VI2_VSYNC_N
, SEL_VI2_0
),
1090 PINMUX_IPSR_MSEL(IP5_20_18
, SCIFA0_TXD_B
, SEL_SCFA_1
),
1091 PINMUX_IPSR_MSEL(IP5_20_18
, VI2_VSYNC_N_B
, SEL_VI2_1
),
1092 PINMUX_IPSR_GPSR(IP5_23_21
, WE1_N
),
1093 PINMUX_IPSR_MSEL(IP5_23_21
, IERX
, SEL_IEB_0
),
1094 PINMUX_IPSR_MSEL(IP5_23_21
, CAN1_RX
, SEL_CAN1_0
),
1095 PINMUX_IPSR_MSEL(IP5_23_21
, VI1_G4
, SEL_VI1_0
),
1096 PINMUX_IPSR_MSEL(IP5_23_21
, VI1_G4_B
, SEL_VI1_1
),
1097 PINMUX_IPSR_GPSR(IP5_23_21
, VI2_R6
),
1098 PINMUX_IPSR_MSEL(IP5_23_21
, SCIFA0_CTS_N_B
, SEL_SCFA_1
),
1099 PINMUX_IPSR_MSEL(IP5_23_21
, IERX_C
, SEL_IEB_2
),
1100 PINMUX_IPSR_MSEL(IP5_26_24
, EX_WAIT0
, SEL_LBS_0
),
1101 PINMUX_IPSR_GPSR(IP5_26_24
, IRQ3
),
1102 PINMUX_IPSR_GPSR(IP5_26_24
, INTC_IRQ3_N
),
1103 PINMUX_IPSR_MSEL(IP5_26_24
, VI3_CLK
, SEL_VI3_0
),
1104 PINMUX_IPSR_MSEL(IP5_26_24
, SCIFA0_RTS_N_B
, SEL_SCFA_1
),
1105 PINMUX_IPSR_MSEL(IP5_26_24
, HRX0_B
, SEL_HSCIF0_1
),
1106 PINMUX_IPSR_MSEL(IP5_26_24
, MSIOF0_SCK_B
, SEL_SOF0_1
),
1107 PINMUX_IPSR_GPSR(IP5_29_27
, DREQ0_N
),
1108 PINMUX_IPSR_MSEL(IP5_29_27
, VI1_HSYNC_N
, SEL_VI1_0
),
1109 PINMUX_IPSR_MSEL(IP5_29_27
, VI1_HSYNC_N_B
, SEL_VI1_1
),
1110 PINMUX_IPSR_GPSR(IP5_29_27
, VI2_R7
),
1111 PINMUX_IPSR_MSEL(IP5_29_27
, SSI_SCK78_C
, SEL_SSI7_2
),
1112 PINMUX_IPSR_MSEL(IP5_29_27
, SSI_WS78_B
, SEL_SSI7_1
),
1114 PINMUX_IPSR_GPSR(IP6_2_0
, DACK0
),
1115 PINMUX_IPSR_GPSR(IP6_2_0
, IRQ0
),
1116 PINMUX_IPSR_GPSR(IP6_2_0
, INTC_IRQ0_N
),
1117 PINMUX_IPSR_MSEL(IP6_2_0
, SSI_SCK6_B
, SEL_SSI6_1
),
1118 PINMUX_IPSR_MSEL(IP6_2_0
, VI1_VSYNC_N
, SEL_VI1_0
),
1119 PINMUX_IPSR_MSEL(IP6_2_0
, VI1_VSYNC_N_B
, SEL_VI1_1
),
1120 PINMUX_IPSR_MSEL(IP6_2_0
, SSI_WS78_C
, SEL_SSI7_2
),
1121 PINMUX_IPSR_GPSR(IP6_5_3
, DREQ1_N
),
1122 PINMUX_IPSR_MSEL(IP6_5_3
, VI1_CLKENB
, SEL_VI1_0
),
1123 PINMUX_IPSR_MSEL(IP6_5_3
, VI1_CLKENB_B
, SEL_VI1_1
),
1124 PINMUX_IPSR_MSEL(IP6_5_3
, SSI_SDATA7_C
, SEL_SSI7_2
),
1125 PINMUX_IPSR_MSEL(IP6_5_3
, SSI_SCK78_B
, SEL_SSI7_1
),
1126 PINMUX_IPSR_GPSR(IP6_8_6
, DACK1
),
1127 PINMUX_IPSR_GPSR(IP6_8_6
, IRQ1
),
1128 PINMUX_IPSR_GPSR(IP6_8_6
, INTC_IRQ1_N
),
1129 PINMUX_IPSR_MSEL(IP6_8_6
, SSI_WS6_B
, SEL_SSI6_1
),
1130 PINMUX_IPSR_MSEL(IP6_8_6
, SSI_SDATA8_C
, SEL_SSI8_2
),
1131 PINMUX_IPSR_GPSR(IP6_10_9
, DREQ2_N
),
1132 PINMUX_IPSR_MSEL(IP6_10_9
, HSCK1_B
, SEL_HSCIF1_1
),
1133 PINMUX_IPSR_MSEL(IP6_10_9
, HCTS0_N_B
, SEL_HSCIF0_1
),
1134 PINMUX_IPSR_MSEL(IP6_10_9
, MSIOF0_TXD_B
, SEL_SOF0_1
),
1135 PINMUX_IPSR_GPSR(IP6_13_11
, DACK2
),
1136 PINMUX_IPSR_GPSR(IP6_13_11
, IRQ2
),
1137 PINMUX_IPSR_GPSR(IP6_13_11
, INTC_IRQ2_N
),
1138 PINMUX_IPSR_MSEL(IP6_13_11
, SSI_SDATA6_B
, SEL_SSI6_1
),
1139 PINMUX_IPSR_MSEL(IP6_13_11
, HRTS0_N_B
, SEL_HSCIF0_1
),
1140 PINMUX_IPSR_MSEL(IP6_13_11
, MSIOF0_RXD_B
, SEL_SOF0_1
),
1141 PINMUX_IPSR_GPSR(IP6_16_14
, ETH_CRS_DV
),
1142 PINMUX_IPSR_MSEL(IP6_16_14
, STP_ISCLK_0_B
, SEL_SSP_1
),
1143 PINMUX_IPSR_MSEL(IP6_16_14
, TS_SDEN0_D
, SEL_TSIF0_3
),
1144 PINMUX_IPSR_MSEL(IP6_16_14
, GLO_Q0_C
, SEL_GPS_2
),
1145 PINMUX_IPSR_MSEL(IP6_16_14
, IIC2_SCL_E
, SEL_IIC2_4
),
1146 PINMUX_IPSR_MSEL(IP6_16_14
, I2C2_SCL_E
, SEL_I2C2_4
),
1147 PINMUX_IPSR_GPSR(IP6_19_17
, ETH_RX_ER
),
1148 PINMUX_IPSR_MSEL(IP6_19_17
, STP_ISD_0_B
, SEL_SSP_1
),
1149 PINMUX_IPSR_MSEL(IP6_19_17
, TS_SPSYNC0_D
, SEL_TSIF0_3
),
1150 PINMUX_IPSR_MSEL(IP6_19_17
, GLO_Q1_C
, SEL_GPS_2
),
1151 PINMUX_IPSR_MSEL(IP6_19_17
, IIC2_SDA_E
, SEL_IIC2_4
),
1152 PINMUX_IPSR_MSEL(IP6_19_17
, I2C2_SDA_E
, SEL_I2C2_4
),
1153 PINMUX_IPSR_GPSR(IP6_22_20
, ETH_RXD0
),
1154 PINMUX_IPSR_MSEL(IP6_22_20
, STP_ISEN_0_B
, SEL_SSP_1
),
1155 PINMUX_IPSR_MSEL(IP6_22_20
, TS_SDAT0_D
, SEL_TSIF0_3
),
1156 PINMUX_IPSR_MSEL(IP6_22_20
, GLO_I0_C
, SEL_GPS_2
),
1157 PINMUX_IPSR_MSEL(IP6_22_20
, SCIFB1_SCK_G
, SEL_SCIFB1_6
),
1158 PINMUX_IPSR_MSEL(IP6_22_20
, SCK1_E
, SEL_SCIF1_4
),
1159 PINMUX_IPSR_GPSR(IP6_25_23
, ETH_RXD1
),
1160 PINMUX_IPSR_MSEL(IP6_25_23
, HRX0_E
, SEL_HSCIF0_4
),
1161 PINMUX_IPSR_MSEL(IP6_25_23
, STP_ISSYNC_0_B
, SEL_SSP_1
),
1162 PINMUX_IPSR_MSEL(IP6_25_23
, TS_SCK0_D
, SEL_TSIF0_3
),
1163 PINMUX_IPSR_MSEL(IP6_25_23
, GLO_I1_C
, SEL_GPS_2
),
1164 PINMUX_IPSR_MSEL(IP6_25_23
, SCIFB1_RXD_G
, SEL_SCIFB1_6
),
1165 PINMUX_IPSR_MSEL(IP6_25_23
, RX1_E
, SEL_SCIF1_4
),
1166 PINMUX_IPSR_GPSR(IP6_28_26
, ETH_LINK
),
1167 PINMUX_IPSR_MSEL(IP6_28_26
, HTX0_E
, SEL_HSCIF0_4
),
1168 PINMUX_IPSR_MSEL(IP6_28_26
, STP_IVCXO27_0_B
, SEL_SSP_1
),
1169 PINMUX_IPSR_MSEL(IP6_28_26
, SCIFB1_TXD_G
, SEL_SCIFB1_6
),
1170 PINMUX_IPSR_MSEL(IP6_28_26
, TX1_E
, SEL_SCIF1_4
),
1171 PINMUX_IPSR_GPSR(IP6_31_29
, ETH_REF_CLK
),
1172 PINMUX_IPSR_MSEL(IP6_31_29
, HCTS0_N_E
, SEL_HSCIF0_4
),
1173 PINMUX_IPSR_MSEL(IP6_31_29
, STP_IVCXO27_1_B
, SEL_SSP_1
),
1174 PINMUX_IPSR_MSEL(IP6_31_29
, HRX0_F
, SEL_HSCIF0_5
),
1176 PINMUX_IPSR_GPSR(IP7_2_0
, ETH_MDIO
),
1177 PINMUX_IPSR_MSEL(IP7_2_0
, HRTS0_N_E
, SEL_HSCIF0_4
),
1178 PINMUX_IPSR_MSEL(IP7_2_0
, SIM0_D_C
, SEL_SIM_2
),
1179 PINMUX_IPSR_MSEL(IP7_2_0
, HCTS0_N_F
, SEL_HSCIF0_5
),
1180 PINMUX_IPSR_GPSR(IP7_5_3
, ETH_TXD1
),
1181 PINMUX_IPSR_MSEL(IP7_5_3
, HTX0_F
, SEL_HSCIF0_5
),
1182 PINMUX_IPSR_MSEL(IP7_5_3
, BPFCLK_G
, SEL_FM_6
),
1183 PINMUX_IPSR_GPSR(IP7_7_6
, ETH_TX_EN
),
1184 PINMUX_IPSR_MSEL(IP7_7_6
, SIM0_CLK_C
, SEL_SIM_2
),
1185 PINMUX_IPSR_MSEL(IP7_7_6
, HRTS0_N_F
, SEL_HSCIF0_5
),
1186 PINMUX_IPSR_GPSR(IP7_9_8
, ETH_MAGIC
),
1187 PINMUX_IPSR_MSEL(IP7_9_8
, SIM0_RST_C
, SEL_SIM_2
),
1188 PINMUX_IPSR_GPSR(IP7_12_10
, ETH_TXD0
),
1189 PINMUX_IPSR_MSEL(IP7_12_10
, STP_ISCLK_1_B
, SEL_SSP_1
),
1190 PINMUX_IPSR_MSEL(IP7_12_10
, TS_SDEN1_C
, SEL_TSIF1_2
),
1191 PINMUX_IPSR_MSEL(IP7_12_10
, GLO_SCLK_C
, SEL_GPS_2
),
1192 PINMUX_IPSR_GPSR(IP7_15_13
, ETH_MDC
),
1193 PINMUX_IPSR_MSEL(IP7_15_13
, STP_ISD_1_B
, SEL_SSP_1
),
1194 PINMUX_IPSR_MSEL(IP7_15_13
, TS_SPSYNC1_C
, SEL_TSIF1_2
),
1195 PINMUX_IPSR_MSEL(IP7_15_13
, GLO_SDATA_C
, SEL_GPS_2
),
1196 PINMUX_IPSR_GPSR(IP7_18_16
, PWM0
),
1197 PINMUX_IPSR_MSEL(IP7_18_16
, SCIFA2_SCK_C
, SEL_SCIFA2_2
),
1198 PINMUX_IPSR_MSEL(IP7_18_16
, STP_ISEN_1_B
, SEL_SSP_1
),
1199 PINMUX_IPSR_MSEL(IP7_18_16
, TS_SDAT1_C
, SEL_TSIF1_2
),
1200 PINMUX_IPSR_MSEL(IP7_18_16
, GLO_SS_C
, SEL_GPS_2
),
1201 PINMUX_IPSR_GPSR(IP7_21_19
, PWM1
),
1202 PINMUX_IPSR_MSEL(IP7_21_19
, SCIFA2_TXD_C
, SEL_SCIFA2_2
),
1203 PINMUX_IPSR_MSEL(IP7_21_19
, STP_ISSYNC_1_B
, SEL_SSP_1
),
1204 PINMUX_IPSR_MSEL(IP7_21_19
, TS_SCK1_C
, SEL_TSIF1_2
),
1205 PINMUX_IPSR_MSEL(IP7_21_19
, GLO_RFON_C
, SEL_GPS_2
),
1206 PINMUX_IPSR_GPSR(IP7_21_19
, PCMOE_N
),
1207 PINMUX_IPSR_GPSR(IP7_24_22
, PWM2
),
1208 PINMUX_IPSR_GPSR(IP7_24_22
, PWMFSW0
),
1209 PINMUX_IPSR_MSEL(IP7_24_22
, SCIFA2_RXD_C
, SEL_SCIFA2_2
),
1210 PINMUX_IPSR_GPSR(IP7_24_22
, PCMWE_N
),
1211 PINMUX_IPSR_MSEL(IP7_24_22
, IECLK_C
, SEL_IEB_2
),
1212 PINMUX_IPSR_GPSR(IP7_26_25
, DU_DOTCLKIN1
),
1213 PINMUX_IPSR_GPSR(IP7_26_25
, AUDIO_CLKC
),
1214 PINMUX_IPSR_GPSR(IP7_26_25
, AUDIO_CLKOUT_C
),
1215 PINMUX_IPSR_MSEL(IP7_28_27
, VI0_CLK
, SEL_VI0_0
),
1216 PINMUX_IPSR_GPSR(IP7_28_27
, ATACS00_N
),
1217 PINMUX_IPSR_GPSR(IP7_28_27
, AVB_RXD1
),
1218 PINMUX_IPSR_MSEL(IP7_30_29
, VI0_DATA0_VI0_B0
, SEL_VI0_0
),
1219 PINMUX_IPSR_GPSR(IP7_30_29
, ATACS10_N
),
1220 PINMUX_IPSR_GPSR(IP7_30_29
, AVB_RXD2
),
1222 PINMUX_IPSR_MSEL(IP8_1_0
, VI0_DATA1_VI0_B1
, SEL_VI0_0
),
1223 PINMUX_IPSR_GPSR(IP8_1_0
, ATARD0_N
),
1224 PINMUX_IPSR_GPSR(IP8_1_0
, AVB_RXD3
),
1225 PINMUX_IPSR_MSEL(IP8_3_2
, VI0_DATA2_VI0_B2
, SEL_VI0_0
),
1226 PINMUX_IPSR_GPSR(IP8_3_2
, ATAWR0_N
),
1227 PINMUX_IPSR_GPSR(IP8_3_2
, AVB_RXD4
),
1228 PINMUX_IPSR_MSEL(IP8_5_4
, VI0_DATA3_VI0_B3
, SEL_VI0_0
),
1229 PINMUX_IPSR_GPSR(IP8_5_4
, ATADIR0_N
),
1230 PINMUX_IPSR_GPSR(IP8_5_4
, AVB_RXD5
),
1231 PINMUX_IPSR_MSEL(IP8_7_6
, VI0_DATA4_VI0_B4
, SEL_VI0_0
),
1232 PINMUX_IPSR_GPSR(IP8_7_6
, ATAG0_N
),
1233 PINMUX_IPSR_GPSR(IP8_7_6
, AVB_RXD6
),
1234 PINMUX_IPSR_MSEL(IP8_9_8
, VI0_DATA5_VI0_B5
, SEL_VI0_0
),
1235 PINMUX_IPSR_GPSR(IP8_9_8
, EX_WAIT1
),
1236 PINMUX_IPSR_GPSR(IP8_9_8
, AVB_RXD7
),
1237 PINMUX_IPSR_MSEL(IP8_11_10
, VI0_DATA6_VI0_B6
, SEL_VI0_0
),
1238 PINMUX_IPSR_GPSR(IP8_11_10
, AVB_RX_ER
),
1239 PINMUX_IPSR_MSEL(IP8_13_12
, VI0_DATA7_VI0_B7
, SEL_VI0_0
),
1240 PINMUX_IPSR_GPSR(IP8_13_12
, AVB_RX_CLK
),
1241 PINMUX_IPSR_MSEL(IP8_15_14
, VI1_CLK
, SEL_VI1_0
),
1242 PINMUX_IPSR_GPSR(IP8_15_14
, AVB_RX_DV
),
1243 PINMUX_IPSR_MSEL(IP8_17_16
, VI1_DATA0_VI1_B0
, SEL_VI1_0
),
1244 PINMUX_IPSR_MSEL(IP8_17_16
, SCIFA1_SCK_D
, SEL_SCIFA1_3
),
1245 PINMUX_IPSR_GPSR(IP8_17_16
, AVB_CRS
),
1246 PINMUX_IPSR_MSEL(IP8_19_18
, VI1_DATA1_VI1_B1
, SEL_VI1_0
),
1247 PINMUX_IPSR_MSEL(IP8_19_18
, SCIFA1_RXD_D
, SEL_SCIFA1_3
),
1248 PINMUX_IPSR_GPSR(IP8_19_18
, AVB_MDC
),
1249 PINMUX_IPSR_MSEL(IP8_21_20
, VI1_DATA2_VI1_B2
, SEL_VI1_0
),
1250 PINMUX_IPSR_MSEL(IP8_21_20
, SCIFA1_TXD_D
, SEL_SCIFA1_3
),
1251 PINMUX_IPSR_GPSR(IP8_21_20
, AVB_MDIO
),
1252 PINMUX_IPSR_MSEL(IP8_23_22
, VI1_DATA3_VI1_B3
, SEL_VI1_0
),
1253 PINMUX_IPSR_MSEL(IP8_23_22
, SCIFA1_CTS_N_D
, SEL_SCIFA1_3
),
1254 PINMUX_IPSR_GPSR(IP8_23_22
, AVB_GTX_CLK
),
1255 PINMUX_IPSR_MSEL(IP8_25_24
, VI1_DATA4_VI1_B4
, SEL_VI1_0
),
1256 PINMUX_IPSR_MSEL(IP8_25_24
, SCIFA1_RTS_N_D
, SEL_SCIFA1_3
),
1257 PINMUX_IPSR_GPSR(IP8_25_24
, AVB_MAGIC
),
1258 PINMUX_IPSR_MSEL(IP8_26
, VI1_DATA5_VI1_B5
, SEL_VI1_0
),
1259 PINMUX_IPSR_GPSR(IP8_26
, AVB_PHY_INT
),
1260 PINMUX_IPSR_MSEL(IP8_27
, VI1_DATA6_VI1_B6
, SEL_VI1_0
),
1261 PINMUX_IPSR_GPSR(IP8_27
, AVB_GTXREFCLK
),
1262 PINMUX_IPSR_GPSR(IP8_28
, SD0_CLK
),
1263 PINMUX_IPSR_MSEL(IP8_28
, VI1_DATA0_VI1_B0_B
, SEL_VI1_1
),
1264 PINMUX_IPSR_GPSR(IP8_30_29
, SD0_CMD
),
1265 PINMUX_IPSR_MSEL(IP8_30_29
, SCIFB1_SCK_B
, SEL_SCIFB1_1
),
1266 PINMUX_IPSR_MSEL(IP8_30_29
, VI1_DATA1_VI1_B1_B
, SEL_VI1_1
),
1268 PINMUX_IPSR_GPSR(IP9_1_0
, SD0_DAT0
),
1269 PINMUX_IPSR_MSEL(IP9_1_0
, SCIFB1_RXD_B
, SEL_SCIFB1_1
),
1270 PINMUX_IPSR_MSEL(IP9_1_0
, VI1_DATA2_VI1_B2_B
, SEL_VI1_1
),
1271 PINMUX_IPSR_GPSR(IP9_3_2
, SD0_DAT1
),
1272 PINMUX_IPSR_MSEL(IP9_3_2
, SCIFB1_TXD_B
, SEL_SCIFB1_1
),
1273 PINMUX_IPSR_MSEL(IP9_3_2
, VI1_DATA3_VI1_B3_B
, SEL_VI1_1
),
1274 PINMUX_IPSR_GPSR(IP9_5_4
, SD0_DAT2
),
1275 PINMUX_IPSR_MSEL(IP9_5_4
, SCIFB1_CTS_N_B
, SEL_SCIFB1_1
),
1276 PINMUX_IPSR_MSEL(IP9_5_4
, VI1_DATA4_VI1_B4_B
, SEL_VI1_1
),
1277 PINMUX_IPSR_GPSR(IP9_7_6
, SD0_DAT3
),
1278 PINMUX_IPSR_MSEL(IP9_7_6
, SCIFB1_RTS_N_B
, SEL_SCIFB1_1
),
1279 PINMUX_IPSR_MSEL(IP9_7_6
, VI1_DATA5_VI1_B5_B
, SEL_VI1_1
),
1280 PINMUX_IPSR_GPSR(IP9_11_8
, SD0_CD
),
1281 PINMUX_IPSR_GPSR(IP9_11_8
, MMC0_D6
),
1282 PINMUX_IPSR_MSEL(IP9_11_8
, TS_SDEN0_B
, SEL_TSIF0_1
),
1283 PINMUX_IPSR_GPSR(IP9_11_8
, USB0_EXTP
),
1284 PINMUX_IPSR_MSEL(IP9_11_8
, GLO_SCLK
, SEL_GPS_0
),
1285 PINMUX_IPSR_MSEL(IP9_11_8
, VI1_DATA6_VI1_B6_B
, SEL_VI1_1
),
1286 PINMUX_IPSR_MSEL(IP9_11_8
, IIC1_SCL_B
, SEL_IIC1_1
),
1287 PINMUX_IPSR_MSEL(IP9_11_8
, I2C1_SCL_B
, SEL_I2C1_1
),
1288 PINMUX_IPSR_MSEL(IP9_11_8
, VI2_DATA6_VI2_B6_B
, SEL_VI2_1
),
1289 PINMUX_IPSR_GPSR(IP9_15_12
, SD0_WP
),
1290 PINMUX_IPSR_GPSR(IP9_15_12
, MMC0_D7
),
1291 PINMUX_IPSR_MSEL(IP9_15_12
, TS_SPSYNC0_B
, SEL_TSIF0_1
),
1292 PINMUX_IPSR_GPSR(IP9_15_12
, USB0_IDIN
),
1293 PINMUX_IPSR_MSEL(IP9_15_12
, GLO_SDATA
, SEL_GPS_0
),
1294 PINMUX_IPSR_MSEL(IP9_15_12
, VI1_DATA7_VI1_B7_B
, SEL_VI1_1
),
1295 PINMUX_IPSR_MSEL(IP9_15_12
, IIC1_SDA_B
, SEL_IIC1_1
),
1296 PINMUX_IPSR_MSEL(IP9_15_12
, I2C1_SDA_B
, SEL_I2C1_1
),
1297 PINMUX_IPSR_MSEL(IP9_15_12
, VI2_DATA7_VI2_B7_B
, SEL_VI2_1
),
1298 PINMUX_IPSR_GPSR(IP9_17_16
, SD1_CLK
),
1299 PINMUX_IPSR_GPSR(IP9_17_16
, AVB_TX_EN
),
1300 PINMUX_IPSR_GPSR(IP9_19_18
, SD1_CMD
),
1301 PINMUX_IPSR_GPSR(IP9_19_18
, AVB_TX_ER
),
1302 PINMUX_IPSR_MSEL(IP9_19_18
, SCIFB0_SCK_B
, SEL_SCIFB_1
),
1303 PINMUX_IPSR_GPSR(IP9_21_20
, SD1_DAT0
),
1304 PINMUX_IPSR_GPSR(IP9_21_20
, AVB_TX_CLK
),
1305 PINMUX_IPSR_MSEL(IP9_21_20
, SCIFB0_RXD_B
, SEL_SCIFB_1
),
1306 PINMUX_IPSR_GPSR(IP9_23_22
, SD1_DAT1
),
1307 PINMUX_IPSR_GPSR(IP9_23_22
, AVB_LINK
),
1308 PINMUX_IPSR_MSEL(IP9_23_22
, SCIFB0_TXD_B
, SEL_SCIFB_1
),
1309 PINMUX_IPSR_GPSR(IP9_25_24
, SD1_DAT2
),
1310 PINMUX_IPSR_GPSR(IP9_25_24
, AVB_COL
),
1311 PINMUX_IPSR_MSEL(IP9_25_24
, SCIFB0_CTS_N_B
, SEL_SCIFB_1
),
1312 PINMUX_IPSR_GPSR(IP9_27_26
, SD1_DAT3
),
1313 PINMUX_IPSR_GPSR(IP9_27_26
, AVB_RXD0
),
1314 PINMUX_IPSR_MSEL(IP9_27_26
, SCIFB0_RTS_N_B
, SEL_SCIFB_1
),
1315 PINMUX_IPSR_GPSR(IP9_31_28
, SD1_CD
),
1316 PINMUX_IPSR_GPSR(IP9_31_28
, MMC1_D6
),
1317 PINMUX_IPSR_MSEL(IP9_31_28
, TS_SDEN1
, SEL_TSIF1_0
),
1318 PINMUX_IPSR_GPSR(IP9_31_28
, USB1_EXTP
),
1319 PINMUX_IPSR_MSEL(IP9_31_28
, GLO_SS
, SEL_GPS_0
),
1320 PINMUX_IPSR_MSEL(IP9_31_28
, VI0_CLK_B
, SEL_VI0_1
),
1321 PINMUX_IPSR_MSEL(IP9_31_28
, IIC2_SCL_D
, SEL_IIC2_3
),
1322 PINMUX_IPSR_MSEL(IP9_31_28
, I2C2_SCL_D
, SEL_I2C2_3
),
1323 PINMUX_IPSR_MSEL(IP9_31_28
, SIM0_CLK_B
, SEL_SIM_1
),
1324 PINMUX_IPSR_MSEL(IP9_31_28
, VI3_CLK_B
, SEL_VI3_1
),
1326 PINMUX_IPSR_GPSR(IP10_3_0
, SD1_WP
),
1327 PINMUX_IPSR_GPSR(IP10_3_0
, MMC1_D7
),
1328 PINMUX_IPSR_MSEL(IP10_3_0
, TS_SPSYNC1
, SEL_TSIF1_0
),
1329 PINMUX_IPSR_GPSR(IP10_3_0
, USB1_IDIN
),
1330 PINMUX_IPSR_MSEL(IP10_3_0
, GLO_RFON
, SEL_GPS_0
),
1331 PINMUX_IPSR_MSEL(IP10_3_0
, VI1_CLK_B
, SEL_VI1_1
),
1332 PINMUX_IPSR_MSEL(IP10_3_0
, IIC2_SDA_D
, SEL_IIC2_3
),
1333 PINMUX_IPSR_MSEL(IP10_3_0
, I2C2_SDA_D
, SEL_I2C2_3
),
1334 PINMUX_IPSR_MSEL(IP10_3_0
, SIM0_D_B
, SEL_SIM_1
),
1335 PINMUX_IPSR_GPSR(IP10_6_4
, SD2_CLK
),
1336 PINMUX_IPSR_GPSR(IP10_6_4
, MMC0_CLK
),
1337 PINMUX_IPSR_MSEL(IP10_6_4
, SIM0_CLK
, SEL_SIM_0
),
1338 PINMUX_IPSR_MSEL(IP10_6_4
, VI0_DATA0_VI0_B0_B
, SEL_VI0_1
),
1339 PINMUX_IPSR_MSEL(IP10_6_4
, TS_SDEN0_C
, SEL_TSIF0_2
),
1340 PINMUX_IPSR_MSEL(IP10_6_4
, GLO_SCLK_B
, SEL_GPS_1
),
1341 PINMUX_IPSR_MSEL(IP10_6_4
, VI3_DATA0_B
, SEL_VI3_1
),
1342 PINMUX_IPSR_GPSR(IP10_10_7
, SD2_CMD
),
1343 PINMUX_IPSR_GPSR(IP10_10_7
, MMC0_CMD
),
1344 PINMUX_IPSR_MSEL(IP10_10_7
, SIM0_D
, SEL_SIM_0
),
1345 PINMUX_IPSR_MSEL(IP10_10_7
, VI0_DATA1_VI0_B1_B
, SEL_VI0_1
),
1346 PINMUX_IPSR_MSEL(IP10_10_7
, SCIFB1_SCK_E
, SEL_SCIFB1_4
),
1347 PINMUX_IPSR_MSEL(IP10_10_7
, SCK1_D
, SEL_SCIF1_3
),
1348 PINMUX_IPSR_MSEL(IP10_10_7
, TS_SPSYNC0_C
, SEL_TSIF0_2
),
1349 PINMUX_IPSR_MSEL(IP10_10_7
, GLO_SDATA_B
, SEL_GPS_1
),
1350 PINMUX_IPSR_MSEL(IP10_10_7
, VI3_DATA1_B
, SEL_VI3_1
),
1351 PINMUX_IPSR_GPSR(IP10_14_11
, SD2_DAT0
),
1352 PINMUX_IPSR_GPSR(IP10_14_11
, MMC0_D0
),
1353 PINMUX_IPSR_MSEL(IP10_14_11
, FMCLK_B
, SEL_FM_1
),
1354 PINMUX_IPSR_MSEL(IP10_14_11
, VI0_DATA2_VI0_B2_B
, SEL_VI0_1
),
1355 PINMUX_IPSR_MSEL(IP10_14_11
, SCIFB1_RXD_E
, SEL_SCIFB1_4
),
1356 PINMUX_IPSR_MSEL(IP10_14_11
, RX1_D
, SEL_SCIF1_3
),
1357 PINMUX_IPSR_MSEL(IP10_14_11
, TS_SDAT0_C
, SEL_TSIF0_2
),
1358 PINMUX_IPSR_MSEL(IP10_14_11
, GLO_SS_B
, SEL_GPS_1
),
1359 PINMUX_IPSR_MSEL(IP10_14_11
, VI3_DATA2_B
, SEL_VI3_1
),
1360 PINMUX_IPSR_GPSR(IP10_18_15
, SD2_DAT1
),
1361 PINMUX_IPSR_GPSR(IP10_18_15
, MMC0_D1
),
1362 PINMUX_IPSR_MSEL(IP10_18_15
, FMIN_B
, SEL_FM_1
),
1363 PINMUX_IPSR_MSEL(IP10_18_15
, VI0_DATA3_VI0_B3_B
, SEL_VI0_1
),
1364 PINMUX_IPSR_MSEL(IP10_18_15
, SCIFB1_TXD_E
, SEL_SCIFB1_4
),
1365 PINMUX_IPSR_MSEL(IP10_18_15
, TX1_D
, SEL_SCIF1_3
),
1366 PINMUX_IPSR_MSEL(IP10_18_15
, TS_SCK0_C
, SEL_TSIF0_2
),
1367 PINMUX_IPSR_MSEL(IP10_18_15
, GLO_RFON_B
, SEL_GPS_1
),
1368 PINMUX_IPSR_MSEL(IP10_18_15
, VI3_DATA3_B
, SEL_VI3_1
),
1369 PINMUX_IPSR_GPSR(IP10_22_19
, SD2_DAT2
),
1370 PINMUX_IPSR_GPSR(IP10_22_19
, MMC0_D2
),
1371 PINMUX_IPSR_MSEL(IP10_22_19
, BPFCLK_B
, SEL_FM_1
),
1372 PINMUX_IPSR_MSEL(IP10_22_19
, VI0_DATA4_VI0_B4_B
, SEL_VI0_1
),
1373 PINMUX_IPSR_MSEL(IP10_22_19
, HRX0_D
, SEL_HSCIF0_3
),
1374 PINMUX_IPSR_MSEL(IP10_22_19
, TS_SDEN1_B
, SEL_TSIF1_1
),
1375 PINMUX_IPSR_MSEL(IP10_22_19
, GLO_Q0_B
, SEL_GPS_1
),
1376 PINMUX_IPSR_MSEL(IP10_22_19
, VI3_DATA4_B
, SEL_VI3_1
),
1377 PINMUX_IPSR_GPSR(IP10_25_23
, SD2_DAT3
),
1378 PINMUX_IPSR_GPSR(IP10_25_23
, MMC0_D3
),
1379 PINMUX_IPSR_MSEL(IP10_25_23
, SIM0_RST
, SEL_SIM_0
),
1380 PINMUX_IPSR_MSEL(IP10_25_23
, VI0_DATA5_VI0_B5_B
, SEL_VI0_1
),
1381 PINMUX_IPSR_MSEL(IP10_25_23
, HTX0_D
, SEL_HSCIF0_3
),
1382 PINMUX_IPSR_MSEL(IP10_25_23
, TS_SPSYNC1_B
, SEL_TSIF1_1
),
1383 PINMUX_IPSR_MSEL(IP10_25_23
, GLO_Q1_B
, SEL_GPS_1
),
1384 PINMUX_IPSR_MSEL(IP10_25_23
, VI3_DATA5_B
, SEL_VI3_1
),
1385 PINMUX_IPSR_GPSR(IP10_29_26
, SD2_CD
),
1386 PINMUX_IPSR_GPSR(IP10_29_26
, MMC0_D4
),
1387 PINMUX_IPSR_MSEL(IP10_29_26
, TS_SDAT0_B
, SEL_TSIF0_1
),
1388 PINMUX_IPSR_GPSR(IP10_29_26
, USB2_EXTP
),
1389 PINMUX_IPSR_MSEL(IP10_29_26
, GLO_I0
, SEL_GPS_0
),
1390 PINMUX_IPSR_MSEL(IP10_29_26
, VI0_DATA6_VI0_B6_B
, SEL_VI0_1
),
1391 PINMUX_IPSR_MSEL(IP10_29_26
, HCTS0_N_D
, SEL_HSCIF0_3
),
1392 PINMUX_IPSR_MSEL(IP10_29_26
, TS_SDAT1_B
, SEL_TSIF1_1
),
1393 PINMUX_IPSR_MSEL(IP10_29_26
, GLO_I0_B
, SEL_GPS_1
),
1394 PINMUX_IPSR_MSEL(IP10_29_26
, VI3_DATA6_B
, SEL_VI3_1
),
1396 PINMUX_IPSR_GPSR(IP11_3_0
, SD2_WP
),
1397 PINMUX_IPSR_GPSR(IP11_3_0
, MMC0_D5
),
1398 PINMUX_IPSR_MSEL(IP11_3_0
, TS_SCK0_B
, SEL_TSIF0_1
),
1399 PINMUX_IPSR_GPSR(IP11_3_0
, USB2_IDIN
),
1400 PINMUX_IPSR_MSEL(IP11_3_0
, GLO_I1
, SEL_GPS_0
),
1401 PINMUX_IPSR_MSEL(IP11_3_0
, VI0_DATA7_VI0_B7_B
, SEL_VI0_1
),
1402 PINMUX_IPSR_MSEL(IP11_3_0
, HRTS0_N_D
, SEL_HSCIF0_3
),
1403 PINMUX_IPSR_MSEL(IP11_3_0
, TS_SCK1_B
, SEL_TSIF1_1
),
1404 PINMUX_IPSR_MSEL(IP11_3_0
, GLO_I1_B
, SEL_GPS_1
),
1405 PINMUX_IPSR_MSEL(IP11_3_0
, VI3_DATA7_B
, SEL_VI3_1
),
1406 PINMUX_IPSR_GPSR(IP11_4
, SD3_CLK
),
1407 PINMUX_IPSR_GPSR(IP11_4
, MMC1_CLK
),
1408 PINMUX_IPSR_GPSR(IP11_6_5
, SD3_CMD
),
1409 PINMUX_IPSR_GPSR(IP11_6_5
, MMC1_CMD
),
1410 PINMUX_IPSR_GPSR(IP11_6_5
, MTS_N
),
1411 PINMUX_IPSR_GPSR(IP11_8_7
, SD3_DAT0
),
1412 PINMUX_IPSR_GPSR(IP11_8_7
, MMC1_D0
),
1413 PINMUX_IPSR_GPSR(IP11_8_7
, STM_N
),
1414 PINMUX_IPSR_GPSR(IP11_10_9
, SD3_DAT1
),
1415 PINMUX_IPSR_GPSR(IP11_10_9
, MMC1_D1
),
1416 PINMUX_IPSR_GPSR(IP11_10_9
, MDATA
),
1417 PINMUX_IPSR_GPSR(IP11_12_11
, SD3_DAT2
),
1418 PINMUX_IPSR_GPSR(IP11_12_11
, MMC1_D2
),
1419 PINMUX_IPSR_GPSR(IP11_12_11
, SDATA
),
1420 PINMUX_IPSR_GPSR(IP11_14_13
, SD3_DAT3
),
1421 PINMUX_IPSR_GPSR(IP11_14_13
, MMC1_D3
),
1422 PINMUX_IPSR_GPSR(IP11_14_13
, SCKZ
),
1423 PINMUX_IPSR_GPSR(IP11_17_15
, SD3_CD
),
1424 PINMUX_IPSR_GPSR(IP11_17_15
, MMC1_D4
),
1425 PINMUX_IPSR_MSEL(IP11_17_15
, TS_SDAT1
, SEL_TSIF1_0
),
1426 PINMUX_IPSR_GPSR(IP11_17_15
, VSP
),
1427 PINMUX_IPSR_MSEL(IP11_17_15
, GLO_Q0
, SEL_GPS_0
),
1428 PINMUX_IPSR_MSEL(IP11_17_15
, SIM0_RST_B
, SEL_SIM_1
),
1429 PINMUX_IPSR_GPSR(IP11_21_18
, SD3_WP
),
1430 PINMUX_IPSR_GPSR(IP11_21_18
, MMC1_D5
),
1431 PINMUX_IPSR_MSEL(IP11_21_18
, TS_SCK1
, SEL_TSIF1_0
),
1432 PINMUX_IPSR_MSEL(IP11_21_18
, GLO_Q1
, SEL_GPS_0
),
1433 PINMUX_IPSR_MSEL(IP11_21_18
, FMIN_C
, SEL_FM_2
),
1434 PINMUX_IPSR_MSEL(IP11_21_18
, FMIN_E
, SEL_FM_4
),
1435 PINMUX_IPSR_MSEL(IP11_21_18
, FMIN_F
, SEL_FM_5
),
1436 PINMUX_IPSR_GPSR(IP11_23_22
, MLB_CLK
),
1437 PINMUX_IPSR_MSEL(IP11_23_22
, IIC2_SCL_B
, SEL_IIC2_1
),
1438 PINMUX_IPSR_MSEL(IP11_23_22
, I2C2_SCL_B
, SEL_I2C2_1
),
1439 PINMUX_IPSR_GPSR(IP11_26_24
, MLB_SIG
),
1440 PINMUX_IPSR_MSEL(IP11_26_24
, SCIFB1_RXD_D
, SEL_SCIFB1_3
),
1441 PINMUX_IPSR_MSEL(IP11_26_24
, RX1_C
, SEL_SCIF1_2
),
1442 PINMUX_IPSR_MSEL(IP11_26_24
, IIC2_SDA_B
, SEL_IIC2_1
),
1443 PINMUX_IPSR_MSEL(IP11_26_24
, I2C2_SDA_B
, SEL_I2C2_1
),
1444 PINMUX_IPSR_GPSR(IP11_29_27
, MLB_DAT
),
1445 PINMUX_IPSR_MSEL(IP11_29_27
, SCIFB1_TXD_D
, SEL_SCIFB1_3
),
1446 PINMUX_IPSR_MSEL(IP11_29_27
, TX1_C
, SEL_SCIF1_2
),
1447 PINMUX_IPSR_MSEL(IP11_29_27
, BPFCLK_C
, SEL_FM_2
),
1448 PINMUX_IPSR_GPSR(IP11_31_30
, SSI_SCK0129
),
1449 PINMUX_IPSR_MSEL(IP11_31_30
, CAN_CLK_B
, SEL_CANCLK_1
),
1450 PINMUX_IPSR_GPSR(IP11_31_30
, MOUT0
),
1452 PINMUX_IPSR_GPSR(IP12_1_0
, SSI_WS0129
),
1453 PINMUX_IPSR_MSEL(IP12_1_0
, CAN0_TX_B
, SEL_CAN0_1
),
1454 PINMUX_IPSR_GPSR(IP12_1_0
, MOUT1
),
1455 PINMUX_IPSR_GPSR(IP12_3_2
, SSI_SDATA0
),
1456 PINMUX_IPSR_MSEL(IP12_3_2
, CAN0_RX_B
, SEL_CAN0_1
),
1457 PINMUX_IPSR_GPSR(IP12_3_2
, MOUT2
),
1458 PINMUX_IPSR_GPSR(IP12_5_4
, SSI_SDATA1
),
1459 PINMUX_IPSR_MSEL(IP12_5_4
, CAN1_TX_B
, SEL_CAN1_1
),
1460 PINMUX_IPSR_GPSR(IP12_5_4
, MOUT5
),
1461 PINMUX_IPSR_GPSR(IP12_7_6
, SSI_SDATA2
),
1462 PINMUX_IPSR_MSEL(IP12_7_6
, CAN1_RX_B
, SEL_CAN1_1
),
1463 PINMUX_IPSR_GPSR(IP12_7_6
, SSI_SCK1
),
1464 PINMUX_IPSR_GPSR(IP12_7_6
, MOUT6
),
1465 PINMUX_IPSR_GPSR(IP12_10_8
, SSI_SCK34
),
1466 PINMUX_IPSR_GPSR(IP12_10_8
, STP_OPWM_0
),
1467 PINMUX_IPSR_MSEL(IP12_10_8
, SCIFB0_SCK
, SEL_SCIFB_0
),
1468 PINMUX_IPSR_MSEL(IP12_10_8
, MSIOF1_SCK
, SEL_SOF1_0
),
1469 PINMUX_IPSR_GPSR(IP12_10_8
, CAN_DEBUG_HW_TRIGGER
),
1470 PINMUX_IPSR_GPSR(IP12_13_11
, SSI_WS34
),
1471 PINMUX_IPSR_MSEL(IP12_13_11
, STP_IVCXO27_0
, SEL_SSP_0
),
1472 PINMUX_IPSR_MSEL(IP12_13_11
, SCIFB0_RXD
, SEL_SCIFB_0
),
1473 PINMUX_IPSR_GPSR(IP12_13_11
, MSIOF1_SYNC
),
1474 PINMUX_IPSR_GPSR(IP12_13_11
, CAN_STEP0
),
1475 PINMUX_IPSR_GPSR(IP12_16_14
, SSI_SDATA3
),
1476 PINMUX_IPSR_MSEL(IP12_16_14
, STP_ISCLK_0
, SEL_SSP_0
),
1477 PINMUX_IPSR_MSEL(IP12_16_14
, SCIFB0_TXD
, SEL_SCIFB_0
),
1478 PINMUX_IPSR_MSEL(IP12_16_14
, MSIOF1_SS1
, SEL_SOF1_0
),
1479 PINMUX_IPSR_GPSR(IP12_16_14
, CAN_TXCLK
),
1480 PINMUX_IPSR_GPSR(IP12_19_17
, SSI_SCK4
),
1481 PINMUX_IPSR_MSEL(IP12_19_17
, STP_ISD_0
, SEL_SSP_0
),
1482 PINMUX_IPSR_MSEL(IP12_19_17
, SCIFB0_CTS_N
, SEL_SCIFB_0
),
1483 PINMUX_IPSR_MSEL(IP12_19_17
, MSIOF1_SS2
, SEL_SOF1_0
),
1484 PINMUX_IPSR_MSEL(IP12_19_17
, SSI_SCK5_C
, SEL_SSI5_2
),
1485 PINMUX_IPSR_GPSR(IP12_19_17
, CAN_DEBUGOUT0
),
1486 PINMUX_IPSR_GPSR(IP12_22_20
, SSI_WS4
),
1487 PINMUX_IPSR_MSEL(IP12_22_20
, STP_ISEN_0
, SEL_SSP_0
),
1488 PINMUX_IPSR_MSEL(IP12_22_20
, SCIFB0_RTS_N
, SEL_SCIFB_0
),
1489 PINMUX_IPSR_MSEL(IP12_22_20
, MSIOF1_TXD
, SEL_SOF1_0
),
1490 PINMUX_IPSR_MSEL(IP12_22_20
, SSI_WS5_C
, SEL_SSI5_2
),
1491 PINMUX_IPSR_GPSR(IP12_22_20
, CAN_DEBUGOUT1
),
1492 PINMUX_IPSR_GPSR(IP12_24_23
, SSI_SDATA4
),
1493 PINMUX_IPSR_MSEL(IP12_24_23
, STP_ISSYNC_0
, SEL_SSP_0
),
1494 PINMUX_IPSR_MSEL(IP12_24_23
, MSIOF1_RXD
, SEL_SOF1_0
),
1495 PINMUX_IPSR_GPSR(IP12_24_23
, CAN_DEBUGOUT2
),
1496 PINMUX_IPSR_MSEL(IP12_27_25
, SSI_SCK5
, SEL_SSI5_0
),
1497 PINMUX_IPSR_MSEL(IP12_27_25
, SCIFB1_SCK
, SEL_SCIFB1_0
),
1498 PINMUX_IPSR_MSEL(IP12_27_25
, IERX_B
, SEL_IEB_1
),
1499 PINMUX_IPSR_GPSR(IP12_27_25
, DU2_EXHSYNC_DU2_HSYNC
),
1500 PINMUX_IPSR_GPSR(IP12_27_25
, QSTH_QHS
),
1501 PINMUX_IPSR_GPSR(IP12_27_25
, CAN_DEBUGOUT3
),
1502 PINMUX_IPSR_MSEL(IP12_30_28
, SSI_WS5
, SEL_SSI5_0
),
1503 PINMUX_IPSR_MSEL(IP12_30_28
, SCIFB1_RXD
, SEL_SCIFB1_0
),
1504 PINMUX_IPSR_MSEL(IP12_30_28
, IECLK_B
, SEL_IEB_1
),
1505 PINMUX_IPSR_GPSR(IP12_30_28
, DU2_EXVSYNC_DU2_VSYNC
),
1506 PINMUX_IPSR_GPSR(IP12_30_28
, QSTB_QHE
),
1507 PINMUX_IPSR_GPSR(IP12_30_28
, CAN_DEBUGOUT4
),
1509 PINMUX_IPSR_MSEL(IP13_2_0
, SSI_SDATA5
, SEL_SSI5_0
),
1510 PINMUX_IPSR_MSEL(IP13_2_0
, SCIFB1_TXD
, SEL_SCIFB1_0
),
1511 PINMUX_IPSR_MSEL(IP13_2_0
, IETX_B
, SEL_IEB_1
),
1512 PINMUX_IPSR_GPSR(IP13_2_0
, DU2_DR2
),
1513 PINMUX_IPSR_GPSR(IP13_2_0
, LCDOUT2
),
1514 PINMUX_IPSR_GPSR(IP13_2_0
, CAN_DEBUGOUT5
),
1515 PINMUX_IPSR_MSEL(IP13_6_3
, SSI_SCK6
, SEL_SSI6_0
),
1516 PINMUX_IPSR_MSEL(IP13_6_3
, SCIFB1_CTS_N
, SEL_SCIFB1_0
),
1517 PINMUX_IPSR_MSEL(IP13_6_3
, BPFCLK_D
, SEL_FM_3
),
1518 PINMUX_IPSR_GPSR(IP13_6_3
, DU2_DR3
),
1519 PINMUX_IPSR_GPSR(IP13_6_3
, LCDOUT3
),
1520 PINMUX_IPSR_GPSR(IP13_6_3
, CAN_DEBUGOUT6
),
1521 PINMUX_IPSR_MSEL(IP13_6_3
, BPFCLK_F
, SEL_FM_5
),
1522 PINMUX_IPSR_MSEL(IP13_9_7
, SSI_WS6
, SEL_SSI6_0
),
1523 PINMUX_IPSR_MSEL(IP13_9_7
, SCIFB1_RTS_N
, SEL_SCIFB1_0
),
1524 PINMUX_IPSR_MSEL(IP13_9_7
, CAN0_TX_D
, SEL_CAN0_3
),
1525 PINMUX_IPSR_GPSR(IP13_9_7
, DU2_DR4
),
1526 PINMUX_IPSR_GPSR(IP13_9_7
, LCDOUT4
),
1527 PINMUX_IPSR_GPSR(IP13_9_7
, CAN_DEBUGOUT7
),
1528 PINMUX_IPSR_MSEL(IP13_12_10
, SSI_SDATA6
, SEL_SSI6_0
),
1529 PINMUX_IPSR_MSEL(IP13_12_10
, FMIN_D
, SEL_FM_3
),
1530 PINMUX_IPSR_GPSR(IP13_12_10
, DU2_DR5
),
1531 PINMUX_IPSR_GPSR(IP13_12_10
, LCDOUT5
),
1532 PINMUX_IPSR_GPSR(IP13_12_10
, CAN_DEBUGOUT8
),
1533 PINMUX_IPSR_MSEL(IP13_15_13
, SSI_SCK78
, SEL_SSI7_0
),
1534 PINMUX_IPSR_MSEL(IP13_15_13
, STP_IVCXO27_1
, SEL_SSP_0
),
1535 PINMUX_IPSR_MSEL(IP13_15_13
, SCK1
, SEL_SCIF1_0
),
1536 PINMUX_IPSR_MSEL(IP13_15_13
, SCIFA1_SCK
, SEL_SCIFA1_0
),
1537 PINMUX_IPSR_GPSR(IP13_15_13
, DU2_DR6
),
1538 PINMUX_IPSR_GPSR(IP13_15_13
, LCDOUT6
),
1539 PINMUX_IPSR_GPSR(IP13_15_13
, CAN_DEBUGOUT9
),
1540 PINMUX_IPSR_MSEL(IP13_18_16
, SSI_WS78
, SEL_SSI7_0
),
1541 PINMUX_IPSR_MSEL(IP13_18_16
, STP_ISCLK_1
, SEL_SSP_0
),
1542 PINMUX_IPSR_MSEL(IP13_18_16
, SCIFB2_SCK
, SEL_SCIFB2_0
),
1543 PINMUX_IPSR_GPSR(IP13_18_16
, SCIFA2_CTS_N
),
1544 PINMUX_IPSR_GPSR(IP13_18_16
, DU2_DR7
),
1545 PINMUX_IPSR_GPSR(IP13_18_16
, LCDOUT7
),
1546 PINMUX_IPSR_GPSR(IP13_18_16
, CAN_DEBUGOUT10
),
1547 PINMUX_IPSR_MSEL(IP13_22_19
, SSI_SDATA7
, SEL_SSI7_0
),
1548 PINMUX_IPSR_MSEL(IP13_22_19
, STP_ISD_1
, SEL_SSP_0
),
1549 PINMUX_IPSR_MSEL(IP13_22_19
, SCIFB2_RXD
, SEL_SCIFB2_0
),
1550 PINMUX_IPSR_GPSR(IP13_22_19
, SCIFA2_RTS_N
),
1551 PINMUX_IPSR_GPSR(IP13_22_19
, TCLK2
),
1552 PINMUX_IPSR_GPSR(IP13_22_19
, QSTVA_QVS
),
1553 PINMUX_IPSR_GPSR(IP13_22_19
, CAN_DEBUGOUT11
),
1554 PINMUX_IPSR_MSEL(IP13_22_19
, BPFCLK_E
, SEL_FM_4
),
1555 PINMUX_IPSR_MSEL(IP13_22_19
, SSI_SDATA7_B
, SEL_SSI7_1
),
1556 PINMUX_IPSR_MSEL(IP13_22_19
, FMIN_G
, SEL_FM_6
),
1557 PINMUX_IPSR_MSEL(IP13_25_23
, SSI_SDATA8
, SEL_SSI8_0
),
1558 PINMUX_IPSR_MSEL(IP13_25_23
, STP_ISEN_1
, SEL_SSP_0
),
1559 PINMUX_IPSR_MSEL(IP13_25_23
, SCIFB2_TXD
, SEL_SCIFB2_0
),
1560 PINMUX_IPSR_MSEL(IP13_25_23
, CAN0_TX_C
, SEL_CAN0_2
),
1561 PINMUX_IPSR_GPSR(IP13_25_23
, CAN_DEBUGOUT12
),
1562 PINMUX_IPSR_MSEL(IP13_25_23
, SSI_SDATA8_B
, SEL_SSI8_1
),
1563 PINMUX_IPSR_GPSR(IP13_28_26
, SSI_SDATA9
),
1564 PINMUX_IPSR_MSEL(IP13_28_26
, STP_ISSYNC_1
, SEL_SSP_0
),
1565 PINMUX_IPSR_MSEL(IP13_28_26
, SCIFB2_CTS_N
, SEL_SCIFB2_0
),
1566 PINMUX_IPSR_GPSR(IP13_28_26
, SSI_WS1
),
1567 PINMUX_IPSR_MSEL(IP13_28_26
, SSI_SDATA5_C
, SEL_SSI5_2
),
1568 PINMUX_IPSR_GPSR(IP13_28_26
, CAN_DEBUGOUT13
),
1569 PINMUX_IPSR_GPSR(IP13_30_29
, AUDIO_CLKA
),
1570 PINMUX_IPSR_MSEL(IP13_30_29
, SCIFB2_RTS_N
, SEL_SCIFB2_0
),
1571 PINMUX_IPSR_GPSR(IP13_30_29
, CAN_DEBUGOUT14
),
1573 PINMUX_IPSR_GPSR(IP14_2_0
, AUDIO_CLKB
),
1574 PINMUX_IPSR_MSEL(IP14_2_0
, SCIF_CLK
, SEL_SCIFCLK_0
),
1575 PINMUX_IPSR_MSEL(IP14_2_0
, CAN0_RX_D
, SEL_CAN0_3
),
1576 PINMUX_IPSR_GPSR(IP14_2_0
, DVC_MUTE
),
1577 PINMUX_IPSR_MSEL(IP14_2_0
, CAN0_RX_C
, SEL_CAN0_2
),
1578 PINMUX_IPSR_GPSR(IP14_2_0
, CAN_DEBUGOUT15
),
1579 PINMUX_IPSR_GPSR(IP14_2_0
, REMOCON
),
1580 PINMUX_IPSR_MSEL(IP14_5_3
, SCIFA0_SCK
, SEL_SCFA_0
),
1581 PINMUX_IPSR_MSEL(IP14_5_3
, HSCK1
, SEL_HSCIF1_0
),
1582 PINMUX_IPSR_GPSR(IP14_5_3
, SCK0
),
1583 PINMUX_IPSR_GPSR(IP14_5_3
, MSIOF3_SS2
),
1584 PINMUX_IPSR_GPSR(IP14_5_3
, DU2_DG2
),
1585 PINMUX_IPSR_GPSR(IP14_5_3
, LCDOUT10
),
1586 PINMUX_IPSR_MSEL(IP14_5_3
, IIC1_SDA_C
, SEL_IIC1_2
),
1587 PINMUX_IPSR_MSEL(IP14_5_3
, I2C1_SDA_C
, SEL_I2C1_2
),
1588 PINMUX_IPSR_MSEL(IP14_8_6
, SCIFA0_RXD
, SEL_SCFA_0
),
1589 PINMUX_IPSR_MSEL(IP14_8_6
, HRX1
, SEL_HSCIF1_0
),
1590 PINMUX_IPSR_MSEL(IP14_8_6
, RX0
, SEL_SCIF0_0
),
1591 PINMUX_IPSR_GPSR(IP14_8_6
, DU2_DR0
),
1592 PINMUX_IPSR_GPSR(IP14_8_6
, LCDOUT0
),
1593 PINMUX_IPSR_MSEL(IP14_11_9
, SCIFA0_TXD
, SEL_SCFA_0
),
1594 PINMUX_IPSR_MSEL(IP14_11_9
, HTX1
, SEL_HSCIF1_0
),
1595 PINMUX_IPSR_MSEL(IP14_11_9
, TX0
, SEL_SCIF0_0
),
1596 PINMUX_IPSR_GPSR(IP14_11_9
, DU2_DR1
),
1597 PINMUX_IPSR_GPSR(IP14_11_9
, LCDOUT1
),
1598 PINMUX_IPSR_MSEL(IP14_15_12
, SCIFA0_CTS_N
, SEL_SCFA_0
),
1599 PINMUX_IPSR_MSEL(IP14_15_12
, HCTS1_N
, SEL_HSCIF1_0
),
1600 PINMUX_IPSR_GPSR(IP14_15_12
, CTS0_N
),
1601 PINMUX_IPSR_MSEL(IP14_15_12
, MSIOF3_SYNC
, SEL_SOF3_0
),
1602 PINMUX_IPSR_GPSR(IP14_15_12
, DU2_DG3
),
1603 PINMUX_IPSR_GPSR(IP14_15_12
, LCDOUT11
),
1604 PINMUX_IPSR_GPSR(IP14_15_12
, PWM0_B
),
1605 PINMUX_IPSR_MSEL(IP14_15_12
, IIC1_SCL_C
, SEL_IIC1_2
),
1606 PINMUX_IPSR_MSEL(IP14_15_12
, I2C1_SCL_C
, SEL_I2C1_2
),
1607 PINMUX_IPSR_MSEL(IP14_18_16
, SCIFA0_RTS_N
, SEL_SCFA_0
),
1608 PINMUX_IPSR_MSEL(IP14_18_16
, HRTS1_N
, SEL_HSCIF1_0
),
1609 PINMUX_IPSR_GPSR(IP14_18_16
, RTS0_N
),
1610 PINMUX_IPSR_GPSR(IP14_18_16
, MSIOF3_SS1
),
1611 PINMUX_IPSR_GPSR(IP14_18_16
, DU2_DG0
),
1612 PINMUX_IPSR_GPSR(IP14_18_16
, LCDOUT8
),
1613 PINMUX_IPSR_GPSR(IP14_18_16
, PWM1_B
),
1614 PINMUX_IPSR_MSEL(IP14_21_19
, SCIFA1_RXD
, SEL_SCIFA1_0
),
1615 PINMUX_IPSR_MSEL(IP14_21_19
, AD_DI
, SEL_ADI_0
),
1616 PINMUX_IPSR_MSEL(IP14_21_19
, RX1
, SEL_SCIF1_0
),
1617 PINMUX_IPSR_GPSR(IP14_21_19
, DU2_EXODDF_DU2_ODDF_DISP_CDE
),
1618 PINMUX_IPSR_GPSR(IP14_21_19
, QCPV_QDE
),
1619 PINMUX_IPSR_MSEL(IP14_24_22
, SCIFA1_TXD
, SEL_SCIFA1_0
),
1620 PINMUX_IPSR_MSEL(IP14_24_22
, AD_DO
, SEL_ADI_0
),
1621 PINMUX_IPSR_MSEL(IP14_24_22
, TX1
, SEL_SCIF1_0
),
1622 PINMUX_IPSR_GPSR(IP14_24_22
, DU2_DG1
),
1623 PINMUX_IPSR_GPSR(IP14_24_22
, LCDOUT9
),
1624 PINMUX_IPSR_MSEL(IP14_27_25
, SCIFA1_CTS_N
, SEL_SCIFA1_0
),
1625 PINMUX_IPSR_MSEL(IP14_27_25
, AD_CLK
, SEL_ADI_0
),
1626 PINMUX_IPSR_GPSR(IP14_27_25
, CTS1_N
),
1627 PINMUX_IPSR_MSEL(IP14_27_25
, MSIOF3_RXD
, SEL_SOF3_0
),
1628 PINMUX_IPSR_GPSR(IP14_27_25
, DU0_DOTCLKOUT
),
1629 PINMUX_IPSR_GPSR(IP14_27_25
, QCLK
),
1630 PINMUX_IPSR_MSEL(IP14_30_28
, SCIFA1_RTS_N
, SEL_SCIFA1_0
),
1631 PINMUX_IPSR_MSEL(IP14_30_28
, AD_NCS_N
, SEL_ADI_0
),
1632 PINMUX_IPSR_GPSR(IP14_30_28
, RTS1_N
),
1633 PINMUX_IPSR_MSEL(IP14_30_28
, MSIOF3_TXD
, SEL_SOF3_0
),
1634 PINMUX_IPSR_GPSR(IP14_30_28
, DU1_DOTCLKOUT
),
1635 PINMUX_IPSR_GPSR(IP14_30_28
, QSTVB_QVE
),
1636 PINMUX_IPSR_MSEL(IP14_30_28
, HRTS0_N_C
, SEL_HSCIF0_2
),
1638 PINMUX_IPSR_MSEL(IP15_2_0
, SCIFA2_SCK
, SEL_SCIFA2_0
),
1639 PINMUX_IPSR_MSEL(IP15_2_0
, FMCLK
, SEL_FM_0
),
1640 PINMUX_IPSR_GPSR(IP15_2_0
, SCK2
),
1641 PINMUX_IPSR_MSEL(IP15_2_0
, MSIOF3_SCK
, SEL_SOF3_0
),
1642 PINMUX_IPSR_GPSR(IP15_2_0
, DU2_DG7
),
1643 PINMUX_IPSR_GPSR(IP15_2_0
, LCDOUT15
),
1644 PINMUX_IPSR_MSEL(IP15_2_0
, SCIF_CLK_B
, SEL_SCIFCLK_1
),
1645 PINMUX_IPSR_MSEL(IP15_5_3
, SCIFA2_RXD
, SEL_SCIFA2_0
),
1646 PINMUX_IPSR_MSEL(IP15_5_3
, FMIN
, SEL_FM_0
),
1647 PINMUX_IPSR_MSEL(IP15_5_3
, TX2
, SEL_SCIF2_0
),
1648 PINMUX_IPSR_GPSR(IP15_5_3
, DU2_DB0
),
1649 PINMUX_IPSR_GPSR(IP15_5_3
, LCDOUT16
),
1650 PINMUX_IPSR_MSEL(IP15_5_3
, IIC2_SCL
, SEL_IIC2_0
),
1651 PINMUX_IPSR_MSEL(IP15_5_3
, I2C2_SCL
, SEL_I2C2_0
),
1652 PINMUX_IPSR_MSEL(IP15_8_6
, SCIFA2_TXD
, SEL_SCIFA2_0
),
1653 PINMUX_IPSR_MSEL(IP15_8_6
, BPFCLK
, SEL_FM_0
),
1654 PINMUX_IPSR_MSEL(IP15_8_6
, RX2
, SEL_SCIF2_0
),
1655 PINMUX_IPSR_GPSR(IP15_8_6
, DU2_DB1
),
1656 PINMUX_IPSR_GPSR(IP15_8_6
, LCDOUT17
),
1657 PINMUX_IPSR_MSEL(IP15_8_6
, IIC2_SDA
, SEL_IIC2_0
),
1658 PINMUX_IPSR_MSEL(IP15_8_6
, I2C2_SDA
, SEL_I2C2_0
),
1659 PINMUX_IPSR_GPSR(IP15_11_9
, HSCK0
),
1660 PINMUX_IPSR_MSEL(IP15_11_9
, TS_SDEN0
, SEL_TSIF0_0
),
1661 PINMUX_IPSR_GPSR(IP15_11_9
, DU2_DG4
),
1662 PINMUX_IPSR_GPSR(IP15_11_9
, LCDOUT12
),
1663 PINMUX_IPSR_MSEL(IP15_11_9
, HCTS0_N_C
, SEL_HSCIF0_2
),
1664 PINMUX_IPSR_MSEL(IP15_13_12
, HRX0
, SEL_HSCIF0_0
),
1665 PINMUX_IPSR_GPSR(IP15_13_12
, DU2_DB2
),
1666 PINMUX_IPSR_GPSR(IP15_13_12
, LCDOUT18
),
1667 PINMUX_IPSR_MSEL(IP15_15_14
, HTX0
, SEL_HSCIF0_0
),
1668 PINMUX_IPSR_GPSR(IP15_15_14
, DU2_DB3
),
1669 PINMUX_IPSR_GPSR(IP15_15_14
, LCDOUT19
),
1670 PINMUX_IPSR_MSEL(IP15_17_16
, HCTS0_N
, SEL_HSCIF0_0
),
1671 PINMUX_IPSR_GPSR(IP15_17_16
, SSI_SCK9
),
1672 PINMUX_IPSR_GPSR(IP15_17_16
, DU2_DB4
),
1673 PINMUX_IPSR_GPSR(IP15_17_16
, LCDOUT20
),
1674 PINMUX_IPSR_MSEL(IP15_19_18
, HRTS0_N
, SEL_HSCIF0_0
),
1675 PINMUX_IPSR_GPSR(IP15_19_18
, SSI_WS9
),
1676 PINMUX_IPSR_GPSR(IP15_19_18
, DU2_DB5
),
1677 PINMUX_IPSR_GPSR(IP15_19_18
, LCDOUT21
),
1678 PINMUX_IPSR_MSEL(IP15_22_20
, MSIOF0_SCK
, SEL_SOF0_0
),
1679 PINMUX_IPSR_MSEL(IP15_22_20
, TS_SDAT0
, SEL_TSIF0_0
),
1680 PINMUX_IPSR_GPSR(IP15_22_20
, ADICLK
),
1681 PINMUX_IPSR_GPSR(IP15_22_20
, DU2_DB6
),
1682 PINMUX_IPSR_GPSR(IP15_22_20
, LCDOUT22
),
1683 PINMUX_IPSR_GPSR(IP15_25_23
, MSIOF0_SYNC
),
1684 PINMUX_IPSR_MSEL(IP15_25_23
, TS_SCK0
, SEL_TSIF0_0
),
1685 PINMUX_IPSR_GPSR(IP15_25_23
, SSI_SCK2
),
1686 PINMUX_IPSR_GPSR(IP15_25_23
, ADIDATA
),
1687 PINMUX_IPSR_GPSR(IP15_25_23
, DU2_DB7
),
1688 PINMUX_IPSR_GPSR(IP15_25_23
, LCDOUT23
),
1689 PINMUX_IPSR_MSEL(IP15_25_23
, HRX0_C
, SEL_SCIFA2_1
),
1690 PINMUX_IPSR_MSEL(IP15_27_26
, MSIOF0_SS1
, SEL_SOF0_0
),
1691 PINMUX_IPSR_GPSR(IP15_27_26
, ADICHS0
),
1692 PINMUX_IPSR_GPSR(IP15_27_26
, DU2_DG5
),
1693 PINMUX_IPSR_GPSR(IP15_27_26
, LCDOUT13
),
1694 PINMUX_IPSR_MSEL(IP15_29_28
, MSIOF0_TXD
, SEL_SOF0_0
),
1695 PINMUX_IPSR_GPSR(IP15_29_28
, ADICHS1
),
1696 PINMUX_IPSR_GPSR(IP15_29_28
, DU2_DG6
),
1697 PINMUX_IPSR_GPSR(IP15_29_28
, LCDOUT14
),
1699 PINMUX_IPSR_MSEL(IP16_2_0
, MSIOF0_SS2
, SEL_SOF0_0
),
1700 PINMUX_IPSR_GPSR(IP16_2_0
, AUDIO_CLKOUT
),
1701 PINMUX_IPSR_GPSR(IP16_2_0
, ADICHS2
),
1702 PINMUX_IPSR_GPSR(IP16_2_0
, DU2_DISP
),
1703 PINMUX_IPSR_GPSR(IP16_2_0
, QPOLA
),
1704 PINMUX_IPSR_MSEL(IP16_2_0
, HTX0_C
, SEL_HSCIF0_2
),
1705 PINMUX_IPSR_MSEL(IP16_2_0
, SCIFA2_TXD_B
, SEL_SCIFA2_1
),
1706 PINMUX_IPSR_MSEL(IP16_5_3
, MSIOF0_RXD
, SEL_SOF0_0
),
1707 PINMUX_IPSR_MSEL(IP16_5_3
, TS_SPSYNC0
, SEL_TSIF0_0
),
1708 PINMUX_IPSR_GPSR(IP16_5_3
, SSI_WS2
),
1709 PINMUX_IPSR_GPSR(IP16_5_3
, ADICS_SAMP
),
1710 PINMUX_IPSR_GPSR(IP16_5_3
, DU2_CDE
),
1711 PINMUX_IPSR_GPSR(IP16_5_3
, QPOLB
),
1712 PINMUX_IPSR_MSEL(IP16_5_3
, SCIFA2_RXD_B
, SEL_HSCIF0_2
),
1713 PINMUX_IPSR_GPSR(IP16_6
, USB1_PWEN
),
1714 PINMUX_IPSR_GPSR(IP16_6
, AUDIO_CLKOUT_D
),
1715 PINMUX_IPSR_GPSR(IP16_7
, USB1_OVC
),
1716 PINMUX_IPSR_MSEL(IP16_7
, TCLK1_B
, SEL_TMU1_1
),
1718 PINMUX_DATA(IIC0_SCL_MARK
, FN_SEL_IIC0_0
),
1719 PINMUX_DATA(IIC0_SDA_MARK
, FN_SEL_IIC0_0
),
1720 PINMUX_DATA(I2C0_SCL_MARK
, FN_SEL_IIC0_1
),
1721 PINMUX_DATA(I2C0_SDA_MARK
, FN_SEL_IIC0_1
),
1723 PINMUX_DATA(IIC3_SCL_MARK
, FN_SEL_IICDVFS_0
),
1724 PINMUX_DATA(IIC3_SDA_MARK
, FN_SEL_IICDVFS_0
),
1725 PINMUX_DATA(I2C3_SCL_MARK
, FN_SEL_IICDVFS_1
),
1726 PINMUX_DATA(I2C3_SDA_MARK
, FN_SEL_IICDVFS_1
),
1729 /* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
1730 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1731 #define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1732 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1734 static const struct sh_pfc_pin pinmux_pins
[] = {
1735 PINMUX_GPIO_GP_ALL(),
1737 /* Pins not associated with a GPIO port */
1738 SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15
),
1739 SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15
),
1740 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15
),
1741 SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15
),
1744 /* - AUDIO CLOCK ------------------------------------------------------------ */
1745 static const unsigned int audio_clk_a_pins
[] = {
1749 static const unsigned int audio_clk_a_mux
[] = {
1752 static const unsigned int audio_clk_b_pins
[] = {
1756 static const unsigned int audio_clk_b_mux
[] = {
1759 static const unsigned int audio_clk_c_pins
[] = {
1763 static const unsigned int audio_clk_c_mux
[] = {
1766 static const unsigned int audio_clkout_pins
[] = {
1770 static const unsigned int audio_clkout_mux
[] = {
1773 static const unsigned int audio_clkout_b_pins
[] = {
1777 static const unsigned int audio_clkout_b_mux
[] = {
1778 AUDIO_CLKOUT_B_MARK
,
1780 static const unsigned int audio_clkout_c_pins
[] = {
1784 static const unsigned int audio_clkout_c_mux
[] = {
1785 AUDIO_CLKOUT_C_MARK
,
1787 static const unsigned int audio_clkout_d_pins
[] = {
1791 static const unsigned int audio_clkout_d_mux
[] = {
1792 AUDIO_CLKOUT_D_MARK
,
1794 /* - AVB -------------------------------------------------------------------- */
1795 static const unsigned int avb_link_pins
[] = {
1798 static const unsigned int avb_link_mux
[] = {
1801 static const unsigned int avb_magic_pins
[] = {
1804 static const unsigned int avb_magic_mux
[] = {
1807 static const unsigned int avb_phy_int_pins
[] = {
1810 static const unsigned int avb_phy_int_mux
[] = {
1813 static const unsigned int avb_mdio_pins
[] = {
1814 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1816 static const unsigned int avb_mdio_mux
[] = {
1817 AVB_MDC_MARK
, AVB_MDIO_MARK
,
1819 static const unsigned int avb_mii_pins
[] = {
1820 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1823 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1826 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1827 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1828 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
1830 static const unsigned int avb_mii_mux
[] = {
1831 AVB_TXD0_MARK
, AVB_TXD1_MARK
, AVB_TXD2_MARK
,
1834 AVB_RXD0_MARK
, AVB_RXD1_MARK
, AVB_RXD2_MARK
,
1837 AVB_RX_ER_MARK
, AVB_RX_CLK_MARK
, AVB_RX_DV_MARK
,
1838 AVB_CRS_MARK
, AVB_TX_EN_MARK
, AVB_TX_ER_MARK
,
1839 AVB_TX_CLK_MARK
, AVB_COL_MARK
,
1841 static const unsigned int avb_gmii_pins
[] = {
1842 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1843 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1844 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1846 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1847 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1848 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1850 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1851 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
1852 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1855 static const unsigned int avb_gmii_mux
[] = {
1856 AVB_TXD0_MARK
, AVB_TXD1_MARK
, AVB_TXD2_MARK
,
1857 AVB_TXD3_MARK
, AVB_TXD4_MARK
, AVB_TXD5_MARK
,
1858 AVB_TXD6_MARK
, AVB_TXD7_MARK
,
1860 AVB_RXD0_MARK
, AVB_RXD1_MARK
, AVB_RXD2_MARK
,
1861 AVB_RXD3_MARK
, AVB_RXD4_MARK
, AVB_RXD5_MARK
,
1862 AVB_RXD6_MARK
, AVB_RXD7_MARK
,
1864 AVB_RX_ER_MARK
, AVB_RX_CLK_MARK
, AVB_RX_DV_MARK
,
1865 AVB_CRS_MARK
, AVB_GTX_CLK_MARK
, AVB_GTXREFCLK_MARK
,
1866 AVB_TX_EN_MARK
, AVB_TX_ER_MARK
, AVB_TX_CLK_MARK
,
1869 /* - DU RGB ----------------------------------------------------------------- */
1870 static const unsigned int du_rgb666_pins
[] = {
1871 /* R[7:2], G[7:2], B[7:2] */
1872 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1873 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1874 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1875 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1876 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1877 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
1879 static const unsigned int du_rgb666_mux
[] = {
1880 DU2_DR7_MARK
, DU2_DR6_MARK
, DU2_DR5_MARK
, DU2_DR4_MARK
,
1881 DU2_DR3_MARK
, DU2_DR2_MARK
,
1882 DU2_DG7_MARK
, DU2_DG6_MARK
, DU2_DG5_MARK
, DU2_DG4_MARK
,
1883 DU2_DG3_MARK
, DU2_DG2_MARK
,
1884 DU2_DB7_MARK
, DU2_DB6_MARK
, DU2_DB5_MARK
, DU2_DB4_MARK
,
1885 DU2_DB3_MARK
, DU2_DB2_MARK
,
1887 static const unsigned int du_rgb888_pins
[] = {
1888 /* R[7:0], G[7:0], B[7:0] */
1889 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1890 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1891 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1892 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1893 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1894 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1895 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1896 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1898 static const unsigned int du_rgb888_mux
[] = {
1899 DU2_DR7_MARK
, DU2_DR6_MARK
, DU2_DR5_MARK
, DU2_DR4_MARK
,
1900 DU2_DR3_MARK
, DU2_DR2_MARK
, DU2_DR1_MARK
, DU2_DR0_MARK
,
1901 DU2_DG7_MARK
, DU2_DG6_MARK
, DU2_DG5_MARK
, DU2_DG4_MARK
,
1902 DU2_DG3_MARK
, DU2_DG2_MARK
, DU2_DG1_MARK
, DU2_DG0_MARK
,
1903 DU2_DB7_MARK
, DU2_DB6_MARK
, DU2_DB5_MARK
, DU2_DB4_MARK
,
1904 DU2_DB3_MARK
, DU2_DB2_MARK
, DU2_DB1_MARK
, DU2_DB0_MARK
,
1906 static const unsigned int du_clk_out_0_pins
[] = {
1910 static const unsigned int du_clk_out_0_mux
[] = {
1913 static const unsigned int du_clk_out_1_pins
[] = {
1917 static const unsigned int du_clk_out_1_mux
[] = {
1920 static const unsigned int du_sync_0_pins
[] = {
1921 /* VSYNC, HSYNC, DISP */
1922 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
1924 static const unsigned int du_sync_0_mux
[] = {
1925 DU2_EXVSYNC_DU2_VSYNC_MARK
, DU2_EXHSYNC_DU2_HSYNC_MARK
,
1926 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
1928 static const unsigned int du_sync_1_pins
[] = {
1929 /* VSYNC, HSYNC, DISP */
1930 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
1932 static const unsigned int du_sync_1_mux
[] = {
1933 DU2_EXVSYNC_DU2_VSYNC_MARK
, DU2_EXHSYNC_DU2_HSYNC_MARK
,
1936 static const unsigned int du_cde_pins
[] = {
1940 static const unsigned int du_cde_mux
[] = {
1943 /* - DU0 -------------------------------------------------------------------- */
1944 static const unsigned int du0_clk_in_pins
[] = {
1948 static const unsigned int du0_clk_in_mux
[] = {
1951 /* - DU1 -------------------------------------------------------------------- */
1952 static const unsigned int du1_clk_in_pins
[] = {
1956 static const unsigned int du1_clk_in_mux
[] = {
1959 /* - DU2 -------------------------------------------------------------------- */
1960 static const unsigned int du2_clk_in_pins
[] = {
1964 static const unsigned int du2_clk_in_mux
[] = {
1967 /* - ETH -------------------------------------------------------------------- */
1968 static const unsigned int eth_link_pins
[] = {
1972 static const unsigned int eth_link_mux
[] = {
1975 static const unsigned int eth_magic_pins
[] = {
1979 static const unsigned int eth_magic_mux
[] = {
1982 static const unsigned int eth_mdio_pins
[] = {
1984 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
1986 static const unsigned int eth_mdio_mux
[] = {
1987 ETH_MDC_MARK
, ETH_MDIO_MARK
,
1989 static const unsigned int eth_rmii_pins
[] = {
1990 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1991 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
1992 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
1993 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
1995 static const unsigned int eth_rmii_mux
[] = {
1996 ETH_RXD0_MARK
, ETH_RXD1_MARK
, ETH_RX_ER_MARK
, ETH_CRS_DV_MARK
,
1997 ETH_TXD0_MARK
, ETH_TXD1_MARK
, ETH_TX_EN_MARK
, ETH_REF_CLK_MARK
,
1999 /* - HSCIF0 ----------------------------------------------------------------- */
2000 static const unsigned int hscif0_data_pins
[] = {
2002 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2004 static const unsigned int hscif0_data_mux
[] = {
2005 HRX0_MARK
, HTX0_MARK
,
2007 static const unsigned int hscif0_clk_pins
[] = {
2011 static const unsigned int hscif0_clk_mux
[] = {
2014 static const unsigned int hscif0_ctrl_pins
[] = {
2016 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2018 static const unsigned int hscif0_ctrl_mux
[] = {
2019 HRTS0_N_MARK
, HCTS0_N_MARK
,
2021 static const unsigned int hscif0_data_b_pins
[] = {
2023 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
2025 static const unsigned int hscif0_data_b_mux
[] = {
2026 HRX0_B_MARK
, HTX0_B_MARK
,
2028 static const unsigned int hscif0_ctrl_b_pins
[] = {
2030 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
2032 static const unsigned int hscif0_ctrl_b_mux
[] = {
2033 HRTS0_N_B_MARK
, HCTS0_N_B_MARK
,
2035 static const unsigned int hscif0_data_c_pins
[] = {
2037 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2039 static const unsigned int hscif0_data_c_mux
[] = {
2040 HRX0_C_MARK
, HTX0_C_MARK
,
2042 static const unsigned int hscif0_ctrl_c_pins
[] = {
2044 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
2046 static const unsigned int hscif0_ctrl_c_mux
[] = {
2047 HRTS0_N_C_MARK
, HCTS0_N_C_MARK
,
2049 static const unsigned int hscif0_data_d_pins
[] = {
2051 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2053 static const unsigned int hscif0_data_d_mux
[] = {
2054 HRX0_D_MARK
, HTX0_D_MARK
,
2056 static const unsigned int hscif0_ctrl_d_pins
[] = {
2058 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
2060 static const unsigned int hscif0_ctrl_d_mux
[] = {
2061 HRTS0_N_D_MARK
, HCTS0_N_D_MARK
,
2063 static const unsigned int hscif0_data_e_pins
[] = {
2065 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2067 static const unsigned int hscif0_data_e_mux
[] = {
2068 HRX0_E_MARK
, HTX0_E_MARK
,
2070 static const unsigned int hscif0_ctrl_e_pins
[] = {
2072 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2074 static const unsigned int hscif0_ctrl_e_mux
[] = {
2075 HRTS0_N_E_MARK
, HCTS0_N_E_MARK
,
2077 static const unsigned int hscif0_data_f_pins
[] = {
2079 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2081 static const unsigned int hscif0_data_f_mux
[] = {
2082 HRX0_F_MARK
, HTX0_F_MARK
,
2084 static const unsigned int hscif0_ctrl_f_pins
[] = {
2086 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2088 static const unsigned int hscif0_ctrl_f_mux
[] = {
2089 HRTS0_N_F_MARK
, HCTS0_N_F_MARK
,
2091 /* - HSCIF1 ----------------------------------------------------------------- */
2092 static const unsigned int hscif1_data_pins
[] = {
2094 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2096 static const unsigned int hscif1_data_mux
[] = {
2097 HRX1_MARK
, HTX1_MARK
,
2099 static const unsigned int hscif1_clk_pins
[] = {
2103 static const unsigned int hscif1_clk_mux
[] = {
2106 static const unsigned int hscif1_ctrl_pins
[] = {
2108 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2110 static const unsigned int hscif1_ctrl_mux
[] = {
2111 HRTS1_N_MARK
, HCTS1_N_MARK
,
2113 static const unsigned int hscif1_data_b_pins
[] = {
2115 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2117 static const unsigned int hscif1_data_b_mux
[] = {
2118 HRX1_B_MARK
, HTX1_B_MARK
,
2120 static const unsigned int hscif1_clk_b_pins
[] = {
2124 static const unsigned int hscif1_clk_b_mux
[] = {
2127 static const unsigned int hscif1_ctrl_b_pins
[] = {
2129 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2131 static const unsigned int hscif1_ctrl_b_mux
[] = {
2132 HRTS1_N_B_MARK
, HCTS1_N_B_MARK
,
2134 /* - I2C0 ------------------------------------------------------------------- */
2135 static const unsigned int i2c0_pins
[] = {
2137 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2139 static const unsigned int i2c0_mux
[] = {
2140 I2C0_SCL_MARK
, I2C0_SDA_MARK
,
2142 /* - I2C1 ------------------------------------------------------------------- */
2143 static const unsigned int i2c1_pins
[] = {
2145 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2147 static const unsigned int i2c1_mux
[] = {
2148 I2C1_SCL_MARK
, I2C1_SDA_MARK
,
2150 static const unsigned int i2c1_b_pins
[] = {
2152 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2154 static const unsigned int i2c1_b_mux
[] = {
2155 I2C1_SCL_B_MARK
, I2C1_SDA_B_MARK
,
2157 static const unsigned int i2c1_c_pins
[] = {
2159 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2161 static const unsigned int i2c1_c_mux
[] = {
2162 I2C1_SCL_C_MARK
, I2C1_SDA_C_MARK
,
2164 /* - I2C2 ------------------------------------------------------------------- */
2165 static const unsigned int i2c2_pins
[] = {
2167 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2169 static const unsigned int i2c2_mux
[] = {
2170 I2C2_SCL_MARK
, I2C2_SDA_MARK
,
2172 static const unsigned int i2c2_b_pins
[] = {
2174 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2176 static const unsigned int i2c2_b_mux
[] = {
2177 I2C2_SCL_B_MARK
, I2C2_SDA_B_MARK
,
2179 static const unsigned int i2c2_c_pins
[] = {
2181 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2183 static const unsigned int i2c2_c_mux
[] = {
2184 I2C2_SCL_C_MARK
, I2C2_SDA_C_MARK
,
2186 static const unsigned int i2c2_d_pins
[] = {
2188 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2190 static const unsigned int i2c2_d_mux
[] = {
2191 I2C2_SCL_D_MARK
, I2C2_SDA_D_MARK
,
2193 static const unsigned int i2c2_e_pins
[] = {
2195 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2197 static const unsigned int i2c2_e_mux
[] = {
2198 I2C2_SCL_E_MARK
, I2C2_SDA_E_MARK
,
2200 /* - I2C3 ------------------------------------------------------------------- */
2201 static const unsigned int i2c3_pins
[] = {
2203 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2205 static const unsigned int i2c3_mux
[] = {
2206 I2C3_SCL_MARK
, I2C3_SDA_MARK
,
2208 /* - IIC0 (I2C4) ------------------------------------------------------------ */
2209 static const unsigned int iic0_pins
[] = {
2211 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2213 static const unsigned int iic0_mux
[] = {
2214 IIC0_SCL_MARK
, IIC0_SDA_MARK
,
2216 /* - IIC1 (I2C5) ------------------------------------------------------------ */
2217 static const unsigned int iic1_pins
[] = {
2219 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2221 static const unsigned int iic1_mux
[] = {
2222 IIC1_SCL_MARK
, IIC1_SDA_MARK
,
2224 static const unsigned int iic1_b_pins
[] = {
2226 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2228 static const unsigned int iic1_b_mux
[] = {
2229 IIC1_SCL_B_MARK
, IIC1_SDA_B_MARK
,
2231 static const unsigned int iic1_c_pins
[] = {
2233 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2235 static const unsigned int iic1_c_mux
[] = {
2236 IIC1_SCL_C_MARK
, IIC1_SDA_C_MARK
,
2238 /* - IIC2 (I2C6) ------------------------------------------------------------ */
2239 static const unsigned int iic2_pins
[] = {
2241 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2243 static const unsigned int iic2_mux
[] = {
2244 IIC2_SCL_MARK
, IIC2_SDA_MARK
,
2246 static const unsigned int iic2_b_pins
[] = {
2248 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2250 static const unsigned int iic2_b_mux
[] = {
2251 IIC2_SCL_B_MARK
, IIC2_SDA_B_MARK
,
2253 static const unsigned int iic2_c_pins
[] = {
2255 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2257 static const unsigned int iic2_c_mux
[] = {
2258 IIC2_SCL_C_MARK
, IIC2_SDA_C_MARK
,
2260 static const unsigned int iic2_d_pins
[] = {
2262 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2264 static const unsigned int iic2_d_mux
[] = {
2265 IIC2_SCL_D_MARK
, IIC2_SDA_D_MARK
,
2267 static const unsigned int iic2_e_pins
[] = {
2269 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2271 static const unsigned int iic2_e_mux
[] = {
2272 IIC2_SCL_E_MARK
, IIC2_SDA_E_MARK
,
2274 /* - IIC3 (I2C7) ------------------------------------------------------------ */
2275 static const unsigned int iic3_pins
[] = {
2277 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2279 static const unsigned int iic3_mux
[] = {
2280 IIC3_SCL_MARK
, IIC3_SDA_MARK
,
2282 /* - INTC ------------------------------------------------------------------- */
2283 static const unsigned int intc_irq0_pins
[] = {
2287 static const unsigned int intc_irq0_mux
[] = {
2290 static const unsigned int intc_irq1_pins
[] = {
2294 static const unsigned int intc_irq1_mux
[] = {
2297 static const unsigned int intc_irq2_pins
[] = {
2301 static const unsigned int intc_irq2_mux
[] = {
2304 static const unsigned int intc_irq3_pins
[] = {
2308 static const unsigned int intc_irq3_mux
[] = {
2311 /* - MLB+ ------------------------------------------------------------------- */
2312 static const unsigned int mlb_3pin_pins
[] = {
2313 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2315 static const unsigned int mlb_3pin_mux
[] = {
2316 MLB_CLK_MARK
, MLB_SIG_MARK
, MLB_DAT_MARK
,
2318 /* - MMCIF0 ----------------------------------------------------------------- */
2319 static const unsigned int mmc0_data1_pins
[] = {
2323 static const unsigned int mmc0_data1_mux
[] = {
2326 static const unsigned int mmc0_data4_pins
[] = {
2328 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2329 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2331 static const unsigned int mmc0_data4_mux
[] = {
2332 MMC0_D0_MARK
, MMC0_D1_MARK
, MMC0_D2_MARK
, MMC0_D3_MARK
,
2334 static const unsigned int mmc0_data8_pins
[] = {
2336 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2337 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2338 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2339 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2341 static const unsigned int mmc0_data8_mux
[] = {
2342 MMC0_D0_MARK
, MMC0_D1_MARK
, MMC0_D2_MARK
, MMC0_D3_MARK
,
2343 MMC0_D4_MARK
, MMC0_D5_MARK
, MMC0_D6_MARK
, MMC0_D7_MARK
,
2345 static const unsigned int mmc0_ctrl_pins
[] = {
2347 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2349 static const unsigned int mmc0_ctrl_mux
[] = {
2350 MMC0_CLK_MARK
, MMC0_CMD_MARK
,
2352 /* - MMCIF1 ----------------------------------------------------------------- */
2353 static const unsigned int mmc1_data1_pins
[] = {
2357 static const unsigned int mmc1_data1_mux
[] = {
2360 static const unsigned int mmc1_data4_pins
[] = {
2362 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2363 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2365 static const unsigned int mmc1_data4_mux
[] = {
2366 MMC1_D0_MARK
, MMC1_D1_MARK
, MMC1_D2_MARK
, MMC1_D3_MARK
,
2368 static const unsigned int mmc1_data8_pins
[] = {
2370 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2371 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2372 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2373 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2375 static const unsigned int mmc1_data8_mux
[] = {
2376 MMC1_D0_MARK
, MMC1_D1_MARK
, MMC1_D2_MARK
, MMC1_D3_MARK
,
2377 MMC1_D4_MARK
, MMC1_D5_MARK
, MMC1_D6_MARK
, MMC1_D7_MARK
,
2379 static const unsigned int mmc1_ctrl_pins
[] = {
2381 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2383 static const unsigned int mmc1_ctrl_mux
[] = {
2384 MMC1_CLK_MARK
, MMC1_CMD_MARK
,
2386 /* - MSIOF0 ----------------------------------------------------------------- */
2387 static const unsigned int msiof0_clk_pins
[] = {
2391 static const unsigned int msiof0_clk_mux
[] = {
2394 static const unsigned int msiof0_sync_pins
[] = {
2398 static const unsigned int msiof0_sync_mux
[] = {
2401 static const unsigned int msiof0_ss1_pins
[] = {
2405 static const unsigned int msiof0_ss1_mux
[] = {
2408 static const unsigned int msiof0_ss2_pins
[] = {
2412 static const unsigned int msiof0_ss2_mux
[] = {
2415 static const unsigned int msiof0_rx_pins
[] = {
2419 static const unsigned int msiof0_rx_mux
[] = {
2422 static const unsigned int msiof0_tx_pins
[] = {
2426 static const unsigned int msiof0_tx_mux
[] = {
2430 static const unsigned int msiof0_clk_b_pins
[] = {
2434 static const unsigned int msiof0_clk_b_mux
[] = {
2437 static const unsigned int msiof0_ss1_b_pins
[] = {
2441 static const unsigned int msiof0_ss1_b_mux
[] = {
2444 static const unsigned int msiof0_ss2_b_pins
[] = {
2448 static const unsigned int msiof0_ss2_b_mux
[] = {
2451 static const unsigned int msiof0_rx_b_pins
[] = {
2455 static const unsigned int msiof0_rx_b_mux
[] = {
2458 static const unsigned int msiof0_tx_b_pins
[] = {
2462 static const unsigned int msiof0_tx_b_mux
[] = {
2465 /* - MSIOF1 ----------------------------------------------------------------- */
2466 static const unsigned int msiof1_clk_pins
[] = {
2470 static const unsigned int msiof1_clk_mux
[] = {
2473 static const unsigned int msiof1_sync_pins
[] = {
2477 static const unsigned int msiof1_sync_mux
[] = {
2480 static const unsigned int msiof1_ss1_pins
[] = {
2484 static const unsigned int msiof1_ss1_mux
[] = {
2487 static const unsigned int msiof1_ss2_pins
[] = {
2491 static const unsigned int msiof1_ss2_mux
[] = {
2494 static const unsigned int msiof1_rx_pins
[] = {
2498 static const unsigned int msiof1_rx_mux
[] = {
2501 static const unsigned int msiof1_tx_pins
[] = {
2505 static const unsigned int msiof1_tx_mux
[] = {
2509 static const unsigned int msiof1_clk_b_pins
[] = {
2513 static const unsigned int msiof1_clk_b_mux
[] = {
2516 static const unsigned int msiof1_ss1_b_pins
[] = {
2520 static const unsigned int msiof1_ss1_b_mux
[] = {
2523 static const unsigned int msiof1_ss2_b_pins
[] = {
2527 static const unsigned int msiof1_ss2_b_mux
[] = {
2530 static const unsigned int msiof1_rx_b_pins
[] = {
2534 static const unsigned int msiof1_rx_b_mux
[] = {
2537 static const unsigned int msiof1_tx_b_pins
[] = {
2541 static const unsigned int msiof1_tx_b_mux
[] = {
2544 /* - MSIOF2 ----------------------------------------------------------------- */
2545 static const unsigned int msiof2_clk_pins
[] = {
2549 static const unsigned int msiof2_clk_mux
[] = {
2552 static const unsigned int msiof2_sync_pins
[] = {
2556 static const unsigned int msiof2_sync_mux
[] = {
2559 static const unsigned int msiof2_ss1_pins
[] = {
2563 static const unsigned int msiof2_ss1_mux
[] = {
2566 static const unsigned int msiof2_ss2_pins
[] = {
2570 static const unsigned int msiof2_ss2_mux
[] = {
2573 static const unsigned int msiof2_rx_pins
[] = {
2577 static const unsigned int msiof2_rx_mux
[] = {
2580 static const unsigned int msiof2_tx_pins
[] = {
2584 static const unsigned int msiof2_tx_mux
[] = {
2587 /* - MSIOF3 ----------------------------------------------------------------- */
2588 static const unsigned int msiof3_clk_pins
[] = {
2592 static const unsigned int msiof3_clk_mux
[] = {
2595 static const unsigned int msiof3_sync_pins
[] = {
2599 static const unsigned int msiof3_sync_mux
[] = {
2602 static const unsigned int msiof3_ss1_pins
[] = {
2606 static const unsigned int msiof3_ss1_mux
[] = {
2609 static const unsigned int msiof3_ss2_pins
[] = {
2613 static const unsigned int msiof3_ss2_mux
[] = {
2616 static const unsigned int msiof3_rx_pins
[] = {
2620 static const unsigned int msiof3_rx_mux
[] = {
2623 static const unsigned int msiof3_tx_pins
[] = {
2627 static const unsigned int msiof3_tx_mux
[] = {
2631 static const unsigned int msiof3_clk_b_pins
[] = {
2635 static const unsigned int msiof3_clk_b_mux
[] = {
2638 static const unsigned int msiof3_sync_b_pins
[] = {
2642 static const unsigned int msiof3_sync_b_mux
[] = {
2645 static const unsigned int msiof3_rx_b_pins
[] = {
2649 static const unsigned int msiof3_rx_b_mux
[] = {
2652 static const unsigned int msiof3_tx_b_pins
[] = {
2656 static const unsigned int msiof3_tx_b_mux
[] = {
2659 /* - PWM -------------------------------------------------------------------- */
2660 static const unsigned int pwm0_pins
[] = {
2663 static const unsigned int pwm0_mux
[] = {
2666 static const unsigned int pwm0_b_pins
[] = {
2669 static const unsigned int pwm0_b_mux
[] = {
2672 static const unsigned int pwm1_pins
[] = {
2675 static const unsigned int pwm1_mux
[] = {
2678 static const unsigned int pwm1_b_pins
[] = {
2681 static const unsigned int pwm1_b_mux
[] = {
2684 static const unsigned int pwm2_pins
[] = {
2687 static const unsigned int pwm2_mux
[] = {
2690 static const unsigned int pwm3_pins
[] = {
2693 static const unsigned int pwm3_mux
[] = {
2696 static const unsigned int pwm4_pins
[] = {
2699 static const unsigned int pwm4_mux
[] = {
2702 static const unsigned int pwm5_pins
[] = {
2705 static const unsigned int pwm5_mux
[] = {
2708 static const unsigned int pwm6_pins
[] = {
2711 static const unsigned int pwm6_mux
[] = {
2714 /* - QSPI ------------------------------------------------------------------- */
2715 static const unsigned int qspi_ctrl_pins
[] = {
2717 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2719 static const unsigned int qspi_ctrl_mux
[] = {
2720 SPCLK_MARK
, SSL_MARK
,
2722 static const unsigned int qspi_data2_pins
[] = {
2723 /* MOSI_IO0, MISO_IO1 */
2724 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2726 static const unsigned int qspi_data2_mux
[] = {
2727 MOSI_IO0_MARK
, MISO_IO1_MARK
,
2729 static const unsigned int qspi_data4_pins
[] = {
2730 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2731 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2734 static const unsigned int qspi_data4_mux
[] = {
2735 MOSI_IO0_MARK
, MISO_IO1_MARK
, IO2_MARK
, IO3_MARK
,
2737 /* - SCIF0 ------------------------------------------------------------------ */
2738 static const unsigned int scif0_data_pins
[] = {
2740 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2742 static const unsigned int scif0_data_mux
[] = {
2745 static const unsigned int scif0_clk_pins
[] = {
2749 static const unsigned int scif0_clk_mux
[] = {
2752 static const unsigned int scif0_ctrl_pins
[] = {
2754 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2756 static const unsigned int scif0_ctrl_mux
[] = {
2757 RTS0_N_MARK
, CTS0_N_MARK
,
2759 static const unsigned int scif0_data_b_pins
[] = {
2761 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2763 static const unsigned int scif0_data_b_mux
[] = {
2764 RX0_B_MARK
, TX0_B_MARK
,
2766 /* - SCIF1 ------------------------------------------------------------------ */
2767 static const unsigned int scif1_data_pins
[] = {
2769 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2771 static const unsigned int scif1_data_mux
[] = {
2774 static const unsigned int scif1_clk_pins
[] = {
2778 static const unsigned int scif1_clk_mux
[] = {
2781 static const unsigned int scif1_ctrl_pins
[] = {
2783 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2785 static const unsigned int scif1_ctrl_mux
[] = {
2786 RTS1_N_MARK
, CTS1_N_MARK
,
2788 static const unsigned int scif1_data_b_pins
[] = {
2790 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2792 static const unsigned int scif1_data_b_mux
[] = {
2793 RX1_B_MARK
, TX1_B_MARK
,
2795 static const unsigned int scif1_data_c_pins
[] = {
2797 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2799 static const unsigned int scif1_data_c_mux
[] = {
2800 RX1_C_MARK
, TX1_C_MARK
,
2802 static const unsigned int scif1_data_d_pins
[] = {
2804 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2806 static const unsigned int scif1_data_d_mux
[] = {
2807 RX1_D_MARK
, TX1_D_MARK
,
2809 static const unsigned int scif1_clk_d_pins
[] = {
2813 static const unsigned int scif1_clk_d_mux
[] = {
2816 static const unsigned int scif1_data_e_pins
[] = {
2818 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2820 static const unsigned int scif1_data_e_mux
[] = {
2821 RX1_E_MARK
, TX1_E_MARK
,
2823 static const unsigned int scif1_clk_e_pins
[] = {
2827 static const unsigned int scif1_clk_e_mux
[] = {
2830 /* - SCIF2 ------------------------------------------------------------------ */
2831 static const unsigned int scif2_data_pins
[] = {
2833 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2835 static const unsigned int scif2_data_mux
[] = {
2838 static const unsigned int scif2_clk_pins
[] = {
2842 static const unsigned int scif2_clk_mux
[] = {
2845 static const unsigned int scif2_data_b_pins
[] = {
2847 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2849 static const unsigned int scif2_data_b_mux
[] = {
2850 RX2_B_MARK
, TX2_B_MARK
,
2852 /* - SCIFA0 ----------------------------------------------------------------- */
2853 static const unsigned int scifa0_data_pins
[] = {
2855 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2857 static const unsigned int scifa0_data_mux
[] = {
2858 SCIFA0_RXD_MARK
, SCIFA0_TXD_MARK
,
2860 static const unsigned int scifa0_clk_pins
[] = {
2864 static const unsigned int scifa0_clk_mux
[] = {
2867 static const unsigned int scifa0_ctrl_pins
[] = {
2869 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2871 static const unsigned int scifa0_ctrl_mux
[] = {
2872 SCIFA0_RTS_N_MARK
, SCIFA0_CTS_N_MARK
,
2874 static const unsigned int scifa0_data_b_pins
[] = {
2876 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2878 static const unsigned int scifa0_data_b_mux
[] = {
2879 SCIFA0_RXD_B_MARK
, SCIFA0_TXD_B_MARK
2881 static const unsigned int scifa0_clk_b_pins
[] = {
2885 static const unsigned int scifa0_clk_b_mux
[] = {
2888 static const unsigned int scifa0_ctrl_b_pins
[] = {
2890 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2892 static const unsigned int scifa0_ctrl_b_mux
[] = {
2893 SCIFA0_RTS_N_B_MARK
, SCIFA0_CTS_N_B_MARK
,
2895 /* - SCIFA1 ----------------------------------------------------------------- */
2896 static const unsigned int scifa1_data_pins
[] = {
2898 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2900 static const unsigned int scifa1_data_mux
[] = {
2901 SCIFA1_RXD_MARK
, SCIFA1_TXD_MARK
,
2903 static const unsigned int scifa1_clk_pins
[] = {
2907 static const unsigned int scifa1_clk_mux
[] = {
2910 static const unsigned int scifa1_ctrl_pins
[] = {
2912 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2914 static const unsigned int scifa1_ctrl_mux
[] = {
2915 SCIFA1_RTS_N_MARK
, SCIFA1_CTS_N_MARK
,
2917 static const unsigned int scifa1_data_b_pins
[] = {
2919 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2921 static const unsigned int scifa1_data_b_mux
[] = {
2922 SCIFA1_RXD_B_MARK
, SCIFA1_TXD_B_MARK
,
2924 static const unsigned int scifa1_clk_b_pins
[] = {
2928 static const unsigned int scifa1_clk_b_mux
[] = {
2931 static const unsigned int scifa1_ctrl_b_pins
[] = {
2933 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2935 static const unsigned int scifa1_ctrl_b_mux
[] = {
2936 SCIFA1_RTS_N_B_MARK
, SCIFA1_CTS_N_B_MARK
,
2938 static const unsigned int scifa1_data_c_pins
[] = {
2940 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2942 static const unsigned int scifa1_data_c_mux
[] = {
2943 SCIFA1_RXD_C_MARK
, SCIFA1_TXD_C_MARK
,
2945 static const unsigned int scifa1_clk_c_pins
[] = {
2949 static const unsigned int scifa1_clk_c_mux
[] = {
2952 static const unsigned int scifa1_ctrl_c_pins
[] = {
2954 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2956 static const unsigned int scifa1_ctrl_c_mux
[] = {
2957 SCIFA1_RTS_N_C_MARK
, SCIFA1_CTS_N_C_MARK
,
2959 static const unsigned int scifa1_data_d_pins
[] = {
2961 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2963 static const unsigned int scifa1_data_d_mux
[] = {
2964 SCIFA1_RXD_D_MARK
, SCIFA1_TXD_D_MARK
,
2966 static const unsigned int scifa1_clk_d_pins
[] = {
2970 static const unsigned int scifa1_clk_d_mux
[] = {
2973 static const unsigned int scifa1_ctrl_d_pins
[] = {
2975 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2977 static const unsigned int scifa1_ctrl_d_mux
[] = {
2978 SCIFA1_RTS_N_D_MARK
, SCIFA1_CTS_N_D_MARK
,
2980 /* - SCIFA2 ----------------------------------------------------------------- */
2981 static const unsigned int scifa2_data_pins
[] = {
2983 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2985 static const unsigned int scifa2_data_mux
[] = {
2986 SCIFA2_RXD_MARK
, SCIFA2_TXD_MARK
,
2988 static const unsigned int scifa2_clk_pins
[] = {
2992 static const unsigned int scifa2_clk_mux
[] = {
2995 static const unsigned int scifa2_ctrl_pins
[] = {
2997 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
2999 static const unsigned int scifa2_ctrl_mux
[] = {
3000 SCIFA2_RTS_N_MARK
, SCIFA2_CTS_N_MARK
,
3002 static const unsigned int scifa2_data_b_pins
[] = {
3004 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
3006 static const unsigned int scifa2_data_b_mux
[] = {
3007 SCIFA2_RXD_B_MARK
, SCIFA2_TXD_B_MARK
,
3009 static const unsigned int scifa2_data_c_pins
[] = {
3011 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
3013 static const unsigned int scifa2_data_c_mux
[] = {
3014 SCIFA2_RXD_C_MARK
, SCIFA2_TXD_C_MARK
,
3016 static const unsigned int scifa2_clk_c_pins
[] = {
3020 static const unsigned int scifa2_clk_c_mux
[] = {
3023 /* - SCIFB0 ----------------------------------------------------------------- */
3024 static const unsigned int scifb0_data_pins
[] = {
3026 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3028 static const unsigned int scifb0_data_mux
[] = {
3029 SCIFB0_RXD_MARK
, SCIFB0_TXD_MARK
,
3031 static const unsigned int scifb0_clk_pins
[] = {
3035 static const unsigned int scifb0_clk_mux
[] = {
3038 static const unsigned int scifb0_ctrl_pins
[] = {
3040 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
3042 static const unsigned int scifb0_ctrl_mux
[] = {
3043 SCIFB0_RTS_N_MARK
, SCIFB0_CTS_N_MARK
,
3045 static const unsigned int scifb0_data_b_pins
[] = {
3047 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3049 static const unsigned int scifb0_data_b_mux
[] = {
3050 SCIFB0_RXD_B_MARK
, SCIFB0_TXD_B_MARK
,
3052 static const unsigned int scifb0_clk_b_pins
[] = {
3056 static const unsigned int scifb0_clk_b_mux
[] = {
3059 static const unsigned int scifb0_ctrl_b_pins
[] = {
3061 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
3063 static const unsigned int scifb0_ctrl_b_mux
[] = {
3064 SCIFB0_RTS_N_B_MARK
, SCIFB0_CTS_N_B_MARK
,
3066 static const unsigned int scifb0_data_c_pins
[] = {
3068 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3070 static const unsigned int scifb0_data_c_mux
[] = {
3071 SCIFB0_RXD_C_MARK
, SCIFB0_TXD_C_MARK
,
3073 /* - SCIFB1 ----------------------------------------------------------------- */
3074 static const unsigned int scifb1_data_pins
[] = {
3076 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3078 static const unsigned int scifb1_data_mux
[] = {
3079 SCIFB1_RXD_MARK
, SCIFB1_TXD_MARK
,
3081 static const unsigned int scifb1_clk_pins
[] = {
3085 static const unsigned int scifb1_clk_mux
[] = {
3088 static const unsigned int scifb1_ctrl_pins
[] = {
3090 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
3092 static const unsigned int scifb1_ctrl_mux
[] = {
3093 SCIFB1_RTS_N_MARK
, SCIFB1_CTS_N_MARK
,
3095 static const unsigned int scifb1_data_b_pins
[] = {
3097 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3099 static const unsigned int scifb1_data_b_mux
[] = {
3100 SCIFB1_RXD_B_MARK
, SCIFB1_TXD_B_MARK
,
3102 static const unsigned int scifb1_clk_b_pins
[] = {
3106 static const unsigned int scifb1_clk_b_mux
[] = {
3109 static const unsigned int scifb1_ctrl_b_pins
[] = {
3111 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
3113 static const unsigned int scifb1_ctrl_b_mux
[] = {
3114 SCIFB1_RTS_N_B_MARK
, SCIFB1_CTS_N_B_MARK
,
3116 static const unsigned int scifb1_data_c_pins
[] = {
3118 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3120 static const unsigned int scifb1_data_c_mux
[] = {
3121 SCIFB1_RXD_C_MARK
, SCIFB1_TXD_C_MARK
,
3123 static const unsigned int scifb1_data_d_pins
[] = {
3125 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
3127 static const unsigned int scifb1_data_d_mux
[] = {
3128 SCIFB1_RXD_D_MARK
, SCIFB1_TXD_D_MARK
,
3130 static const unsigned int scifb1_data_e_pins
[] = {
3132 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
3134 static const unsigned int scifb1_data_e_mux
[] = {
3135 SCIFB1_RXD_E_MARK
, SCIFB1_TXD_E_MARK
,
3137 static const unsigned int scifb1_clk_e_pins
[] = {
3141 static const unsigned int scifb1_clk_e_mux
[] = {
3144 static const unsigned int scifb1_data_f_pins
[] = {
3146 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3148 static const unsigned int scifb1_data_f_mux
[] = {
3149 SCIFB1_RXD_F_MARK
, SCIFB1_TXD_F_MARK
,
3151 static const unsigned int scifb1_data_g_pins
[] = {
3153 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3155 static const unsigned int scifb1_data_g_mux
[] = {
3156 SCIFB1_RXD_G_MARK
, SCIFB1_TXD_G_MARK
,
3158 static const unsigned int scifb1_clk_g_pins
[] = {
3162 static const unsigned int scifb1_clk_g_mux
[] = {
3165 /* - SCIFB2 ----------------------------------------------------------------- */
3166 static const unsigned int scifb2_data_pins
[] = {
3168 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3170 static const unsigned int scifb2_data_mux
[] = {
3171 SCIFB2_RXD_MARK
, SCIFB2_TXD_MARK
,
3173 static const unsigned int scifb2_clk_pins
[] = {
3177 static const unsigned int scifb2_clk_mux
[] = {
3180 static const unsigned int scifb2_ctrl_pins
[] = {
3182 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
3184 static const unsigned int scifb2_ctrl_mux
[] = {
3185 SCIFB2_RTS_N_MARK
, SCIFB2_CTS_N_MARK
,
3187 static const unsigned int scifb2_data_b_pins
[] = {
3189 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
3191 static const unsigned int scifb2_data_b_mux
[] = {
3192 SCIFB2_RXD_B_MARK
, SCIFB2_TXD_B_MARK
,
3194 static const unsigned int scifb2_clk_b_pins
[] = {
3198 static const unsigned int scifb2_clk_b_mux
[] = {
3201 static const unsigned int scifb2_ctrl_b_pins
[] = {
3203 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
3205 static const unsigned int scifb2_ctrl_b_mux
[] = {
3206 SCIFB2_RTS_N_B_MARK
, SCIFB2_CTS_N_B_MARK
,
3208 static const unsigned int scifb2_data_c_pins
[] = {
3210 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3212 static const unsigned int scifb2_data_c_mux
[] = {
3213 SCIFB2_RXD_C_MARK
, SCIFB2_TXD_C_MARK
,
3215 /* - SCIF Clock ------------------------------------------------------------- */
3216 static const unsigned int scif_clk_pins
[] = {
3220 static const unsigned int scif_clk_mux
[] = {
3223 static const unsigned int scif_clk_b_pins
[] = {
3227 static const unsigned int scif_clk_b_mux
[] = {
3230 /* - SDHI0 ------------------------------------------------------------------ */
3231 static const unsigned int sdhi0_data1_pins
[] = {
3235 static const unsigned int sdhi0_data1_mux
[] = {
3238 static const unsigned int sdhi0_data4_pins
[] = {
3240 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3242 static const unsigned int sdhi0_data4_mux
[] = {
3243 SD0_DAT0_MARK
, SD0_DAT1_MARK
, SD0_DAT2_MARK
, SD0_DAT3_MARK
,
3245 static const unsigned int sdhi0_ctrl_pins
[] = {
3247 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3249 static const unsigned int sdhi0_ctrl_mux
[] = {
3250 SD0_CLK_MARK
, SD0_CMD_MARK
,
3252 static const unsigned int sdhi0_cd_pins
[] = {
3256 static const unsigned int sdhi0_cd_mux
[] = {
3259 static const unsigned int sdhi0_wp_pins
[] = {
3263 static const unsigned int sdhi0_wp_mux
[] = {
3266 /* - SDHI1 ------------------------------------------------------------------ */
3267 static const unsigned int sdhi1_data1_pins
[] = {
3271 static const unsigned int sdhi1_data1_mux
[] = {
3274 static const unsigned int sdhi1_data4_pins
[] = {
3276 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3278 static const unsigned int sdhi1_data4_mux
[] = {
3279 SD1_DAT0_MARK
, SD1_DAT1_MARK
, SD1_DAT2_MARK
, SD1_DAT3_MARK
,
3281 static const unsigned int sdhi1_ctrl_pins
[] = {
3283 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3285 static const unsigned int sdhi1_ctrl_mux
[] = {
3286 SD1_CLK_MARK
, SD1_CMD_MARK
,
3288 static const unsigned int sdhi1_cd_pins
[] = {
3292 static const unsigned int sdhi1_cd_mux
[] = {
3295 static const unsigned int sdhi1_wp_pins
[] = {
3299 static const unsigned int sdhi1_wp_mux
[] = {
3302 /* - SDHI2 ------------------------------------------------------------------ */
3303 static const unsigned int sdhi2_data1_pins
[] = {
3307 static const unsigned int sdhi2_data1_mux
[] = {
3310 static const unsigned int sdhi2_data4_pins
[] = {
3312 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
3314 static const unsigned int sdhi2_data4_mux
[] = {
3315 SD2_DAT0_MARK
, SD2_DAT1_MARK
, SD2_DAT2_MARK
, SD2_DAT3_MARK
,
3317 static const unsigned int sdhi2_ctrl_pins
[] = {
3319 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
3321 static const unsigned int sdhi2_ctrl_mux
[] = {
3322 SD2_CLK_MARK
, SD2_CMD_MARK
,
3324 static const unsigned int sdhi2_cd_pins
[] = {
3328 static const unsigned int sdhi2_cd_mux
[] = {
3331 static const unsigned int sdhi2_wp_pins
[] = {
3335 static const unsigned int sdhi2_wp_mux
[] = {
3338 /* - SDHI3 ------------------------------------------------------------------ */
3339 static const unsigned int sdhi3_data1_pins
[] = {
3343 static const unsigned int sdhi3_data1_mux
[] = {
3346 static const unsigned int sdhi3_data4_pins
[] = {
3348 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
3350 static const unsigned int sdhi3_data4_mux
[] = {
3351 SD3_DAT0_MARK
, SD3_DAT1_MARK
, SD3_DAT2_MARK
, SD3_DAT3_MARK
,
3353 static const unsigned int sdhi3_ctrl_pins
[] = {
3355 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
3357 static const unsigned int sdhi3_ctrl_mux
[] = {
3358 SD3_CLK_MARK
, SD3_CMD_MARK
,
3360 static const unsigned int sdhi3_cd_pins
[] = {
3364 static const unsigned int sdhi3_cd_mux
[] = {
3367 static const unsigned int sdhi3_wp_pins
[] = {
3371 static const unsigned int sdhi3_wp_mux
[] = {
3374 /* - SSI -------------------------------------------------------------------- */
3375 static const unsigned int ssi0_data_pins
[] = {
3379 static const unsigned int ssi0_data_mux
[] = {
3382 static const unsigned int ssi0129_ctrl_pins
[] = {
3384 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3386 static const unsigned int ssi0129_ctrl_mux
[] = {
3387 SSI_SCK0129_MARK
, SSI_WS0129_MARK
,
3389 static const unsigned int ssi1_data_pins
[] = {
3393 static const unsigned int ssi1_data_mux
[] = {
3396 static const unsigned int ssi1_ctrl_pins
[] = {
3398 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3400 static const unsigned int ssi1_ctrl_mux
[] = {
3401 SSI_SCK1_MARK
, SSI_WS1_MARK
,
3403 static const unsigned int ssi2_data_pins
[] = {
3407 static const unsigned int ssi2_data_mux
[] = {
3410 static const unsigned int ssi2_ctrl_pins
[] = {
3412 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3414 static const unsigned int ssi2_ctrl_mux
[] = {
3415 SSI_SCK2_MARK
, SSI_WS2_MARK
,
3417 static const unsigned int ssi3_data_pins
[] = {
3421 static const unsigned int ssi3_data_mux
[] = {
3424 static const unsigned int ssi34_ctrl_pins
[] = {
3426 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3428 static const unsigned int ssi34_ctrl_mux
[] = {
3429 SSI_SCK34_MARK
, SSI_WS34_MARK
,
3431 static const unsigned int ssi4_data_pins
[] = {
3435 static const unsigned int ssi4_data_mux
[] = {
3438 static const unsigned int ssi4_ctrl_pins
[] = {
3440 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3442 static const unsigned int ssi4_ctrl_mux
[] = {
3443 SSI_SCK4_MARK
, SSI_WS4_MARK
,
3445 static const unsigned int ssi5_pins
[] = {
3446 /* SDATA5, SCK, WS */
3447 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3449 static const unsigned int ssi5_mux
[] = {
3450 SSI_SDATA5_MARK
, SSI_SCK5_MARK
, SSI_WS5_MARK
,
3452 static const unsigned int ssi5_b_pins
[] = {
3453 /* SDATA5, SCK, WS */
3454 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3456 static const unsigned int ssi5_b_mux
[] = {
3457 SSI_SDATA5_B_MARK
, SSI_SCK5_B_MARK
, SSI_WS5_B_MARK
3459 static const unsigned int ssi5_c_pins
[] = {
3460 /* SDATA5, SCK, WS */
3461 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3463 static const unsigned int ssi5_c_mux
[] = {
3464 SSI_SDATA5_C_MARK
, SSI_SCK5_C_MARK
, SSI_WS5_C_MARK
,
3466 static const unsigned int ssi6_pins
[] = {
3467 /* SDATA6, SCK, WS */
3468 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3470 static const unsigned int ssi6_mux
[] = {
3471 SSI_SDATA6_MARK
, SSI_SCK6_MARK
, SSI_WS6_MARK
,
3473 static const unsigned int ssi6_b_pins
[] = {
3474 /* SDATA6, SCK, WS */
3475 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3477 static const unsigned int ssi6_b_mux
[] = {
3478 SSI_SDATA6_B_MARK
, SSI_SCK6_B_MARK
, SSI_WS6_B_MARK
,
3480 static const unsigned int ssi7_data_pins
[] = {
3484 static const unsigned int ssi7_data_mux
[] = {
3487 static const unsigned int ssi7_b_data_pins
[] = {
3491 static const unsigned int ssi7_b_data_mux
[] = {
3494 static const unsigned int ssi7_c_data_pins
[] = {
3498 static const unsigned int ssi7_c_data_mux
[] = {
3501 static const unsigned int ssi78_ctrl_pins
[] = {
3503 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3505 static const unsigned int ssi78_ctrl_mux
[] = {
3506 SSI_SCK78_MARK
, SSI_WS78_MARK
,
3508 static const unsigned int ssi78_b_ctrl_pins
[] = {
3510 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3512 static const unsigned int ssi78_b_ctrl_mux
[] = {
3513 SSI_SCK78_B_MARK
, SSI_WS78_B_MARK
,
3515 static const unsigned int ssi78_c_ctrl_pins
[] = {
3517 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3519 static const unsigned int ssi78_c_ctrl_mux
[] = {
3520 SSI_SCK78_C_MARK
, SSI_WS78_C_MARK
,
3522 static const unsigned int ssi8_data_pins
[] = {
3526 static const unsigned int ssi8_data_mux
[] = {
3529 static const unsigned int ssi8_b_data_pins
[] = {
3533 static const unsigned int ssi8_b_data_mux
[] = {
3536 static const unsigned int ssi8_c_data_pins
[] = {
3540 static const unsigned int ssi8_c_data_mux
[] = {
3543 static const unsigned int ssi9_data_pins
[] = {
3547 static const unsigned int ssi9_data_mux
[] = {
3550 static const unsigned int ssi9_ctrl_pins
[] = {
3552 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3554 static const unsigned int ssi9_ctrl_mux
[] = {
3555 SSI_SCK9_MARK
, SSI_WS9_MARK
,
3557 /* - TPU0 ------------------------------------------------------------------- */
3558 static const unsigned int tpu0_to0_pins
[] = {
3562 static const unsigned int tpu0_to0_mux
[] = {
3565 static const unsigned int tpu0_to1_pins
[] = {
3569 static const unsigned int tpu0_to1_mux
[] = {
3572 static const unsigned int tpu0_to2_pins
[] = {
3576 static const unsigned int tpu0_to2_mux
[] = {
3579 static const unsigned int tpu0_to3_pins
[] = {
3583 static const unsigned int tpu0_to3_mux
[] = {
3586 /* - USB0 ------------------------------------------------------------------- */
3587 static const unsigned int usb0_pins
[] = {
3588 /* PWEN, OVC/VBUS */
3589 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3591 static const unsigned int usb0_mux
[] = {
3592 USB0_PWEN_MARK
, USB0_OVC_VBUS_MARK
,
3594 static const unsigned int usb0_ovc_vbus_pins
[] = {
3598 static const unsigned int usb0_ovc_vbus_mux
[] = {
3601 /* - USB1 ------------------------------------------------------------------- */
3602 static const unsigned int usb1_pins
[] = {
3604 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3606 static const unsigned int usb1_mux
[] = {
3607 USB1_PWEN_MARK
, USB1_OVC_MARK
,
3609 /* - USB2 ------------------------------------------------------------------- */
3610 static const unsigned int usb2_pins
[] = {
3612 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3614 static const unsigned int usb2_mux
[] = {
3615 USB2_PWEN_MARK
, USB2_OVC_MARK
,
3617 /* - VIN0 ------------------------------------------------------------------- */
3618 static const union vin_data vin0_data_pins
= {
3621 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3622 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3623 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3624 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3626 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3627 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3628 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3629 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3631 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3632 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3633 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3634 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3637 static const union vin_data vin0_data_mux
= {
3640 VI0_DATA0_VI0_B0_MARK
, VI0_DATA1_VI0_B1_MARK
,
3641 VI0_DATA2_VI0_B2_MARK
, VI0_DATA3_VI0_B3_MARK
,
3642 VI0_DATA4_VI0_B4_MARK
, VI0_DATA5_VI0_B5_MARK
,
3643 VI0_DATA6_VI0_B6_MARK
, VI0_DATA7_VI0_B7_MARK
,
3645 VI0_G0_MARK
, VI0_G1_MARK
,
3646 VI0_G2_MARK
, VI0_G3_MARK
,
3647 VI0_G4_MARK
, VI0_G5_MARK
,
3648 VI0_G6_MARK
, VI0_G7_MARK
,
3650 VI0_R0_MARK
, VI0_R1_MARK
,
3651 VI0_R2_MARK
, VI0_R3_MARK
,
3652 VI0_R4_MARK
, VI0_R5_MARK
,
3653 VI0_R6_MARK
, VI0_R7_MARK
,
3656 static const unsigned int vin0_data18_pins
[] = {
3658 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3659 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3660 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3662 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3663 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3664 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3666 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3667 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3668 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3670 static const unsigned int vin0_data18_mux
[] = {
3672 VI0_DATA2_VI0_B2_MARK
, VI0_DATA3_VI0_B3_MARK
,
3673 VI0_DATA4_VI0_B4_MARK
, VI0_DATA5_VI0_B5_MARK
,
3674 VI0_DATA6_VI0_B6_MARK
, VI0_DATA7_VI0_B7_MARK
,
3676 VI0_G2_MARK
, VI0_G3_MARK
,
3677 VI0_G4_MARK
, VI0_G5_MARK
,
3678 VI0_G6_MARK
, VI0_G7_MARK
,
3680 VI0_R2_MARK
, VI0_R3_MARK
,
3681 VI0_R4_MARK
, VI0_R5_MARK
,
3682 VI0_R6_MARK
, VI0_R7_MARK
,
3684 static const unsigned int vin0_sync_pins
[] = {
3685 RCAR_GP_PIN(0, 12), /* HSYNC */
3686 RCAR_GP_PIN(0, 13), /* VSYNC */
3688 static const unsigned int vin0_sync_mux
[] = {
3692 static const unsigned int vin0_field_pins
[] = {
3695 static const unsigned int vin0_field_mux
[] = {
3698 static const unsigned int vin0_clkenb_pins
[] = {
3701 static const unsigned int vin0_clkenb_mux
[] = {
3704 static const unsigned int vin0_clk_pins
[] = {
3707 static const unsigned int vin0_clk_mux
[] = {
3710 /* - VIN1 ------------------------------------------------------------------- */
3711 static const union vin_data vin1_data_pins
= {
3714 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3715 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3716 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3717 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3719 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3720 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3721 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3722 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3724 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3725 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3726 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3727 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3730 static const union vin_data vin1_data_mux
= {
3733 VI1_DATA0_VI1_B0_MARK
, VI1_DATA1_VI1_B1_MARK
,
3734 VI1_DATA2_VI1_B2_MARK
, VI1_DATA3_VI1_B3_MARK
,
3735 VI1_DATA4_VI1_B4_MARK
, VI1_DATA5_VI1_B5_MARK
,
3736 VI1_DATA6_VI1_B6_MARK
, VI1_DATA7_VI1_B7_MARK
,
3738 VI1_G0_MARK
, VI1_G1_MARK
,
3739 VI1_G2_MARK
, VI1_G3_MARK
,
3740 VI1_G4_MARK
, VI1_G5_MARK
,
3741 VI1_G6_MARK
, VI1_G7_MARK
,
3743 VI1_R0_MARK
, VI1_R1_MARK
,
3744 VI1_R2_MARK
, VI1_R3_MARK
,
3745 VI1_R4_MARK
, VI1_R5_MARK
,
3746 VI1_R6_MARK
, VI1_R7_MARK
,
3749 static const unsigned int vin1_data18_pins
[] = {
3751 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3752 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3753 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3755 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3756 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3757 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3759 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3760 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3761 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3763 static const unsigned int vin1_data18_mux
[] = {
3765 VI1_DATA2_VI1_B2_MARK
, VI1_DATA3_VI1_B3_MARK
,
3766 VI1_DATA4_VI1_B4_MARK
, VI1_DATA5_VI1_B5_MARK
,
3767 VI1_DATA6_VI1_B6_MARK
, VI1_DATA7_VI1_B7_MARK
,
3769 VI1_G2_MARK
, VI1_G3_MARK
,
3770 VI1_G4_MARK
, VI1_G5_MARK
,
3771 VI1_G6_MARK
, VI1_G7_MARK
,
3773 VI1_R2_MARK
, VI1_R3_MARK
,
3774 VI1_R4_MARK
, VI1_R5_MARK
,
3775 VI1_R6_MARK
, VI1_R7_MARK
,
3777 static const unsigned int vin1_sync_pins
[] = {
3778 RCAR_GP_PIN(1, 24), /* HSYNC */
3779 RCAR_GP_PIN(1, 25), /* VSYNC */
3781 static const unsigned int vin1_sync_mux
[] = {
3785 static const unsigned int vin1_field_pins
[] = {
3788 static const unsigned int vin1_field_mux
[] = {
3791 static const unsigned int vin1_clkenb_pins
[] = {
3794 static const unsigned int vin1_clkenb_mux
[] = {
3797 static const unsigned int vin1_clk_pins
[] = {
3800 static const unsigned int vin1_clk_mux
[] = {
3803 /* - VIN2 ----------------------------------------------------------------- */
3804 static const union vin_data vin2_data_pins
= {
3807 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3808 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3809 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3810 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3812 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3813 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3814 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3815 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3817 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3818 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3819 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3820 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3823 static const union vin_data vin2_data_mux
= {
3826 VI2_DATA0_VI2_B0_MARK
, VI2_DATA1_VI2_B1_MARK
,
3827 VI2_DATA2_VI2_B2_MARK
, VI2_DATA3_VI2_B3_MARK
,
3828 VI2_DATA4_VI2_B4_MARK
, VI2_DATA5_VI2_B5_MARK
,
3829 VI2_DATA6_VI2_B6_MARK
, VI2_DATA7_VI2_B7_MARK
,
3831 VI2_G0_MARK
, VI2_G1_MARK
,
3832 VI2_G2_MARK
, VI2_G3_MARK
,
3833 VI2_G4_MARK
, VI2_G5_MARK
,
3834 VI2_G6_MARK
, VI2_G7_MARK
,
3836 VI2_R0_MARK
, VI2_R1_MARK
,
3837 VI2_R2_MARK
, VI2_R3_MARK
,
3838 VI2_R4_MARK
, VI2_R5_MARK
,
3839 VI2_R6_MARK
, VI2_R7_MARK
,
3842 static const unsigned int vin2_data18_pins
[] = {
3844 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3845 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3846 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3848 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3849 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3850 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3852 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3853 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3854 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3856 static const unsigned int vin2_data18_mux
[] = {
3858 VI2_DATA2_VI2_B2_MARK
, VI2_DATA3_VI2_B3_MARK
,
3859 VI2_DATA4_VI2_B4_MARK
, VI2_DATA5_VI2_B5_MARK
,
3860 VI2_DATA6_VI2_B6_MARK
, VI2_DATA7_VI2_B7_MARK
,
3862 VI2_G2_MARK
, VI2_G3_MARK
,
3863 VI2_G4_MARK
, VI2_G5_MARK
,
3864 VI2_G6_MARK
, VI2_G7_MARK
,
3866 VI2_R2_MARK
, VI2_R3_MARK
,
3867 VI2_R4_MARK
, VI2_R5_MARK
,
3868 VI2_R6_MARK
, VI2_R7_MARK
,
3870 static const unsigned int vin2_sync_pins
[] = {
3871 RCAR_GP_PIN(1, 16), /* HSYNC */
3872 RCAR_GP_PIN(1, 21), /* VSYNC */
3874 static const unsigned int vin2_sync_mux
[] = {
3878 static const unsigned int vin2_field_pins
[] = {
3881 static const unsigned int vin2_field_mux
[] = {
3884 static const unsigned int vin2_clkenb_pins
[] = {
3887 static const unsigned int vin2_clkenb_mux
[] = {
3890 static const unsigned int vin2_clk_pins
[] = {
3893 static const unsigned int vin2_clk_mux
[] = {
3896 /* - VIN3 ----------------------------------------------------------------- */
3897 static const unsigned int vin3_data8_pins
[] = {
3898 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3899 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3900 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3901 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3903 static const unsigned int vin3_data8_mux
[] = {
3904 VI3_DATA0_MARK
, VI3_DATA1_MARK
,
3905 VI3_DATA2_MARK
, VI3_DATA3_MARK
,
3906 VI3_DATA4_MARK
, VI3_DATA5_MARK
,
3907 VI3_DATA6_MARK
, VI3_DATA7_MARK
,
3909 static const unsigned int vin3_sync_pins
[] = {
3910 RCAR_GP_PIN(1, 16), /* HSYNC */
3911 RCAR_GP_PIN(1, 17), /* VSYNC */
3913 static const unsigned int vin3_sync_mux
[] = {
3917 static const unsigned int vin3_field_pins
[] = {
3920 static const unsigned int vin3_field_mux
[] = {
3923 static const unsigned int vin3_clkenb_pins
[] = {
3926 static const unsigned int vin3_clkenb_mux
[] = {
3929 static const unsigned int vin3_clk_pins
[] = {
3932 static const unsigned int vin3_clk_mux
[] = {
3936 static const struct sh_pfc_pin_group pinmux_groups
[] = {
3937 SH_PFC_PIN_GROUP(audio_clk_a
),
3938 SH_PFC_PIN_GROUP(audio_clk_b
),
3939 SH_PFC_PIN_GROUP(audio_clk_c
),
3940 SH_PFC_PIN_GROUP(audio_clkout
),
3941 SH_PFC_PIN_GROUP(audio_clkout_b
),
3942 SH_PFC_PIN_GROUP(audio_clkout_c
),
3943 SH_PFC_PIN_GROUP(audio_clkout_d
),
3944 SH_PFC_PIN_GROUP(avb_link
),
3945 SH_PFC_PIN_GROUP(avb_magic
),
3946 SH_PFC_PIN_GROUP(avb_phy_int
),
3947 SH_PFC_PIN_GROUP(avb_mdio
),
3948 SH_PFC_PIN_GROUP(avb_mii
),
3949 SH_PFC_PIN_GROUP(avb_gmii
),
3950 SH_PFC_PIN_GROUP(du_rgb666
),
3951 SH_PFC_PIN_GROUP(du_rgb888
),
3952 SH_PFC_PIN_GROUP(du_clk_out_0
),
3953 SH_PFC_PIN_GROUP(du_clk_out_1
),
3954 SH_PFC_PIN_GROUP(du_sync_0
),
3955 SH_PFC_PIN_GROUP(du_sync_1
),
3956 SH_PFC_PIN_GROUP(du_cde
),
3957 SH_PFC_PIN_GROUP(du0_clk_in
),
3958 SH_PFC_PIN_GROUP(du1_clk_in
),
3959 SH_PFC_PIN_GROUP(du2_clk_in
),
3960 SH_PFC_PIN_GROUP(eth_link
),
3961 SH_PFC_PIN_GROUP(eth_magic
),
3962 SH_PFC_PIN_GROUP(eth_mdio
),
3963 SH_PFC_PIN_GROUP(eth_rmii
),
3964 SH_PFC_PIN_GROUP(hscif0_data
),
3965 SH_PFC_PIN_GROUP(hscif0_clk
),
3966 SH_PFC_PIN_GROUP(hscif0_ctrl
),
3967 SH_PFC_PIN_GROUP(hscif0_data_b
),
3968 SH_PFC_PIN_GROUP(hscif0_ctrl_b
),
3969 SH_PFC_PIN_GROUP(hscif0_data_c
),
3970 SH_PFC_PIN_GROUP(hscif0_ctrl_c
),
3971 SH_PFC_PIN_GROUP(hscif0_data_d
),
3972 SH_PFC_PIN_GROUP(hscif0_ctrl_d
),
3973 SH_PFC_PIN_GROUP(hscif0_data_e
),
3974 SH_PFC_PIN_GROUP(hscif0_ctrl_e
),
3975 SH_PFC_PIN_GROUP(hscif0_data_f
),
3976 SH_PFC_PIN_GROUP(hscif0_ctrl_f
),
3977 SH_PFC_PIN_GROUP(hscif1_data
),
3978 SH_PFC_PIN_GROUP(hscif1_clk
),
3979 SH_PFC_PIN_GROUP(hscif1_ctrl
),
3980 SH_PFC_PIN_GROUP(hscif1_data_b
),
3981 SH_PFC_PIN_GROUP(hscif1_clk_b
),
3982 SH_PFC_PIN_GROUP(hscif1_ctrl_b
),
3983 SH_PFC_PIN_GROUP(i2c0
),
3984 SH_PFC_PIN_GROUP(i2c1
),
3985 SH_PFC_PIN_GROUP(i2c1_b
),
3986 SH_PFC_PIN_GROUP(i2c1_c
),
3987 SH_PFC_PIN_GROUP(i2c2
),
3988 SH_PFC_PIN_GROUP(i2c2_b
),
3989 SH_PFC_PIN_GROUP(i2c2_c
),
3990 SH_PFC_PIN_GROUP(i2c2_d
),
3991 SH_PFC_PIN_GROUP(i2c2_e
),
3992 SH_PFC_PIN_GROUP(i2c3
),
3993 SH_PFC_PIN_GROUP(iic0
),
3994 SH_PFC_PIN_GROUP(iic1
),
3995 SH_PFC_PIN_GROUP(iic1_b
),
3996 SH_PFC_PIN_GROUP(iic1_c
),
3997 SH_PFC_PIN_GROUP(iic2
),
3998 SH_PFC_PIN_GROUP(iic2_b
),
3999 SH_PFC_PIN_GROUP(iic2_c
),
4000 SH_PFC_PIN_GROUP(iic2_d
),
4001 SH_PFC_PIN_GROUP(iic2_e
),
4002 SH_PFC_PIN_GROUP(iic3
),
4003 SH_PFC_PIN_GROUP(intc_irq0
),
4004 SH_PFC_PIN_GROUP(intc_irq1
),
4005 SH_PFC_PIN_GROUP(intc_irq2
),
4006 SH_PFC_PIN_GROUP(intc_irq3
),
4007 SH_PFC_PIN_GROUP(mlb_3pin
),
4008 SH_PFC_PIN_GROUP(mmc0_data1
),
4009 SH_PFC_PIN_GROUP(mmc0_data4
),
4010 SH_PFC_PIN_GROUP(mmc0_data8
),
4011 SH_PFC_PIN_GROUP(mmc0_ctrl
),
4012 SH_PFC_PIN_GROUP(mmc1_data1
),
4013 SH_PFC_PIN_GROUP(mmc1_data4
),
4014 SH_PFC_PIN_GROUP(mmc1_data8
),
4015 SH_PFC_PIN_GROUP(mmc1_ctrl
),
4016 SH_PFC_PIN_GROUP(msiof0_clk
),
4017 SH_PFC_PIN_GROUP(msiof0_sync
),
4018 SH_PFC_PIN_GROUP(msiof0_ss1
),
4019 SH_PFC_PIN_GROUP(msiof0_ss2
),
4020 SH_PFC_PIN_GROUP(msiof0_rx
),
4021 SH_PFC_PIN_GROUP(msiof0_tx
),
4022 SH_PFC_PIN_GROUP(msiof0_clk_b
),
4023 SH_PFC_PIN_GROUP(msiof0_ss1_b
),
4024 SH_PFC_PIN_GROUP(msiof0_ss2_b
),
4025 SH_PFC_PIN_GROUP(msiof0_rx_b
),
4026 SH_PFC_PIN_GROUP(msiof0_tx_b
),
4027 SH_PFC_PIN_GROUP(msiof1_clk
),
4028 SH_PFC_PIN_GROUP(msiof1_sync
),
4029 SH_PFC_PIN_GROUP(msiof1_ss1
),
4030 SH_PFC_PIN_GROUP(msiof1_ss2
),
4031 SH_PFC_PIN_GROUP(msiof1_rx
),
4032 SH_PFC_PIN_GROUP(msiof1_tx
),
4033 SH_PFC_PIN_GROUP(msiof1_clk_b
),
4034 SH_PFC_PIN_GROUP(msiof1_ss1_b
),
4035 SH_PFC_PIN_GROUP(msiof1_ss2_b
),
4036 SH_PFC_PIN_GROUP(msiof1_rx_b
),
4037 SH_PFC_PIN_GROUP(msiof1_tx_b
),
4038 SH_PFC_PIN_GROUP(msiof2_clk
),
4039 SH_PFC_PIN_GROUP(msiof2_sync
),
4040 SH_PFC_PIN_GROUP(msiof2_ss1
),
4041 SH_PFC_PIN_GROUP(msiof2_ss2
),
4042 SH_PFC_PIN_GROUP(msiof2_rx
),
4043 SH_PFC_PIN_GROUP(msiof2_tx
),
4044 SH_PFC_PIN_GROUP(msiof3_clk
),
4045 SH_PFC_PIN_GROUP(msiof3_sync
),
4046 SH_PFC_PIN_GROUP(msiof3_ss1
),
4047 SH_PFC_PIN_GROUP(msiof3_ss2
),
4048 SH_PFC_PIN_GROUP(msiof3_rx
),
4049 SH_PFC_PIN_GROUP(msiof3_tx
),
4050 SH_PFC_PIN_GROUP(msiof3_clk_b
),
4051 SH_PFC_PIN_GROUP(msiof3_sync_b
),
4052 SH_PFC_PIN_GROUP(msiof3_rx_b
),
4053 SH_PFC_PIN_GROUP(msiof3_tx_b
),
4054 SH_PFC_PIN_GROUP(pwm0
),
4055 SH_PFC_PIN_GROUP(pwm0_b
),
4056 SH_PFC_PIN_GROUP(pwm1
),
4057 SH_PFC_PIN_GROUP(pwm1_b
),
4058 SH_PFC_PIN_GROUP(pwm2
),
4059 SH_PFC_PIN_GROUP(pwm3
),
4060 SH_PFC_PIN_GROUP(pwm4
),
4061 SH_PFC_PIN_GROUP(pwm5
),
4062 SH_PFC_PIN_GROUP(pwm6
),
4063 SH_PFC_PIN_GROUP(qspi_ctrl
),
4064 SH_PFC_PIN_GROUP(qspi_data2
),
4065 SH_PFC_PIN_GROUP(qspi_data4
),
4066 SH_PFC_PIN_GROUP(scif0_data
),
4067 SH_PFC_PIN_GROUP(scif0_clk
),
4068 SH_PFC_PIN_GROUP(scif0_ctrl
),
4069 SH_PFC_PIN_GROUP(scif0_data_b
),
4070 SH_PFC_PIN_GROUP(scif1_data
),
4071 SH_PFC_PIN_GROUP(scif1_clk
),
4072 SH_PFC_PIN_GROUP(scif1_ctrl
),
4073 SH_PFC_PIN_GROUP(scif1_data_b
),
4074 SH_PFC_PIN_GROUP(scif1_data_c
),
4075 SH_PFC_PIN_GROUP(scif1_data_d
),
4076 SH_PFC_PIN_GROUP(scif1_clk_d
),
4077 SH_PFC_PIN_GROUP(scif1_data_e
),
4078 SH_PFC_PIN_GROUP(scif1_clk_e
),
4079 SH_PFC_PIN_GROUP(scif2_data
),
4080 SH_PFC_PIN_GROUP(scif2_clk
),
4081 SH_PFC_PIN_GROUP(scif2_data_b
),
4082 SH_PFC_PIN_GROUP(scifa0_data
),
4083 SH_PFC_PIN_GROUP(scifa0_clk
),
4084 SH_PFC_PIN_GROUP(scifa0_ctrl
),
4085 SH_PFC_PIN_GROUP(scifa0_data_b
),
4086 SH_PFC_PIN_GROUP(scifa0_clk_b
),
4087 SH_PFC_PIN_GROUP(scifa0_ctrl_b
),
4088 SH_PFC_PIN_GROUP(scifa1_data
),
4089 SH_PFC_PIN_GROUP(scifa1_clk
),
4090 SH_PFC_PIN_GROUP(scifa1_ctrl
),
4091 SH_PFC_PIN_GROUP(scifa1_data_b
),
4092 SH_PFC_PIN_GROUP(scifa1_clk_b
),
4093 SH_PFC_PIN_GROUP(scifa1_ctrl_b
),
4094 SH_PFC_PIN_GROUP(scifa1_data_c
),
4095 SH_PFC_PIN_GROUP(scifa1_clk_c
),
4096 SH_PFC_PIN_GROUP(scifa1_ctrl_c
),
4097 SH_PFC_PIN_GROUP(scifa1_data_d
),
4098 SH_PFC_PIN_GROUP(scifa1_clk_d
),
4099 SH_PFC_PIN_GROUP(scifa1_ctrl_d
),
4100 SH_PFC_PIN_GROUP(scifa2_data
),
4101 SH_PFC_PIN_GROUP(scifa2_clk
),
4102 SH_PFC_PIN_GROUP(scifa2_ctrl
),
4103 SH_PFC_PIN_GROUP(scifa2_data_b
),
4104 SH_PFC_PIN_GROUP(scifa2_data_c
),
4105 SH_PFC_PIN_GROUP(scifa2_clk_c
),
4106 SH_PFC_PIN_GROUP(scifb0_data
),
4107 SH_PFC_PIN_GROUP(scifb0_clk
),
4108 SH_PFC_PIN_GROUP(scifb0_ctrl
),
4109 SH_PFC_PIN_GROUP(scifb0_data_b
),
4110 SH_PFC_PIN_GROUP(scifb0_clk_b
),
4111 SH_PFC_PIN_GROUP(scifb0_ctrl_b
),
4112 SH_PFC_PIN_GROUP(scifb0_data_c
),
4113 SH_PFC_PIN_GROUP(scifb1_data
),
4114 SH_PFC_PIN_GROUP(scifb1_clk
),
4115 SH_PFC_PIN_GROUP(scifb1_ctrl
),
4116 SH_PFC_PIN_GROUP(scifb1_data_b
),
4117 SH_PFC_PIN_GROUP(scifb1_clk_b
),
4118 SH_PFC_PIN_GROUP(scifb1_ctrl_b
),
4119 SH_PFC_PIN_GROUP(scifb1_data_c
),
4120 SH_PFC_PIN_GROUP(scifb1_data_d
),
4121 SH_PFC_PIN_GROUP(scifb1_data_e
),
4122 SH_PFC_PIN_GROUP(scifb1_clk_e
),
4123 SH_PFC_PIN_GROUP(scifb1_data_f
),
4124 SH_PFC_PIN_GROUP(scifb1_data_g
),
4125 SH_PFC_PIN_GROUP(scifb1_clk_g
),
4126 SH_PFC_PIN_GROUP(scifb2_data
),
4127 SH_PFC_PIN_GROUP(scifb2_clk
),
4128 SH_PFC_PIN_GROUP(scifb2_ctrl
),
4129 SH_PFC_PIN_GROUP(scifb2_data_b
),
4130 SH_PFC_PIN_GROUP(scifb2_clk_b
),
4131 SH_PFC_PIN_GROUP(scifb2_ctrl_b
),
4132 SH_PFC_PIN_GROUP(scifb2_data_c
),
4133 SH_PFC_PIN_GROUP(scif_clk
),
4134 SH_PFC_PIN_GROUP(scif_clk_b
),
4135 SH_PFC_PIN_GROUP(sdhi0_data1
),
4136 SH_PFC_PIN_GROUP(sdhi0_data4
),
4137 SH_PFC_PIN_GROUP(sdhi0_ctrl
),
4138 SH_PFC_PIN_GROUP(sdhi0_cd
),
4139 SH_PFC_PIN_GROUP(sdhi0_wp
),
4140 SH_PFC_PIN_GROUP(sdhi1_data1
),
4141 SH_PFC_PIN_GROUP(sdhi1_data4
),
4142 SH_PFC_PIN_GROUP(sdhi1_ctrl
),
4143 SH_PFC_PIN_GROUP(sdhi1_cd
),
4144 SH_PFC_PIN_GROUP(sdhi1_wp
),
4145 SH_PFC_PIN_GROUP(sdhi2_data1
),
4146 SH_PFC_PIN_GROUP(sdhi2_data4
),
4147 SH_PFC_PIN_GROUP(sdhi2_ctrl
),
4148 SH_PFC_PIN_GROUP(sdhi2_cd
),
4149 SH_PFC_PIN_GROUP(sdhi2_wp
),
4150 SH_PFC_PIN_GROUP(sdhi3_data1
),
4151 SH_PFC_PIN_GROUP(sdhi3_data4
),
4152 SH_PFC_PIN_GROUP(sdhi3_ctrl
),
4153 SH_PFC_PIN_GROUP(sdhi3_cd
),
4154 SH_PFC_PIN_GROUP(sdhi3_wp
),
4155 SH_PFC_PIN_GROUP(ssi0_data
),
4156 SH_PFC_PIN_GROUP(ssi0129_ctrl
),
4157 SH_PFC_PIN_GROUP(ssi1_data
),
4158 SH_PFC_PIN_GROUP(ssi1_ctrl
),
4159 SH_PFC_PIN_GROUP(ssi2_data
),
4160 SH_PFC_PIN_GROUP(ssi2_ctrl
),
4161 SH_PFC_PIN_GROUP(ssi3_data
),
4162 SH_PFC_PIN_GROUP(ssi34_ctrl
),
4163 SH_PFC_PIN_GROUP(ssi4_data
),
4164 SH_PFC_PIN_GROUP(ssi4_ctrl
),
4165 SH_PFC_PIN_GROUP(ssi5
),
4166 SH_PFC_PIN_GROUP(ssi5_b
),
4167 SH_PFC_PIN_GROUP(ssi5_c
),
4168 SH_PFC_PIN_GROUP(ssi6
),
4169 SH_PFC_PIN_GROUP(ssi6_b
),
4170 SH_PFC_PIN_GROUP(ssi7_data
),
4171 SH_PFC_PIN_GROUP(ssi7_b_data
),
4172 SH_PFC_PIN_GROUP(ssi7_c_data
),
4173 SH_PFC_PIN_GROUP(ssi78_ctrl
),
4174 SH_PFC_PIN_GROUP(ssi78_b_ctrl
),
4175 SH_PFC_PIN_GROUP(ssi78_c_ctrl
),
4176 SH_PFC_PIN_GROUP(ssi8_data
),
4177 SH_PFC_PIN_GROUP(ssi8_b_data
),
4178 SH_PFC_PIN_GROUP(ssi8_c_data
),
4179 SH_PFC_PIN_GROUP(ssi9_data
),
4180 SH_PFC_PIN_GROUP(ssi9_ctrl
),
4181 SH_PFC_PIN_GROUP(tpu0_to0
),
4182 SH_PFC_PIN_GROUP(tpu0_to1
),
4183 SH_PFC_PIN_GROUP(tpu0_to2
),
4184 SH_PFC_PIN_GROUP(tpu0_to3
),
4185 SH_PFC_PIN_GROUP(usb0
),
4186 SH_PFC_PIN_GROUP(usb0_ovc_vbus
),
4187 SH_PFC_PIN_GROUP(usb1
),
4188 SH_PFC_PIN_GROUP(usb2
),
4189 VIN_DATA_PIN_GROUP(vin0_data
, 24),
4190 VIN_DATA_PIN_GROUP(vin0_data
, 20),
4191 SH_PFC_PIN_GROUP(vin0_data18
),
4192 VIN_DATA_PIN_GROUP(vin0_data
, 16),
4193 VIN_DATA_PIN_GROUP(vin0_data
, 12),
4194 VIN_DATA_PIN_GROUP(vin0_data
, 10),
4195 VIN_DATA_PIN_GROUP(vin0_data
, 8),
4196 VIN_DATA_PIN_GROUP(vin0_data
, 4),
4197 SH_PFC_PIN_GROUP(vin0_sync
),
4198 SH_PFC_PIN_GROUP(vin0_field
),
4199 SH_PFC_PIN_GROUP(vin0_clkenb
),
4200 SH_PFC_PIN_GROUP(vin0_clk
),
4201 VIN_DATA_PIN_GROUP(vin1_data
, 24),
4202 VIN_DATA_PIN_GROUP(vin1_data
, 20),
4203 SH_PFC_PIN_GROUP(vin1_data18
),
4204 VIN_DATA_PIN_GROUP(vin1_data
, 16),
4205 VIN_DATA_PIN_GROUP(vin1_data
, 12),
4206 VIN_DATA_PIN_GROUP(vin1_data
, 10),
4207 VIN_DATA_PIN_GROUP(vin1_data
, 8),
4208 VIN_DATA_PIN_GROUP(vin1_data
, 4),
4209 SH_PFC_PIN_GROUP(vin1_sync
),
4210 SH_PFC_PIN_GROUP(vin1_field
),
4211 SH_PFC_PIN_GROUP(vin1_clkenb
),
4212 SH_PFC_PIN_GROUP(vin1_clk
),
4213 VIN_DATA_PIN_GROUP(vin2_data
, 24),
4214 SH_PFC_PIN_GROUP(vin2_data18
),
4215 VIN_DATA_PIN_GROUP(vin2_data
, 16),
4216 VIN_DATA_PIN_GROUP(vin2_data
, 8),
4217 VIN_DATA_PIN_GROUP(vin2_data
, 4),
4218 SH_PFC_PIN_GROUP(vin2_sync
),
4219 SH_PFC_PIN_GROUP(vin2_field
),
4220 SH_PFC_PIN_GROUP(vin2_clkenb
),
4221 SH_PFC_PIN_GROUP(vin2_clk
),
4222 SH_PFC_PIN_GROUP(vin3_data8
),
4223 SH_PFC_PIN_GROUP(vin3_sync
),
4224 SH_PFC_PIN_GROUP(vin3_field
),
4225 SH_PFC_PIN_GROUP(vin3_clkenb
),
4226 SH_PFC_PIN_GROUP(vin3_clk
),
4229 static const char * const audio_clk_groups
[] = {
4239 static const char * const avb_groups
[] = {
4248 static const char * const du_groups
[] = {
4258 static const char * const du0_groups
[] = {
4262 static const char * const du1_groups
[] = {
4266 static const char * const du2_groups
[] = {
4270 static const char * const eth_groups
[] = {
4277 static const char * const hscif0_groups
[] = {
4293 static const char * const hscif1_groups
[] = {
4302 static const char * const i2c0_groups
[] = {
4306 static const char * const i2c1_groups
[] = {
4312 static const char * const i2c2_groups
[] = {
4320 static const char * const i2c3_groups
[] = {
4324 static const char * const iic0_groups
[] = {
4328 static const char * const iic1_groups
[] = {
4334 static const char * const iic2_groups
[] = {
4342 static const char * const iic3_groups
[] = {
4346 static const char * const intc_groups
[] = {
4353 static const char * const mlb_groups
[] = {
4357 static const char * const mmc0_groups
[] = {
4364 static const char * const mmc1_groups
[] = {
4371 static const char * const msiof0_groups
[] = {
4385 static const char * const msiof1_groups
[] = {
4399 static const char * const msiof2_groups
[] = {
4408 static const char * const msiof3_groups
[] = {
4421 static const char * const pwm0_groups
[] = {
4426 static const char * const pwm1_groups
[] = {
4431 static const char * const pwm2_groups
[] = {
4435 static const char * const pwm3_groups
[] = {
4439 static const char * const pwm4_groups
[] = {
4443 static const char * const pwm5_groups
[] = {
4447 static const char * const pwm6_groups
[] = {
4451 static const char * const qspi_groups
[] = {
4457 static const char * const scif0_groups
[] = {
4464 static const char * const scif1_groups
[] = {
4476 static const char * const scif2_groups
[] = {
4482 static const char * const scifa0_groups
[] = {
4491 static const char * const scifa1_groups
[] = {
4506 static const char * const scifa2_groups
[] = {
4515 static const char * const scifb0_groups
[] = {
4525 static const char * const scifb1_groups
[] = {
4541 static const char * const scifb2_groups
[] = {
4551 static const char * const scif_clk_groups
[] = {
4556 static const char * const sdhi0_groups
[] = {
4564 static const char * const sdhi1_groups
[] = {
4572 static const char * const sdhi2_groups
[] = {
4580 static const char * const sdhi3_groups
[] = {
4588 static const char * const ssi_groups
[] = {
4617 static const char * const tpu0_groups
[] = {
4624 static const char * const usb0_groups
[] = {
4629 static const char * const usb1_groups
[] = {
4633 static const char * const usb2_groups
[] = {
4637 static const char * const vin0_groups
[] = {
4652 static const char * const vin1_groups
[] = {
4667 static const char * const vin2_groups
[] = {
4679 static const char * const vin3_groups
[] = {
4687 static const struct sh_pfc_function pinmux_functions
[] = {
4688 SH_PFC_FUNCTION(audio_clk
),
4689 SH_PFC_FUNCTION(avb
),
4690 SH_PFC_FUNCTION(du
),
4691 SH_PFC_FUNCTION(du0
),
4692 SH_PFC_FUNCTION(du1
),
4693 SH_PFC_FUNCTION(du2
),
4694 SH_PFC_FUNCTION(eth
),
4695 SH_PFC_FUNCTION(hscif0
),
4696 SH_PFC_FUNCTION(hscif1
),
4697 SH_PFC_FUNCTION(i2c0
),
4698 SH_PFC_FUNCTION(i2c1
),
4699 SH_PFC_FUNCTION(i2c2
),
4700 SH_PFC_FUNCTION(i2c3
),
4701 SH_PFC_FUNCTION(iic0
),
4702 SH_PFC_FUNCTION(iic1
),
4703 SH_PFC_FUNCTION(iic2
),
4704 SH_PFC_FUNCTION(iic3
),
4705 SH_PFC_FUNCTION(intc
),
4706 SH_PFC_FUNCTION(mlb
),
4707 SH_PFC_FUNCTION(mmc0
),
4708 SH_PFC_FUNCTION(mmc1
),
4709 SH_PFC_FUNCTION(msiof0
),
4710 SH_PFC_FUNCTION(msiof1
),
4711 SH_PFC_FUNCTION(msiof2
),
4712 SH_PFC_FUNCTION(msiof3
),
4713 SH_PFC_FUNCTION(pwm0
),
4714 SH_PFC_FUNCTION(pwm1
),
4715 SH_PFC_FUNCTION(pwm2
),
4716 SH_PFC_FUNCTION(pwm3
),
4717 SH_PFC_FUNCTION(pwm4
),
4718 SH_PFC_FUNCTION(pwm5
),
4719 SH_PFC_FUNCTION(pwm6
),
4720 SH_PFC_FUNCTION(qspi
),
4721 SH_PFC_FUNCTION(scif0
),
4722 SH_PFC_FUNCTION(scif1
),
4723 SH_PFC_FUNCTION(scif2
),
4724 SH_PFC_FUNCTION(scifa0
),
4725 SH_PFC_FUNCTION(scifa1
),
4726 SH_PFC_FUNCTION(scifa2
),
4727 SH_PFC_FUNCTION(scifb0
),
4728 SH_PFC_FUNCTION(scifb1
),
4729 SH_PFC_FUNCTION(scifb2
),
4730 SH_PFC_FUNCTION(scif_clk
),
4731 SH_PFC_FUNCTION(sdhi0
),
4732 SH_PFC_FUNCTION(sdhi1
),
4733 SH_PFC_FUNCTION(sdhi2
),
4734 SH_PFC_FUNCTION(sdhi3
),
4735 SH_PFC_FUNCTION(ssi
),
4736 SH_PFC_FUNCTION(tpu0
),
4737 SH_PFC_FUNCTION(usb0
),
4738 SH_PFC_FUNCTION(usb1
),
4739 SH_PFC_FUNCTION(usb2
),
4740 SH_PFC_FUNCTION(vin0
),
4741 SH_PFC_FUNCTION(vin1
),
4742 SH_PFC_FUNCTION(vin2
),
4743 SH_PFC_FUNCTION(vin3
),
4746 static const struct pinmux_cfg_reg pinmux_config_regs
[] = {
4747 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4748 GP_0_31_FN
, FN_IP3_17_15
,
4749 GP_0_30_FN
, FN_IP3_14_12
,
4750 GP_0_29_FN
, FN_IP3_11_8
,
4751 GP_0_28_FN
, FN_IP3_7_4
,
4752 GP_0_27_FN
, FN_IP3_3_0
,
4753 GP_0_26_FN
, FN_IP2_28_26
,
4754 GP_0_25_FN
, FN_IP2_25_22
,
4755 GP_0_24_FN
, FN_IP2_21_18
,
4756 GP_0_23_FN
, FN_IP2_17_15
,
4757 GP_0_22_FN
, FN_IP2_14_12
,
4758 GP_0_21_FN
, FN_IP2_11_9
,
4759 GP_0_20_FN
, FN_IP2_8_6
,
4760 GP_0_19_FN
, FN_IP2_5_3
,
4761 GP_0_18_FN
, FN_IP2_2_0
,
4762 GP_0_17_FN
, FN_IP1_29_28
,
4763 GP_0_16_FN
, FN_IP1_27_26
,
4764 GP_0_15_FN
, FN_IP1_25_22
,
4765 GP_0_14_FN
, FN_IP1_21_18
,
4766 GP_0_13_FN
, FN_IP1_17_15
,
4767 GP_0_12_FN
, FN_IP1_14_12
,
4768 GP_0_11_FN
, FN_IP1_11_8
,
4769 GP_0_10_FN
, FN_IP1_7_4
,
4770 GP_0_9_FN
, FN_IP1_3_0
,
4771 GP_0_8_FN
, FN_IP0_30_27
,
4772 GP_0_7_FN
, FN_IP0_26_23
,
4773 GP_0_6_FN
, FN_IP0_22_20
,
4774 GP_0_5_FN
, FN_IP0_19_16
,
4775 GP_0_4_FN
, FN_IP0_15_12
,
4776 GP_0_3_FN
, FN_IP0_11_9
,
4777 GP_0_2_FN
, FN_IP0_8_6
,
4778 GP_0_1_FN
, FN_IP0_5_3
,
4779 GP_0_0_FN
, FN_IP0_2_0
}
4781 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4784 GP_1_29_FN
, FN_IP6_13_11
,
4785 GP_1_28_FN
, FN_IP6_10_9
,
4786 GP_1_27_FN
, FN_IP6_8_6
,
4787 GP_1_26_FN
, FN_IP6_5_3
,
4788 GP_1_25_FN
, FN_IP6_2_0
,
4789 GP_1_24_FN
, FN_IP5_29_27
,
4790 GP_1_23_FN
, FN_IP5_26_24
,
4791 GP_1_22_FN
, FN_IP5_23_21
,
4792 GP_1_21_FN
, FN_IP5_20_18
,
4793 GP_1_20_FN
, FN_IP5_17_15
,
4794 GP_1_19_FN
, FN_IP5_14_13
,
4795 GP_1_18_FN
, FN_IP5_12_10
,
4796 GP_1_17_FN
, FN_IP5_9_6
,
4797 GP_1_16_FN
, FN_IP5_5_3
,
4798 GP_1_15_FN
, FN_IP5_2_0
,
4799 GP_1_14_FN
, FN_IP4_29_27
,
4800 GP_1_13_FN
, FN_IP4_26_24
,
4801 GP_1_12_FN
, FN_IP4_23_21
,
4802 GP_1_11_FN
, FN_IP4_20_18
,
4803 GP_1_10_FN
, FN_IP4_17_15
,
4804 GP_1_9_FN
, FN_IP4_14_12
,
4805 GP_1_8_FN
, FN_IP4_11_9
,
4806 GP_1_7_FN
, FN_IP4_8_6
,
4807 GP_1_6_FN
, FN_IP4_5_3
,
4808 GP_1_5_FN
, FN_IP4_2_0
,
4809 GP_1_4_FN
, FN_IP3_31_29
,
4810 GP_1_3_FN
, FN_IP3_28_26
,
4811 GP_1_2_FN
, FN_IP3_25_23
,
4812 GP_1_1_FN
, FN_IP3_22_20
,
4813 GP_1_0_FN
, FN_IP3_19_18
, }
4815 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4818 GP_2_29_FN
, FN_IP7_15_13
,
4819 GP_2_28_FN
, FN_IP7_12_10
,
4820 GP_2_27_FN
, FN_IP7_9_8
,
4821 GP_2_26_FN
, FN_IP7_7_6
,
4822 GP_2_25_FN
, FN_IP7_5_3
,
4823 GP_2_24_FN
, FN_IP7_2_0
,
4824 GP_2_23_FN
, FN_IP6_31_29
,
4825 GP_2_22_FN
, FN_IP6_28_26
,
4826 GP_2_21_FN
, FN_IP6_25_23
,
4827 GP_2_20_FN
, FN_IP6_22_20
,
4828 GP_2_19_FN
, FN_IP6_19_17
,
4829 GP_2_18_FN
, FN_IP6_16_14
,
4830 GP_2_17_FN
, FN_VI1_DATA7_VI1_B7
,
4831 GP_2_16_FN
, FN_IP8_27
,
4832 GP_2_15_FN
, FN_IP8_26
,
4833 GP_2_14_FN
, FN_IP8_25_24
,
4834 GP_2_13_FN
, FN_IP8_23_22
,
4835 GP_2_12_FN
, FN_IP8_21_20
,
4836 GP_2_11_FN
, FN_IP8_19_18
,
4837 GP_2_10_FN
, FN_IP8_17_16
,
4838 GP_2_9_FN
, FN_IP8_15_14
,
4839 GP_2_8_FN
, FN_IP8_13_12
,
4840 GP_2_7_FN
, FN_IP8_11_10
,
4841 GP_2_6_FN
, FN_IP8_9_8
,
4842 GP_2_5_FN
, FN_IP8_7_6
,
4843 GP_2_4_FN
, FN_IP8_5_4
,
4844 GP_2_3_FN
, FN_IP8_3_2
,
4845 GP_2_2_FN
, FN_IP8_1_0
,
4846 GP_2_1_FN
, FN_IP7_30_29
,
4847 GP_2_0_FN
, FN_IP7_28_27
}
4849 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4850 GP_3_31_FN
, FN_IP11_21_18
,
4851 GP_3_30_FN
, FN_IP11_17_15
,
4852 GP_3_29_FN
, FN_IP11_14_13
,
4853 GP_3_28_FN
, FN_IP11_12_11
,
4854 GP_3_27_FN
, FN_IP11_10_9
,
4855 GP_3_26_FN
, FN_IP11_8_7
,
4856 GP_3_25_FN
, FN_IP11_6_5
,
4857 GP_3_24_FN
, FN_IP11_4
,
4858 GP_3_23_FN
, FN_IP11_3_0
,
4859 GP_3_22_FN
, FN_IP10_29_26
,
4860 GP_3_21_FN
, FN_IP10_25_23
,
4861 GP_3_20_FN
, FN_IP10_22_19
,
4862 GP_3_19_FN
, FN_IP10_18_15
,
4863 GP_3_18_FN
, FN_IP10_14_11
,
4864 GP_3_17_FN
, FN_IP10_10_7
,
4865 GP_3_16_FN
, FN_IP10_6_4
,
4866 GP_3_15_FN
, FN_IP10_3_0
,
4867 GP_3_14_FN
, FN_IP9_31_28
,
4868 GP_3_13_FN
, FN_IP9_27_26
,
4869 GP_3_12_FN
, FN_IP9_25_24
,
4870 GP_3_11_FN
, FN_IP9_23_22
,
4871 GP_3_10_FN
, FN_IP9_21_20
,
4872 GP_3_9_FN
, FN_IP9_19_18
,
4873 GP_3_8_FN
, FN_IP9_17_16
,
4874 GP_3_7_FN
, FN_IP9_15_12
,
4875 GP_3_6_FN
, FN_IP9_11_8
,
4876 GP_3_5_FN
, FN_IP9_7_6
,
4877 GP_3_4_FN
, FN_IP9_5_4
,
4878 GP_3_3_FN
, FN_IP9_3_2
,
4879 GP_3_2_FN
, FN_IP9_1_0
,
4880 GP_3_1_FN
, FN_IP8_30_29
,
4881 GP_3_0_FN
, FN_IP8_28
}
4883 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4884 GP_4_31_FN
, FN_IP14_18_16
,
4885 GP_4_30_FN
, FN_IP14_15_12
,
4886 GP_4_29_FN
, FN_IP14_11_9
,
4887 GP_4_28_FN
, FN_IP14_8_6
,
4888 GP_4_27_FN
, FN_IP14_5_3
,
4889 GP_4_26_FN
, FN_IP14_2_0
,
4890 GP_4_25_FN
, FN_IP13_30_29
,
4891 GP_4_24_FN
, FN_IP13_28_26
,
4892 GP_4_23_FN
, FN_IP13_25_23
,
4893 GP_4_22_FN
, FN_IP13_22_19
,
4894 GP_4_21_FN
, FN_IP13_18_16
,
4895 GP_4_20_FN
, FN_IP13_15_13
,
4896 GP_4_19_FN
, FN_IP13_12_10
,
4897 GP_4_18_FN
, FN_IP13_9_7
,
4898 GP_4_17_FN
, FN_IP13_6_3
,
4899 GP_4_16_FN
, FN_IP13_2_0
,
4900 GP_4_15_FN
, FN_IP12_30_28
,
4901 GP_4_14_FN
, FN_IP12_27_25
,
4902 GP_4_13_FN
, FN_IP12_24_23
,
4903 GP_4_12_FN
, FN_IP12_22_20
,
4904 GP_4_11_FN
, FN_IP12_19_17
,
4905 GP_4_10_FN
, FN_IP12_16_14
,
4906 GP_4_9_FN
, FN_IP12_13_11
,
4907 GP_4_8_FN
, FN_IP12_10_8
,
4908 GP_4_7_FN
, FN_IP12_7_6
,
4909 GP_4_6_FN
, FN_IP12_5_4
,
4910 GP_4_5_FN
, FN_IP12_3_2
,
4911 GP_4_4_FN
, FN_IP12_1_0
,
4912 GP_4_3_FN
, FN_IP11_31_30
,
4913 GP_4_2_FN
, FN_IP11_29_27
,
4914 GP_4_1_FN
, FN_IP11_26_24
,
4915 GP_4_0_FN
, FN_IP11_23_22
}
4917 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4918 GP_5_31_FN
, FN_IP7_24_22
,
4919 GP_5_30_FN
, FN_IP7_21_19
,
4920 GP_5_29_FN
, FN_IP7_18_16
,
4921 GP_5_28_FN
, FN_DU_DOTCLKIN2
,
4922 GP_5_27_FN
, FN_IP7_26_25
,
4923 GP_5_26_FN
, FN_DU_DOTCLKIN0
,
4924 GP_5_25_FN
, FN_AVS2
,
4925 GP_5_24_FN
, FN_AVS1
,
4926 GP_5_23_FN
, FN_USB2_OVC
,
4927 GP_5_22_FN
, FN_USB2_PWEN
,
4928 GP_5_21_FN
, FN_IP16_7
,
4929 GP_5_20_FN
, FN_IP16_6
,
4930 GP_5_19_FN
, FN_USB0_OVC_VBUS
,
4931 GP_5_18_FN
, FN_USB0_PWEN
,
4932 GP_5_17_FN
, FN_IP16_5_3
,
4933 GP_5_16_FN
, FN_IP16_2_0
,
4934 GP_5_15_FN
, FN_IP15_29_28
,
4935 GP_5_14_FN
, FN_IP15_27_26
,
4936 GP_5_13_FN
, FN_IP15_25_23
,
4937 GP_5_12_FN
, FN_IP15_22_20
,
4938 GP_5_11_FN
, FN_IP15_19_18
,
4939 GP_5_10_FN
, FN_IP15_17_16
,
4940 GP_5_9_FN
, FN_IP15_15_14
,
4941 GP_5_8_FN
, FN_IP15_13_12
,
4942 GP_5_7_FN
, FN_IP15_11_9
,
4943 GP_5_6_FN
, FN_IP15_8_6
,
4944 GP_5_5_FN
, FN_IP15_5_3
,
4945 GP_5_4_FN
, FN_IP15_2_0
,
4946 GP_5_3_FN
, FN_IP14_30_28
,
4947 GP_5_2_FN
, FN_IP14_27_25
,
4948 GP_5_1_FN
, FN_IP14_24_22
,
4949 GP_5_0_FN
, FN_IP14_21_19
}
4951 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4952 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
4956 FN_D8
, FN_SCIFA1_SCK_C
, FN_AVB_TXD0
, 0,
4957 FN_VI0_G0
, FN_VI0_G0_B
, FN_VI2_DATA0_VI2_B0
,
4958 0, 0, 0, 0, 0, 0, 0, 0, 0,
4960 FN_D7
, FN_AD_DI_B
, FN_IIC2_SDA_C
,
4961 FN_VI3_DATA7
, FN_VI0_R3
, FN_VI0_R3_B
, FN_I2C2_SDA_C
,
4962 FN_TCLK1
, 0, 0, 0, 0, 0, 0, 0, 0,
4964 FN_D6
, FN_IIC2_SCL_C
, FN_VI3_DATA6
, FN_VI0_R2
, FN_VI0_R2_B
,
4965 FN_I2C2_SCL_C
, 0, 0,
4967 FN_D5
, FN_SCIFB1_TXD_F
, FN_SCIFB0_TXD_C
, FN_VI3_DATA5
,
4968 FN_VI0_R1
, FN_VI0_R1_B
, FN_TX0_B
,
4969 0, 0, 0, 0, 0, 0, 0, 0, 0,
4971 FN_D4
, FN_SCIFB1_RXD_F
, FN_SCIFB0_RXD_C
, FN_VI3_DATA4
,
4972 FN_VI0_R0
, FN_VI0_R0_B
, FN_RX0_B
,
4973 0, 0, 0, 0, 0, 0, 0, 0, 0,
4975 FN_D3
, FN_MSIOF3_TXD_B
, FN_VI3_DATA3
, FN_VI0_G7
, FN_VI0_G7_B
,
4978 FN_D2
, FN_MSIOF3_RXD_B
, FN_VI3_DATA2
, FN_VI0_G6
, FN_VI0_G6_B
,
4981 FN_D1
, FN_MSIOF3_SYNC_B
, FN_VI3_DATA1
, FN_VI0_G5
, FN_VI0_G5_B
,
4984 FN_D0
, FN_MSIOF3_SCK_B
, FN_VI3_DATA0
, FN_VI0_G4
, FN_VI0_G4_B
,
4987 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4988 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
4992 FN_A1
, FN_PWM4
, 0, 0,
4994 FN_A0
, FN_PWM3
, 0, 0,
4996 FN_D15
, FN_SCIFB1_TXD_C
, FN_AVB_TXD7
, FN_TX1_B
,
4997 FN_VI0_FIELD
, FN_VI0_FIELD_B
, FN_VI2_DATA7_VI2_B7
,
4998 0, 0, 0, 0, 0, 0, 0, 0, 0,
5000 FN_D14
, FN_SCIFB1_RXD_C
, FN_AVB_TXD6
, FN_RX1_B
,
5001 FN_VI0_CLKENB
, FN_VI0_CLKENB_B
, FN_VI2_DATA6_VI2_B6
,
5002 0, 0, 0, 0, 0, 0, 0, 0, 0,
5004 FN_D13
, FN_AVB_TXD5
, FN_VI0_VSYNC_N
,
5005 FN_VI0_VSYNC_N_B
, FN_VI2_DATA5_VI2_B5
,
5008 FN_D12
, FN_SCIFA1_RTS_N_C
, FN_AVB_TXD4
,
5009 FN_VI0_HSYNC_N
, FN_VI0_HSYNC_N_B
, FN_VI2_DATA4_VI2_B4
,
5012 FN_D11
, FN_SCIFA1_CTS_N_C
, FN_AVB_TXD3
, 0,
5013 FN_VI0_G3
, FN_VI0_G3_B
, FN_VI2_DATA3_VI2_B3
,
5014 0, 0, 0, 0, 0, 0, 0, 0, 0,
5016 FN_D10
, FN_SCIFA1_TXD_C
, FN_AVB_TXD2
, 0,
5017 FN_VI0_G2
, FN_VI0_G2_B
, FN_VI2_DATA2_VI2_B2
,
5018 0, 0, 0, 0, 0, 0, 0, 0, 0,
5020 FN_D9
, FN_SCIFA1_RXD_C
, FN_AVB_TXD1
, 0,
5021 FN_VI0_G1
, FN_VI0_G1_B
, FN_VI2_DATA1_VI2_B1
,
5022 0, 0, 0, 0, 0, 0, 0, 0, 0, }
5024 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5025 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
5027 0, 0, 0, 0, 0, 0, 0, 0,
5029 FN_A10
, FN_SSI_SDATA5_B
, FN_MSIOF2_SYNC
, FN_VI0_R6
,
5030 FN_VI0_R6_B
, FN_VI2_DATA2_VI2_B2_B
, 0, 0,
5032 FN_A9
, FN_SCIFA1_CTS_N_B
, FN_SSI_WS5_B
, FN_VI0_R5
,
5033 FN_VI0_R5_B
, FN_SCIFB2_TXD_C
, FN_TX2_B
, FN_VI2_DATA1_VI2_B1_B
,
5034 0, 0, 0, 0, 0, 0, 0, 0,
5036 FN_A8
, FN_SCIFA1_RXD_B
, FN_SSI_SCK5_B
, FN_VI0_R4
,
5037 FN_VI0_R4_B
, FN_SCIFB2_RXD_C
, FN_RX2_B
, FN_VI2_DATA0_VI2_B0_B
,
5038 0, 0, 0, 0, 0, 0, 0, 0,
5040 FN_A7
, FN_SCIFA1_SCK_B
, FN_AUDIO_CLKOUT_B
, FN_TPU0TO3
,
5043 FN_A6
, FN_SCIFA1_RTS_N_B
, FN_TPU0TO2
, 0, 0, 0, 0, 0,
5045 FN_A5
, FN_SCIFA1_TXD_B
, FN_TPU0TO1
, 0, 0, 0, 0, 0,
5047 FN_A4
, FN_MSIOF1_TXD_B
, FN_TPU0TO0
, 0, 0, 0, 0, 0,
5049 FN_A3
, FN_PWM6
, FN_MSIOF1_SS2_B
, 0, 0, 0, 0, 0,
5051 FN_A2
, FN_PWM5
, FN_MSIOF1_SS1_B
, 0, 0, 0, 0, 0, }
5053 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5054 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
5056 FN_A20
, FN_SPCLK
, FN_VI1_R3
, FN_VI1_R3_B
, FN_VI2_G4
,
5059 FN_A19
, FN_AD_NCS_N_B
, FN_ATACS01_N
, FN_EX_WAIT0_B
,
5062 FN_A18
, FN_AD_CLK_B
, FN_ATAG1_N
, 0, 0, 0, 0, 0,
5064 FN_A17
, FN_AD_DO_B
, FN_ATADIR1_N
, 0, 0, 0, 0, 0,
5066 FN_A16
, FN_ATAWR1_N
, 0, 0,
5068 FN_A15
, FN_SCIFB2_SCK_B
, FN_ATARD1_N
, FN_MSIOF2_SS2
,
5071 FN_A14
, FN_SCIFB2_TXD_B
, FN_ATACS11_N
, FN_MSIOF2_SS1
,
5074 FN_A13
, FN_SCIFB2_RTS_N_B
, FN_EX_WAIT2
,
5075 FN_MSIOF2_RXD
, FN_VI1_R2
, FN_VI1_R2_B
, FN_VI2_G2
,
5076 FN_VI2_DATA5_VI2_B5_B
, 0, 0, 0, 0, 0, 0, 0, 0,
5078 FN_A12
, FN_SCIFB2_RXD_B
, FN_MSIOF2_TXD
, FN_VI1_R1
,
5079 FN_VI1_R1_B
, FN_VI2_G1
, FN_VI2_DATA4_VI2_B4_B
,
5080 0, 0, 0, 0, 0, 0, 0, 0, 0,
5082 FN_A11
, FN_SCIFB2_CTS_N_B
, FN_MSIOF2_SCK
, FN_VI1_R0
,
5083 FN_VI1_R0_B
, FN_VI2_G0
, FN_VI2_DATA3_VI2_B3_B
, 0,
5084 0, 0, 0, 0, 0, 0, 0, 0, }
5086 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5087 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
5091 FN_EX_CS2_N
, FN_GPS_SIGN
, FN_HRTS1_N_B
,
5092 FN_VI3_CLKENB
, FN_VI1_G0
, FN_VI1_G0_B
, FN_VI2_R2
, 0,
5094 FN_EX_CS1_N
, FN_GPS_CLK
, FN_HCTS1_N_B
, FN_VI1_FIELD
,
5095 FN_VI1_FIELD_B
, FN_VI2_R1
, 0, 0,
5097 FN_EX_CS0_N
, FN_HRX1_B
, FN_VI1_G5
, FN_VI1_G5_B
, FN_VI2_R0
,
5098 FN_HTX0_B
, FN_MSIOF0_SS1_B
, 0,
5100 FN_CS1_N_A26
, FN_SPEEDIN
, FN_VI0_R7
, FN_VI0_R7_B
,
5101 FN_VI2_CLK
, FN_VI2_CLK_B
, 0, 0,
5103 FN_CS0_N
, FN_VI1_R6
, FN_VI1_R6_B
, FN_VI2_G3
, FN_MSIOF0_SS2_B
,
5106 FN_A25
, FN_SSL
, FN_VI1_G6
, FN_VI1_G6_B
, FN_VI2_FIELD
,
5107 FN_VI2_FIELD_B
, 0, 0,
5109 FN_A24
, FN_IO3
, FN_VI1_R7
, FN_VI1_R7_B
, FN_VI2_CLKENB
,
5110 FN_VI2_CLKENB_B
, 0, 0,
5112 FN_A23
, FN_IO2
, FN_VI1_G7
, FN_VI1_G7_B
, FN_VI2_G7
, 0, 0, 0,
5114 FN_A22
, FN_MISO_IO1
, FN_VI1_R5
, FN_VI1_R5_B
, FN_VI2_G6
, 0, 0, 0,
5116 FN_A21
, FN_MOSI_IO0
, FN_VI1_R4
, FN_VI1_R4_B
, FN_VI2_G5
, 0, 0, 0,
5119 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5120 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
5124 FN_DREQ0_N
, FN_VI1_HSYNC_N
, FN_VI1_HSYNC_N_B
, FN_VI2_R7
,
5125 FN_SSI_SCK78_C
, FN_SSI_WS78_B
, 0, 0,
5127 FN_EX_WAIT0
, FN_IRQ3
, FN_INTC_IRQ3_N
,
5128 FN_VI3_CLK
, FN_SCIFA0_RTS_N_B
, FN_HRX0_B
,
5131 FN_WE1_N
, FN_IERX
, FN_CAN1_RX
, FN_VI1_G4
,
5132 FN_VI1_G4_B
, FN_VI2_R6
, FN_SCIFA0_CTS_N_B
, FN_IERX_C
,
5134 FN_WE0_N
, FN_IECLK
, FN_CAN_CLK
,
5135 FN_VI2_VSYNC_N
, FN_SCIFA0_TXD_B
, FN_VI2_VSYNC_N_B
, 0, 0,
5137 FN_RD_WR_N
, FN_VI1_G3
, FN_VI1_G3_B
, FN_VI2_R5
, FN_SCIFA0_RXD_B
,
5138 FN_INTC_IRQ4_N
, 0, 0,
5140 FN_RD_N
, FN_CAN0_TX
, FN_SCIFA0_SCK_B
, 0,
5142 FN_BS_N
, FN_IETX
, FN_HTX1_B
, FN_CAN1_TX
, FN_DRACK0
, FN_IETX_C
,
5145 FN_EX_CS5_N
, FN_CAN0_RX
, FN_MSIOF1_RXD_B
, FN_VI3_VSYNC_N
,
5146 FN_VI1_G2
, FN_VI1_G2_B
, FN_VI2_R4
, FN_IIC1_SDA
, FN_INTC_EN1_N
,
5147 FN_I2C1_SDA
, 0, 0, 0, 0, 0, 0,
5149 FN_EX_CS4_N
, FN_MSIOF1_SCK_B
, FN_VI3_HSYNC_N
,
5150 FN_VI2_HSYNC_N
, FN_IIC1_SCL
, FN_VI2_HSYNC_N_B
,
5151 FN_INTC_EN0_N
, FN_I2C1_SCL
,
5153 FN_EX_CS3_N
, FN_GPS_MAG
, FN_VI3_FIELD
, FN_VI1_G1
, FN_VI1_G1_B
,
5156 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5157 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
5159 FN_ETH_REF_CLK
, 0, FN_HCTS0_N_E
,
5160 FN_STP_IVCXO27_1_B
, FN_HRX0_F
, 0, 0, 0,
5162 FN_ETH_LINK
, 0, FN_HTX0_E
,
5163 FN_STP_IVCXO27_0_B
, FN_SCIFB1_TXD_G
, FN_TX1_E
, 0, 0,
5165 FN_ETH_RXD1
, 0, FN_HRX0_E
, FN_STP_ISSYNC_0_B
,
5166 FN_TS_SCK0_D
, FN_GLO_I1_C
, FN_SCIFB1_RXD_G
, FN_RX1_E
,
5168 FN_ETH_RXD0
, 0, FN_STP_ISEN_0_B
, FN_TS_SDAT0_D
,
5169 FN_GLO_I0_C
, FN_SCIFB1_SCK_G
, FN_SCK1_E
, 0,
5171 FN_ETH_RX_ER
, 0, FN_STP_ISD_0_B
,
5172 FN_TS_SPSYNC0_D
, FN_GLO_Q1_C
, FN_IIC2_SDA_E
, FN_I2C2_SDA_E
, 0,
5174 FN_ETH_CRS_DV
, 0, FN_STP_ISCLK_0_B
,
5175 FN_TS_SDEN0_D
, FN_GLO_Q0_C
, FN_IIC2_SCL_E
,
5178 FN_DACK2
, FN_IRQ2
, FN_INTC_IRQ2_N
,
5179 FN_SSI_SDATA6_B
, FN_HRTS0_N_B
, FN_MSIOF0_RXD_B
, 0, 0,
5181 FN_DREQ2_N
, FN_HSCK1_B
, FN_HCTS0_N_B
, FN_MSIOF0_TXD_B
,
5183 FN_DACK1
, FN_IRQ1
, FN_INTC_IRQ1_N
, FN_SSI_WS6_B
,
5184 FN_SSI_SDATA8_C
, 0, 0, 0,
5186 FN_DREQ1_N
, FN_VI1_CLKENB
, FN_VI1_CLKENB_B
,
5187 FN_SSI_SDATA7_C
, FN_SSI_SCK78_B
, 0, 0, 0,
5189 FN_DACK0
, FN_IRQ0
, FN_INTC_IRQ0_N
, FN_SSI_SCK6_B
,
5190 FN_VI1_VSYNC_N
, FN_VI1_VSYNC_N_B
, FN_SSI_WS78_C
, 0, }
5192 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5193 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
5197 FN_VI0_DATA0_VI0_B0
, FN_ATACS10_N
, FN_AVB_RXD2
, 0,
5199 FN_VI0_CLK
, FN_ATACS00_N
, FN_AVB_RXD1
, 0,
5201 FN_DU_DOTCLKIN1
, FN_AUDIO_CLKC
, FN_AUDIO_CLKOUT_C
, 0,
5203 FN_PWM2
, FN_PWMFSW0
, FN_SCIFA2_RXD_C
, FN_PCMWE_N
, FN_IECLK_C
,
5206 FN_PWM1
, FN_SCIFA2_TXD_C
, FN_STP_ISSYNC_1_B
, FN_TS_SCK1_C
,
5207 FN_GLO_RFON_C
, FN_PCMOE_N
, 0, 0,
5209 FN_PWM0
, FN_SCIFA2_SCK_C
, FN_STP_ISEN_1_B
, FN_TS_SDAT1_C
,
5210 FN_GLO_SS_C
, 0, 0, 0,
5212 FN_ETH_MDC
, 0, FN_STP_ISD_1_B
,
5213 FN_TS_SPSYNC1_C
, FN_GLO_SDATA_C
, 0, 0, 0,
5215 FN_ETH_TXD0
, 0, FN_STP_ISCLK_1_B
, FN_TS_SDEN1_C
,
5216 FN_GLO_SCLK_C
, 0, 0, 0,
5218 FN_ETH_MAGIC
, 0, FN_SIM0_RST_C
, 0,
5220 FN_ETH_TX_EN
, 0, FN_SIM0_CLK_C
, FN_HRTS0_N_F
,
5222 FN_ETH_TXD1
, 0, FN_HTX0_F
, FN_BPFCLK_G
, 0, 0, 0, 0,
5224 FN_ETH_MDIO
, 0, FN_HRTS0_N_E
,
5225 FN_SIM0_D_C
, FN_HCTS0_N_F
, 0, 0, 0, }
5227 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5228 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
5229 2, 2, 2, 2, 2, 2, 2) {
5233 FN_SD0_CMD
, FN_SCIFB1_SCK_B
, FN_VI1_DATA1_VI1_B1_B
, 0,
5235 FN_SD0_CLK
, FN_VI1_DATA0_VI1_B0_B
,
5237 FN_VI1_DATA6_VI1_B6
, FN_AVB_GTXREFCLK
,
5239 FN_VI1_DATA5_VI1_B5
, FN_AVB_PHY_INT
,
5241 FN_VI1_DATA4_VI1_B4
, FN_SCIFA1_RTS_N_D
,
5244 FN_VI1_DATA3_VI1_B3
, FN_SCIFA1_CTS_N_D
, FN_AVB_GTX_CLK
, 0,
5246 FN_VI1_DATA2_VI1_B2
, FN_SCIFA1_TXD_D
, FN_AVB_MDIO
, 0,
5248 FN_VI1_DATA1_VI1_B1
, FN_SCIFA1_RXD_D
, FN_AVB_MDC
, 0,
5250 FN_VI1_DATA0_VI1_B0
, FN_SCIFA1_SCK_D
, FN_AVB_CRS
, 0,
5252 FN_VI1_CLK
, FN_AVB_RX_DV
, 0, 0,
5254 FN_VI0_DATA7_VI0_B7
, FN_AVB_RX_CLK
, 0, 0,
5256 FN_VI0_DATA6_VI0_B6
, FN_AVB_RX_ER
, 0, 0,
5258 FN_VI0_DATA5_VI0_B5
, FN_EX_WAIT1
, FN_AVB_RXD7
, 0,
5260 FN_VI0_DATA4_VI0_B4
, FN_ATAG0_N
, FN_AVB_RXD6
, 0,
5262 FN_VI0_DATA3_VI0_B3
, FN_ATADIR0_N
, FN_AVB_RXD5
, 0,
5264 FN_VI0_DATA2_VI0_B2
, FN_ATAWR0_N
, FN_AVB_RXD4
, 0,
5266 FN_VI0_DATA1_VI0_B1
, FN_ATARD0_N
, FN_AVB_RXD3
, 0, }
5268 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5269 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
5271 FN_SD1_CD
, FN_MMC1_D6
, FN_TS_SDEN1
, FN_USB1_EXTP
,
5272 FN_GLO_SS
, FN_VI0_CLK_B
, FN_IIC2_SCL_D
, FN_I2C2_SCL_D
,
5273 FN_SIM0_CLK_B
, FN_VI3_CLK_B
, 0, 0, 0, 0, 0, 0,
5275 FN_SD1_DAT3
, FN_AVB_RXD0
, 0, FN_SCIFB0_RTS_N_B
,
5277 FN_SD1_DAT2
, FN_AVB_COL
, 0, FN_SCIFB0_CTS_N_B
,
5279 FN_SD1_DAT1
, FN_AVB_LINK
, 0, FN_SCIFB0_TXD_B
,
5281 FN_SD1_DAT0
, FN_AVB_TX_CLK
, 0, FN_SCIFB0_RXD_B
,
5283 FN_SD1_CMD
, FN_AVB_TX_ER
, 0, FN_SCIFB0_SCK_B
,
5285 FN_SD1_CLK
, FN_AVB_TX_EN
, 0, 0,
5287 FN_SD0_WP
, FN_MMC0_D7
, FN_TS_SPSYNC0_B
, FN_USB0_IDIN
,
5288 FN_GLO_SDATA
, FN_VI1_DATA7_VI1_B7_B
, FN_IIC1_SDA_B
,
5289 FN_I2C1_SDA_B
, FN_VI2_DATA7_VI2_B7_B
, 0, 0, 0, 0, 0, 0, 0,
5291 FN_SD0_CD
, FN_MMC0_D6
, FN_TS_SDEN0_B
, FN_USB0_EXTP
,
5292 FN_GLO_SCLK
, FN_VI1_DATA6_VI1_B6_B
, FN_IIC1_SCL_B
,
5293 FN_I2C1_SCL_B
, FN_VI2_DATA6_VI2_B6_B
, 0, 0, 0, 0, 0, 0, 0,
5295 FN_SD0_DAT3
, FN_SCIFB1_RTS_N_B
, FN_VI1_DATA5_VI1_B5_B
, 0,
5297 FN_SD0_DAT2
, FN_SCIFB1_CTS_N_B
, FN_VI1_DATA4_VI1_B4_B
, 0,
5299 FN_SD0_DAT1
, FN_SCIFB1_TXD_B
, FN_VI1_DATA3_VI1_B3_B
, 0,
5301 FN_SD0_DAT0
, FN_SCIFB1_RXD_B
, FN_VI1_DATA2_VI1_B2_B
, 0, }
5303 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5304 2, 4, 3, 4, 4, 4, 4, 3, 4) {
5305 /* IP10_31_30 [2] */
5307 /* IP10_29_26 [4] */
5308 FN_SD2_CD
, FN_MMC0_D4
, FN_TS_SDAT0_B
, FN_USB2_EXTP
, FN_GLO_I0
,
5309 FN_VI0_DATA6_VI0_B6_B
, FN_HCTS0_N_D
, FN_TS_SDAT1_B
,
5310 FN_GLO_I0_B
, FN_VI3_DATA6_B
, 0, 0, 0, 0, 0, 0,
5311 /* IP10_25_23 [3] */
5312 FN_SD2_DAT3
, FN_MMC0_D3
, FN_SIM0_RST
, FN_VI0_DATA5_VI0_B5_B
,
5313 FN_HTX0_D
, FN_TS_SPSYNC1_B
, FN_GLO_Q1_B
, FN_VI3_DATA5_B
,
5314 /* IP10_22_19 [4] */
5315 FN_SD2_DAT2
, FN_MMC0_D2
, FN_BPFCLK_B
, 0,
5316 FN_VI0_DATA4_VI0_B4_B
, FN_HRX0_D
, FN_TS_SDEN1_B
,
5317 FN_GLO_Q0_B
, FN_VI3_DATA4_B
, 0, 0, 0, 0, 0, 0, 0,
5318 /* IP10_18_15 [4] */
5319 FN_SD2_DAT1
, FN_MMC0_D1
, FN_FMIN_B
, 0,
5320 FN_VI0_DATA3_VI0_B3_B
, FN_SCIFB1_TXD_E
, FN_TX1_D
,
5321 FN_TS_SCK0_C
, FN_GLO_RFON_B
, FN_VI3_DATA3_B
,
5323 /* IP10_14_11 [4] */
5324 FN_SD2_DAT0
, FN_MMC0_D0
, FN_FMCLK_B
,
5325 FN_VI0_DATA2_VI0_B2_B
, FN_SCIFB1_RXD_E
, FN_RX1_D
,
5326 FN_TS_SDAT0_C
, FN_GLO_SS_B
, FN_VI3_DATA2_B
,
5327 0, 0, 0, 0, 0, 0, 0,
5329 FN_SD2_CMD
, FN_MMC0_CMD
, FN_SIM0_D
,
5330 FN_VI0_DATA1_VI0_B1_B
, FN_SCIFB1_SCK_E
, FN_SCK1_D
,
5331 FN_TS_SPSYNC0_C
, FN_GLO_SDATA_B
, FN_VI3_DATA1_B
,
5332 0, 0, 0, 0, 0, 0, 0,
5334 FN_SD2_CLK
, FN_MMC0_CLK
, FN_SIM0_CLK
,
5335 FN_VI0_DATA0_VI0_B0_B
, FN_TS_SDEN0_C
, FN_GLO_SCLK_B
,
5338 FN_SD1_WP
, FN_MMC1_D7
, FN_TS_SPSYNC1
, FN_USB1_IDIN
,
5339 FN_GLO_RFON
, FN_VI1_CLK_B
, FN_IIC2_SDA_D
, FN_I2C2_SDA_D
,
5340 FN_SIM0_D_B
, 0, 0, 0, 0, 0, 0, 0, }
5342 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5343 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
5344 /* IP11_31_30 [2] */
5345 FN_SSI_SCK0129
, FN_CAN_CLK_B
, FN_MOUT0
, 0,
5346 /* IP11_29_27 [3] */
5347 FN_MLB_DAT
, 0, FN_SCIFB1_TXD_D
, FN_TX1_C
, FN_BPFCLK_C
,
5349 /* IP11_26_24 [3] */
5350 FN_MLB_SIG
, FN_SCIFB1_RXD_D
, FN_RX1_C
, FN_IIC2_SDA_B
, FN_I2C2_SDA_B
,
5352 /* IP11_23_22 [2] */
5353 FN_MLB_CLK
, FN_IIC2_SCL_B
, FN_I2C2_SCL_B
, 0,
5354 /* IP11_21_18 [4] */
5355 FN_SD3_WP
, FN_MMC1_D5
, FN_TS_SCK1
, FN_GLO_Q1
, FN_FMIN_C
,
5356 0, FN_FMIN_E
, 0, FN_FMIN_F
, 0, 0, 0, 0, 0, 0, 0,
5357 /* IP11_17_15 [3] */
5358 FN_SD3_CD
, FN_MMC1_D4
, FN_TS_SDAT1
,
5359 FN_VSP
, FN_GLO_Q0
, FN_SIM0_RST_B
, 0, 0,
5360 /* IP11_14_13 [2] */
5361 FN_SD3_DAT3
, FN_MMC1_D3
, FN_SCKZ
, 0,
5362 /* IP11_12_11 [2] */
5363 FN_SD3_DAT2
, FN_MMC1_D2
, FN_SDATA
, 0,
5365 FN_SD3_DAT1
, FN_MMC1_D1
, FN_MDATA
, 0,
5367 FN_SD3_DAT0
, FN_MMC1_D0
, FN_STM_N
, 0,
5369 FN_SD3_CMD
, FN_MMC1_CMD
, FN_MTS_N
, 0,
5371 FN_SD3_CLK
, FN_MMC1_CLK
,
5373 FN_SD2_WP
, FN_MMC0_D5
, FN_TS_SCK0_B
, FN_USB2_IDIN
,
5374 FN_GLO_I1
, FN_VI0_DATA7_VI0_B7_B
, FN_HRTS0_N_D
,
5375 FN_TS_SCK1_B
, FN_GLO_I1_B
, FN_VI3_DATA7_B
, 0, 0, 0, 0, 0, 0, }
5377 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5378 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5381 /* IP12_30_28 [3] */
5382 FN_SSI_WS5
, FN_SCIFB1_RXD
, FN_IECLK_B
,
5383 FN_DU2_EXVSYNC_DU2_VSYNC
, FN_QSTB_QHE
,
5384 FN_CAN_DEBUGOUT4
, 0, 0,
5385 /* IP12_27_25 [3] */
5386 FN_SSI_SCK5
, FN_SCIFB1_SCK
,
5387 FN_IERX_B
, FN_DU2_EXHSYNC_DU2_HSYNC
, FN_QSTH_QHS
,
5388 FN_CAN_DEBUGOUT3
, 0, 0,
5389 /* IP12_24_23 [2] */
5390 FN_SSI_SDATA4
, FN_STP_ISSYNC_0
, FN_MSIOF1_RXD
,
5392 /* IP12_22_20 [3] */
5393 FN_SSI_WS4
, FN_STP_ISEN_0
, FN_SCIFB0_RTS_N
,
5394 FN_MSIOF1_TXD
, FN_SSI_WS5_C
, FN_CAN_DEBUGOUT1
, 0, 0,
5395 /* IP12_19_17 [3] */
5396 FN_SSI_SCK4
, FN_STP_ISD_0
, FN_SCIFB0_CTS_N
,
5397 FN_MSIOF1_SS2
, FN_SSI_SCK5_C
, FN_CAN_DEBUGOUT0
, 0, 0,
5398 /* IP12_16_14 [3] */
5399 FN_SSI_SDATA3
, FN_STP_ISCLK_0
,
5400 FN_SCIFB0_TXD
, FN_MSIOF1_SS1
, FN_CAN_TXCLK
, 0, 0, 0,
5401 /* IP12_13_11 [3] */
5402 FN_SSI_WS34
, FN_STP_IVCXO27_0
, FN_SCIFB0_RXD
, FN_MSIOF1_SYNC
,
5403 FN_CAN_STEP0
, 0, 0, 0,
5405 FN_SSI_SCK34
, FN_STP_OPWM_0
, FN_SCIFB0_SCK
,
5406 FN_MSIOF1_SCK
, FN_CAN_DEBUG_HW_TRIGGER
, 0, 0, 0,
5408 FN_SSI_SDATA2
, FN_CAN1_RX_B
, FN_SSI_SCK1
, FN_MOUT6
,
5410 FN_SSI_SDATA1
, FN_CAN1_TX_B
, FN_MOUT5
, 0,
5412 FN_SSI_SDATA0
, FN_CAN0_RX_B
, FN_MOUT2
, 0,
5414 FN_SSI_WS0129
, FN_CAN0_TX_B
, FN_MOUT1
, 0, }
5416 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5417 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
5420 /* IP13_30_29 [2] */
5421 FN_AUDIO_CLKA
, FN_SCIFB2_RTS_N
, FN_CAN_DEBUGOUT14
, 0,
5422 /* IP13_28_26 [3] */
5423 FN_SSI_SDATA9
, FN_STP_ISSYNC_1
, FN_SCIFB2_CTS_N
, FN_SSI_WS1
,
5424 FN_SSI_SDATA5_C
, FN_CAN_DEBUGOUT13
, 0, 0,
5425 /* IP13_25_23 [3] */
5426 FN_SSI_SDATA8
, FN_STP_ISEN_1
, FN_SCIFB2_TXD
, FN_CAN0_TX_C
,
5427 FN_CAN_DEBUGOUT12
, FN_SSI_SDATA8_B
, 0, 0,
5428 /* IP13_22_19 [4] */
5429 FN_SSI_SDATA7
, FN_STP_ISD_1
, FN_SCIFB2_RXD
, FN_SCIFA2_RTS_N
,
5430 FN_TCLK2
, FN_QSTVA_QVS
, FN_CAN_DEBUGOUT11
, FN_BPFCLK_E
,
5431 0, FN_SSI_SDATA7_B
, FN_FMIN_G
, 0, 0, 0, 0, 0,
5432 /* IP13_18_16 [3] */
5433 FN_SSI_WS78
, FN_STP_ISCLK_1
, FN_SCIFB2_SCK
, FN_SCIFA2_CTS_N
,
5434 FN_DU2_DR7
, FN_LCDOUT7
, FN_CAN_DEBUGOUT10
, 0,
5435 /* IP13_15_13 [3] */
5436 FN_SSI_SCK78
, FN_STP_IVCXO27_1
, FN_SCK1
, FN_SCIFA1_SCK
,
5437 FN_DU2_DR6
, FN_LCDOUT6
, FN_CAN_DEBUGOUT9
, 0,
5438 /* IP13_12_10 [3] */
5439 FN_SSI_SDATA6
, FN_FMIN_D
, 0, FN_DU2_DR5
, FN_LCDOUT5
,
5440 FN_CAN_DEBUGOUT8
, 0, 0,
5442 FN_SSI_WS6
, FN_SCIFB1_RTS_N
, FN_CAN0_TX_D
, FN_DU2_DR4
,
5443 FN_LCDOUT4
, FN_CAN_DEBUGOUT7
, 0, 0,
5445 FN_SSI_SCK6
, FN_SCIFB1_CTS_N
, FN_BPFCLK_D
, 0,
5446 FN_DU2_DR3
, FN_LCDOUT3
, FN_CAN_DEBUGOUT6
,
5447 FN_BPFCLK_F
, 0, 0, 0, 0, 0, 0, 0, 0,
5449 FN_SSI_SDATA5
, FN_SCIFB1_TXD
, FN_IETX_B
, FN_DU2_DR2
,
5450 FN_LCDOUT2
, FN_CAN_DEBUGOUT5
, 0, 0, }
5452 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5453 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
5456 /* IP14_30_28 [3] */
5457 FN_SCIFA1_RTS_N
, FN_AD_NCS_N
, FN_RTS1_N
,
5458 FN_MSIOF3_TXD
, FN_DU1_DOTCLKOUT
, FN_QSTVB_QVE
,
5460 /* IP14_27_25 [3] */
5461 FN_SCIFA1_CTS_N
, FN_AD_CLK
, FN_CTS1_N
, FN_MSIOF3_RXD
,
5462 FN_DU0_DOTCLKOUT
, FN_QCLK
, 0, 0,
5463 /* IP14_24_22 [3] */
5464 FN_SCIFA1_TXD
, FN_AD_DO
, FN_TX1
, FN_DU2_DG1
,
5465 FN_LCDOUT9
, 0, 0, 0,
5466 /* IP14_21_19 [3] */
5467 FN_SCIFA1_RXD
, FN_AD_DI
, FN_RX1
,
5468 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE
, FN_QCPV_QDE
, 0, 0, 0,
5469 /* IP14_18_16 [3] */
5470 FN_SCIFA0_RTS_N
, FN_HRTS1_N
, FN_RTS0_N
,
5471 FN_MSIOF3_SS1
, FN_DU2_DG0
, FN_LCDOUT8
, FN_PWM1_B
, 0,
5472 /* IP14_15_12 [4] */
5473 FN_SCIFA0_CTS_N
, FN_HCTS1_N
, FN_CTS0_N
, FN_MSIOF3_SYNC
,
5474 FN_DU2_DG3
, FN_LCDOUT11
, FN_PWM0_B
, FN_IIC1_SCL_C
, FN_I2C1_SCL_C
,
5475 0, 0, 0, 0, 0, 0, 0,
5477 FN_SCIFA0_TXD
, FN_HTX1
, FN_TX0
, FN_DU2_DR1
, FN_LCDOUT1
,
5480 FN_SCIFA0_RXD
, FN_HRX1
, FN_RX0
, FN_DU2_DR0
, FN_LCDOUT0
,
5483 FN_SCIFA0_SCK
, FN_HSCK1
, FN_SCK0
, FN_MSIOF3_SS2
, FN_DU2_DG2
,
5484 FN_LCDOUT10
, FN_IIC1_SDA_C
, FN_I2C1_SDA_C
,
5486 FN_AUDIO_CLKB
, FN_SCIF_CLK
, FN_CAN0_RX_D
,
5487 FN_DVC_MUTE
, FN_CAN0_RX_C
, FN_CAN_DEBUGOUT15
,
5490 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5491 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
5492 /* IP15_31_30 [2] */
5494 /* IP15_29_28 [2] */
5495 FN_MSIOF0_TXD
, FN_ADICHS1
, FN_DU2_DG6
, FN_LCDOUT14
,
5496 /* IP15_27_26 [2] */
5497 FN_MSIOF0_SS1
, FN_ADICHS0
, FN_DU2_DG5
, FN_LCDOUT13
,
5498 /* IP15_25_23 [3] */
5499 FN_MSIOF0_SYNC
, FN_TS_SCK0
, FN_SSI_SCK2
, FN_ADIDATA
,
5500 FN_DU2_DB7
, FN_LCDOUT23
, FN_HRX0_C
, 0,
5501 /* IP15_22_20 [3] */
5502 FN_MSIOF0_SCK
, FN_TS_SDAT0
, FN_ADICLK
,
5503 FN_DU2_DB6
, FN_LCDOUT22
, 0, 0, 0,
5504 /* IP15_19_18 [2] */
5505 FN_HRTS0_N
, FN_SSI_WS9
, FN_DU2_DB5
, FN_LCDOUT21
,
5506 /* IP15_17_16 [2] */
5507 FN_HCTS0_N
, FN_SSI_SCK9
, FN_DU2_DB4
, FN_LCDOUT20
,
5508 /* IP15_15_14 [2] */
5509 FN_HTX0
, FN_DU2_DB3
, FN_LCDOUT19
, 0,
5510 /* IP15_13_12 [2] */
5511 FN_HRX0
, FN_DU2_DB2
, FN_LCDOUT18
, 0,
5513 FN_HSCK0
, FN_TS_SDEN0
, FN_DU2_DG4
, FN_LCDOUT12
, FN_HCTS0_N_C
,
5516 FN_SCIFA2_TXD
, FN_BPFCLK
, FN_RX2
, FN_DU2_DB1
, FN_LCDOUT17
,
5517 FN_IIC2_SDA
, FN_I2C2_SDA
, 0,
5519 FN_SCIFA2_RXD
, FN_FMIN
, FN_TX2
, FN_DU2_DB0
, FN_LCDOUT16
,
5520 FN_IIC2_SCL
, FN_I2C2_SCL
, 0,
5522 FN_SCIFA2_SCK
, FN_FMCLK
, FN_SCK2
, FN_MSIOF3_SCK
, FN_DU2_DG7
,
5523 FN_LCDOUT15
, FN_SCIF_CLK_B
, 0, }
5525 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5526 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
5527 /* IP16_31_28 [4] */
5528 0, 0, 0, 0, 0, 0, 0, 0,
5529 0, 0, 0, 0, 0, 0, 0, 0,
5530 /* IP16_27_24 [4] */
5531 0, 0, 0, 0, 0, 0, 0, 0,
5532 0, 0, 0, 0, 0, 0, 0, 0,
5533 /* IP16_23_20 [4] */
5534 0, 0, 0, 0, 0, 0, 0, 0,
5535 0, 0, 0, 0, 0, 0, 0, 0,
5536 /* IP16_19_16 [4] */
5537 0, 0, 0, 0, 0, 0, 0, 0,
5538 0, 0, 0, 0, 0, 0, 0, 0,
5539 /* IP16_15_12 [4] */
5540 0, 0, 0, 0, 0, 0, 0, 0,
5541 0, 0, 0, 0, 0, 0, 0, 0,
5543 0, 0, 0, 0, 0, 0, 0, 0,
5544 0, 0, 0, 0, 0, 0, 0, 0,
5546 FN_USB1_OVC
, FN_TCLK1_B
,
5548 FN_USB1_PWEN
, FN_AUDIO_CLKOUT_D
,
5550 FN_MSIOF0_RXD
, FN_TS_SPSYNC0
, FN_SSI_WS2
,
5551 FN_ADICS_SAMP
, FN_DU2_CDE
, FN_QPOLB
, FN_SCIFA2_RXD_B
, 0,
5553 FN_MSIOF0_SS2
, FN_AUDIO_CLKOUT
, FN_ADICHS2
,
5554 FN_DU2_DISP
, FN_QPOLA
, FN_HTX0_C
, FN_SCIFA2_TXD_B
, 0, }
5556 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5557 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
5558 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
5560 FN_SEL_SCIF1_0
, FN_SEL_SCIF1_1
, FN_SEL_SCIF1_2
, FN_SEL_SCIF1_3
,
5561 FN_SEL_SCIF1_4
, 0, 0, 0,
5563 FN_SEL_SCIFB_0
, FN_SEL_SCIFB_1
, FN_SEL_SCIFB_2
, 0,
5564 /* SEL_SCIFB2 [2] */
5565 FN_SEL_SCIFB2_0
, FN_SEL_SCIFB2_1
, FN_SEL_SCIFB2_2
, 0,
5566 /* SEL_SCIFB1 [3] */
5567 FN_SEL_SCIFB1_0
, FN_SEL_SCIFB1_1
, FN_SEL_SCIFB1_2
,
5568 FN_SEL_SCIFB1_3
, FN_SEL_SCIFB1_4
, FN_SEL_SCIFB1_5
,
5570 /* SEL_SCIFA1 [2] */
5571 FN_SEL_SCIFA1_0
, FN_SEL_SCIFA1_1
, FN_SEL_SCIFA1_2
,
5574 FN_SEL_SCIF0_0
, FN_SEL_SCIF0_1
,
5576 FN_SEL_SCFA_0
, FN_SEL_SCFA_1
,
5578 FN_SEL_SOF1_0
, FN_SEL_SOF1_1
,
5580 FN_SEL_SSI7_0
, FN_SEL_SSI7_1
, FN_SEL_SSI7_2
, 0,
5582 FN_SEL_SSI6_0
, FN_SEL_SSI6_1
,
5584 FN_SEL_SSI5_0
, FN_SEL_SSI5_1
, FN_SEL_SSI5_2
, 0,
5586 FN_SEL_VI3_0
, FN_SEL_VI3_1
,
5588 FN_SEL_VI2_0
, FN_SEL_VI2_1
,
5590 FN_SEL_VI1_0
, FN_SEL_VI1_1
,
5592 FN_SEL_VI0_0
, FN_SEL_VI0_1
,
5594 FN_SEL_TSIF1_0
, FN_SEL_TSIF1_1
, FN_SEL_TSIF1_2
, 0,
5598 FN_SEL_LBS_0
, FN_SEL_LBS_1
,
5600 FN_SEL_TSIF0_0
, FN_SEL_TSIF0_1
, FN_SEL_TSIF0_2
, FN_SEL_TSIF0_3
,
5602 FN_SEL_SOF3_0
, FN_SEL_SOF3_1
,
5604 FN_SEL_SOF0_0
, FN_SEL_SOF0_1
, }
5606 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5607 3, 1, 1, 1, 2, 1, 2, 1, 2,
5608 1, 1, 1, 3, 3, 2, 3, 2, 2) {
5610 0, 0, 0, 0, 0, 0, 0, 0,
5612 FN_SEL_TMU1_0
, FN_SEL_TMU1_1
,
5613 /* SEL_HSCIF1 [1] */
5614 FN_SEL_HSCIF1_0
, FN_SEL_HSCIF1_1
,
5615 /* SEL_SCIFCLK [1] */
5616 FN_SEL_SCIFCLK_0
, FN_SEL_SCIFCLK_1
,
5618 FN_SEL_CAN0_0
, FN_SEL_CAN0_1
, FN_SEL_CAN0_2
, FN_SEL_CAN0_3
,
5619 /* SEL_CANCLK [1] */
5620 FN_SEL_CANCLK_0
, FN_SEL_CANCLK_1
,
5621 /* SEL_SCIFA2 [2] */
5622 FN_SEL_SCIFA2_0
, FN_SEL_SCIFA2_1
, FN_SEL_SCIFA2_2
, 0,
5624 FN_SEL_CAN1_0
, FN_SEL_CAN1_1
,
5628 FN_SEL_SCIF2_0
, FN_SEL_SCIF2_1
,
5630 FN_SEL_ADI_0
, FN_SEL_ADI_1
,
5632 FN_SEL_SSP_0
, FN_SEL_SSP_1
,
5634 FN_SEL_FM_0
, FN_SEL_FM_1
, FN_SEL_FM_2
, FN_SEL_FM_3
,
5635 FN_SEL_FM_4
, FN_SEL_FM_5
, FN_SEL_FM_6
, 0,
5636 /* SEL_HSCIF0 [3] */
5637 FN_SEL_HSCIF0_0
, FN_SEL_HSCIF0_1
, FN_SEL_HSCIF0_2
,
5638 FN_SEL_HSCIF0_3
, FN_SEL_HSCIF0_4
, FN_SEL_HSCIF0_5
, 0, 0,
5640 FN_SEL_GPS_0
, FN_SEL_GPS_1
, FN_SEL_GPS_2
, 0,
5642 0, 0, 0, 0, 0, 0, 0, 0,
5644 FN_SEL_SIM_0
, FN_SEL_SIM_1
, FN_SEL_SIM_2
, 0,
5646 FN_SEL_SSI8_0
, FN_SEL_SSI8_1
, FN_SEL_SSI8_2
, 0, }
5648 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5649 1, 1, 2, 4, 4, 2, 2,
5651 /* SEL_IICDVFS [1] */
5652 FN_SEL_IICDVFS_0
, FN_SEL_IICDVFS_1
,
5654 FN_SEL_IIC0_0
, FN_SEL_IIC0_1
,
5658 0, 0, 0, 0, 0, 0, 0, 0,
5659 0, 0, 0, 0, 0, 0, 0, 0,
5661 0, 0, 0, 0, 0, 0, 0, 0,
5662 0, 0, 0, 0, 0, 0, 0, 0,
5666 FN_SEL_IEB_0
, FN_SEL_IEB_1
, FN_SEL_IEB_2
, 0,
5668 0, 0, 0, 0, 0, 0, 0, 0,
5669 0, 0, 0, 0, 0, 0, 0, 0,
5673 FN_SEL_IIC2_0
, FN_SEL_IIC2_1
, FN_SEL_IIC2_2
, FN_SEL_IIC2_3
,
5674 FN_SEL_IIC2_4
, 0, 0, 0,
5676 FN_SEL_IIC1_0
, FN_SEL_IIC1_1
, FN_SEL_IIC1_2
, 0,
5678 FN_SEL_I2C2_0
, FN_SEL_I2C2_1
, FN_SEL_I2C2_2
, FN_SEL_I2C2_3
,
5679 FN_SEL_I2C2_4
, 0, 0, 0,
5681 FN_SEL_I2C1_0
, FN_SEL_I2C1_1
, FN_SEL_I2C1_2
, 0, }
5686 static int r8a7790_pin_to_pocctrl(struct sh_pfc
*pfc
, unsigned int pin
, u32
*pocctrl
)
5688 if (pin
< RCAR_GP_PIN(3, 0) || pin
> RCAR_GP_PIN(3, 31))
5691 *pocctrl
= 0xe606008c;
5693 return 31 - (pin
& 0x1f);
5696 static const struct soc_device_attribute r8a7790_tdsel
[] = {
5697 { .soc_id
= "r8a7790", .revision
= "ES1.0" },
5701 static int r8a7790_pinmux_soc_init(struct sh_pfc
*pfc
)
5703 /* Initialize TDSEL on old revisions */
5704 if (soc_device_match(r8a7790_tdsel
))
5705 sh_pfc_write(pfc
, 0xe6060088, 0x00155554);
5710 static const struct sh_pfc_soc_operations r8a7790_pinmux_ops
= {
5711 .init
= r8a7790_pinmux_soc_init
,
5712 .pin_to_pocctrl
= r8a7790_pin_to_pocctrl
,
5715 const struct sh_pfc_soc_info r8a7790_pinmux_info
= {
5716 .name
= "r8a77900_pfc",
5717 .ops
= &r8a7790_pinmux_ops
,
5718 .unlock_reg
= 0xe6060000, /* PMMR */
5720 .function
= { PINMUX_FUNCTION_BEGIN
, PINMUX_FUNCTION_END
},
5722 .pins
= pinmux_pins
,
5723 .nr_pins
= ARRAY_SIZE(pinmux_pins
),
5724 .groups
= pinmux_groups
,
5725 .nr_groups
= ARRAY_SIZE(pinmux_groups
),
5726 .functions
= pinmux_functions
,
5727 .nr_functions
= ARRAY_SIZE(pinmux_functions
),
5729 .cfg_regs
= pinmux_config_regs
,
5731 .pinmux_data
= pinmux_data
,
5732 .pinmux_data_size
= ARRAY_SIZE(pinmux_data
),