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Merge tag 'watchdog-for-linus-v4.10' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
1 /*
2 * R8A7795 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11 #include <linux/kernel.h>
12
13 #include "core.h"
14 #include "sh_pfc.h"
15
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
17 SH_PFC_PIN_CFG_PULL_UP | \
18 SH_PFC_PIN_CFG_PULL_DOWN)
19
20 #define CPU_ALL_PORT(fn, sfx) \
21 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
30 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
33 /*
34 * F_() : just information
35 * FM() : macro for FN_xxx / xxx_MARK
36 */
37
38 /* GPSR0 */
39 #define GPSR0_15 F_(D15, IP7_11_8)
40 #define GPSR0_14 F_(D14, IP7_7_4)
41 #define GPSR0_13 F_(D13, IP7_3_0)
42 #define GPSR0_12 F_(D12, IP6_31_28)
43 #define GPSR0_11 F_(D11, IP6_27_24)
44 #define GPSR0_10 F_(D10, IP6_23_20)
45 #define GPSR0_9 F_(D9, IP6_19_16)
46 #define GPSR0_8 F_(D8, IP6_15_12)
47 #define GPSR0_7 F_(D7, IP6_11_8)
48 #define GPSR0_6 F_(D6, IP6_7_4)
49 #define GPSR0_5 F_(D5, IP6_3_0)
50 #define GPSR0_4 F_(D4, IP5_31_28)
51 #define GPSR0_3 F_(D3, IP5_27_24)
52 #define GPSR0_2 F_(D2, IP5_23_20)
53 #define GPSR0_1 F_(D1, IP5_19_16)
54 #define GPSR0_0 F_(D0, IP5_15_12)
55
56 /* GPSR1 */
57 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
58 #define GPSR1_26 F_(WE1_N, IP5_7_4)
59 #define GPSR1_25 F_(WE0_N, IP5_3_0)
60 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
61 #define GPSR1_23 F_(RD_N, IP4_27_24)
62 #define GPSR1_22 F_(BS_N, IP4_23_20)
63 #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
64 #define GPSR1_20 F_(CS0_N, IP4_15_12)
65 #define GPSR1_19 F_(A19, IP4_11_8)
66 #define GPSR1_18 F_(A18, IP4_7_4)
67 #define GPSR1_17 F_(A17, IP4_3_0)
68 #define GPSR1_16 F_(A16, IP3_31_28)
69 #define GPSR1_15 F_(A15, IP3_27_24)
70 #define GPSR1_14 F_(A14, IP3_23_20)
71 #define GPSR1_13 F_(A13, IP3_19_16)
72 #define GPSR1_12 F_(A12, IP3_15_12)
73 #define GPSR1_11 F_(A11, IP3_11_8)
74 #define GPSR1_10 F_(A10, IP3_7_4)
75 #define GPSR1_9 F_(A9, IP3_3_0)
76 #define GPSR1_8 F_(A8, IP2_31_28)
77 #define GPSR1_7 F_(A7, IP2_27_24)
78 #define GPSR1_6 F_(A6, IP2_23_20)
79 #define GPSR1_5 F_(A5, IP2_19_16)
80 #define GPSR1_4 F_(A4, IP2_15_12)
81 #define GPSR1_3 F_(A3, IP2_11_8)
82 #define GPSR1_2 F_(A2, IP2_7_4)
83 #define GPSR1_1 F_(A1, IP2_3_0)
84 #define GPSR1_0 F_(A0, IP1_31_28)
85
86 /* GPSR2 */
87 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
88 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
89 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
90 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
91 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
92 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
93 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
94 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
95 #define GPSR2_6 F_(PWM0, IP1_19_16)
96 #define GPSR2_5 F_(IRQ5, IP1_15_12)
97 #define GPSR2_4 F_(IRQ4, IP1_11_8)
98 #define GPSR2_3 F_(IRQ3, IP1_7_4)
99 #define GPSR2_2 F_(IRQ2, IP1_3_0)
100 #define GPSR2_1 F_(IRQ1, IP0_31_28)
101 #define GPSR2_0 F_(IRQ0, IP0_27_24)
102
103 /* GPSR3 */
104 #define GPSR3_15 F_(SD1_WP, IP10_23_20)
105 #define GPSR3_14 F_(SD1_CD, IP10_19_16)
106 #define GPSR3_13 F_(SD0_WP, IP10_15_12)
107 #define GPSR3_12 F_(SD0_CD, IP10_11_8)
108 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
109 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
110 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
111 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
112 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
113 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
114 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
115 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
116 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
117 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
118 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
119 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
120
121 /* GPSR4 */
122 #define GPSR4_17 FM(SD3_DS)
123 #define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
124 #define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
125 #define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
126 #define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
127 #define GPSR4_12 FM(SD3_DAT3)
128 #define GPSR4_11 FM(SD3_DAT2)
129 #define GPSR4_10 FM(SD3_DAT1)
130 #define GPSR4_9 FM(SD3_DAT0)
131 #define GPSR4_8 FM(SD3_CMD)
132 #define GPSR4_7 FM(SD3_CLK)
133 #define GPSR4_6 F_(SD2_DS, IP9_23_20)
134 #define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
135 #define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
136 #define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
137 #define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
138 #define GPSR4_1 FM(SD2_CMD)
139 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
140
141 /* GPSR5 */
142 #define GPSR5_25 F_(MLB_DAT, IP13_19_16)
143 #define GPSR5_24 F_(MLB_SIG, IP13_15_12)
144 #define GPSR5_23 F_(MLB_CLK, IP13_11_8)
145 #define GPSR5_22 FM(MSIOF0_RXD)
146 #define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
147 #define GPSR5_20 FM(MSIOF0_TXD)
148 #define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
149 #define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
150 #define GPSR5_17 FM(MSIOF0_SCK)
151 #define GPSR5_16 F_(HRTS0_N, IP12_27_24)
152 #define GPSR5_15 F_(HCTS0_N, IP12_23_20)
153 #define GPSR5_14 F_(HTX0, IP12_19_16)
154 #define GPSR5_13 F_(HRX0, IP12_15_12)
155 #define GPSR5_12 F_(HSCK0, IP12_11_8)
156 #define GPSR5_11 F_(RX2_A, IP12_7_4)
157 #define GPSR5_10 F_(TX2_A, IP12_3_0)
158 #define GPSR5_9 F_(SCK2, IP11_31_28)
159 #define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24)
160 #define GPSR5_7 F_(CTS1_N, IP11_23_20)
161 #define GPSR5_6 F_(TX1_A, IP11_19_16)
162 #define GPSR5_5 F_(RX1_A, IP11_15_12)
163 #define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8)
164 #define GPSR5_3 F_(CTS0_N, IP11_7_4)
165 #define GPSR5_2 F_(TX0, IP11_3_0)
166 #define GPSR5_1 F_(RX0, IP10_31_28)
167 #define GPSR5_0 F_(SCK0, IP10_27_24)
168
169 /* GPSR6 */
170 #define GPSR6_31 F_(USB31_OVC, IP17_7_4)
171 #define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
172 #define GPSR6_29 F_(USB30_OVC, IP16_31_28)
173 #define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
174 #define GPSR6_27 F_(USB1_OVC, IP16_23_20)
175 #define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
176 #define GPSR6_25 F_(USB0_OVC, IP16_15_12)
177 #define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
178 #define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
179 #define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
180 #define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
181 #define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
182 #define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
183 #define GPSR6_18 F_(SSI_WS78, IP15_19_16)
184 #define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
185 #define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
186 #define GPSR6_15 F_(SSI_WS6, IP15_7_4)
187 #define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
188 #define GPSR6_13 FM(SSI_SDATA5)
189 #define GPSR6_12 FM(SSI_WS5)
190 #define GPSR6_11 FM(SSI_SCK5)
191 #define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
192 #define GPSR6_9 F_(SSI_WS4, IP14_27_24)
193 #define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
194 #define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
195 #define GPSR6_6 F_(SSI_WS34, IP14_15_12)
196 #define GPSR6_5 F_(SSI_SCK34, IP14_11_8)
197 #define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
198 #define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
199 #define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
200 #define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
201 #define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
202
203 /* GPSR7 */
204 #define GPSR7_3 FM(HDMI1_CEC)
205 #define GPSR7_2 FM(HDMI0_CEC)
206 #define GPSR7_1 FM(AVS2)
207 #define GPSR7_0 FM(AVS1)
208
209
210 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
211 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230
231 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
232 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318
319 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
320 #define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP14_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP14_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355
356 #define PINMUX_GPSR \
357 \
358 GPSR6_31 \
359 GPSR6_30 \
360 GPSR6_29 \
361 GPSR6_28 \
362 GPSR1_27 GPSR6_27 \
363 GPSR1_26 GPSR6_26 \
364 GPSR1_25 GPSR5_25 GPSR6_25 \
365 GPSR1_24 GPSR5_24 GPSR6_24 \
366 GPSR1_23 GPSR5_23 GPSR6_23 \
367 GPSR1_22 GPSR5_22 GPSR6_22 \
368 GPSR1_21 GPSR5_21 GPSR6_21 \
369 GPSR1_20 GPSR5_20 GPSR6_20 \
370 GPSR1_19 GPSR5_19 GPSR6_19 \
371 GPSR1_18 GPSR5_18 GPSR6_18 \
372 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
373 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
374 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
375 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
376 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
377 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
378 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
379 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
380 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
381 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
382 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
383 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
384 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
385 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
386 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
387 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
388 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
389 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
390
391 #define PINMUX_IPSR \
392 \
393 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
394 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
395 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
396 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
397 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
398 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
399 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
400 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
401 \
402 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
403 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
404 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
405 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
406 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
407 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
408 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
409 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
410 \
411 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
412 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
413 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
414 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
415 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
416 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
417 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
418 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
419 \
420 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
421 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
422 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
423 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
424 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
425 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
426 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
427 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
428 \
429 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
430 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
431 FM(IP16_11_8) IP16_11_8 \
432 FM(IP16_15_12) IP16_15_12 \
433 FM(IP16_19_16) IP16_19_16 \
434 FM(IP16_23_20) IP16_23_20 \
435 FM(IP16_27_24) IP16_27_24 \
436 FM(IP16_31_28) IP16_31_28
437
438 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
439 #define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
440 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
441 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
442 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
443 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
444 #define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
445 #define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
446 #define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
447 #define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
448 #define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
449 #define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
450 #define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
451 #define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
452 #define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
453 #define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
454 #define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
455 #define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
456 #define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
457 #define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
458 #define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
459 #define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
460
461 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
462 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
463 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
464 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
465 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
466 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
467 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
468 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
469 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
470 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
471 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
472 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
473 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
474 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
475 #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
476 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
477 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
478 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
479 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
480 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
481 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
482 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
483 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
484
485 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
486 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
487 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
488 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
489 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
490
491 #define PINMUX_MOD_SELS\
492 \
493 MOD_SEL1_31_30 MOD_SEL2_31 \
494 MOD_SEL0_30_29 MOD_SEL2_30 \
495 MOD_SEL1_29_28_27 MOD_SEL2_29 \
496 MOD_SEL0_28_27 \
497 \
498 MOD_SEL0_26_25_24 MOD_SEL1_26 \
499 MOD_SEL1_25_24 \
500 \
501 MOD_SEL0_23 MOD_SEL1_23_22_21 \
502 MOD_SEL0_22 \
503 MOD_SEL0_21_20 \
504 MOD_SEL1_20 \
505 MOD_SEL0_19 MOD_SEL1_19 \
506 MOD_SEL0_18 MOD_SEL1_18_17 \
507 MOD_SEL0_17 \
508 MOD_SEL0_16_15 MOD_SEL1_16 \
509 MOD_SEL1_15_14 \
510 MOD_SEL0_14 \
511 MOD_SEL0_13 MOD_SEL1_13 \
512 MOD_SEL0_12 MOD_SEL1_12 \
513 MOD_SEL0_11 MOD_SEL1_11 \
514 MOD_SEL0_10 MOD_SEL1_10 \
515 MOD_SEL0_9 MOD_SEL1_9 \
516 MOD_SEL0_8 \
517 MOD_SEL0_7_6 \
518 MOD_SEL1_6 \
519 MOD_SEL0_5_4 MOD_SEL1_5 \
520 MOD_SEL1_4 \
521 MOD_SEL0_3 MOD_SEL1_3 \
522 MOD_SEL0_2_1 MOD_SEL1_2 \
523 MOD_SEL1_1 \
524 MOD_SEL1_0 MOD_SEL2_0
525
526 /*
527 * These pins are not able to be muxed but have other properties
528 * that can be set, such as drive-strength or pull-up/pull-down enable.
529 */
530 #define PINMUX_STATIC \
531 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
532 FM(QSPI0_IO2) FM(QSPI0_IO3) \
533 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
534 FM(QSPI1_IO2) FM(QSPI1_IO3) \
535 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
536 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
537 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
538 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
539 FM(CLKOUT) FM(PRESETOUT) \
540 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
541 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF)
542
543 enum {
544 PINMUX_RESERVED = 0,
545
546 PINMUX_DATA_BEGIN,
547 GP_ALL(DATA),
548 PINMUX_DATA_END,
549
550 #define F_(x, y)
551 #define FM(x) FN_##x,
552 PINMUX_FUNCTION_BEGIN,
553 GP_ALL(FN),
554 PINMUX_GPSR
555 PINMUX_IPSR
556 PINMUX_MOD_SELS
557 PINMUX_FUNCTION_END,
558 #undef F_
559 #undef FM
560
561 #define F_(x, y)
562 #define FM(x) x##_MARK,
563 PINMUX_MARK_BEGIN,
564 PINMUX_GPSR
565 PINMUX_IPSR
566 PINMUX_MOD_SELS
567 PINMUX_STATIC
568 PINMUX_MARK_END,
569 #undef F_
570 #undef FM
571 };
572
573 static const u16 pinmux_data[] = {
574 PINMUX_DATA_GP_ALL(),
575
576 PINMUX_SINGLE(AVS1),
577 PINMUX_SINGLE(AVS2),
578 PINMUX_SINGLE(HDMI0_CEC),
579 PINMUX_SINGLE(HDMI1_CEC),
580 PINMUX_SINGLE(I2C_SEL_0_1),
581 PINMUX_SINGLE(I2C_SEL_3_1),
582 PINMUX_SINGLE(I2C_SEL_5_1),
583 PINMUX_SINGLE(MSIOF0_RXD),
584 PINMUX_SINGLE(MSIOF0_SCK),
585 PINMUX_SINGLE(MSIOF0_TXD),
586 PINMUX_SINGLE(SD2_CMD),
587 PINMUX_SINGLE(SD3_CLK),
588 PINMUX_SINGLE(SD3_CMD),
589 PINMUX_SINGLE(SD3_DAT0),
590 PINMUX_SINGLE(SD3_DAT1),
591 PINMUX_SINGLE(SD3_DAT2),
592 PINMUX_SINGLE(SD3_DAT3),
593 PINMUX_SINGLE(SD3_DS),
594 PINMUX_SINGLE(SSI_SCK5),
595 PINMUX_SINGLE(SSI_SDATA5),
596 PINMUX_SINGLE(SSI_WS5),
597
598 /* IPSR0 */
599 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
600 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
601
602 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
603 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
604 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
605
606 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
607 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
608 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
609
610 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
611 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
612 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
613
614 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
615 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
616 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
617
618 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
619 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
620 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
621
622 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
623 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
624 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
625 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
626 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
627 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
628
629 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
630 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
631 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
632 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
633 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
634 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
635
636 /* IPSR1 */
637 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
638 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
639 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
640 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
642
643 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
644 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
645 PINMUX_IPSR_GPSR(IP1_7_4, A25),
646 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
647 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
648 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
649
650 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
651 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
652 PINMUX_IPSR_GPSR(IP1_11_8, A24),
653 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
654 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
655 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
656
657 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
658 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
659 PINMUX_IPSR_GPSR(IP1_15_12, A23),
660 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
661 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
662 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
663
664 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
665 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
666 PINMUX_IPSR_GPSR(IP1_19_16, A22),
667 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
668 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
669
670 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
671 PINMUX_IPSR_GPSR(IP1_23_20, A21),
672 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
673 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
674 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
675
676 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
677 PINMUX_IPSR_GPSR(IP1_27_24, A20),
678 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
679 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
680
681 PINMUX_IPSR_GPSR(IP1_31_28, A0),
682 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
683 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
684 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
685 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
686 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
687
688 /* IPSR2 */
689 PINMUX_IPSR_GPSR(IP2_3_0, A1),
690 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
691 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
692 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
693 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
694 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
695
696 PINMUX_IPSR_GPSR(IP2_7_4, A2),
697 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
698 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
699 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
700 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
701 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
702
703 PINMUX_IPSR_GPSR(IP2_11_8, A3),
704 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
705 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
706 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
707 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
708 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
709
710 PINMUX_IPSR_GPSR(IP2_15_12, A4),
711 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
712 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
713 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
714 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
715 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
716
717 PINMUX_IPSR_GPSR(IP2_19_16, A5),
718 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
719 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
720 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
721 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
722 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
723 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
724
725 PINMUX_IPSR_GPSR(IP2_23_20, A6),
726 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
727 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
728 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
729 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
730 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
731 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
732
733 PINMUX_IPSR_GPSR(IP2_27_24, A7),
734 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
735 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
736 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
737 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
738 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
739 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
740
741 PINMUX_IPSR_GPSR(IP2_31_28, A8),
742 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
743 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
744 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
745 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
746 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
747 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
748
749 /* IPSR3 */
750 PINMUX_IPSR_GPSR(IP3_3_0, A9),
751 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
752 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
753 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
754
755 PINMUX_IPSR_GPSR(IP3_7_4, A10),
756 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
757 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
758 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
759
760 PINMUX_IPSR_GPSR(IP3_11_8, A11),
761 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
762 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
763 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
764 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
765 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
766 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
767 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
768 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
769
770 PINMUX_IPSR_GPSR(IP3_15_12, A12),
771 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
772 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
773 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
774 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
775 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
776
777 PINMUX_IPSR_GPSR(IP3_19_16, A13),
778 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
779 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
780 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
781 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
782 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
783
784 PINMUX_IPSR_GPSR(IP3_23_20, A14),
785 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
786 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
787 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
788 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
789 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
790
791 PINMUX_IPSR_GPSR(IP3_27_24, A15),
792 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
793 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
794 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
795 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
796 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
797
798 PINMUX_IPSR_GPSR(IP3_31_28, A16),
799 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
800 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
801 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
802
803 /* IPSR4 */
804 PINMUX_IPSR_GPSR(IP4_3_0, A17),
805 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
806 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
807 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
808
809 PINMUX_IPSR_GPSR(IP4_7_4, A18),
810 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
811 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
812 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
813
814 PINMUX_IPSR_GPSR(IP4_11_8, A19),
815 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
816 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
817 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
818
819 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
820 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
821
822 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
823 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
824 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
825
826 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
827 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
828 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
829 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
830 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
831 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
832 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
833 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
834
835 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
836 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
837 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
838 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
839 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
840 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
841
842 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
843 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
844 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
845 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
846 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
847 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
848
849 /* IPSR5 */
850 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
851 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
852 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
853 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
854 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
855 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
856 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
857
858 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
859 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
860 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
861 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
862 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
863 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
864 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
865 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
866
867 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
868 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
869 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
870 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
871
872 PINMUX_IPSR_GPSR(IP5_15_12, D0),
873 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
874 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
875 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
876 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
877
878 PINMUX_IPSR_GPSR(IP5_19_16, D1),
879 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
880 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
881 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
882 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
883
884 PINMUX_IPSR_GPSR(IP5_23_20, D2),
885 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
886 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
887 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
888
889 PINMUX_IPSR_GPSR(IP5_27_24, D3),
890 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
891 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
892 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
893
894 PINMUX_IPSR_GPSR(IP5_31_28, D4),
895 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
896 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
897 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
898
899 /* IPSR6 */
900 PINMUX_IPSR_GPSR(IP6_3_0, D5),
901 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
902 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
903 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
904
905 PINMUX_IPSR_GPSR(IP6_7_4, D6),
906 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
907 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
908 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
909
910 PINMUX_IPSR_GPSR(IP6_11_8, D7),
911 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
912 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
913 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
914
915 PINMUX_IPSR_GPSR(IP6_15_12, D8),
916 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
917 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
918 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
919 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
920 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
921
922 PINMUX_IPSR_GPSR(IP6_19_16, D9),
923 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
924 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
925 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
926 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
927
928 PINMUX_IPSR_GPSR(IP6_23_20, D10),
929 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
930 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
931 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
932 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
933 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
934 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
935
936 PINMUX_IPSR_GPSR(IP6_27_24, D11),
937 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
938 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
939 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
940 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
941 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
942 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
943
944 PINMUX_IPSR_GPSR(IP6_31_28, D12),
945 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
946 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
947 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
948 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
949 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
950
951 /* IPSR7 */
952 PINMUX_IPSR_GPSR(IP7_3_0, D13),
953 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
954 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
955 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
956 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
957 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
958
959 PINMUX_IPSR_GPSR(IP7_7_4, D14),
960 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
961 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
962 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
963 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
964 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
965 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
966
967 PINMUX_IPSR_GPSR(IP7_11_8, D15),
968 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
969 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
970 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
971 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
972 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
973 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
974
975 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
976
977 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
978 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
979 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
980
981 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
982 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
983 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
984
985 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
986 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
987 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
988 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
989
990 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
991 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
992 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
993 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
994
995 /* IPSR8 */
996 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
997 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
998 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
999 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1000
1001 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1002 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1003 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1004 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1005
1006 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1007 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1008 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1009
1010 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1011 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1012 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1013 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1014
1015 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1016 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1017 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1018 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1019 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1020
1021 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1022 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1023 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1024 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1025 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1026
1027 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1028 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1029 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1030 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1031 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1032
1033 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1034 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1035 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1036 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1037 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1038
1039 /* IPSR9 */
1040 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1041
1042 PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0),
1043
1044 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1),
1045
1046 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2),
1047
1048 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3),
1049
1050 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS),
1051 PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1),
1052
1053 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4),
1054 PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
1055
1056 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5),
1057 PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
1058
1059 /* IPSR10 */
1060 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6),
1061 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD),
1062
1063 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7),
1064 PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP),
1065
1066 PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD),
1067 PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
1068 PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1069
1070 PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
1071 PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
1072
1073 PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD),
1074 PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1075
1076 PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP),
1077 PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1),
1078
1079 PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
1080 PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
1081 PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1082 PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
1083 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
1084 PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1085 PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1086 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1087 PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2),
1088
1089 PINMUX_IPSR_GPSR(IP10_31_28, RX0),
1090 PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
1091 PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
1092 PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1093 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1094
1095 /* IPSR11 */
1096 PINMUX_IPSR_GPSR(IP11_3_0, TX0),
1097 PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
1098 PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1099 PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1100 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1101
1102 PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N),
1103 PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1104 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1105 PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1106 PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1107 PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1108 PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
1109 PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
1110
1111 PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N_TANS),
1112 PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1113 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1114 PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
1115 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
1116 PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1117 PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1118 PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1),
1119
1120 PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
1121 PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
1122 PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1123 PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1124 PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1125
1126 PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
1127 PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
1128 PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1129 PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1130 PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
1131
1132 PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N),
1133 PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1134 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1135 PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1136 PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1137 PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
1138 PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
1139
1140 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
1141 PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1142 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1143 PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1144 PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1145 PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
1146 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0),
1147
1148 PINMUX_IPSR_GPSR(IP11_31_28, SCK2),
1149 PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1150 PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1151 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
1152 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1153 PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1154 PINMUX_IPSR_GPSR(IP11_31_28, ADICLK),
1155
1156 /* IPSR12 */
1157 PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
1158 PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
1159 PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
1160 PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
1161 PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
1162 PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
1163
1164 PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
1165 PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
1166 PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
1167 PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
1168 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1169 PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
1170
1171 PINMUX_IPSR_GPSR(IP12_11_8, HSCK0),
1172 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1173 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
1174 PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
1175 PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
1176 PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1177 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1178
1179 PINMUX_IPSR_GPSR(IP12_15_12, HRX0),
1180 PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1181 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
1182 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1183 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1184 PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
1185
1186 PINMUX_IPSR_GPSR(IP12_19_16, HTX0),
1187 PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1188 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
1189 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1190 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1191 PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
1192
1193 PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N),
1194 PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
1195 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1196 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
1197 PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1198 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1199 PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1200 PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
1201
1202 PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N),
1203 PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
1204 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1205 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
1206 PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1207 PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
1208 PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
1209
1210 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1211 PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
1212
1213 /* IPSR13 */
1214 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1215 PINMUX_IPSR_GPSR(IP13_3_0, RX5),
1216 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
1217 PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
1218 PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1219 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
1220 PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1221
1222 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1223 PINMUX_IPSR_GPSR(IP13_7_4, TX5),
1224 PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1225 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
1226 PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
1227 PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1228 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
1229 PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1230
1231 PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK),
1232 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1233 PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
1234
1235 PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG),
1236 PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
1237 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1238 PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
1239
1240 PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT),
1241 PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
1242 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1243
1244 PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239),
1245 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1246
1247 PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239),
1248 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1249
1250 PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0),
1251 PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1252
1253 /* IPSR14 */
1254 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
1255
1256 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
1257 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
1258
1259 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK34),
1260 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1261 PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1262
1263 PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS34),
1264 PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1265 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1266 PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1267
1268 PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3),
1269 PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1270 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1271 PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
1272 PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1273 PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
1274 PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
1275
1276 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4),
1277 PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
1278 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1279 PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1280 PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1281 PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1282 PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1283
1284 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4),
1285 PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
1286 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1287 PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1288 PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1289 PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1290 PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1291
1292 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4),
1293 PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
1294 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1295 PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1296 PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1297 PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
1298 PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
1299
1300 /* IPSR15 */
1301 PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6),
1302 PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN),
1303 PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1304
1305 PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6),
1306 PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC),
1307 PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
1308
1309 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6),
1310 PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1311 PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0),
1312
1313 PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78),
1314 PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
1315 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1316 PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
1317 PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1318 PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1319 PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1320
1321 PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78),
1322 PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
1323 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1324 PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1325 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1328
1329 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7),
1330 PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1331 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1332 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1333 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1337
1338 PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8),
1339 PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1340 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1341 PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
1345
1346 PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
1347 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
1348 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1349 PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
1351 PINMUX_IPSR_GPSR(IP15_31_28, SCK1),
1352 PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1353 PINMUX_IPSR_GPSR(IP15_31_28, SCK5),
1354
1355 /* IPSR16 */
1356 PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
1357 PINMUX_IPSR_GPSR(IP16_3_0, CC5_OSCOUT),
1358
1359 PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
1360 PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1361 PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1362 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
1363 PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1364
1365 PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN),
1366 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1367 PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
1368 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1369 PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
1370 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1371
1372 PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC),
1373 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
1374 PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
1375 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
1376 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
1377
1378 PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN),
1379 PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1380 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
1382 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1383 PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
1384 PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1385 PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1386
1387 PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC),
1388 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1389 PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1391 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1392 PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
1393 PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1394 PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
1395
1396 PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN),
1397 PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
1398 PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
1399 PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1400 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
1401 PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1402 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
1403 PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1404 PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0),
1405
1406 PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC),
1407 PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
1408 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
1409 PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1410 PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1411 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1412 PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
1413 PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
1414 PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1),
1415
1416 /* IPSR17 */
1417 PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN),
1418 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
1419 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
1420 PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1421 PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1422 PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
1423 PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2),
1424
1425 PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC),
1426 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
1427 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
1428 PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1429 PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1430 PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
1431 PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
1432
1433 /*
1434 * Static pins can not be muxed between different functions but
1435 * still needs a mark entry in the pinmux list. Add each static
1436 * pin to the list without an associated function. The sh-pfc
1437 * core will do the right thing and skip trying to mux then pin
1438 * while still applying configuration to it
1439 */
1440 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1441 PINMUX_STATIC
1442 #undef FM
1443 };
1444
1445 /*
1446 * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
1447 * Physical layout rows: A - AW, cols: 1 - 39.
1448 */
1449 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1450 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1451 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1452
1453 static const struct sh_pfc_pin pinmux_pins[] = {
1454 PINMUX_GPIO_GP_ALL(),
1455
1456 /*
1457 * Pins not associated with a GPIO port.
1458 *
1459 * The pin positions are different between different r8a7795
1460 * packages, all that is needed for the pfc driver is a unique
1461 * number for each pin. To this end use the pin layout from
1462 * R-Car H3SiP to calculate a unique number for each pin.
1463 */
1464 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1465 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1466 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1467 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1468 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1469 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1470 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1471 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1472 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1473 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1474 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1475 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1476 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1477 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1478 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1479 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1480 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1481 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1482 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1483 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1484 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1485 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1486 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1487 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1488 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1489 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1490 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1491 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1492 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1493 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1494 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1495 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1496 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1497 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1498 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1499 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1500 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1501 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1502 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1503 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1504 };
1505
1506 /* - AUDIO CLOCK ------------------------------------------------------------ */
1507 static const unsigned int audio_clk_a_a_pins[] = {
1508 /* CLK A */
1509 RCAR_GP_PIN(6, 22),
1510 };
1511 static const unsigned int audio_clk_a_a_mux[] = {
1512 AUDIO_CLKA_A_MARK,
1513 };
1514 static const unsigned int audio_clk_a_b_pins[] = {
1515 /* CLK A */
1516 RCAR_GP_PIN(5, 4),
1517 };
1518 static const unsigned int audio_clk_a_b_mux[] = {
1519 AUDIO_CLKA_B_MARK,
1520 };
1521 static const unsigned int audio_clk_a_c_pins[] = {
1522 /* CLK A */
1523 RCAR_GP_PIN(5, 19),
1524 };
1525 static const unsigned int audio_clk_a_c_mux[] = {
1526 AUDIO_CLKA_C_MARK,
1527 };
1528 static const unsigned int audio_clk_b_a_pins[] = {
1529 /* CLK B */
1530 RCAR_GP_PIN(5, 12),
1531 };
1532 static const unsigned int audio_clk_b_a_mux[] = {
1533 AUDIO_CLKB_A_MARK,
1534 };
1535 static const unsigned int audio_clk_b_b_pins[] = {
1536 /* CLK B */
1537 RCAR_GP_PIN(6, 23),
1538 };
1539 static const unsigned int audio_clk_b_b_mux[] = {
1540 AUDIO_CLKB_B_MARK,
1541 };
1542 static const unsigned int audio_clk_c_a_pins[] = {
1543 /* CLK C */
1544 RCAR_GP_PIN(5, 21),
1545 };
1546 static const unsigned int audio_clk_c_a_mux[] = {
1547 AUDIO_CLKC_A_MARK,
1548 };
1549 static const unsigned int audio_clk_c_b_pins[] = {
1550 /* CLK C */
1551 RCAR_GP_PIN(5, 0),
1552 };
1553 static const unsigned int audio_clk_c_b_mux[] = {
1554 AUDIO_CLKC_B_MARK,
1555 };
1556 static const unsigned int audio_clkout_a_pins[] = {
1557 /* CLKOUT */
1558 RCAR_GP_PIN(5, 18),
1559 };
1560 static const unsigned int audio_clkout_a_mux[] = {
1561 AUDIO_CLKOUT_A_MARK,
1562 };
1563 static const unsigned int audio_clkout_b_pins[] = {
1564 /* CLKOUT */
1565 RCAR_GP_PIN(6, 28),
1566 };
1567 static const unsigned int audio_clkout_b_mux[] = {
1568 AUDIO_CLKOUT_B_MARK,
1569 };
1570 static const unsigned int audio_clkout_c_pins[] = {
1571 /* CLKOUT */
1572 RCAR_GP_PIN(5, 3),
1573 };
1574 static const unsigned int audio_clkout_c_mux[] = {
1575 AUDIO_CLKOUT_C_MARK,
1576 };
1577 static const unsigned int audio_clkout_d_pins[] = {
1578 /* CLKOUT */
1579 RCAR_GP_PIN(5, 21),
1580 };
1581 static const unsigned int audio_clkout_d_mux[] = {
1582 AUDIO_CLKOUT_D_MARK,
1583 };
1584 static const unsigned int audio_clkout1_a_pins[] = {
1585 /* CLKOUT1 */
1586 RCAR_GP_PIN(5, 15),
1587 };
1588 static const unsigned int audio_clkout1_a_mux[] = {
1589 AUDIO_CLKOUT1_A_MARK,
1590 };
1591 static const unsigned int audio_clkout1_b_pins[] = {
1592 /* CLKOUT1 */
1593 RCAR_GP_PIN(6, 29),
1594 };
1595 static const unsigned int audio_clkout1_b_mux[] = {
1596 AUDIO_CLKOUT1_B_MARK,
1597 };
1598 static const unsigned int audio_clkout2_a_pins[] = {
1599 /* CLKOUT2 */
1600 RCAR_GP_PIN(5, 16),
1601 };
1602 static const unsigned int audio_clkout2_a_mux[] = {
1603 AUDIO_CLKOUT2_A_MARK,
1604 };
1605 static const unsigned int audio_clkout2_b_pins[] = {
1606 /* CLKOUT2 */
1607 RCAR_GP_PIN(6, 30),
1608 };
1609 static const unsigned int audio_clkout2_b_mux[] = {
1610 AUDIO_CLKOUT2_B_MARK,
1611 };
1612
1613 static const unsigned int audio_clkout3_a_pins[] = {
1614 /* CLKOUT3 */
1615 RCAR_GP_PIN(5, 19),
1616 };
1617 static const unsigned int audio_clkout3_a_mux[] = {
1618 AUDIO_CLKOUT3_A_MARK,
1619 };
1620 static const unsigned int audio_clkout3_b_pins[] = {
1621 /* CLKOUT3 */
1622 RCAR_GP_PIN(6, 31),
1623 };
1624 static const unsigned int audio_clkout3_b_mux[] = {
1625 AUDIO_CLKOUT3_B_MARK,
1626 };
1627
1628 /* - EtherAVB --------------------------------------------------------------- */
1629 static const unsigned int avb_link_pins[] = {
1630 /* AVB_LINK */
1631 RCAR_GP_PIN(2, 12),
1632 };
1633 static const unsigned int avb_link_mux[] = {
1634 AVB_LINK_MARK,
1635 };
1636 static const unsigned int avb_magic_pins[] = {
1637 /* AVB_MAGIC_ */
1638 RCAR_GP_PIN(2, 10),
1639 };
1640 static const unsigned int avb_magic_mux[] = {
1641 AVB_MAGIC_MARK,
1642 };
1643 static const unsigned int avb_phy_int_pins[] = {
1644 /* AVB_PHY_INT */
1645 RCAR_GP_PIN(2, 11),
1646 };
1647 static const unsigned int avb_phy_int_mux[] = {
1648 AVB_PHY_INT_MARK,
1649 };
1650 static const unsigned int avb_mdc_pins[] = {
1651 /* AVB_MDC, AVB_MDIO */
1652 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1653 };
1654 static const unsigned int avb_mdc_mux[] = {
1655 AVB_MDC_MARK, AVB_MDIO_MARK,
1656 };
1657 static const unsigned int avb_mii_pins[] = {
1658 /*
1659 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1660 * AVB_TD1, AVB_TD2, AVB_TD3,
1661 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1662 * AVB_RD1, AVB_RD2, AVB_RD3,
1663 * AVB_TXCREFCLK
1664 */
1665 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1666 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1667 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1668 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1669 PIN_NUMBER('A', 12),
1670
1671 };
1672 static const unsigned int avb_mii_mux[] = {
1673 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1674 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1675 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1676 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1677 AVB_TXCREFCLK_MARK,
1678 };
1679 static const unsigned int avb_avtp_pps_pins[] = {
1680 /* AVB_AVTP_PPS */
1681 RCAR_GP_PIN(2, 6),
1682 };
1683 static const unsigned int avb_avtp_pps_mux[] = {
1684 AVB_AVTP_PPS_MARK,
1685 };
1686 static const unsigned int avb_avtp_match_a_pins[] = {
1687 /* AVB_AVTP_MATCH_A */
1688 RCAR_GP_PIN(2, 13),
1689 };
1690 static const unsigned int avb_avtp_match_a_mux[] = {
1691 AVB_AVTP_MATCH_A_MARK,
1692 };
1693 static const unsigned int avb_avtp_capture_a_pins[] = {
1694 /* AVB_AVTP_CAPTURE_A */
1695 RCAR_GP_PIN(2, 14),
1696 };
1697 static const unsigned int avb_avtp_capture_a_mux[] = {
1698 AVB_AVTP_CAPTURE_A_MARK,
1699 };
1700 static const unsigned int avb_avtp_match_b_pins[] = {
1701 /* AVB_AVTP_MATCH_B */
1702 RCAR_GP_PIN(1, 8),
1703 };
1704 static const unsigned int avb_avtp_match_b_mux[] = {
1705 AVB_AVTP_MATCH_B_MARK,
1706 };
1707 static const unsigned int avb_avtp_capture_b_pins[] = {
1708 /* AVB_AVTP_CAPTURE_B */
1709 RCAR_GP_PIN(1, 11),
1710 };
1711 static const unsigned int avb_avtp_capture_b_mux[] = {
1712 AVB_AVTP_CAPTURE_B_MARK,
1713 };
1714
1715 /* - CAN ------------------------------------------------------------------ */
1716 static const unsigned int can0_data_a_pins[] = {
1717 /* TX, RX */
1718 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1719 };
1720 static const unsigned int can0_data_a_mux[] = {
1721 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1722 };
1723 static const unsigned int can0_data_b_pins[] = {
1724 /* TX, RX */
1725 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1726 };
1727 static const unsigned int can0_data_b_mux[] = {
1728 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1729 };
1730 static const unsigned int can1_data_pins[] = {
1731 /* TX, RX */
1732 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1733 };
1734 static const unsigned int can1_data_mux[] = {
1735 CAN1_TX_MARK, CAN1_RX_MARK,
1736 };
1737
1738 /* - CAN Clock -------------------------------------------------------------- */
1739 static const unsigned int can_clk_pins[] = {
1740 /* CLK */
1741 RCAR_GP_PIN(1, 25),
1742 };
1743 static const unsigned int can_clk_mux[] = {
1744 CAN_CLK_MARK,
1745 };
1746
1747 /* - CAN FD --------------------------------------------------------------- */
1748 static const unsigned int canfd0_data_a_pins[] = {
1749 /* TX, RX */
1750 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1751 };
1752 static const unsigned int canfd0_data_a_mux[] = {
1753 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1754 };
1755 static const unsigned int canfd0_data_b_pins[] = {
1756 /* TX, RX */
1757 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1758 };
1759 static const unsigned int canfd0_data_b_mux[] = {
1760 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1761 };
1762 static const unsigned int canfd1_data_pins[] = {
1763 /* TX, RX */
1764 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1765 };
1766 static const unsigned int canfd1_data_mux[] = {
1767 CANFD1_TX_MARK, CANFD1_RX_MARK,
1768 };
1769
1770 /* - DRIF0 --------------------------------------------------------------- */
1771 static const unsigned int drif0_ctrl_a_pins[] = {
1772 /* CLK, SYNC */
1773 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1774 };
1775 static const unsigned int drif0_ctrl_a_mux[] = {
1776 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1777 };
1778 static const unsigned int drif0_data0_a_pins[] = {
1779 /* D0 */
1780 RCAR_GP_PIN(6, 10),
1781 };
1782 static const unsigned int drif0_data0_a_mux[] = {
1783 RIF0_D0_A_MARK,
1784 };
1785 static const unsigned int drif0_data1_a_pins[] = {
1786 /* D1 */
1787 RCAR_GP_PIN(6, 7),
1788 };
1789 static const unsigned int drif0_data1_a_mux[] = {
1790 RIF0_D1_A_MARK,
1791 };
1792 static const unsigned int drif0_ctrl_b_pins[] = {
1793 /* CLK, SYNC */
1794 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1795 };
1796 static const unsigned int drif0_ctrl_b_mux[] = {
1797 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1798 };
1799 static const unsigned int drif0_data0_b_pins[] = {
1800 /* D0 */
1801 RCAR_GP_PIN(5, 1),
1802 };
1803 static const unsigned int drif0_data0_b_mux[] = {
1804 RIF0_D0_B_MARK,
1805 };
1806 static const unsigned int drif0_data1_b_pins[] = {
1807 /* D1 */
1808 RCAR_GP_PIN(5, 2),
1809 };
1810 static const unsigned int drif0_data1_b_mux[] = {
1811 RIF0_D1_B_MARK,
1812 };
1813 static const unsigned int drif0_ctrl_c_pins[] = {
1814 /* CLK, SYNC */
1815 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1816 };
1817 static const unsigned int drif0_ctrl_c_mux[] = {
1818 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1819 };
1820 static const unsigned int drif0_data0_c_pins[] = {
1821 /* D0 */
1822 RCAR_GP_PIN(5, 13),
1823 };
1824 static const unsigned int drif0_data0_c_mux[] = {
1825 RIF0_D0_C_MARK,
1826 };
1827 static const unsigned int drif0_data1_c_pins[] = {
1828 /* D1 */
1829 RCAR_GP_PIN(5, 14),
1830 };
1831 static const unsigned int drif0_data1_c_mux[] = {
1832 RIF0_D1_C_MARK,
1833 };
1834 /* - DRIF1 --------------------------------------------------------------- */
1835 static const unsigned int drif1_ctrl_a_pins[] = {
1836 /* CLK, SYNC */
1837 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1838 };
1839 static const unsigned int drif1_ctrl_a_mux[] = {
1840 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1841 };
1842 static const unsigned int drif1_data0_a_pins[] = {
1843 /* D0 */
1844 RCAR_GP_PIN(6, 19),
1845 };
1846 static const unsigned int drif1_data0_a_mux[] = {
1847 RIF1_D0_A_MARK,
1848 };
1849 static const unsigned int drif1_data1_a_pins[] = {
1850 /* D1 */
1851 RCAR_GP_PIN(6, 20),
1852 };
1853 static const unsigned int drif1_data1_a_mux[] = {
1854 RIF1_D1_A_MARK,
1855 };
1856 static const unsigned int drif1_ctrl_b_pins[] = {
1857 /* CLK, SYNC */
1858 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1859 };
1860 static const unsigned int drif1_ctrl_b_mux[] = {
1861 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1862 };
1863 static const unsigned int drif1_data0_b_pins[] = {
1864 /* D0 */
1865 RCAR_GP_PIN(5, 7),
1866 };
1867 static const unsigned int drif1_data0_b_mux[] = {
1868 RIF1_D0_B_MARK,
1869 };
1870 static const unsigned int drif1_data1_b_pins[] = {
1871 /* D1 */
1872 RCAR_GP_PIN(5, 8),
1873 };
1874 static const unsigned int drif1_data1_b_mux[] = {
1875 RIF1_D1_B_MARK,
1876 };
1877 static const unsigned int drif1_ctrl_c_pins[] = {
1878 /* CLK, SYNC */
1879 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1880 };
1881 static const unsigned int drif1_ctrl_c_mux[] = {
1882 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1883 };
1884 static const unsigned int drif1_data0_c_pins[] = {
1885 /* D0 */
1886 RCAR_GP_PIN(5, 6),
1887 };
1888 static const unsigned int drif1_data0_c_mux[] = {
1889 RIF1_D0_C_MARK,
1890 };
1891 static const unsigned int drif1_data1_c_pins[] = {
1892 /* D1 */
1893 RCAR_GP_PIN(5, 10),
1894 };
1895 static const unsigned int drif1_data1_c_mux[] = {
1896 RIF1_D1_C_MARK,
1897 };
1898 /* - DRIF2 --------------------------------------------------------------- */
1899 static const unsigned int drif2_ctrl_a_pins[] = {
1900 /* CLK, SYNC */
1901 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1902 };
1903 static const unsigned int drif2_ctrl_a_mux[] = {
1904 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1905 };
1906 static const unsigned int drif2_data0_a_pins[] = {
1907 /* D0 */
1908 RCAR_GP_PIN(6, 7),
1909 };
1910 static const unsigned int drif2_data0_a_mux[] = {
1911 RIF2_D0_A_MARK,
1912 };
1913 static const unsigned int drif2_data1_a_pins[] = {
1914 /* D1 */
1915 RCAR_GP_PIN(6, 10),
1916 };
1917 static const unsigned int drif2_data1_a_mux[] = {
1918 RIF2_D1_A_MARK,
1919 };
1920 static const unsigned int drif2_ctrl_b_pins[] = {
1921 /* CLK, SYNC */
1922 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1923 };
1924 static const unsigned int drif2_ctrl_b_mux[] = {
1925 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1926 };
1927 static const unsigned int drif2_data0_b_pins[] = {
1928 /* D0 */
1929 RCAR_GP_PIN(6, 30),
1930 };
1931 static const unsigned int drif2_data0_b_mux[] = {
1932 RIF2_D0_B_MARK,
1933 };
1934 static const unsigned int drif2_data1_b_pins[] = {
1935 /* D1 */
1936 RCAR_GP_PIN(6, 31),
1937 };
1938 static const unsigned int drif2_data1_b_mux[] = {
1939 RIF2_D1_B_MARK,
1940 };
1941 /* - DRIF3 --------------------------------------------------------------- */
1942 static const unsigned int drif3_ctrl_a_pins[] = {
1943 /* CLK, SYNC */
1944 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1945 };
1946 static const unsigned int drif3_ctrl_a_mux[] = {
1947 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1948 };
1949 static const unsigned int drif3_data0_a_pins[] = {
1950 /* D0 */
1951 RCAR_GP_PIN(6, 19),
1952 };
1953 static const unsigned int drif3_data0_a_mux[] = {
1954 RIF3_D0_A_MARK,
1955 };
1956 static const unsigned int drif3_data1_a_pins[] = {
1957 /* D1 */
1958 RCAR_GP_PIN(6, 20),
1959 };
1960 static const unsigned int drif3_data1_a_mux[] = {
1961 RIF3_D1_A_MARK,
1962 };
1963 static const unsigned int drif3_ctrl_b_pins[] = {
1964 /* CLK, SYNC */
1965 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1966 };
1967 static const unsigned int drif3_ctrl_b_mux[] = {
1968 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1969 };
1970 static const unsigned int drif3_data0_b_pins[] = {
1971 /* D0 */
1972 RCAR_GP_PIN(6, 28),
1973 };
1974 static const unsigned int drif3_data0_b_mux[] = {
1975 RIF3_D0_B_MARK,
1976 };
1977 static const unsigned int drif3_data1_b_pins[] = {
1978 /* D1 */
1979 RCAR_GP_PIN(6, 29),
1980 };
1981 static const unsigned int drif3_data1_b_mux[] = {
1982 RIF3_D1_B_MARK,
1983 };
1984
1985 /* - DU --------------------------------------------------------------------- */
1986 static const unsigned int du_rgb666_pins[] = {
1987 /* R[7:2], G[7:2], B[7:2] */
1988 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1989 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1990 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1991 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1992 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1993 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1994 };
1995 static const unsigned int du_rgb666_mux[] = {
1996 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1997 DU_DR3_MARK, DU_DR2_MARK,
1998 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1999 DU_DG3_MARK, DU_DG2_MARK,
2000 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2001 DU_DB3_MARK, DU_DB2_MARK,
2002 };
2003 static const unsigned int du_rgb888_pins[] = {
2004 /* R[7:0], G[7:0], B[7:0] */
2005 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2006 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2007 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2008 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2009 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2010 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2011 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2012 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2013 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2014 };
2015 static const unsigned int du_rgb888_mux[] = {
2016 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2017 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2018 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2019 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2020 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2021 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2022 };
2023 static const unsigned int du_clk_out_0_pins[] = {
2024 /* CLKOUT */
2025 RCAR_GP_PIN(1, 27),
2026 };
2027 static const unsigned int du_clk_out_0_mux[] = {
2028 DU_DOTCLKOUT0_MARK
2029 };
2030 static const unsigned int du_clk_out_1_pins[] = {
2031 /* CLKOUT */
2032 RCAR_GP_PIN(2, 3),
2033 };
2034 static const unsigned int du_clk_out_1_mux[] = {
2035 DU_DOTCLKOUT1_MARK
2036 };
2037 static const unsigned int du_sync_pins[] = {
2038 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2039 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2040 };
2041 static const unsigned int du_sync_mux[] = {
2042 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2043 };
2044 static const unsigned int du_oddf_pins[] = {
2045 /* EXDISP/EXODDF/EXCDE */
2046 RCAR_GP_PIN(2, 2),
2047 };
2048 static const unsigned int du_oddf_mux[] = {
2049 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2050 };
2051 static const unsigned int du_cde_pins[] = {
2052 /* CDE */
2053 RCAR_GP_PIN(2, 0),
2054 };
2055 static const unsigned int du_cde_mux[] = {
2056 DU_CDE_MARK,
2057 };
2058 static const unsigned int du_disp_pins[] = {
2059 /* DISP */
2060 RCAR_GP_PIN(2, 1),
2061 };
2062 static const unsigned int du_disp_mux[] = {
2063 DU_DISP_MARK,
2064 };
2065 /* - HSCIF0 ----------------------------------------------------------------- */
2066 static const unsigned int hscif0_data_pins[] = {
2067 /* RX, TX */
2068 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2069 };
2070 static const unsigned int hscif0_data_mux[] = {
2071 HRX0_MARK, HTX0_MARK,
2072 };
2073 static const unsigned int hscif0_clk_pins[] = {
2074 /* SCK */
2075 RCAR_GP_PIN(5, 12),
2076 };
2077 static const unsigned int hscif0_clk_mux[] = {
2078 HSCK0_MARK,
2079 };
2080 static const unsigned int hscif0_ctrl_pins[] = {
2081 /* RTS, CTS */
2082 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2083 };
2084 static const unsigned int hscif0_ctrl_mux[] = {
2085 HRTS0_N_MARK, HCTS0_N_MARK,
2086 };
2087 /* - HSCIF1 ----------------------------------------------------------------- */
2088 static const unsigned int hscif1_data_a_pins[] = {
2089 /* RX, TX */
2090 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2091 };
2092 static const unsigned int hscif1_data_a_mux[] = {
2093 HRX1_A_MARK, HTX1_A_MARK,
2094 };
2095 static const unsigned int hscif1_clk_a_pins[] = {
2096 /* SCK */
2097 RCAR_GP_PIN(6, 21),
2098 };
2099 static const unsigned int hscif1_clk_a_mux[] = {
2100 HSCK1_A_MARK,
2101 };
2102 static const unsigned int hscif1_ctrl_a_pins[] = {
2103 /* RTS, CTS */
2104 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2105 };
2106 static const unsigned int hscif1_ctrl_a_mux[] = {
2107 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2108 };
2109
2110 static const unsigned int hscif1_data_b_pins[] = {
2111 /* RX, TX */
2112 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2113 };
2114 static const unsigned int hscif1_data_b_mux[] = {
2115 HRX1_B_MARK, HTX1_B_MARK,
2116 };
2117 static const unsigned int hscif1_clk_b_pins[] = {
2118 /* SCK */
2119 RCAR_GP_PIN(5, 0),
2120 };
2121 static const unsigned int hscif1_clk_b_mux[] = {
2122 HSCK1_B_MARK,
2123 };
2124 static const unsigned int hscif1_ctrl_b_pins[] = {
2125 /* RTS, CTS */
2126 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2127 };
2128 static const unsigned int hscif1_ctrl_b_mux[] = {
2129 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2130 };
2131 /* - HSCIF2 ----------------------------------------------------------------- */
2132 static const unsigned int hscif2_data_a_pins[] = {
2133 /* RX, TX */
2134 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2135 };
2136 static const unsigned int hscif2_data_a_mux[] = {
2137 HRX2_A_MARK, HTX2_A_MARK,
2138 };
2139 static const unsigned int hscif2_clk_a_pins[] = {
2140 /* SCK */
2141 RCAR_GP_PIN(6, 10),
2142 };
2143 static const unsigned int hscif2_clk_a_mux[] = {
2144 HSCK2_A_MARK,
2145 };
2146 static const unsigned int hscif2_ctrl_a_pins[] = {
2147 /* RTS, CTS */
2148 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2149 };
2150 static const unsigned int hscif2_ctrl_a_mux[] = {
2151 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2152 };
2153
2154 static const unsigned int hscif2_data_b_pins[] = {
2155 /* RX, TX */
2156 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2157 };
2158 static const unsigned int hscif2_data_b_mux[] = {
2159 HRX2_B_MARK, HTX2_B_MARK,
2160 };
2161 static const unsigned int hscif2_clk_b_pins[] = {
2162 /* SCK */
2163 RCAR_GP_PIN(6, 21),
2164 };
2165 static const unsigned int hscif2_clk_b_mux[] = {
2166 HSCK1_B_MARK,
2167 };
2168 static const unsigned int hscif2_ctrl_b_pins[] = {
2169 /* RTS, CTS */
2170 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2171 };
2172 static const unsigned int hscif2_ctrl_b_mux[] = {
2173 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2174 };
2175 /* - HSCIF3 ----------------------------------------------------------------- */
2176 static const unsigned int hscif3_data_a_pins[] = {
2177 /* RX, TX */
2178 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2179 };
2180 static const unsigned int hscif3_data_a_mux[] = {
2181 HRX3_A_MARK, HTX3_A_MARK,
2182 };
2183 static const unsigned int hscif3_clk_pins[] = {
2184 /* SCK */
2185 RCAR_GP_PIN(1, 22),
2186 };
2187 static const unsigned int hscif3_clk_mux[] = {
2188 HSCK3_MARK,
2189 };
2190 static const unsigned int hscif3_ctrl_pins[] = {
2191 /* RTS, CTS */
2192 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2193 };
2194 static const unsigned int hscif3_ctrl_mux[] = {
2195 HRTS3_N_MARK, HCTS3_N_MARK,
2196 };
2197
2198 static const unsigned int hscif3_data_b_pins[] = {
2199 /* RX, TX */
2200 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2201 };
2202 static const unsigned int hscif3_data_b_mux[] = {
2203 HRX3_B_MARK, HTX3_B_MARK,
2204 };
2205 static const unsigned int hscif3_data_c_pins[] = {
2206 /* RX, TX */
2207 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2208 };
2209 static const unsigned int hscif3_data_c_mux[] = {
2210 HRX3_C_MARK, HTX3_C_MARK,
2211 };
2212 static const unsigned int hscif3_data_d_pins[] = {
2213 /* RX, TX */
2214 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2215 };
2216 static const unsigned int hscif3_data_d_mux[] = {
2217 HRX3_D_MARK, HTX3_D_MARK,
2218 };
2219 /* - HSCIF4 ----------------------------------------------------------------- */
2220 static const unsigned int hscif4_data_a_pins[] = {
2221 /* RX, TX */
2222 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2223 };
2224 static const unsigned int hscif4_data_a_mux[] = {
2225 HRX4_A_MARK, HTX4_A_MARK,
2226 };
2227 static const unsigned int hscif4_clk_pins[] = {
2228 /* SCK */
2229 RCAR_GP_PIN(1, 11),
2230 };
2231 static const unsigned int hscif4_clk_mux[] = {
2232 HSCK4_MARK,
2233 };
2234 static const unsigned int hscif4_ctrl_pins[] = {
2235 /* RTS, CTS */
2236 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2237 };
2238 static const unsigned int hscif4_ctrl_mux[] = {
2239 HRTS4_N_MARK, HCTS3_N_MARK,
2240 };
2241
2242 static const unsigned int hscif4_data_b_pins[] = {
2243 /* RX, TX */
2244 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2245 };
2246 static const unsigned int hscif4_data_b_mux[] = {
2247 HRX4_B_MARK, HTX4_B_MARK,
2248 };
2249
2250 /* - I2C -------------------------------------------------------------------- */
2251 static const unsigned int i2c1_a_pins[] = {
2252 /* SDA, SCL */
2253 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2254 };
2255 static const unsigned int i2c1_a_mux[] = {
2256 SDA1_A_MARK, SCL1_A_MARK,
2257 };
2258 static const unsigned int i2c1_b_pins[] = {
2259 /* SDA, SCL */
2260 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2261 };
2262 static const unsigned int i2c1_b_mux[] = {
2263 SDA1_B_MARK, SCL1_B_MARK,
2264 };
2265 static const unsigned int i2c2_a_pins[] = {
2266 /* SDA, SCL */
2267 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2268 };
2269 static const unsigned int i2c2_a_mux[] = {
2270 SDA2_A_MARK, SCL2_A_MARK,
2271 };
2272 static const unsigned int i2c2_b_pins[] = {
2273 /* SDA, SCL */
2274 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2275 };
2276 static const unsigned int i2c2_b_mux[] = {
2277 SDA2_B_MARK, SCL2_B_MARK,
2278 };
2279 static const unsigned int i2c6_a_pins[] = {
2280 /* SDA, SCL */
2281 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2282 };
2283 static const unsigned int i2c6_a_mux[] = {
2284 SDA6_A_MARK, SCL6_A_MARK,
2285 };
2286 static const unsigned int i2c6_b_pins[] = {
2287 /* SDA, SCL */
2288 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2289 };
2290 static const unsigned int i2c6_b_mux[] = {
2291 SDA6_B_MARK, SCL6_B_MARK,
2292 };
2293 static const unsigned int i2c6_c_pins[] = {
2294 /* SDA, SCL */
2295 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2296 };
2297 static const unsigned int i2c6_c_mux[] = {
2298 SDA6_C_MARK, SCL6_C_MARK,
2299 };
2300
2301 /* - INTC-EX ---------------------------------------------------------------- */
2302 static const unsigned int intc_ex_irq0_pins[] = {
2303 /* IRQ0 */
2304 RCAR_GP_PIN(2, 0),
2305 };
2306 static const unsigned int intc_ex_irq0_mux[] = {
2307 IRQ0_MARK,
2308 };
2309 static const unsigned int intc_ex_irq1_pins[] = {
2310 /* IRQ1 */
2311 RCAR_GP_PIN(2, 1),
2312 };
2313 static const unsigned int intc_ex_irq1_mux[] = {
2314 IRQ1_MARK,
2315 };
2316 static const unsigned int intc_ex_irq2_pins[] = {
2317 /* IRQ2 */
2318 RCAR_GP_PIN(2, 2),
2319 };
2320 static const unsigned int intc_ex_irq2_mux[] = {
2321 IRQ2_MARK,
2322 };
2323 static const unsigned int intc_ex_irq3_pins[] = {
2324 /* IRQ3 */
2325 RCAR_GP_PIN(2, 3),
2326 };
2327 static const unsigned int intc_ex_irq3_mux[] = {
2328 IRQ3_MARK,
2329 };
2330 static const unsigned int intc_ex_irq4_pins[] = {
2331 /* IRQ4 */
2332 RCAR_GP_PIN(2, 4),
2333 };
2334 static const unsigned int intc_ex_irq4_mux[] = {
2335 IRQ4_MARK,
2336 };
2337 static const unsigned int intc_ex_irq5_pins[] = {
2338 /* IRQ5 */
2339 RCAR_GP_PIN(2, 5),
2340 };
2341 static const unsigned int intc_ex_irq5_mux[] = {
2342 IRQ5_MARK,
2343 };
2344
2345 /* - MSIOF0 ----------------------------------------------------------------- */
2346 static const unsigned int msiof0_clk_pins[] = {
2347 /* SCK */
2348 RCAR_GP_PIN(5, 17),
2349 };
2350 static const unsigned int msiof0_clk_mux[] = {
2351 MSIOF0_SCK_MARK,
2352 };
2353 static const unsigned int msiof0_sync_pins[] = {
2354 /* SYNC */
2355 RCAR_GP_PIN(5, 18),
2356 };
2357 static const unsigned int msiof0_sync_mux[] = {
2358 MSIOF0_SYNC_MARK,
2359 };
2360 static const unsigned int msiof0_ss1_pins[] = {
2361 /* SS1 */
2362 RCAR_GP_PIN(5, 19),
2363 };
2364 static const unsigned int msiof0_ss1_mux[] = {
2365 MSIOF0_SS1_MARK,
2366 };
2367 static const unsigned int msiof0_ss2_pins[] = {
2368 /* SS2 */
2369 RCAR_GP_PIN(5, 21),
2370 };
2371 static const unsigned int msiof0_ss2_mux[] = {
2372 MSIOF0_SS2_MARK,
2373 };
2374 static const unsigned int msiof0_txd_pins[] = {
2375 /* TXD */
2376 RCAR_GP_PIN(5, 20),
2377 };
2378 static const unsigned int msiof0_txd_mux[] = {
2379 MSIOF0_TXD_MARK,
2380 };
2381 static const unsigned int msiof0_rxd_pins[] = {
2382 /* RXD */
2383 RCAR_GP_PIN(5, 22),
2384 };
2385 static const unsigned int msiof0_rxd_mux[] = {
2386 MSIOF0_RXD_MARK,
2387 };
2388 /* - MSIOF1 ----------------------------------------------------------------- */
2389 static const unsigned int msiof1_clk_a_pins[] = {
2390 /* SCK */
2391 RCAR_GP_PIN(6, 8),
2392 };
2393 static const unsigned int msiof1_clk_a_mux[] = {
2394 MSIOF1_SCK_A_MARK,
2395 };
2396 static const unsigned int msiof1_sync_a_pins[] = {
2397 /* SYNC */
2398 RCAR_GP_PIN(6, 9),
2399 };
2400 static const unsigned int msiof1_sync_a_mux[] = {
2401 MSIOF1_SYNC_A_MARK,
2402 };
2403 static const unsigned int msiof1_ss1_a_pins[] = {
2404 /* SS1 */
2405 RCAR_GP_PIN(6, 5),
2406 };
2407 static const unsigned int msiof1_ss1_a_mux[] = {
2408 MSIOF1_SS1_A_MARK,
2409 };
2410 static const unsigned int msiof1_ss2_a_pins[] = {
2411 /* SS2 */
2412 RCAR_GP_PIN(6, 6),
2413 };
2414 static const unsigned int msiof1_ss2_a_mux[] = {
2415 MSIOF1_SS2_A_MARK,
2416 };
2417 static const unsigned int msiof1_txd_a_pins[] = {
2418 /* TXD */
2419 RCAR_GP_PIN(6, 7),
2420 };
2421 static const unsigned int msiof1_txd_a_mux[] = {
2422 MSIOF1_TXD_A_MARK,
2423 };
2424 static const unsigned int msiof1_rxd_a_pins[] = {
2425 /* RXD */
2426 RCAR_GP_PIN(6, 10),
2427 };
2428 static const unsigned int msiof1_rxd_a_mux[] = {
2429 MSIOF1_RXD_A_MARK,
2430 };
2431 static const unsigned int msiof1_clk_b_pins[] = {
2432 /* SCK */
2433 RCAR_GP_PIN(5, 9),
2434 };
2435 static const unsigned int msiof1_clk_b_mux[] = {
2436 MSIOF1_SCK_B_MARK,
2437 };
2438 static const unsigned int msiof1_sync_b_pins[] = {
2439 /* SYNC */
2440 RCAR_GP_PIN(5, 3),
2441 };
2442 static const unsigned int msiof1_sync_b_mux[] = {
2443 MSIOF1_SYNC_B_MARK,
2444 };
2445 static const unsigned int msiof1_ss1_b_pins[] = {
2446 /* SS1 */
2447 RCAR_GP_PIN(5, 4),
2448 };
2449 static const unsigned int msiof1_ss1_b_mux[] = {
2450 MSIOF1_SS1_B_MARK,
2451 };
2452 static const unsigned int msiof1_ss2_b_pins[] = {
2453 /* SS2 */
2454 RCAR_GP_PIN(5, 0),
2455 };
2456 static const unsigned int msiof1_ss2_b_mux[] = {
2457 MSIOF1_SS2_B_MARK,
2458 };
2459 static const unsigned int msiof1_txd_b_pins[] = {
2460 /* TXD */
2461 RCAR_GP_PIN(5, 8),
2462 };
2463 static const unsigned int msiof1_txd_b_mux[] = {
2464 MSIOF1_TXD_B_MARK,
2465 };
2466 static const unsigned int msiof1_rxd_b_pins[] = {
2467 /* RXD */
2468 RCAR_GP_PIN(5, 7),
2469 };
2470 static const unsigned int msiof1_rxd_b_mux[] = {
2471 MSIOF1_RXD_B_MARK,
2472 };
2473 static const unsigned int msiof1_clk_c_pins[] = {
2474 /* SCK */
2475 RCAR_GP_PIN(6, 17),
2476 };
2477 static const unsigned int msiof1_clk_c_mux[] = {
2478 MSIOF1_SCK_C_MARK,
2479 };
2480 static const unsigned int msiof1_sync_c_pins[] = {
2481 /* SYNC */
2482 RCAR_GP_PIN(6, 18),
2483 };
2484 static const unsigned int msiof1_sync_c_mux[] = {
2485 MSIOF1_SYNC_C_MARK,
2486 };
2487 static const unsigned int msiof1_ss1_c_pins[] = {
2488 /* SS1 */
2489 RCAR_GP_PIN(6, 21),
2490 };
2491 static const unsigned int msiof1_ss1_c_mux[] = {
2492 MSIOF1_SS1_C_MARK,
2493 };
2494 static const unsigned int msiof1_ss2_c_pins[] = {
2495 /* SS2 */
2496 RCAR_GP_PIN(6, 27),
2497 };
2498 static const unsigned int msiof1_ss2_c_mux[] = {
2499 MSIOF1_SS2_C_MARK,
2500 };
2501 static const unsigned int msiof1_txd_c_pins[] = {
2502 /* TXD */
2503 RCAR_GP_PIN(6, 20),
2504 };
2505 static const unsigned int msiof1_txd_c_mux[] = {
2506 MSIOF1_TXD_C_MARK,
2507 };
2508 static const unsigned int msiof1_rxd_c_pins[] = {
2509 /* RXD */
2510 RCAR_GP_PIN(6, 19),
2511 };
2512 static const unsigned int msiof1_rxd_c_mux[] = {
2513 MSIOF1_RXD_C_MARK,
2514 };
2515 static const unsigned int msiof1_clk_d_pins[] = {
2516 /* SCK */
2517 RCAR_GP_PIN(5, 12),
2518 };
2519 static const unsigned int msiof1_clk_d_mux[] = {
2520 MSIOF1_SCK_D_MARK,
2521 };
2522 static const unsigned int msiof1_sync_d_pins[] = {
2523 /* SYNC */
2524 RCAR_GP_PIN(5, 15),
2525 };
2526 static const unsigned int msiof1_sync_d_mux[] = {
2527 MSIOF1_SYNC_D_MARK,
2528 };
2529 static const unsigned int msiof1_ss1_d_pins[] = {
2530 /* SS1 */
2531 RCAR_GP_PIN(5, 16),
2532 };
2533 static const unsigned int msiof1_ss1_d_mux[] = {
2534 MSIOF1_SS1_D_MARK,
2535 };
2536 static const unsigned int msiof1_ss2_d_pins[] = {
2537 /* SS2 */
2538 RCAR_GP_PIN(5, 21),
2539 };
2540 static const unsigned int msiof1_ss2_d_mux[] = {
2541 MSIOF1_SS2_D_MARK,
2542 };
2543 static const unsigned int msiof1_txd_d_pins[] = {
2544 /* TXD */
2545 RCAR_GP_PIN(5, 14),
2546 };
2547 static const unsigned int msiof1_txd_d_mux[] = {
2548 MSIOF1_TXD_D_MARK,
2549 };
2550 static const unsigned int msiof1_rxd_d_pins[] = {
2551 /* RXD */
2552 RCAR_GP_PIN(5, 13),
2553 };
2554 static const unsigned int msiof1_rxd_d_mux[] = {
2555 MSIOF1_RXD_D_MARK,
2556 };
2557 static const unsigned int msiof1_clk_e_pins[] = {
2558 /* SCK */
2559 RCAR_GP_PIN(3, 0),
2560 };
2561 static const unsigned int msiof1_clk_e_mux[] = {
2562 MSIOF1_SCK_E_MARK,
2563 };
2564 static const unsigned int msiof1_sync_e_pins[] = {
2565 /* SYNC */
2566 RCAR_GP_PIN(3, 1),
2567 };
2568 static const unsigned int msiof1_sync_e_mux[] = {
2569 MSIOF1_SYNC_E_MARK,
2570 };
2571 static const unsigned int msiof1_ss1_e_pins[] = {
2572 /* SS1 */
2573 RCAR_GP_PIN(3, 4),
2574 };
2575 static const unsigned int msiof1_ss1_e_mux[] = {
2576 MSIOF1_SS1_E_MARK,
2577 };
2578 static const unsigned int msiof1_ss2_e_pins[] = {
2579 /* SS2 */
2580 RCAR_GP_PIN(3, 5),
2581 };
2582 static const unsigned int msiof1_ss2_e_mux[] = {
2583 MSIOF1_SS2_E_MARK,
2584 };
2585 static const unsigned int msiof1_txd_e_pins[] = {
2586 /* TXD */
2587 RCAR_GP_PIN(3, 3),
2588 };
2589 static const unsigned int msiof1_txd_e_mux[] = {
2590 MSIOF1_TXD_E_MARK,
2591 };
2592 static const unsigned int msiof1_rxd_e_pins[] = {
2593 /* RXD */
2594 RCAR_GP_PIN(3, 2),
2595 };
2596 static const unsigned int msiof1_rxd_e_mux[] = {
2597 MSIOF1_RXD_E_MARK,
2598 };
2599 static const unsigned int msiof1_clk_f_pins[] = {
2600 /* SCK */
2601 RCAR_GP_PIN(5, 23),
2602 };
2603 static const unsigned int msiof1_clk_f_mux[] = {
2604 MSIOF1_SCK_F_MARK,
2605 };
2606 static const unsigned int msiof1_sync_f_pins[] = {
2607 /* SYNC */
2608 RCAR_GP_PIN(5, 24),
2609 };
2610 static const unsigned int msiof1_sync_f_mux[] = {
2611 MSIOF1_SYNC_F_MARK,
2612 };
2613 static const unsigned int msiof1_ss1_f_pins[] = {
2614 /* SS1 */
2615 RCAR_GP_PIN(6, 1),
2616 };
2617 static const unsigned int msiof1_ss1_f_mux[] = {
2618 MSIOF1_SS1_F_MARK,
2619 };
2620 static const unsigned int msiof1_ss2_f_pins[] = {
2621 /* SS2 */
2622 RCAR_GP_PIN(6, 2),
2623 };
2624 static const unsigned int msiof1_ss2_f_mux[] = {
2625 MSIOF1_SS2_F_MARK,
2626 };
2627 static const unsigned int msiof1_txd_f_pins[] = {
2628 /* TXD */
2629 RCAR_GP_PIN(6, 0),
2630 };
2631 static const unsigned int msiof1_txd_f_mux[] = {
2632 MSIOF1_TXD_F_MARK,
2633 };
2634 static const unsigned int msiof1_rxd_f_pins[] = {
2635 /* RXD */
2636 RCAR_GP_PIN(5, 25),
2637 };
2638 static const unsigned int msiof1_rxd_f_mux[] = {
2639 MSIOF1_RXD_F_MARK,
2640 };
2641 static const unsigned int msiof1_clk_g_pins[] = {
2642 /* SCK */
2643 RCAR_GP_PIN(3, 6),
2644 };
2645 static const unsigned int msiof1_clk_g_mux[] = {
2646 MSIOF1_SCK_G_MARK,
2647 };
2648 static const unsigned int msiof1_sync_g_pins[] = {
2649 /* SYNC */
2650 RCAR_GP_PIN(3, 7),
2651 };
2652 static const unsigned int msiof1_sync_g_mux[] = {
2653 MSIOF1_SYNC_G_MARK,
2654 };
2655 static const unsigned int msiof1_ss1_g_pins[] = {
2656 /* SS1 */
2657 RCAR_GP_PIN(3, 10),
2658 };
2659 static const unsigned int msiof1_ss1_g_mux[] = {
2660 MSIOF1_SS1_G_MARK,
2661 };
2662 static const unsigned int msiof1_ss2_g_pins[] = {
2663 /* SS2 */
2664 RCAR_GP_PIN(3, 11),
2665 };
2666 static const unsigned int msiof1_ss2_g_mux[] = {
2667 MSIOF1_SS2_G_MARK,
2668 };
2669 static const unsigned int msiof1_txd_g_pins[] = {
2670 /* TXD */
2671 RCAR_GP_PIN(3, 9),
2672 };
2673 static const unsigned int msiof1_txd_g_mux[] = {
2674 MSIOF1_TXD_G_MARK,
2675 };
2676 static const unsigned int msiof1_rxd_g_pins[] = {
2677 /* RXD */
2678 RCAR_GP_PIN(3, 8),
2679 };
2680 static const unsigned int msiof1_rxd_g_mux[] = {
2681 MSIOF1_RXD_G_MARK,
2682 };
2683 /* - MSIOF2 ----------------------------------------------------------------- */
2684 static const unsigned int msiof2_clk_a_pins[] = {
2685 /* SCK */
2686 RCAR_GP_PIN(1, 9),
2687 };
2688 static const unsigned int msiof2_clk_a_mux[] = {
2689 MSIOF2_SCK_A_MARK,
2690 };
2691 static const unsigned int msiof2_sync_a_pins[] = {
2692 /* SYNC */
2693 RCAR_GP_PIN(1, 8),
2694 };
2695 static const unsigned int msiof2_sync_a_mux[] = {
2696 MSIOF2_SYNC_A_MARK,
2697 };
2698 static const unsigned int msiof2_ss1_a_pins[] = {
2699 /* SS1 */
2700 RCAR_GP_PIN(1, 6),
2701 };
2702 static const unsigned int msiof2_ss1_a_mux[] = {
2703 MSIOF2_SS1_A_MARK,
2704 };
2705 static const unsigned int msiof2_ss2_a_pins[] = {
2706 /* SS2 */
2707 RCAR_GP_PIN(1, 7),
2708 };
2709 static const unsigned int msiof2_ss2_a_mux[] = {
2710 MSIOF2_SS2_A_MARK,
2711 };
2712 static const unsigned int msiof2_txd_a_pins[] = {
2713 /* TXD */
2714 RCAR_GP_PIN(1, 11),
2715 };
2716 static const unsigned int msiof2_txd_a_mux[] = {
2717 MSIOF2_TXD_A_MARK,
2718 };
2719 static const unsigned int msiof2_rxd_a_pins[] = {
2720 /* RXD */
2721 RCAR_GP_PIN(1, 10),
2722 };
2723 static const unsigned int msiof2_rxd_a_mux[] = {
2724 MSIOF2_RXD_A_MARK,
2725 };
2726 static const unsigned int msiof2_clk_b_pins[] = {
2727 /* SCK */
2728 RCAR_GP_PIN(0, 4),
2729 };
2730 static const unsigned int msiof2_clk_b_mux[] = {
2731 MSIOF2_SCK_B_MARK,
2732 };
2733 static const unsigned int msiof2_sync_b_pins[] = {
2734 /* SYNC */
2735 RCAR_GP_PIN(0, 5),
2736 };
2737 static const unsigned int msiof2_sync_b_mux[] = {
2738 MSIOF2_SYNC_B_MARK,
2739 };
2740 static const unsigned int msiof2_ss1_b_pins[] = {
2741 /* SS1 */
2742 RCAR_GP_PIN(0, 0),
2743 };
2744 static const unsigned int msiof2_ss1_b_mux[] = {
2745 MSIOF2_SS1_B_MARK,
2746 };
2747 static const unsigned int msiof2_ss2_b_pins[] = {
2748 /* SS2 */
2749 RCAR_GP_PIN(0, 1),
2750 };
2751 static const unsigned int msiof2_ss2_b_mux[] = {
2752 MSIOF2_SS2_B_MARK,
2753 };
2754 static const unsigned int msiof2_txd_b_pins[] = {
2755 /* TXD */
2756 RCAR_GP_PIN(0, 7),
2757 };
2758 static const unsigned int msiof2_txd_b_mux[] = {
2759 MSIOF2_TXD_B_MARK,
2760 };
2761 static const unsigned int msiof2_rxd_b_pins[] = {
2762 /* RXD */
2763 RCAR_GP_PIN(0, 6),
2764 };
2765 static const unsigned int msiof2_rxd_b_mux[] = {
2766 MSIOF2_RXD_B_MARK,
2767 };
2768 static const unsigned int msiof2_clk_c_pins[] = {
2769 /* SCK */
2770 RCAR_GP_PIN(2, 12),
2771 };
2772 static const unsigned int msiof2_clk_c_mux[] = {
2773 MSIOF2_SCK_C_MARK,
2774 };
2775 static const unsigned int msiof2_sync_c_pins[] = {
2776 /* SYNC */
2777 RCAR_GP_PIN(2, 11),
2778 };
2779 static const unsigned int msiof2_sync_c_mux[] = {
2780 MSIOF2_SYNC_C_MARK,
2781 };
2782 static const unsigned int msiof2_ss1_c_pins[] = {
2783 /* SS1 */
2784 RCAR_GP_PIN(2, 10),
2785 };
2786 static const unsigned int msiof2_ss1_c_mux[] = {
2787 MSIOF2_SS1_C_MARK,
2788 };
2789 static const unsigned int msiof2_ss2_c_pins[] = {
2790 /* SS2 */
2791 RCAR_GP_PIN(2, 9),
2792 };
2793 static const unsigned int msiof2_ss2_c_mux[] = {
2794 MSIOF2_SS2_C_MARK,
2795 };
2796 static const unsigned int msiof2_txd_c_pins[] = {
2797 /* TXD */
2798 RCAR_GP_PIN(2, 14),
2799 };
2800 static const unsigned int msiof2_txd_c_mux[] = {
2801 MSIOF2_TXD_C_MARK,
2802 };
2803 static const unsigned int msiof2_rxd_c_pins[] = {
2804 /* RXD */
2805 RCAR_GP_PIN(2, 13),
2806 };
2807 static const unsigned int msiof2_rxd_c_mux[] = {
2808 MSIOF2_RXD_C_MARK,
2809 };
2810 static const unsigned int msiof2_clk_d_pins[] = {
2811 /* SCK */
2812 RCAR_GP_PIN(0, 8),
2813 };
2814 static const unsigned int msiof2_clk_d_mux[] = {
2815 MSIOF2_SCK_D_MARK,
2816 };
2817 static const unsigned int msiof2_sync_d_pins[] = {
2818 /* SYNC */
2819 RCAR_GP_PIN(0, 9),
2820 };
2821 static const unsigned int msiof2_sync_d_mux[] = {
2822 MSIOF2_SYNC_D_MARK,
2823 };
2824 static const unsigned int msiof2_ss1_d_pins[] = {
2825 /* SS1 */
2826 RCAR_GP_PIN(0, 12),
2827 };
2828 static const unsigned int msiof2_ss1_d_mux[] = {
2829 MSIOF2_SS1_D_MARK,
2830 };
2831 static const unsigned int msiof2_ss2_d_pins[] = {
2832 /* SS2 */
2833 RCAR_GP_PIN(0, 13),
2834 };
2835 static const unsigned int msiof2_ss2_d_mux[] = {
2836 MSIOF2_SS2_D_MARK,
2837 };
2838 static const unsigned int msiof2_txd_d_pins[] = {
2839 /* TXD */
2840 RCAR_GP_PIN(0, 11),
2841 };
2842 static const unsigned int msiof2_txd_d_mux[] = {
2843 MSIOF2_TXD_D_MARK,
2844 };
2845 static const unsigned int msiof2_rxd_d_pins[] = {
2846 /* RXD */
2847 RCAR_GP_PIN(0, 10),
2848 };
2849 static const unsigned int msiof2_rxd_d_mux[] = {
2850 MSIOF2_RXD_D_MARK,
2851 };
2852 /* - MSIOF3 ----------------------------------------------------------------- */
2853 static const unsigned int msiof3_clk_a_pins[] = {
2854 /* SCK */
2855 RCAR_GP_PIN(0, 0),
2856 };
2857 static const unsigned int msiof3_clk_a_mux[] = {
2858 MSIOF3_SCK_A_MARK,
2859 };
2860 static const unsigned int msiof3_sync_a_pins[] = {
2861 /* SYNC */
2862 RCAR_GP_PIN(0, 1),
2863 };
2864 static const unsigned int msiof3_sync_a_mux[] = {
2865 MSIOF3_SYNC_A_MARK,
2866 };
2867 static const unsigned int msiof3_ss1_a_pins[] = {
2868 /* SS1 */
2869 RCAR_GP_PIN(0, 14),
2870 };
2871 static const unsigned int msiof3_ss1_a_mux[] = {
2872 MSIOF3_SS1_A_MARK,
2873 };
2874 static const unsigned int msiof3_ss2_a_pins[] = {
2875 /* SS2 */
2876 RCAR_GP_PIN(0, 15),
2877 };
2878 static const unsigned int msiof3_ss2_a_mux[] = {
2879 MSIOF3_SS2_A_MARK,
2880 };
2881 static const unsigned int msiof3_txd_a_pins[] = {
2882 /* TXD */
2883 RCAR_GP_PIN(0, 3),
2884 };
2885 static const unsigned int msiof3_txd_a_mux[] = {
2886 MSIOF3_TXD_A_MARK,
2887 };
2888 static const unsigned int msiof3_rxd_a_pins[] = {
2889 /* RXD */
2890 RCAR_GP_PIN(0, 2),
2891 };
2892 static const unsigned int msiof3_rxd_a_mux[] = {
2893 MSIOF3_RXD_A_MARK,
2894 };
2895 static const unsigned int msiof3_clk_b_pins[] = {
2896 /* SCK */
2897 RCAR_GP_PIN(1, 2),
2898 };
2899 static const unsigned int msiof3_clk_b_mux[] = {
2900 MSIOF3_SCK_B_MARK,
2901 };
2902 static const unsigned int msiof3_sync_b_pins[] = {
2903 /* SYNC */
2904 RCAR_GP_PIN(1, 0),
2905 };
2906 static const unsigned int msiof3_sync_b_mux[] = {
2907 MSIOF3_SYNC_B_MARK,
2908 };
2909 static const unsigned int msiof3_ss1_b_pins[] = {
2910 /* SS1 */
2911 RCAR_GP_PIN(1, 4),
2912 };
2913 static const unsigned int msiof3_ss1_b_mux[] = {
2914 MSIOF3_SS1_B_MARK,
2915 };
2916 static const unsigned int msiof3_ss2_b_pins[] = {
2917 /* SS2 */
2918 RCAR_GP_PIN(1, 5),
2919 };
2920 static const unsigned int msiof3_ss2_b_mux[] = {
2921 MSIOF3_SS2_B_MARK,
2922 };
2923 static const unsigned int msiof3_txd_b_pins[] = {
2924 /* TXD */
2925 RCAR_GP_PIN(1, 1),
2926 };
2927 static const unsigned int msiof3_txd_b_mux[] = {
2928 MSIOF3_TXD_B_MARK,
2929 };
2930 static const unsigned int msiof3_rxd_b_pins[] = {
2931 /* RXD */
2932 RCAR_GP_PIN(1, 3),
2933 };
2934 static const unsigned int msiof3_rxd_b_mux[] = {
2935 MSIOF3_RXD_B_MARK,
2936 };
2937 static const unsigned int msiof3_clk_c_pins[] = {
2938 /* SCK */
2939 RCAR_GP_PIN(1, 12),
2940 };
2941 static const unsigned int msiof3_clk_c_mux[] = {
2942 MSIOF3_SCK_C_MARK,
2943 };
2944 static const unsigned int msiof3_sync_c_pins[] = {
2945 /* SYNC */
2946 RCAR_GP_PIN(1, 13),
2947 };
2948 static const unsigned int msiof3_sync_c_mux[] = {
2949 MSIOF3_SYNC_C_MARK,
2950 };
2951 static const unsigned int msiof3_txd_c_pins[] = {
2952 /* TXD */
2953 RCAR_GP_PIN(1, 15),
2954 };
2955 static const unsigned int msiof3_txd_c_mux[] = {
2956 MSIOF3_TXD_C_MARK,
2957 };
2958 static const unsigned int msiof3_rxd_c_pins[] = {
2959 /* RXD */
2960 RCAR_GP_PIN(1, 14),
2961 };
2962 static const unsigned int msiof3_rxd_c_mux[] = {
2963 MSIOF3_RXD_C_MARK,
2964 };
2965 static const unsigned int msiof3_clk_d_pins[] = {
2966 /* SCK */
2967 RCAR_GP_PIN(1, 22),
2968 };
2969 static const unsigned int msiof3_clk_d_mux[] = {
2970 MSIOF3_SCK_D_MARK,
2971 };
2972 static const unsigned int msiof3_sync_d_pins[] = {
2973 /* SYNC */
2974 RCAR_GP_PIN(1, 23),
2975 };
2976 static const unsigned int msiof3_sync_d_mux[] = {
2977 MSIOF3_SYNC_D_MARK,
2978 };
2979 static const unsigned int msiof3_ss1_d_pins[] = {
2980 /* SS1 */
2981 RCAR_GP_PIN(1, 26),
2982 };
2983 static const unsigned int msiof3_ss1_d_mux[] = {
2984 MSIOF3_SS1_D_MARK,
2985 };
2986 static const unsigned int msiof3_txd_d_pins[] = {
2987 /* TXD */
2988 RCAR_GP_PIN(1, 25),
2989 };
2990 static const unsigned int msiof3_txd_d_mux[] = {
2991 MSIOF3_TXD_D_MARK,
2992 };
2993 static const unsigned int msiof3_rxd_d_pins[] = {
2994 /* RXD */
2995 RCAR_GP_PIN(1, 24),
2996 };
2997 static const unsigned int msiof3_rxd_d_mux[] = {
2998 MSIOF3_RXD_D_MARK,
2999 };
3000
3001 /* - PWM0 --------------------------------------------------------------------*/
3002 static const unsigned int pwm0_pins[] = {
3003 /* PWM */
3004 RCAR_GP_PIN(2, 6),
3005 };
3006 static const unsigned int pwm0_mux[] = {
3007 PWM0_MARK,
3008 };
3009 /* - PWM1 --------------------------------------------------------------------*/
3010 static const unsigned int pwm1_a_pins[] = {
3011 /* PWM */
3012 RCAR_GP_PIN(2, 7),
3013 };
3014 static const unsigned int pwm1_a_mux[] = {
3015 PWM1_A_MARK,
3016 };
3017 static const unsigned int pwm1_b_pins[] = {
3018 /* PWM */
3019 RCAR_GP_PIN(1, 8),
3020 };
3021 static const unsigned int pwm1_b_mux[] = {
3022 PWM1_B_MARK,
3023 };
3024 /* - PWM2 --------------------------------------------------------------------*/
3025 static const unsigned int pwm2_a_pins[] = {
3026 /* PWM */
3027 RCAR_GP_PIN(2, 8),
3028 };
3029 static const unsigned int pwm2_a_mux[] = {
3030 PWM2_A_MARK,
3031 };
3032 static const unsigned int pwm2_b_pins[] = {
3033 /* PWM */
3034 RCAR_GP_PIN(1, 11),
3035 };
3036 static const unsigned int pwm2_b_mux[] = {
3037 PWM2_B_MARK,
3038 };
3039 /* - PWM3 --------------------------------------------------------------------*/
3040 static const unsigned int pwm3_a_pins[] = {
3041 /* PWM */
3042 RCAR_GP_PIN(1, 0),
3043 };
3044 static const unsigned int pwm3_a_mux[] = {
3045 PWM3_A_MARK,
3046 };
3047 static const unsigned int pwm3_b_pins[] = {
3048 /* PWM */
3049 RCAR_GP_PIN(2, 2),
3050 };
3051 static const unsigned int pwm3_b_mux[] = {
3052 PWM3_B_MARK,
3053 };
3054 /* - PWM4 --------------------------------------------------------------------*/
3055 static const unsigned int pwm4_a_pins[] = {
3056 /* PWM */
3057 RCAR_GP_PIN(1, 1),
3058 };
3059 static const unsigned int pwm4_a_mux[] = {
3060 PWM4_A_MARK,
3061 };
3062 static const unsigned int pwm4_b_pins[] = {
3063 /* PWM */
3064 RCAR_GP_PIN(2, 3),
3065 };
3066 static const unsigned int pwm4_b_mux[] = {
3067 PWM4_B_MARK,
3068 };
3069 /* - PWM5 --------------------------------------------------------------------*/
3070 static const unsigned int pwm5_a_pins[] = {
3071 /* PWM */
3072 RCAR_GP_PIN(1, 2),
3073 };
3074 static const unsigned int pwm5_a_mux[] = {
3075 PWM5_A_MARK,
3076 };
3077 static const unsigned int pwm5_b_pins[] = {
3078 /* PWM */
3079 RCAR_GP_PIN(2, 4),
3080 };
3081 static const unsigned int pwm5_b_mux[] = {
3082 PWM5_B_MARK,
3083 };
3084 /* - PWM6 --------------------------------------------------------------------*/
3085 static const unsigned int pwm6_a_pins[] = {
3086 /* PWM */
3087 RCAR_GP_PIN(1, 3),
3088 };
3089 static const unsigned int pwm6_a_mux[] = {
3090 PWM6_A_MARK,
3091 };
3092 static const unsigned int pwm6_b_pins[] = {
3093 /* PWM */
3094 RCAR_GP_PIN(2, 5),
3095 };
3096 static const unsigned int pwm6_b_mux[] = {
3097 PWM6_B_MARK,
3098 };
3099
3100 /* - SATA --------------------------------------------------------------------*/
3101 static const unsigned int sata0_devslp_a_pins[] = {
3102 /* DEVSLP */
3103 RCAR_GP_PIN(6, 16),
3104 };
3105 static const unsigned int sata0_devslp_a_mux[] = {
3106 SATA_DEVSLP_A_MARK,
3107 };
3108 static const unsigned int sata0_devslp_b_pins[] = {
3109 /* DEVSLP */
3110 RCAR_GP_PIN(4, 6),
3111 };
3112 static const unsigned int sata0_devslp_b_mux[] = {
3113 SATA_DEVSLP_B_MARK,
3114 };
3115
3116 /* - SCIF0 ------------------------------------------------------------------ */
3117 static const unsigned int scif0_data_pins[] = {
3118 /* RX, TX */
3119 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3120 };
3121 static const unsigned int scif0_data_mux[] = {
3122 RX0_MARK, TX0_MARK,
3123 };
3124 static const unsigned int scif0_clk_pins[] = {
3125 /* SCK */
3126 RCAR_GP_PIN(5, 0),
3127 };
3128 static const unsigned int scif0_clk_mux[] = {
3129 SCK0_MARK,
3130 };
3131 static const unsigned int scif0_ctrl_pins[] = {
3132 /* RTS, CTS */
3133 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3134 };
3135 static const unsigned int scif0_ctrl_mux[] = {
3136 RTS0_N_TANS_MARK, CTS0_N_MARK,
3137 };
3138 /* - SCIF1 ------------------------------------------------------------------ */
3139 static const unsigned int scif1_data_a_pins[] = {
3140 /* RX, TX */
3141 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3142 };
3143 static const unsigned int scif1_data_a_mux[] = {
3144 RX1_A_MARK, TX1_A_MARK,
3145 };
3146 static const unsigned int scif1_clk_pins[] = {
3147 /* SCK */
3148 RCAR_GP_PIN(6, 21),
3149 };
3150 static const unsigned int scif1_clk_mux[] = {
3151 SCK1_MARK,
3152 };
3153 static const unsigned int scif1_ctrl_pins[] = {
3154 /* RTS, CTS */
3155 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3156 };
3157 static const unsigned int scif1_ctrl_mux[] = {
3158 RTS1_N_TANS_MARK, CTS1_N_MARK,
3159 };
3160
3161 static const unsigned int scif1_data_b_pins[] = {
3162 /* RX, TX */
3163 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3164 };
3165 static const unsigned int scif1_data_b_mux[] = {
3166 RX1_B_MARK, TX1_B_MARK,
3167 };
3168 /* - SCIF2 ------------------------------------------------------------------ */
3169 static const unsigned int scif2_data_a_pins[] = {
3170 /* RX, TX */
3171 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3172 };
3173 static const unsigned int scif2_data_a_mux[] = {
3174 RX2_A_MARK, TX2_A_MARK,
3175 };
3176 static const unsigned int scif2_clk_pins[] = {
3177 /* SCK */
3178 RCAR_GP_PIN(5, 9),
3179 };
3180 static const unsigned int scif2_clk_mux[] = {
3181 SCK2_MARK,
3182 };
3183 static const unsigned int scif2_data_b_pins[] = {
3184 /* RX, TX */
3185 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3186 };
3187 static const unsigned int scif2_data_b_mux[] = {
3188 RX2_B_MARK, TX2_B_MARK,
3189 };
3190 /* - SCIF3 ------------------------------------------------------------------ */
3191 static const unsigned int scif3_data_a_pins[] = {
3192 /* RX, TX */
3193 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3194 };
3195 static const unsigned int scif3_data_a_mux[] = {
3196 RX3_A_MARK, TX3_A_MARK,
3197 };
3198 static const unsigned int scif3_clk_pins[] = {
3199 /* SCK */
3200 RCAR_GP_PIN(1, 22),
3201 };
3202 static const unsigned int scif3_clk_mux[] = {
3203 SCK3_MARK,
3204 };
3205 static const unsigned int scif3_ctrl_pins[] = {
3206 /* RTS, CTS */
3207 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3208 };
3209 static const unsigned int scif3_ctrl_mux[] = {
3210 RTS3_N_TANS_MARK, CTS3_N_MARK,
3211 };
3212 static const unsigned int scif3_data_b_pins[] = {
3213 /* RX, TX */
3214 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3215 };
3216 static const unsigned int scif3_data_b_mux[] = {
3217 RX3_B_MARK, TX3_B_MARK,
3218 };
3219 /* - SCIF4 ------------------------------------------------------------------ */
3220 static const unsigned int scif4_data_a_pins[] = {
3221 /* RX, TX */
3222 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3223 };
3224 static const unsigned int scif4_data_a_mux[] = {
3225 RX4_A_MARK, TX4_A_MARK,
3226 };
3227 static const unsigned int scif4_clk_a_pins[] = {
3228 /* SCK */
3229 RCAR_GP_PIN(2, 10),
3230 };
3231 static const unsigned int scif4_clk_a_mux[] = {
3232 SCK4_A_MARK,
3233 };
3234 static const unsigned int scif4_ctrl_a_pins[] = {
3235 /* RTS, CTS */
3236 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3237 };
3238 static const unsigned int scif4_ctrl_a_mux[] = {
3239 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3240 };
3241 static const unsigned int scif4_data_b_pins[] = {
3242 /* RX, TX */
3243 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3244 };
3245 static const unsigned int scif4_data_b_mux[] = {
3246 RX4_B_MARK, TX4_B_MARK,
3247 };
3248 static const unsigned int scif4_clk_b_pins[] = {
3249 /* SCK */
3250 RCAR_GP_PIN(1, 5),
3251 };
3252 static const unsigned int scif4_clk_b_mux[] = {
3253 SCK4_B_MARK,
3254 };
3255 static const unsigned int scif4_ctrl_b_pins[] = {
3256 /* RTS, CTS */
3257 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3258 };
3259 static const unsigned int scif4_ctrl_b_mux[] = {
3260 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3261 };
3262 static const unsigned int scif4_data_c_pins[] = {
3263 /* RX, TX */
3264 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3265 };
3266 static const unsigned int scif4_data_c_mux[] = {
3267 RX4_C_MARK, TX4_C_MARK,
3268 };
3269 static const unsigned int scif4_clk_c_pins[] = {
3270 /* SCK */
3271 RCAR_GP_PIN(0, 8),
3272 };
3273 static const unsigned int scif4_clk_c_mux[] = {
3274 SCK4_C_MARK,
3275 };
3276 static const unsigned int scif4_ctrl_c_pins[] = {
3277 /* RTS, CTS */
3278 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3279 };
3280 static const unsigned int scif4_ctrl_c_mux[] = {
3281 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3282 };
3283 /* - SCIF5 ------------------------------------------------------------------ */
3284 static const unsigned int scif5_data_pins[] = {
3285 /* RX, TX */
3286 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3287 };
3288 static const unsigned int scif5_data_mux[] = {
3289 RX5_MARK, TX5_MARK,
3290 };
3291 static const unsigned int scif5_clk_pins[] = {
3292 /* SCK */
3293 RCAR_GP_PIN(6, 21),
3294 };
3295 static const unsigned int scif5_clk_mux[] = {
3296 SCK5_MARK,
3297 };
3298 /* - SDHI0 ------------------------------------------------------------------ */
3299 static const unsigned int sdhi0_data1_pins[] = {
3300 /* D0 */
3301 RCAR_GP_PIN(3, 2),
3302 };
3303 static const unsigned int sdhi0_data1_mux[] = {
3304 SD0_DAT0_MARK,
3305 };
3306 static const unsigned int sdhi0_data4_pins[] = {
3307 /* D[0:3] */
3308 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3309 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3310 };
3311 static const unsigned int sdhi0_data4_mux[] = {
3312 SD0_DAT0_MARK, SD0_DAT1_MARK,
3313 SD0_DAT2_MARK, SD0_DAT3_MARK,
3314 };
3315 static const unsigned int sdhi0_ctrl_pins[] = {
3316 /* CLK, CMD */
3317 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3318 };
3319 static const unsigned int sdhi0_ctrl_mux[] = {
3320 SD0_CLK_MARK, SD0_CMD_MARK,
3321 };
3322 static const unsigned int sdhi0_cd_pins[] = {
3323 /* CD */
3324 RCAR_GP_PIN(3, 12),
3325 };
3326 static const unsigned int sdhi0_cd_mux[] = {
3327 SD0_CD_MARK,
3328 };
3329 static const unsigned int sdhi0_wp_pins[] = {
3330 /* WP */
3331 RCAR_GP_PIN(3, 13),
3332 };
3333 static const unsigned int sdhi0_wp_mux[] = {
3334 SD0_WP_MARK,
3335 };
3336 /* - SDHI1 ------------------------------------------------------------------ */
3337 static const unsigned int sdhi1_data1_pins[] = {
3338 /* D0 */
3339 RCAR_GP_PIN(3, 8),
3340 };
3341 static const unsigned int sdhi1_data1_mux[] = {
3342 SD1_DAT0_MARK,
3343 };
3344 static const unsigned int sdhi1_data4_pins[] = {
3345 /* D[0:3] */
3346 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3347 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3348 };
3349 static const unsigned int sdhi1_data4_mux[] = {
3350 SD1_DAT0_MARK, SD1_DAT1_MARK,
3351 SD1_DAT2_MARK, SD1_DAT3_MARK,
3352 };
3353 static const unsigned int sdhi1_ctrl_pins[] = {
3354 /* CLK, CMD */
3355 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3356 };
3357 static const unsigned int sdhi1_ctrl_mux[] = {
3358 SD1_CLK_MARK, SD1_CMD_MARK,
3359 };
3360 static const unsigned int sdhi1_cd_pins[] = {
3361 /* CD */
3362 RCAR_GP_PIN(3, 14),
3363 };
3364 static const unsigned int sdhi1_cd_mux[] = {
3365 SD1_CD_MARK,
3366 };
3367 static const unsigned int sdhi1_wp_pins[] = {
3368 /* WP */
3369 RCAR_GP_PIN(3, 15),
3370 };
3371 static const unsigned int sdhi1_wp_mux[] = {
3372 SD1_WP_MARK,
3373 };
3374 /* - SDHI2 ------------------------------------------------------------------ */
3375 static const unsigned int sdhi2_data1_pins[] = {
3376 /* D0 */
3377 RCAR_GP_PIN(4, 2),
3378 };
3379 static const unsigned int sdhi2_data1_mux[] = {
3380 SD2_DAT0_MARK,
3381 };
3382 static const unsigned int sdhi2_data4_pins[] = {
3383 /* D[0:3] */
3384 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3385 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3386 };
3387 static const unsigned int sdhi2_data4_mux[] = {
3388 SD2_DAT0_MARK, SD2_DAT1_MARK,
3389 SD2_DAT2_MARK, SD2_DAT3_MARK,
3390 };
3391 static const unsigned int sdhi2_data8_pins[] = {
3392 /* D[0:7] */
3393 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3394 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3395 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3396 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3397 };
3398 static const unsigned int sdhi2_data8_mux[] = {
3399 SD2_DAT0_MARK, SD2_DAT1_MARK,
3400 SD2_DAT2_MARK, SD2_DAT3_MARK,
3401 SD2_DAT4_MARK, SD2_DAT5_MARK,
3402 SD2_DAT6_MARK, SD2_DAT7_MARK,
3403 };
3404 static const unsigned int sdhi2_ctrl_pins[] = {
3405 /* CLK, CMD */
3406 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3407 };
3408 static const unsigned int sdhi2_ctrl_mux[] = {
3409 SD2_CLK_MARK, SD2_CMD_MARK,
3410 };
3411 static const unsigned int sdhi2_cd_a_pins[] = {
3412 /* CD */
3413 RCAR_GP_PIN(4, 13),
3414 };
3415 static const unsigned int sdhi2_cd_a_mux[] = {
3416 SD2_CD_A_MARK,
3417 };
3418 static const unsigned int sdhi2_cd_b_pins[] = {
3419 /* CD */
3420 RCAR_GP_PIN(5, 10),
3421 };
3422 static const unsigned int sdhi2_cd_b_mux[] = {
3423 SD2_CD_B_MARK,
3424 };
3425 static const unsigned int sdhi2_wp_a_pins[] = {
3426 /* WP */
3427 RCAR_GP_PIN(4, 14),
3428 };
3429 static const unsigned int sdhi2_wp_a_mux[] = {
3430 SD2_WP_A_MARK,
3431 };
3432 static const unsigned int sdhi2_wp_b_pins[] = {
3433 /* WP */
3434 RCAR_GP_PIN(5, 11),
3435 };
3436 static const unsigned int sdhi2_wp_b_mux[] = {
3437 SD2_WP_B_MARK,
3438 };
3439 static const unsigned int sdhi2_ds_pins[] = {
3440 /* DS */
3441 RCAR_GP_PIN(4, 6),
3442 };
3443 static const unsigned int sdhi2_ds_mux[] = {
3444 SD2_DS_MARK,
3445 };
3446 /* - SDHI3 ------------------------------------------------------------------ */
3447 static const unsigned int sdhi3_data1_pins[] = {
3448 /* D0 */
3449 RCAR_GP_PIN(4, 9),
3450 };
3451 static const unsigned int sdhi3_data1_mux[] = {
3452 SD3_DAT0_MARK,
3453 };
3454 static const unsigned int sdhi3_data4_pins[] = {
3455 /* D[0:3] */
3456 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3457 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3458 };
3459 static const unsigned int sdhi3_data4_mux[] = {
3460 SD3_DAT0_MARK, SD3_DAT1_MARK,
3461 SD3_DAT2_MARK, SD3_DAT3_MARK,
3462 };
3463 static const unsigned int sdhi3_data8_pins[] = {
3464 /* D[0:7] */
3465 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3466 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3467 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3468 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3469 };
3470 static const unsigned int sdhi3_data8_mux[] = {
3471 SD3_DAT0_MARK, SD3_DAT1_MARK,
3472 SD3_DAT2_MARK, SD3_DAT3_MARK,
3473 SD3_DAT4_MARK, SD3_DAT5_MARK,
3474 SD3_DAT6_MARK, SD3_DAT7_MARK,
3475 };
3476 static const unsigned int sdhi3_ctrl_pins[] = {
3477 /* CLK, CMD */
3478 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3479 };
3480 static const unsigned int sdhi3_ctrl_mux[] = {
3481 SD3_CLK_MARK, SD3_CMD_MARK,
3482 };
3483 static const unsigned int sdhi3_cd_pins[] = {
3484 /* CD */
3485 RCAR_GP_PIN(4, 15),
3486 };
3487 static const unsigned int sdhi3_cd_mux[] = {
3488 SD3_CD_MARK,
3489 };
3490 static const unsigned int sdhi3_wp_pins[] = {
3491 /* WP */
3492 RCAR_GP_PIN(4, 16),
3493 };
3494 static const unsigned int sdhi3_wp_mux[] = {
3495 SD3_WP_MARK,
3496 };
3497 static const unsigned int sdhi3_ds_pins[] = {
3498 /* DS */
3499 RCAR_GP_PIN(4, 17),
3500 };
3501 static const unsigned int sdhi3_ds_mux[] = {
3502 SD3_DS_MARK,
3503 };
3504
3505 /* - SCIF Clock ------------------------------------------------------------- */
3506 static const unsigned int scif_clk_a_pins[] = {
3507 /* SCIF_CLK */
3508 RCAR_GP_PIN(6, 23),
3509 };
3510 static const unsigned int scif_clk_a_mux[] = {
3511 SCIF_CLK_A_MARK,
3512 };
3513 static const unsigned int scif_clk_b_pins[] = {
3514 /* SCIF_CLK */
3515 RCAR_GP_PIN(5, 9),
3516 };
3517 static const unsigned int scif_clk_b_mux[] = {
3518 SCIF_CLK_B_MARK,
3519 };
3520
3521 /* - SSI -------------------------------------------------------------------- */
3522 static const unsigned int ssi0_data_pins[] = {
3523 /* SDATA */
3524 RCAR_GP_PIN(6, 2),
3525 };
3526 static const unsigned int ssi0_data_mux[] = {
3527 SSI_SDATA0_MARK,
3528 };
3529 static const unsigned int ssi01239_ctrl_pins[] = {
3530 /* SCK, WS */
3531 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3532 };
3533 static const unsigned int ssi01239_ctrl_mux[] = {
3534 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3535 };
3536 static const unsigned int ssi1_data_a_pins[] = {
3537 /* SDATA */
3538 RCAR_GP_PIN(6, 3),
3539 };
3540 static const unsigned int ssi1_data_a_mux[] = {
3541 SSI_SDATA1_A_MARK,
3542 };
3543 static const unsigned int ssi1_data_b_pins[] = {
3544 /* SDATA */
3545 RCAR_GP_PIN(5, 12),
3546 };
3547 static const unsigned int ssi1_data_b_mux[] = {
3548 SSI_SDATA1_B_MARK,
3549 };
3550 static const unsigned int ssi1_ctrl_a_pins[] = {
3551 /* SCK, WS */
3552 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3553 };
3554 static const unsigned int ssi1_ctrl_a_mux[] = {
3555 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3556 };
3557 static const unsigned int ssi1_ctrl_b_pins[] = {
3558 /* SCK, WS */
3559 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3560 };
3561 static const unsigned int ssi1_ctrl_b_mux[] = {
3562 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3563 };
3564 static const unsigned int ssi2_data_a_pins[] = {
3565 /* SDATA */
3566 RCAR_GP_PIN(6, 4),
3567 };
3568 static const unsigned int ssi2_data_a_mux[] = {
3569 SSI_SDATA2_A_MARK,
3570 };
3571 static const unsigned int ssi2_data_b_pins[] = {
3572 /* SDATA */
3573 RCAR_GP_PIN(5, 13),
3574 };
3575 static const unsigned int ssi2_data_b_mux[] = {
3576 SSI_SDATA2_B_MARK,
3577 };
3578 static const unsigned int ssi2_ctrl_a_pins[] = {
3579 /* SCK, WS */
3580 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3581 };
3582 static const unsigned int ssi2_ctrl_a_mux[] = {
3583 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3584 };
3585 static const unsigned int ssi2_ctrl_b_pins[] = {
3586 /* SCK, WS */
3587 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3588 };
3589 static const unsigned int ssi2_ctrl_b_mux[] = {
3590 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3591 };
3592 static const unsigned int ssi3_data_pins[] = {
3593 /* SDATA */
3594 RCAR_GP_PIN(6, 7),
3595 };
3596 static const unsigned int ssi3_data_mux[] = {
3597 SSI_SDATA3_MARK,
3598 };
3599 static const unsigned int ssi34_ctrl_pins[] = {
3600 /* SCK, WS */
3601 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3602 };
3603 static const unsigned int ssi34_ctrl_mux[] = {
3604 SSI_SCK34_MARK, SSI_WS34_MARK,
3605 };
3606 static const unsigned int ssi4_data_pins[] = {
3607 /* SDATA */
3608 RCAR_GP_PIN(6, 10),
3609 };
3610 static const unsigned int ssi4_data_mux[] = {
3611 SSI_SDATA4_MARK,
3612 };
3613 static const unsigned int ssi4_ctrl_pins[] = {
3614 /* SCK, WS */
3615 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3616 };
3617 static const unsigned int ssi4_ctrl_mux[] = {
3618 SSI_SCK4_MARK, SSI_WS4_MARK,
3619 };
3620 static const unsigned int ssi5_data_pins[] = {
3621 /* SDATA */
3622 RCAR_GP_PIN(6, 13),
3623 };
3624 static const unsigned int ssi5_data_mux[] = {
3625 SSI_SDATA5_MARK,
3626 };
3627 static const unsigned int ssi5_ctrl_pins[] = {
3628 /* SCK, WS */
3629 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3630 };
3631 static const unsigned int ssi5_ctrl_mux[] = {
3632 SSI_SCK5_MARK, SSI_WS5_MARK,
3633 };
3634 static const unsigned int ssi6_data_pins[] = {
3635 /* SDATA */
3636 RCAR_GP_PIN(6, 16),
3637 };
3638 static const unsigned int ssi6_data_mux[] = {
3639 SSI_SDATA6_MARK,
3640 };
3641 static const unsigned int ssi6_ctrl_pins[] = {
3642 /* SCK, WS */
3643 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3644 };
3645 static const unsigned int ssi6_ctrl_mux[] = {
3646 SSI_SCK6_MARK, SSI_WS6_MARK,
3647 };
3648 static const unsigned int ssi7_data_pins[] = {
3649 /* SDATA */
3650 RCAR_GP_PIN(6, 19),
3651 };
3652 static const unsigned int ssi7_data_mux[] = {
3653 SSI_SDATA7_MARK,
3654 };
3655 static const unsigned int ssi78_ctrl_pins[] = {
3656 /* SCK, WS */
3657 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3658 };
3659 static const unsigned int ssi78_ctrl_mux[] = {
3660 SSI_SCK78_MARK, SSI_WS78_MARK,
3661 };
3662 static const unsigned int ssi8_data_pins[] = {
3663 /* SDATA */
3664 RCAR_GP_PIN(6, 20),
3665 };
3666 static const unsigned int ssi8_data_mux[] = {
3667 SSI_SDATA8_MARK,
3668 };
3669 static const unsigned int ssi9_data_a_pins[] = {
3670 /* SDATA */
3671 RCAR_GP_PIN(6, 21),
3672 };
3673 static const unsigned int ssi9_data_a_mux[] = {
3674 SSI_SDATA9_A_MARK,
3675 };
3676 static const unsigned int ssi9_data_b_pins[] = {
3677 /* SDATA */
3678 RCAR_GP_PIN(5, 14),
3679 };
3680 static const unsigned int ssi9_data_b_mux[] = {
3681 SSI_SDATA9_B_MARK,
3682 };
3683 static const unsigned int ssi9_ctrl_a_pins[] = {
3684 /* SCK, WS */
3685 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3686 };
3687 static const unsigned int ssi9_ctrl_a_mux[] = {
3688 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3689 };
3690 static const unsigned int ssi9_ctrl_b_pins[] = {
3691 /* SCK, WS */
3692 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3693 };
3694 static const unsigned int ssi9_ctrl_b_mux[] = {
3695 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3696 };
3697
3698 /* - USB0 ------------------------------------------------------------------- */
3699 static const unsigned int usb0_pins[] = {
3700 /* PWEN, OVC */
3701 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3702 };
3703 static const unsigned int usb0_mux[] = {
3704 USB0_PWEN_MARK, USB0_OVC_MARK,
3705 };
3706 /* - USB1 ------------------------------------------------------------------- */
3707 static const unsigned int usb1_pins[] = {
3708 /* PWEN, OVC */
3709 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3710 };
3711 static const unsigned int usb1_mux[] = {
3712 USB1_PWEN_MARK, USB1_OVC_MARK,
3713 };
3714 /* - USB2 ------------------------------------------------------------------- */
3715 static const unsigned int usb2_pins[] = {
3716 /* PWEN, OVC */
3717 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3718 };
3719 static const unsigned int usb2_mux[] = {
3720 USB2_PWEN_MARK, USB2_OVC_MARK,
3721 };
3722
3723 /* - QSPI0 ------------------------------------------------------------------ */
3724 static const unsigned int qspi0_ctrl_pins[] = {
3725 /* QSPI0_SPCLK, QSPI0_SSL */
3726 PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3),
3727 };
3728 static const unsigned int qspi0_ctrl_mux[] = {
3729 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3730 };
3731 static const unsigned int qspi0_data2_pins[] = {
3732 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3733 PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
3734 };
3735 static const unsigned int qspi0_data2_mux[] = {
3736 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3737 };
3738 static const unsigned int qspi0_data4_pins[] = {
3739 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
3740 PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
3741 PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6),
3742 };
3743 static const unsigned int qspi0_data4_mux[] = {
3744 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3745 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3746 };
3747 /* - QSPI1 ------------------------------------------------------------------ */
3748 static const unsigned int qspi1_ctrl_pins[] = {
3749 /* QSPI1_SPCLK, QSPI1_SSL */
3750 PIN_NUMBER('V', 3), PIN_NUMBER('V', 5),
3751 };
3752 static const unsigned int qspi1_ctrl_mux[] = {
3753 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3754 };
3755 static const unsigned int qspi1_data2_pins[] = {
3756 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3757 PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
3758 };
3759 static const unsigned int qspi1_data2_mux[] = {
3760 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3761 };
3762 static const unsigned int qspi1_data4_pins[] = {
3763 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
3764 PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
3765 PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3),
3766 };
3767 static const unsigned int qspi1_data4_mux[] = {
3768 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3769 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3770 };
3771
3772 static const struct sh_pfc_pin_group pinmux_groups[] = {
3773 SH_PFC_PIN_GROUP(audio_clk_a_a),
3774 SH_PFC_PIN_GROUP(audio_clk_a_b),
3775 SH_PFC_PIN_GROUP(audio_clk_a_c),
3776 SH_PFC_PIN_GROUP(audio_clk_b_a),
3777 SH_PFC_PIN_GROUP(audio_clk_b_b),
3778 SH_PFC_PIN_GROUP(audio_clk_c_a),
3779 SH_PFC_PIN_GROUP(audio_clk_c_b),
3780 SH_PFC_PIN_GROUP(audio_clkout_a),
3781 SH_PFC_PIN_GROUP(audio_clkout_b),
3782 SH_PFC_PIN_GROUP(audio_clkout_c),
3783 SH_PFC_PIN_GROUP(audio_clkout_d),
3784 SH_PFC_PIN_GROUP(audio_clkout1_a),
3785 SH_PFC_PIN_GROUP(audio_clkout1_b),
3786 SH_PFC_PIN_GROUP(audio_clkout2_a),
3787 SH_PFC_PIN_GROUP(audio_clkout2_b),
3788 SH_PFC_PIN_GROUP(audio_clkout3_a),
3789 SH_PFC_PIN_GROUP(audio_clkout3_b),
3790 SH_PFC_PIN_GROUP(avb_link),
3791 SH_PFC_PIN_GROUP(avb_magic),
3792 SH_PFC_PIN_GROUP(avb_phy_int),
3793 SH_PFC_PIN_GROUP(avb_mdc),
3794 SH_PFC_PIN_GROUP(avb_mii),
3795 SH_PFC_PIN_GROUP(avb_avtp_pps),
3796 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3797 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3798 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3799 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3800 SH_PFC_PIN_GROUP(can0_data_a),
3801 SH_PFC_PIN_GROUP(can0_data_b),
3802 SH_PFC_PIN_GROUP(can1_data),
3803 SH_PFC_PIN_GROUP(can_clk),
3804 SH_PFC_PIN_GROUP(canfd0_data_a),
3805 SH_PFC_PIN_GROUP(canfd0_data_b),
3806 SH_PFC_PIN_GROUP(canfd1_data),
3807 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3808 SH_PFC_PIN_GROUP(drif0_data0_a),
3809 SH_PFC_PIN_GROUP(drif0_data1_a),
3810 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3811 SH_PFC_PIN_GROUP(drif0_data0_b),
3812 SH_PFC_PIN_GROUP(drif0_data1_b),
3813 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3814 SH_PFC_PIN_GROUP(drif0_data0_c),
3815 SH_PFC_PIN_GROUP(drif0_data1_c),
3816 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3817 SH_PFC_PIN_GROUP(drif1_data0_a),
3818 SH_PFC_PIN_GROUP(drif1_data1_a),
3819 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3820 SH_PFC_PIN_GROUP(drif1_data0_b),
3821 SH_PFC_PIN_GROUP(drif1_data1_b),
3822 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3823 SH_PFC_PIN_GROUP(drif1_data0_c),
3824 SH_PFC_PIN_GROUP(drif1_data1_c),
3825 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3826 SH_PFC_PIN_GROUP(drif2_data0_a),
3827 SH_PFC_PIN_GROUP(drif2_data1_a),
3828 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3829 SH_PFC_PIN_GROUP(drif2_data0_b),
3830 SH_PFC_PIN_GROUP(drif2_data1_b),
3831 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3832 SH_PFC_PIN_GROUP(drif3_data0_a),
3833 SH_PFC_PIN_GROUP(drif3_data1_a),
3834 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3835 SH_PFC_PIN_GROUP(drif3_data0_b),
3836 SH_PFC_PIN_GROUP(drif3_data1_b),
3837 SH_PFC_PIN_GROUP(du_rgb666),
3838 SH_PFC_PIN_GROUP(du_rgb888),
3839 SH_PFC_PIN_GROUP(du_clk_out_0),
3840 SH_PFC_PIN_GROUP(du_clk_out_1),
3841 SH_PFC_PIN_GROUP(du_sync),
3842 SH_PFC_PIN_GROUP(du_oddf),
3843 SH_PFC_PIN_GROUP(du_cde),
3844 SH_PFC_PIN_GROUP(du_disp),
3845 SH_PFC_PIN_GROUP(hscif0_data),
3846 SH_PFC_PIN_GROUP(hscif0_clk),
3847 SH_PFC_PIN_GROUP(hscif0_ctrl),
3848 SH_PFC_PIN_GROUP(hscif1_data_a),
3849 SH_PFC_PIN_GROUP(hscif1_clk_a),
3850 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3851 SH_PFC_PIN_GROUP(hscif1_data_b),
3852 SH_PFC_PIN_GROUP(hscif1_clk_b),
3853 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3854 SH_PFC_PIN_GROUP(hscif2_data_a),
3855 SH_PFC_PIN_GROUP(hscif2_clk_a),
3856 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3857 SH_PFC_PIN_GROUP(hscif2_data_b),
3858 SH_PFC_PIN_GROUP(hscif2_clk_b),
3859 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3860 SH_PFC_PIN_GROUP(hscif3_data_a),
3861 SH_PFC_PIN_GROUP(hscif3_clk),
3862 SH_PFC_PIN_GROUP(hscif3_ctrl),
3863 SH_PFC_PIN_GROUP(hscif3_data_b),
3864 SH_PFC_PIN_GROUP(hscif3_data_c),
3865 SH_PFC_PIN_GROUP(hscif3_data_d),
3866 SH_PFC_PIN_GROUP(hscif4_data_a),
3867 SH_PFC_PIN_GROUP(hscif4_clk),
3868 SH_PFC_PIN_GROUP(hscif4_ctrl),
3869 SH_PFC_PIN_GROUP(hscif4_data_b),
3870 SH_PFC_PIN_GROUP(i2c1_a),
3871 SH_PFC_PIN_GROUP(i2c1_b),
3872 SH_PFC_PIN_GROUP(i2c2_a),
3873 SH_PFC_PIN_GROUP(i2c2_b),
3874 SH_PFC_PIN_GROUP(i2c6_a),
3875 SH_PFC_PIN_GROUP(i2c6_b),
3876 SH_PFC_PIN_GROUP(i2c6_c),
3877 SH_PFC_PIN_GROUP(intc_ex_irq0),
3878 SH_PFC_PIN_GROUP(intc_ex_irq1),
3879 SH_PFC_PIN_GROUP(intc_ex_irq2),
3880 SH_PFC_PIN_GROUP(intc_ex_irq3),
3881 SH_PFC_PIN_GROUP(intc_ex_irq4),
3882 SH_PFC_PIN_GROUP(intc_ex_irq5),
3883 SH_PFC_PIN_GROUP(msiof0_clk),
3884 SH_PFC_PIN_GROUP(msiof0_sync),
3885 SH_PFC_PIN_GROUP(msiof0_ss1),
3886 SH_PFC_PIN_GROUP(msiof0_ss2),
3887 SH_PFC_PIN_GROUP(msiof0_txd),
3888 SH_PFC_PIN_GROUP(msiof0_rxd),
3889 SH_PFC_PIN_GROUP(msiof1_clk_a),
3890 SH_PFC_PIN_GROUP(msiof1_sync_a),
3891 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3892 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3893 SH_PFC_PIN_GROUP(msiof1_txd_a),
3894 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3895 SH_PFC_PIN_GROUP(msiof1_clk_b),
3896 SH_PFC_PIN_GROUP(msiof1_sync_b),
3897 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3898 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3899 SH_PFC_PIN_GROUP(msiof1_txd_b),
3900 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3901 SH_PFC_PIN_GROUP(msiof1_clk_c),
3902 SH_PFC_PIN_GROUP(msiof1_sync_c),
3903 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3904 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3905 SH_PFC_PIN_GROUP(msiof1_txd_c),
3906 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3907 SH_PFC_PIN_GROUP(msiof1_clk_d),
3908 SH_PFC_PIN_GROUP(msiof1_sync_d),
3909 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3910 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3911 SH_PFC_PIN_GROUP(msiof1_txd_d),
3912 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3913 SH_PFC_PIN_GROUP(msiof1_clk_e),
3914 SH_PFC_PIN_GROUP(msiof1_sync_e),
3915 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3916 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3917 SH_PFC_PIN_GROUP(msiof1_txd_e),
3918 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3919 SH_PFC_PIN_GROUP(msiof1_clk_f),
3920 SH_PFC_PIN_GROUP(msiof1_sync_f),
3921 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3922 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3923 SH_PFC_PIN_GROUP(msiof1_txd_f),
3924 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3925 SH_PFC_PIN_GROUP(msiof1_clk_g),
3926 SH_PFC_PIN_GROUP(msiof1_sync_g),
3927 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3928 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3929 SH_PFC_PIN_GROUP(msiof1_txd_g),
3930 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3931 SH_PFC_PIN_GROUP(msiof2_clk_a),
3932 SH_PFC_PIN_GROUP(msiof2_sync_a),
3933 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3934 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3935 SH_PFC_PIN_GROUP(msiof2_txd_a),
3936 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3937 SH_PFC_PIN_GROUP(msiof2_clk_b),
3938 SH_PFC_PIN_GROUP(msiof2_sync_b),
3939 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3940 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3941 SH_PFC_PIN_GROUP(msiof2_txd_b),
3942 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3943 SH_PFC_PIN_GROUP(msiof2_clk_c),
3944 SH_PFC_PIN_GROUP(msiof2_sync_c),
3945 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3946 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3947 SH_PFC_PIN_GROUP(msiof2_txd_c),
3948 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3949 SH_PFC_PIN_GROUP(msiof2_clk_d),
3950 SH_PFC_PIN_GROUP(msiof2_sync_d),
3951 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3952 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3953 SH_PFC_PIN_GROUP(msiof2_txd_d),
3954 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3955 SH_PFC_PIN_GROUP(msiof3_clk_a),
3956 SH_PFC_PIN_GROUP(msiof3_sync_a),
3957 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3958 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3959 SH_PFC_PIN_GROUP(msiof3_txd_a),
3960 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3961 SH_PFC_PIN_GROUP(msiof3_clk_b),
3962 SH_PFC_PIN_GROUP(msiof3_sync_b),
3963 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3964 SH_PFC_PIN_GROUP(msiof3_ss2_b),
3965 SH_PFC_PIN_GROUP(msiof3_txd_b),
3966 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3967 SH_PFC_PIN_GROUP(msiof3_clk_c),
3968 SH_PFC_PIN_GROUP(msiof3_sync_c),
3969 SH_PFC_PIN_GROUP(msiof3_txd_c),
3970 SH_PFC_PIN_GROUP(msiof3_rxd_c),
3971 SH_PFC_PIN_GROUP(msiof3_clk_d),
3972 SH_PFC_PIN_GROUP(msiof3_sync_d),
3973 SH_PFC_PIN_GROUP(msiof3_ss1_d),
3974 SH_PFC_PIN_GROUP(msiof3_txd_d),
3975 SH_PFC_PIN_GROUP(msiof3_rxd_d),
3976 SH_PFC_PIN_GROUP(pwm0),
3977 SH_PFC_PIN_GROUP(pwm1_a),
3978 SH_PFC_PIN_GROUP(pwm1_b),
3979 SH_PFC_PIN_GROUP(pwm2_a),
3980 SH_PFC_PIN_GROUP(pwm2_b),
3981 SH_PFC_PIN_GROUP(pwm3_a),
3982 SH_PFC_PIN_GROUP(pwm3_b),
3983 SH_PFC_PIN_GROUP(pwm4_a),
3984 SH_PFC_PIN_GROUP(pwm4_b),
3985 SH_PFC_PIN_GROUP(pwm5_a),
3986 SH_PFC_PIN_GROUP(pwm5_b),
3987 SH_PFC_PIN_GROUP(pwm6_a),
3988 SH_PFC_PIN_GROUP(pwm6_b),
3989 SH_PFC_PIN_GROUP(sata0_devslp_a),
3990 SH_PFC_PIN_GROUP(sata0_devslp_b),
3991 SH_PFC_PIN_GROUP(scif0_data),
3992 SH_PFC_PIN_GROUP(scif0_clk),
3993 SH_PFC_PIN_GROUP(scif0_ctrl),
3994 SH_PFC_PIN_GROUP(scif1_data_a),
3995 SH_PFC_PIN_GROUP(scif1_clk),
3996 SH_PFC_PIN_GROUP(scif1_ctrl),
3997 SH_PFC_PIN_GROUP(scif1_data_b),
3998 SH_PFC_PIN_GROUP(scif2_data_a),
3999 SH_PFC_PIN_GROUP(scif2_clk),
4000 SH_PFC_PIN_GROUP(scif2_data_b),
4001 SH_PFC_PIN_GROUP(scif3_data_a),
4002 SH_PFC_PIN_GROUP(scif3_clk),
4003 SH_PFC_PIN_GROUP(scif3_ctrl),
4004 SH_PFC_PIN_GROUP(scif3_data_b),
4005 SH_PFC_PIN_GROUP(scif4_data_a),
4006 SH_PFC_PIN_GROUP(scif4_clk_a),
4007 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4008 SH_PFC_PIN_GROUP(scif4_data_b),
4009 SH_PFC_PIN_GROUP(scif4_clk_b),
4010 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4011 SH_PFC_PIN_GROUP(scif4_data_c),
4012 SH_PFC_PIN_GROUP(scif4_clk_c),
4013 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4014 SH_PFC_PIN_GROUP(scif5_data),
4015 SH_PFC_PIN_GROUP(scif5_clk),
4016 SH_PFC_PIN_GROUP(scif_clk_a),
4017 SH_PFC_PIN_GROUP(scif_clk_b),
4018 SH_PFC_PIN_GROUP(sdhi0_data1),
4019 SH_PFC_PIN_GROUP(sdhi0_data4),
4020 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4021 SH_PFC_PIN_GROUP(sdhi0_cd),
4022 SH_PFC_PIN_GROUP(sdhi0_wp),
4023 SH_PFC_PIN_GROUP(sdhi1_data1),
4024 SH_PFC_PIN_GROUP(sdhi1_data4),
4025 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4026 SH_PFC_PIN_GROUP(sdhi1_cd),
4027 SH_PFC_PIN_GROUP(sdhi1_wp),
4028 SH_PFC_PIN_GROUP(sdhi2_data1),
4029 SH_PFC_PIN_GROUP(sdhi2_data4),
4030 SH_PFC_PIN_GROUP(sdhi2_data8),
4031 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4032 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4033 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4034 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4035 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4036 SH_PFC_PIN_GROUP(sdhi2_ds),
4037 SH_PFC_PIN_GROUP(sdhi3_data1),
4038 SH_PFC_PIN_GROUP(sdhi3_data4),
4039 SH_PFC_PIN_GROUP(sdhi3_data8),
4040 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4041 SH_PFC_PIN_GROUP(sdhi3_cd),
4042 SH_PFC_PIN_GROUP(sdhi3_wp),
4043 SH_PFC_PIN_GROUP(sdhi3_ds),
4044 SH_PFC_PIN_GROUP(ssi0_data),
4045 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4046 SH_PFC_PIN_GROUP(ssi1_data_a),
4047 SH_PFC_PIN_GROUP(ssi1_data_b),
4048 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4049 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4050 SH_PFC_PIN_GROUP(ssi2_data_a),
4051 SH_PFC_PIN_GROUP(ssi2_data_b),
4052 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4053 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4054 SH_PFC_PIN_GROUP(ssi3_data),
4055 SH_PFC_PIN_GROUP(ssi34_ctrl),
4056 SH_PFC_PIN_GROUP(ssi4_data),
4057 SH_PFC_PIN_GROUP(ssi4_ctrl),
4058 SH_PFC_PIN_GROUP(ssi5_data),
4059 SH_PFC_PIN_GROUP(ssi5_ctrl),
4060 SH_PFC_PIN_GROUP(ssi6_data),
4061 SH_PFC_PIN_GROUP(ssi6_ctrl),
4062 SH_PFC_PIN_GROUP(ssi7_data),
4063 SH_PFC_PIN_GROUP(ssi78_ctrl),
4064 SH_PFC_PIN_GROUP(ssi8_data),
4065 SH_PFC_PIN_GROUP(ssi9_data_a),
4066 SH_PFC_PIN_GROUP(ssi9_data_b),
4067 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4068 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4069 SH_PFC_PIN_GROUP(usb0),
4070 SH_PFC_PIN_GROUP(usb1),
4071 SH_PFC_PIN_GROUP(usb2),
4072 SH_PFC_PIN_GROUP(qspi0_ctrl),
4073 SH_PFC_PIN_GROUP(qspi0_data2),
4074 SH_PFC_PIN_GROUP(qspi0_data4),
4075 SH_PFC_PIN_GROUP(qspi1_ctrl),
4076 SH_PFC_PIN_GROUP(qspi1_data2),
4077 SH_PFC_PIN_GROUP(qspi1_data4),
4078 };
4079
4080 static const char * const audio_clk_groups[] = {
4081 "audio_clk_a_a",
4082 "audio_clk_a_b",
4083 "audio_clk_a_c",
4084 "audio_clk_b_a",
4085 "audio_clk_b_b",
4086 "audio_clk_c_a",
4087 "audio_clk_c_b",
4088 "audio_clkout_a",
4089 "audio_clkout_b",
4090 "audio_clkout_c",
4091 "audio_clkout_d",
4092 "audio_clkout1_a",
4093 "audio_clkout1_b",
4094 "audio_clkout2_a",
4095 "audio_clkout2_b",
4096 "audio_clkout3_a",
4097 "audio_clkout3_b",
4098 };
4099
4100 static const char * const avb_groups[] = {
4101 "avb_link",
4102 "avb_magic",
4103 "avb_phy_int",
4104 "avb_mdc",
4105 "avb_mii",
4106 "avb_avtp_pps",
4107 "avb_avtp_match_a",
4108 "avb_avtp_capture_a",
4109 "avb_avtp_match_b",
4110 "avb_avtp_capture_b",
4111 };
4112
4113 static const char * const can0_groups[] = {
4114 "can0_data_a",
4115 "can0_data_b",
4116 };
4117
4118 static const char * const can1_groups[] = {
4119 "can1_data",
4120 };
4121
4122 static const char * const can_clk_groups[] = {
4123 "can_clk",
4124 };
4125
4126 static const char * const canfd0_groups[] = {
4127 "canfd0_data_a",
4128 "canfd0_data_b",
4129 };
4130
4131 static const char * const canfd1_groups[] = {
4132 "canfd1_data",
4133 };
4134
4135 static const char * const drif0_groups[] = {
4136 "drif0_ctrl_a",
4137 "drif0_data0_a",
4138 "drif0_data1_a",
4139 "drif0_ctrl_b",
4140 "drif0_data0_b",
4141 "drif0_data1_b",
4142 "drif0_ctrl_c",
4143 "drif0_data0_c",
4144 "drif0_data1_c",
4145 };
4146
4147 static const char * const drif1_groups[] = {
4148 "drif1_ctrl_a",
4149 "drif1_data0_a",
4150 "drif1_data1_a",
4151 "drif1_ctrl_b",
4152 "drif1_data0_b",
4153 "drif1_data1_b",
4154 "drif1_ctrl_c",
4155 "drif1_data0_c",
4156 "drif1_data1_c",
4157 };
4158
4159 static const char * const drif2_groups[] = {
4160 "drif2_ctrl_a",
4161 "drif2_data0_a",
4162 "drif2_data1_a",
4163 "drif2_ctrl_b",
4164 "drif2_data0_b",
4165 "drif2_data1_b",
4166 };
4167
4168 static const char * const drif3_groups[] = {
4169 "drif3_ctrl_a",
4170 "drif3_data0_a",
4171 "drif3_data1_a",
4172 "drif3_ctrl_b",
4173 "drif3_data0_b",
4174 "drif3_data1_b",
4175 };
4176
4177 static const char * const du_groups[] = {
4178 "du_rgb666",
4179 "du_rgb888",
4180 "du_clk_out_0",
4181 "du_clk_out_1",
4182 "du_sync",
4183 "du_oddf",
4184 "du_cde",
4185 "du_disp",
4186 };
4187
4188 static const char * const hscif0_groups[] = {
4189 "hscif0_data",
4190 "hscif0_clk",
4191 "hscif0_ctrl",
4192 };
4193
4194 static const char * const hscif1_groups[] = {
4195 "hscif1_data_a",
4196 "hscif1_clk_a",
4197 "hscif1_ctrl_a",
4198 "hscif1_data_b",
4199 "hscif1_clk_b",
4200 "hscif1_ctrl_b",
4201 };
4202
4203 static const char * const hscif2_groups[] = {
4204 "hscif2_data_a",
4205 "hscif2_clk_a",
4206 "hscif2_ctrl_a",
4207 "hscif2_data_b",
4208 "hscif2_clk_b",
4209 "hscif2_ctrl_b",
4210 };
4211
4212 static const char * const hscif3_groups[] = {
4213 "hscif3_data_a",
4214 "hscif3_clk",
4215 "hscif3_ctrl",
4216 "hscif3_data_b",
4217 "hscif3_data_c",
4218 "hscif3_data_d",
4219 };
4220
4221 static const char * const hscif4_groups[] = {
4222 "hscif4_data_a",
4223 "hscif4_clk",
4224 "hscif4_ctrl",
4225 "hscif4_data_b",
4226 };
4227
4228 static const char * const i2c1_groups[] = {
4229 "i2c1_a",
4230 "i2c1_b",
4231 };
4232
4233 static const char * const i2c2_groups[] = {
4234 "i2c2_a",
4235 "i2c2_b",
4236 };
4237
4238 static const char * const i2c6_groups[] = {
4239 "i2c6_a",
4240 "i2c6_b",
4241 "i2c6_c",
4242 };
4243
4244 static const char * const intc_ex_groups[] = {
4245 "intc_ex_irq0",
4246 "intc_ex_irq1",
4247 "intc_ex_irq2",
4248 "intc_ex_irq3",
4249 "intc_ex_irq4",
4250 "intc_ex_irq5",
4251 };
4252
4253 static const char * const msiof0_groups[] = {
4254 "msiof0_clk",
4255 "msiof0_sync",
4256 "msiof0_ss1",
4257 "msiof0_ss2",
4258 "msiof0_txd",
4259 "msiof0_rxd",
4260 };
4261
4262 static const char * const msiof1_groups[] = {
4263 "msiof1_clk_a",
4264 "msiof1_sync_a",
4265 "msiof1_ss1_a",
4266 "msiof1_ss2_a",
4267 "msiof1_txd_a",
4268 "msiof1_rxd_a",
4269 "msiof1_clk_b",
4270 "msiof1_sync_b",
4271 "msiof1_ss1_b",
4272 "msiof1_ss2_b",
4273 "msiof1_txd_b",
4274 "msiof1_rxd_b",
4275 "msiof1_clk_c",
4276 "msiof1_sync_c",
4277 "msiof1_ss1_c",
4278 "msiof1_ss2_c",
4279 "msiof1_txd_c",
4280 "msiof1_rxd_c",
4281 "msiof1_clk_d",
4282 "msiof1_sync_d",
4283 "msiof1_ss1_d",
4284 "msiof1_ss2_d",
4285 "msiof1_txd_d",
4286 "msiof1_rxd_d",
4287 "msiof1_clk_e",
4288 "msiof1_sync_e",
4289 "msiof1_ss1_e",
4290 "msiof1_ss2_e",
4291 "msiof1_txd_e",
4292 "msiof1_rxd_e",
4293 "msiof1_clk_f",
4294 "msiof1_sync_f",
4295 "msiof1_ss1_f",
4296 "msiof1_ss2_f",
4297 "msiof1_txd_f",
4298 "msiof1_rxd_f",
4299 "msiof1_clk_g",
4300 "msiof1_sync_g",
4301 "msiof1_ss1_g",
4302 "msiof1_ss2_g",
4303 "msiof1_txd_g",
4304 "msiof1_rxd_g",
4305 };
4306
4307 static const char * const msiof2_groups[] = {
4308 "msiof2_clk_a",
4309 "msiof2_sync_a",
4310 "msiof2_ss1_a",
4311 "msiof2_ss2_a",
4312 "msiof2_txd_a",
4313 "msiof2_rxd_a",
4314 "msiof2_clk_b",
4315 "msiof2_sync_b",
4316 "msiof2_ss1_b",
4317 "msiof2_ss2_b",
4318 "msiof2_txd_b",
4319 "msiof2_rxd_b",
4320 "msiof2_clk_c",
4321 "msiof2_sync_c",
4322 "msiof2_ss1_c",
4323 "msiof2_ss2_c",
4324 "msiof2_txd_c",
4325 "msiof2_rxd_c",
4326 "msiof2_clk_d",
4327 "msiof2_sync_d",
4328 "msiof2_ss1_d",
4329 "msiof2_ss2_d",
4330 "msiof2_txd_d",
4331 "msiof2_rxd_d",
4332 };
4333
4334 static const char * const msiof3_groups[] = {
4335 "msiof3_clk_a",
4336 "msiof3_sync_a",
4337 "msiof3_ss1_a",
4338 "msiof3_ss2_a",
4339 "msiof3_txd_a",
4340 "msiof3_rxd_a",
4341 "msiof3_clk_b",
4342 "msiof3_sync_b",
4343 "msiof3_ss1_b",
4344 "msiof3_ss2_b",
4345 "msiof3_txd_b",
4346 "msiof3_rxd_b",
4347 "msiof3_clk_c",
4348 "msiof3_sync_c",
4349 "msiof3_txd_c",
4350 "msiof3_rxd_c",
4351 "msiof3_clk_d",
4352 "msiof3_sync_d",
4353 "msiof3_ss1_d",
4354 "msiof3_txd_d",
4355 "msiof3_rxd_d",
4356 };
4357
4358 static const char * const pwm0_groups[] = {
4359 "pwm0",
4360 };
4361
4362 static const char * const pwm1_groups[] = {
4363 "pwm1_a",
4364 "pwm1_b",
4365 };
4366
4367 static const char * const pwm2_groups[] = {
4368 "pwm2_a",
4369 "pwm2_b",
4370 };
4371
4372 static const char * const pwm3_groups[] = {
4373 "pwm3_a",
4374 "pwm3_b",
4375 };
4376
4377 static const char * const pwm4_groups[] = {
4378 "pwm4_a",
4379 "pwm4_b",
4380 };
4381
4382 static const char * const pwm5_groups[] = {
4383 "pwm5_a",
4384 "pwm5_b",
4385 };
4386
4387 static const char * const pwm6_groups[] = {
4388 "pwm6_a",
4389 "pwm6_b",
4390 };
4391
4392 static const char * const sata0_groups[] = {
4393 "sata0_devslp_a",
4394 "sata0_devslp_b",
4395 };
4396
4397 static const char * const scif0_groups[] = {
4398 "scif0_data",
4399 "scif0_clk",
4400 "scif0_ctrl",
4401 };
4402
4403 static const char * const scif1_groups[] = {
4404 "scif1_data_a",
4405 "scif1_clk",
4406 "scif1_ctrl",
4407 "scif1_data_b",
4408 };
4409
4410 static const char * const scif2_groups[] = {
4411 "scif2_data_a",
4412 "scif2_clk",
4413 "scif2_data_b",
4414 };
4415
4416 static const char * const scif3_groups[] = {
4417 "scif3_data_a",
4418 "scif3_clk",
4419 "scif3_ctrl",
4420 "scif3_data_b",
4421 };
4422
4423 static const char * const scif4_groups[] = {
4424 "scif4_data_a",
4425 "scif4_clk_a",
4426 "scif4_ctrl_a",
4427 "scif4_data_b",
4428 "scif4_clk_b",
4429 "scif4_ctrl_b",
4430 "scif4_data_c",
4431 "scif4_clk_c",
4432 "scif4_ctrl_c",
4433 };
4434
4435 static const char * const scif5_groups[] = {
4436 "scif5_data",
4437 "scif5_clk",
4438 };
4439
4440 static const char * const scif_clk_groups[] = {
4441 "scif_clk_a",
4442 "scif_clk_b",
4443 };
4444
4445 static const char * const sdhi0_groups[] = {
4446 "sdhi0_data1",
4447 "sdhi0_data4",
4448 "sdhi0_ctrl",
4449 "sdhi0_cd",
4450 "sdhi0_wp",
4451 };
4452
4453 static const char * const sdhi1_groups[] = {
4454 "sdhi1_data1",
4455 "sdhi1_data4",
4456 "sdhi1_ctrl",
4457 "sdhi1_cd",
4458 "sdhi1_wp",
4459 };
4460
4461 static const char * const sdhi2_groups[] = {
4462 "sdhi2_data1",
4463 "sdhi2_data4",
4464 "sdhi2_data8",
4465 "sdhi2_ctrl",
4466 "sdhi2_cd_a",
4467 "sdhi2_wp_a",
4468 "sdhi2_cd_b",
4469 "sdhi2_wp_b",
4470 "sdhi2_ds",
4471 };
4472
4473 static const char * const sdhi3_groups[] = {
4474 "sdhi3_data1",
4475 "sdhi3_data4",
4476 "sdhi3_data8",
4477 "sdhi3_ctrl",
4478 "sdhi3_cd",
4479 "sdhi3_wp",
4480 "sdhi3_ds",
4481 };
4482
4483 static const char * const ssi_groups[] = {
4484 "ssi0_data",
4485 "ssi01239_ctrl",
4486 "ssi1_data_a",
4487 "ssi1_data_b",
4488 "ssi1_ctrl_a",
4489 "ssi1_ctrl_b",
4490 "ssi2_data_a",
4491 "ssi2_data_b",
4492 "ssi2_ctrl_a",
4493 "ssi2_ctrl_b",
4494 "ssi3_data",
4495 "ssi34_ctrl",
4496 "ssi4_data",
4497 "ssi4_ctrl",
4498 "ssi5_data",
4499 "ssi5_ctrl",
4500 "ssi6_data",
4501 "ssi6_ctrl",
4502 "ssi7_data",
4503 "ssi78_ctrl",
4504 "ssi8_data",
4505 "ssi9_data_a",
4506 "ssi9_data_b",
4507 "ssi9_ctrl_a",
4508 "ssi9_ctrl_b",
4509 };
4510
4511 static const char * const usb0_groups[] = {
4512 "usb0",
4513 };
4514
4515 static const char * const usb1_groups[] = {
4516 "usb1",
4517 };
4518
4519 static const char * const usb2_groups[] = {
4520 "usb2",
4521 };
4522
4523 static const char * const qspi0_groups[] = {
4524 "qspi0_ctrl",
4525 "qspi0_data2",
4526 "qspi0_data4",
4527 };
4528
4529 static const char * const qspi1_groups[] = {
4530 "qspi1_ctrl",
4531 "qspi1_data2",
4532 "qspi1_data4",
4533 };
4534
4535 static const struct sh_pfc_function pinmux_functions[] = {
4536 SH_PFC_FUNCTION(audio_clk),
4537 SH_PFC_FUNCTION(avb),
4538 SH_PFC_FUNCTION(can0),
4539 SH_PFC_FUNCTION(can1),
4540 SH_PFC_FUNCTION(can_clk),
4541 SH_PFC_FUNCTION(canfd0),
4542 SH_PFC_FUNCTION(canfd1),
4543 SH_PFC_FUNCTION(drif0),
4544 SH_PFC_FUNCTION(drif1),
4545 SH_PFC_FUNCTION(drif2),
4546 SH_PFC_FUNCTION(drif3),
4547 SH_PFC_FUNCTION(du),
4548 SH_PFC_FUNCTION(hscif0),
4549 SH_PFC_FUNCTION(hscif1),
4550 SH_PFC_FUNCTION(hscif2),
4551 SH_PFC_FUNCTION(hscif3),
4552 SH_PFC_FUNCTION(hscif4),
4553 SH_PFC_FUNCTION(i2c1),
4554 SH_PFC_FUNCTION(i2c2),
4555 SH_PFC_FUNCTION(i2c6),
4556 SH_PFC_FUNCTION(intc_ex),
4557 SH_PFC_FUNCTION(msiof0),
4558 SH_PFC_FUNCTION(msiof1),
4559 SH_PFC_FUNCTION(msiof2),
4560 SH_PFC_FUNCTION(msiof3),
4561 SH_PFC_FUNCTION(pwm0),
4562 SH_PFC_FUNCTION(pwm1),
4563 SH_PFC_FUNCTION(pwm2),
4564 SH_PFC_FUNCTION(pwm3),
4565 SH_PFC_FUNCTION(pwm4),
4566 SH_PFC_FUNCTION(pwm5),
4567 SH_PFC_FUNCTION(pwm6),
4568 SH_PFC_FUNCTION(sata0),
4569 SH_PFC_FUNCTION(scif0),
4570 SH_PFC_FUNCTION(scif1),
4571 SH_PFC_FUNCTION(scif2),
4572 SH_PFC_FUNCTION(scif3),
4573 SH_PFC_FUNCTION(scif4),
4574 SH_PFC_FUNCTION(scif5),
4575 SH_PFC_FUNCTION(scif_clk),
4576 SH_PFC_FUNCTION(sdhi0),
4577 SH_PFC_FUNCTION(sdhi1),
4578 SH_PFC_FUNCTION(sdhi2),
4579 SH_PFC_FUNCTION(sdhi3),
4580 SH_PFC_FUNCTION(ssi),
4581 SH_PFC_FUNCTION(usb0),
4582 SH_PFC_FUNCTION(usb1),
4583 SH_PFC_FUNCTION(usb2),
4584 SH_PFC_FUNCTION(qspi0),
4585 SH_PFC_FUNCTION(qspi1),
4586 };
4587
4588 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4589 #define F_(x, y) FN_##y
4590 #define FM(x) FN_##x
4591 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4592 0, 0,
4593 0, 0,
4594 0, 0,
4595 0, 0,
4596 0, 0,
4597 0, 0,
4598 0, 0,
4599 0, 0,
4600 0, 0,
4601 0, 0,
4602 0, 0,
4603 0, 0,
4604 0, 0,
4605 0, 0,
4606 0, 0,
4607 0, 0,
4608 GP_0_15_FN, GPSR0_15,
4609 GP_0_14_FN, GPSR0_14,
4610 GP_0_13_FN, GPSR0_13,
4611 GP_0_12_FN, GPSR0_12,
4612 GP_0_11_FN, GPSR0_11,
4613 GP_0_10_FN, GPSR0_10,
4614 GP_0_9_FN, GPSR0_9,
4615 GP_0_8_FN, GPSR0_8,
4616 GP_0_7_FN, GPSR0_7,
4617 GP_0_6_FN, GPSR0_6,
4618 GP_0_5_FN, GPSR0_5,
4619 GP_0_4_FN, GPSR0_4,
4620 GP_0_3_FN, GPSR0_3,
4621 GP_0_2_FN, GPSR0_2,
4622 GP_0_1_FN, GPSR0_1,
4623 GP_0_0_FN, GPSR0_0, }
4624 },
4625 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4626 0, 0,
4627 0, 0,
4628 0, 0,
4629 0, 0,
4630 GP_1_27_FN, GPSR1_27,
4631 GP_1_26_FN, GPSR1_26,
4632 GP_1_25_FN, GPSR1_25,
4633 GP_1_24_FN, GPSR1_24,
4634 GP_1_23_FN, GPSR1_23,
4635 GP_1_22_FN, GPSR1_22,
4636 GP_1_21_FN, GPSR1_21,
4637 GP_1_20_FN, GPSR1_20,
4638 GP_1_19_FN, GPSR1_19,
4639 GP_1_18_FN, GPSR1_18,
4640 GP_1_17_FN, GPSR1_17,
4641 GP_1_16_FN, GPSR1_16,
4642 GP_1_15_FN, GPSR1_15,
4643 GP_1_14_FN, GPSR1_14,
4644 GP_1_13_FN, GPSR1_13,
4645 GP_1_12_FN, GPSR1_12,
4646 GP_1_11_FN, GPSR1_11,
4647 GP_1_10_FN, GPSR1_10,
4648 GP_1_9_FN, GPSR1_9,
4649 GP_1_8_FN, GPSR1_8,
4650 GP_1_7_FN, GPSR1_7,
4651 GP_1_6_FN, GPSR1_6,
4652 GP_1_5_FN, GPSR1_5,
4653 GP_1_4_FN, GPSR1_4,
4654 GP_1_3_FN, GPSR1_3,
4655 GP_1_2_FN, GPSR1_2,
4656 GP_1_1_FN, GPSR1_1,
4657 GP_1_0_FN, GPSR1_0, }
4658 },
4659 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4660 0, 0,
4661 0, 0,
4662 0, 0,
4663 0, 0,
4664 0, 0,
4665 0, 0,
4666 0, 0,
4667 0, 0,
4668 0, 0,
4669 0, 0,
4670 0, 0,
4671 0, 0,
4672 0, 0,
4673 0, 0,
4674 0, 0,
4675 0, 0,
4676 0, 0,
4677 GP_2_14_FN, GPSR2_14,
4678 GP_2_13_FN, GPSR2_13,
4679 GP_2_12_FN, GPSR2_12,
4680 GP_2_11_FN, GPSR2_11,
4681 GP_2_10_FN, GPSR2_10,
4682 GP_2_9_FN, GPSR2_9,
4683 GP_2_8_FN, GPSR2_8,
4684 GP_2_7_FN, GPSR2_7,
4685 GP_2_6_FN, GPSR2_6,
4686 GP_2_5_FN, GPSR2_5,
4687 GP_2_4_FN, GPSR2_4,
4688 GP_2_3_FN, GPSR2_3,
4689 GP_2_2_FN, GPSR2_2,
4690 GP_2_1_FN, GPSR2_1,
4691 GP_2_0_FN, GPSR2_0, }
4692 },
4693 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4694 0, 0,
4695 0, 0,
4696 0, 0,
4697 0, 0,
4698 0, 0,
4699 0, 0,
4700 0, 0,
4701 0, 0,
4702 0, 0,
4703 0, 0,
4704 0, 0,
4705 0, 0,
4706 0, 0,
4707 0, 0,
4708 0, 0,
4709 0, 0,
4710 GP_3_15_FN, GPSR3_15,
4711 GP_3_14_FN, GPSR3_14,
4712 GP_3_13_FN, GPSR3_13,
4713 GP_3_12_FN, GPSR3_12,
4714 GP_3_11_FN, GPSR3_11,
4715 GP_3_10_FN, GPSR3_10,
4716 GP_3_9_FN, GPSR3_9,
4717 GP_3_8_FN, GPSR3_8,
4718 GP_3_7_FN, GPSR3_7,
4719 GP_3_6_FN, GPSR3_6,
4720 GP_3_5_FN, GPSR3_5,
4721 GP_3_4_FN, GPSR3_4,
4722 GP_3_3_FN, GPSR3_3,
4723 GP_3_2_FN, GPSR3_2,
4724 GP_3_1_FN, GPSR3_1,
4725 GP_3_0_FN, GPSR3_0, }
4726 },
4727 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4728 0, 0,
4729 0, 0,
4730 0, 0,
4731 0, 0,
4732 0, 0,
4733 0, 0,
4734 0, 0,
4735 0, 0,
4736 0, 0,
4737 0, 0,
4738 0, 0,
4739 0, 0,
4740 0, 0,
4741 0, 0,
4742 GP_4_17_FN, GPSR4_17,
4743 GP_4_16_FN, GPSR4_16,
4744 GP_4_15_FN, GPSR4_15,
4745 GP_4_14_FN, GPSR4_14,
4746 GP_4_13_FN, GPSR4_13,
4747 GP_4_12_FN, GPSR4_12,
4748 GP_4_11_FN, GPSR4_11,
4749 GP_4_10_FN, GPSR4_10,
4750 GP_4_9_FN, GPSR4_9,
4751 GP_4_8_FN, GPSR4_8,
4752 GP_4_7_FN, GPSR4_7,
4753 GP_4_6_FN, GPSR4_6,
4754 GP_4_5_FN, GPSR4_5,
4755 GP_4_4_FN, GPSR4_4,
4756 GP_4_3_FN, GPSR4_3,
4757 GP_4_2_FN, GPSR4_2,
4758 GP_4_1_FN, GPSR4_1,
4759 GP_4_0_FN, GPSR4_0, }
4760 },
4761 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4762 0, 0,
4763 0, 0,
4764 0, 0,
4765 0, 0,
4766 0, 0,
4767 0, 0,
4768 GP_5_25_FN, GPSR5_25,
4769 GP_5_24_FN, GPSR5_24,
4770 GP_5_23_FN, GPSR5_23,
4771 GP_5_22_FN, GPSR5_22,
4772 GP_5_21_FN, GPSR5_21,
4773 GP_5_20_FN, GPSR5_20,
4774 GP_5_19_FN, GPSR5_19,
4775 GP_5_18_FN, GPSR5_18,
4776 GP_5_17_FN, GPSR5_17,
4777 GP_5_16_FN, GPSR5_16,
4778 GP_5_15_FN, GPSR5_15,
4779 GP_5_14_FN, GPSR5_14,
4780 GP_5_13_FN, GPSR5_13,
4781 GP_5_12_FN, GPSR5_12,
4782 GP_5_11_FN, GPSR5_11,
4783 GP_5_10_FN, GPSR5_10,
4784 GP_5_9_FN, GPSR5_9,
4785 GP_5_8_FN, GPSR5_8,
4786 GP_5_7_FN, GPSR5_7,
4787 GP_5_6_FN, GPSR5_6,
4788 GP_5_5_FN, GPSR5_5,
4789 GP_5_4_FN, GPSR5_4,
4790 GP_5_3_FN, GPSR5_3,
4791 GP_5_2_FN, GPSR5_2,
4792 GP_5_1_FN, GPSR5_1,
4793 GP_5_0_FN, GPSR5_0, }
4794 },
4795 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4796 GP_6_31_FN, GPSR6_31,
4797 GP_6_30_FN, GPSR6_30,
4798 GP_6_29_FN, GPSR6_29,
4799 GP_6_28_FN, GPSR6_28,
4800 GP_6_27_FN, GPSR6_27,
4801 GP_6_26_FN, GPSR6_26,
4802 GP_6_25_FN, GPSR6_25,
4803 GP_6_24_FN, GPSR6_24,
4804 GP_6_23_FN, GPSR6_23,
4805 GP_6_22_FN, GPSR6_22,
4806 GP_6_21_FN, GPSR6_21,
4807 GP_6_20_FN, GPSR6_20,
4808 GP_6_19_FN, GPSR6_19,
4809 GP_6_18_FN, GPSR6_18,
4810 GP_6_17_FN, GPSR6_17,
4811 GP_6_16_FN, GPSR6_16,
4812 GP_6_15_FN, GPSR6_15,
4813 GP_6_14_FN, GPSR6_14,
4814 GP_6_13_FN, GPSR6_13,
4815 GP_6_12_FN, GPSR6_12,
4816 GP_6_11_FN, GPSR6_11,
4817 GP_6_10_FN, GPSR6_10,
4818 GP_6_9_FN, GPSR6_9,
4819 GP_6_8_FN, GPSR6_8,
4820 GP_6_7_FN, GPSR6_7,
4821 GP_6_6_FN, GPSR6_6,
4822 GP_6_5_FN, GPSR6_5,
4823 GP_6_4_FN, GPSR6_4,
4824 GP_6_3_FN, GPSR6_3,
4825 GP_6_2_FN, GPSR6_2,
4826 GP_6_1_FN, GPSR6_1,
4827 GP_6_0_FN, GPSR6_0, }
4828 },
4829 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4830 0, 0,
4831 0, 0,
4832 0, 0,
4833 0, 0,
4834 0, 0,
4835 0, 0,
4836 0, 0,
4837 0, 0,
4838 0, 0,
4839 0, 0,
4840 0, 0,
4841 0, 0,
4842 0, 0,
4843 0, 0,
4844 0, 0,
4845 0, 0,
4846 0, 0,
4847 0, 0,
4848 0, 0,
4849 0, 0,
4850 0, 0,
4851 0, 0,
4852 0, 0,
4853 0, 0,
4854 0, 0,
4855 0, 0,
4856 0, 0,
4857 0, 0,
4858 GP_7_3_FN, GPSR7_3,
4859 GP_7_2_FN, GPSR7_2,
4860 GP_7_1_FN, GPSR7_1,
4861 GP_7_0_FN, GPSR7_0, }
4862 },
4863 #undef F_
4864 #undef FM
4865
4866 #define F_(x, y) x,
4867 #define FM(x) FN_##x,
4868 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4869 IP0_31_28
4870 IP0_27_24
4871 IP0_23_20
4872 IP0_19_16
4873 IP0_15_12
4874 IP0_11_8
4875 IP0_7_4
4876 IP0_3_0 }
4877 },
4878 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4879 IP1_31_28
4880 IP1_27_24
4881 IP1_23_20
4882 IP1_19_16
4883 IP1_15_12
4884 IP1_11_8
4885 IP1_7_4
4886 IP1_3_0 }
4887 },
4888 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4889 IP2_31_28
4890 IP2_27_24
4891 IP2_23_20
4892 IP2_19_16
4893 IP2_15_12
4894 IP2_11_8
4895 IP2_7_4
4896 IP2_3_0 }
4897 },
4898 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4899 IP3_31_28
4900 IP3_27_24
4901 IP3_23_20
4902 IP3_19_16
4903 IP3_15_12
4904 IP3_11_8
4905 IP3_7_4
4906 IP3_3_0 }
4907 },
4908 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4909 IP4_31_28
4910 IP4_27_24
4911 IP4_23_20
4912 IP4_19_16
4913 IP4_15_12
4914 IP4_11_8
4915 IP4_7_4
4916 IP4_3_0 }
4917 },
4918 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4919 IP5_31_28
4920 IP5_27_24
4921 IP5_23_20
4922 IP5_19_16
4923 IP5_15_12
4924 IP5_11_8
4925 IP5_7_4
4926 IP5_3_0 }
4927 },
4928 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4929 IP6_31_28
4930 IP6_27_24
4931 IP6_23_20
4932 IP6_19_16
4933 IP6_15_12
4934 IP6_11_8
4935 IP6_7_4
4936 IP6_3_0 }
4937 },
4938 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4939 IP7_31_28
4940 IP7_27_24
4941 IP7_23_20
4942 IP7_19_16
4943 IP7_15_12
4944 IP7_11_8
4945 IP7_7_4
4946 IP7_3_0 }
4947 },
4948 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4949 IP8_31_28
4950 IP8_27_24
4951 IP8_23_20
4952 IP8_19_16
4953 IP8_15_12
4954 IP8_11_8
4955 IP8_7_4
4956 IP8_3_0 }
4957 },
4958 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4959 IP9_31_28
4960 IP9_27_24
4961 IP9_23_20
4962 IP9_19_16
4963 IP9_15_12
4964 IP9_11_8
4965 IP9_7_4
4966 IP9_3_0 }
4967 },
4968 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4969 IP10_31_28
4970 IP10_27_24
4971 IP10_23_20
4972 IP10_19_16
4973 IP10_15_12
4974 IP10_11_8
4975 IP10_7_4
4976 IP10_3_0 }
4977 },
4978 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4979 IP11_31_28
4980 IP11_27_24
4981 IP11_23_20
4982 IP11_19_16
4983 IP11_15_12
4984 IP11_11_8
4985 IP11_7_4
4986 IP11_3_0 }
4987 },
4988 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4989 IP12_31_28
4990 IP12_27_24
4991 IP12_23_20
4992 IP12_19_16
4993 IP12_15_12
4994 IP12_11_8
4995 IP12_7_4
4996 IP12_3_0 }
4997 },
4998 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
4999 IP13_31_28
5000 IP13_27_24
5001 IP13_23_20
5002 IP13_19_16
5003 IP13_15_12
5004 IP13_11_8
5005 IP13_7_4
5006 IP13_3_0 }
5007 },
5008 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5009 IP14_31_28
5010 IP14_27_24
5011 IP14_23_20
5012 IP14_19_16
5013 IP14_15_12
5014 IP14_11_8
5015 IP14_7_4
5016 IP14_3_0 }
5017 },
5018 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5019 IP15_31_28
5020 IP15_27_24
5021 IP15_23_20
5022 IP15_19_16
5023 IP15_15_12
5024 IP15_11_8
5025 IP15_7_4
5026 IP15_3_0 }
5027 },
5028 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5029 IP16_31_28
5030 IP16_27_24
5031 IP16_23_20
5032 IP16_19_16
5033 IP16_15_12
5034 IP16_11_8
5035 IP16_7_4
5036 IP16_3_0 }
5037 },
5038 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5039 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5040 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5041 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5042 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5043 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5044 /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5045 IP17_7_4
5046 IP17_3_0 }
5047 },
5048 #undef F_
5049 #undef FM
5050
5051 #define F_(x, y) x,
5052 #define FM(x) FN_##x,
5053 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5054 1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
5055 2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
5056 0, 0, /* RESERVED 31 */
5057 MOD_SEL0_30_29
5058 MOD_SEL0_28_27
5059 MOD_SEL0_26_25_24
5060 MOD_SEL0_23
5061 MOD_SEL0_22
5062 MOD_SEL0_21_20
5063 MOD_SEL0_19
5064 MOD_SEL0_18
5065 MOD_SEL0_17
5066 MOD_SEL0_16_15
5067 MOD_SEL0_14
5068 MOD_SEL0_13
5069 MOD_SEL0_12
5070 MOD_SEL0_11
5071 MOD_SEL0_10
5072 MOD_SEL0_9
5073 MOD_SEL0_8
5074 MOD_SEL0_7_6
5075 MOD_SEL0_5_4
5076 MOD_SEL0_3
5077 MOD_SEL0_2_1
5078 0, 0, /* RESERVED 0 */ }
5079 },
5080 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5081 2, 3, 1, 2, 3, 1, 1, 2, 1,
5082 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5083 MOD_SEL1_31_30
5084 MOD_SEL1_29_28_27
5085 MOD_SEL1_26
5086 MOD_SEL1_25_24
5087 MOD_SEL1_23_22_21
5088 MOD_SEL1_20
5089 MOD_SEL1_19
5090 MOD_SEL1_18_17
5091 MOD_SEL1_16
5092 MOD_SEL1_15_14
5093 MOD_SEL1_13
5094 MOD_SEL1_12
5095 MOD_SEL1_11
5096 MOD_SEL1_10
5097 MOD_SEL1_9
5098 0, 0, 0, 0, /* RESERVED 8, 7 */
5099 MOD_SEL1_6
5100 MOD_SEL1_5
5101 MOD_SEL1_4
5102 MOD_SEL1_3
5103 MOD_SEL1_2
5104 MOD_SEL1_1
5105 MOD_SEL1_0 }
5106 },
5107 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5108 1, 1, 1, 1, 4, 4, 4,
5109 4, 4, 4, 1, 2, 1) {
5110 MOD_SEL2_31
5111 MOD_SEL2_30
5112 MOD_SEL2_29
5113 /* RESERVED 28 */
5114 0, 0,
5115 /* RESERVED 27, 26, 25, 24 */
5116 0, 0, 0, 0, 0, 0, 0, 0,
5117 0, 0, 0, 0, 0, 0, 0, 0,
5118 /* RESERVED 23, 22, 21, 20 */
5119 0, 0, 0, 0, 0, 0, 0, 0,
5120 0, 0, 0, 0, 0, 0, 0, 0,
5121 /* RESERVED 19, 18, 17, 16 */
5122 0, 0, 0, 0, 0, 0, 0, 0,
5123 0, 0, 0, 0, 0, 0, 0, 0,
5124 /* RESERVED 15, 14, 13, 12 */
5125 0, 0, 0, 0, 0, 0, 0, 0,
5126 0, 0, 0, 0, 0, 0, 0, 0,
5127 /* RESERVED 11, 10, 9, 8 */
5128 0, 0, 0, 0, 0, 0, 0, 0,
5129 0, 0, 0, 0, 0, 0, 0, 0,
5130 /* RESERVED 7, 6, 5, 4 */
5131 0, 0, 0, 0, 0, 0, 0, 0,
5132 0, 0, 0, 0, 0, 0, 0, 0,
5133 /* RESERVED 3 */
5134 0, 0,
5135 /* RESERVED 2, 1 */
5136 0, 0, 0, 0,
5137 MOD_SEL2_0 }
5138 },
5139 { },
5140 };
5141
5142 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5143 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5144 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5145 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5146 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5147 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5148 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5149 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5150 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5151 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5152 } },
5153 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5154 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5155 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5156 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5157 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5158 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5159 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5160 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5161 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5162 } },
5163 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5164 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5165 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5166 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5167 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5168 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5169 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5170 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5171 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5172 } },
5173 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5174 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5175 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5176 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5177 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5178 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5179 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5180 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5181 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5182 } },
5183 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5184 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5185 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5186 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5187 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5188 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5189 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5190 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5191 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5192 } },
5193 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5194 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5195 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5196 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5197 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5198 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5199 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5200 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5201 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5202 } },
5203 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5204 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5205 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5206 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5207 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5208 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5209 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5210 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5211 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5212 } },
5213 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5214 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5215 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5216 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5217 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5218 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5219 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5220 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5221 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5222 } },
5223 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5224 { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
5225 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5226 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5227 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5228 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5229 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5230 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5231 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5232 } },
5233 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5234 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5235 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5236 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5237 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5238 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5239 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5240 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5241 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5242 } },
5243 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5244 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5245 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5246 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5247 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5248 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5249 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5250 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5251 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5252 } },
5253 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5254 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5255 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5256 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5257 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5258 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5259 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
5260 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5261 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5262 } },
5263 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5264 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5265 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5266 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5267 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5268 } },
5269 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5270 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5271 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5272 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5273 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5274 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5275 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5276 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5277 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5278 } },
5279 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5280 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5281 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5282 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5283 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5284 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5285 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5286 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5287 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5288 } },
5289 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5290 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5291 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5292 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5293 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5294 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5295 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5296 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5297 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5298 } },
5299 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5300 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5301 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5302 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5303 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5304 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5305 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5306 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5307 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5308 } },
5309 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5310 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5311 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5312 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5313 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5314 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5315 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5316 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5317 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5318 } },
5319 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5320 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
5321 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5322 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5323 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5324 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
5325 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5326 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5327 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5328 } },
5329 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5330 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5331 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5332 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5333 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5334 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5335 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5336 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5337 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5338 } },
5339 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5340 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5341 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5342 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5343 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5344 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5345 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5346 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5347 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5348 } },
5349 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5350 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5351 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5352 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5353 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5354 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */
5355 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */
5356 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5357 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5358 } },
5359 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5360 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5361 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5362 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5363 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5364 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5365 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5366 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5367 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5368 } },
5369 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5370 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5371 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5372 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5373 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5374 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5375 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5376 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5377 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5378 } },
5379 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5380 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5381 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5382 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5383 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5384 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5385 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */
5386 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */
5387 } },
5388 { },
5389 };
5390
5391 static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5392 {
5393 int bit = -EINVAL;
5394
5395 *pocctrl = 0xe6060380;
5396
5397 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5398 bit = pin & 0x1f;
5399
5400 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5401 bit = (pin & 0x1f) + 12;
5402
5403 return bit;
5404 }
5405
5406 #define PUEN 0xe6060400
5407 #define PUD 0xe6060440
5408
5409 #define PU0 0x00
5410 #define PU1 0x04
5411 #define PU2 0x08
5412 #define PU3 0x0c
5413 #define PU4 0x10
5414 #define PU5 0x14
5415 #define PU6 0x18
5416
5417 static const struct sh_pfc_bias_info bias_info[] = {
5418 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
5419 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
5420 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
5421
5422 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
5423 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
5424 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
5425 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
5426 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
5427 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
5428 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
5429 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
5430 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
5431 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
5432 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
5433 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
5434 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
5435 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
5436 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
5437 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
5438 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
5439 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
5440 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
5441 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
5442 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
5443 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
5444 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
5445 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
5446 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
5447 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
5448 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
5449 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
5450 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
5451 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
5452 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
5453 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
5454
5455 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
5456 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
5457 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
5458 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
5459 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
5460 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
5461 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
5462 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
5463 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
5464 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
5465 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
5466 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
5467 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
5468 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
5469 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
5470 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
5471 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
5472 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
5473 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
5474 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
5475 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
5476 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
5477 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
5478 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
5479 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
5480 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
5481 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
5482 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
5483
5484 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
5485 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
5486 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
5487 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
5488 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
5489 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
5490 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
5491 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
5492 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
5493 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
5494 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
5495 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
5496 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
5497 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
5498 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
5499 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
5500 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
5501 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
5502 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
5503 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
5504 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
5505 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
5506
5507 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
5508 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
5509 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
5510 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
5511 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
5512 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
5513 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
5514 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
5515 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
5516 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
5517 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
5518 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
5519 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
5520 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
5521 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
5522 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
5523 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
5524 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
5525 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
5526 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
5527 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
5528 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
5529 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
5530 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
5531 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
5532 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
5533 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
5534 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
5535 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
5536 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
5537 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
5538 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
5539
5540 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
5541 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
5542 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
5543 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
5544 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
5545 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
5546 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
5547 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
5548 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
5549 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
5550 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
5551 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
5552 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
5553 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
5554 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
5555 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
5556 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
5557 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
5558 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
5559 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
5560 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
5561 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
5562 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
5563 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
5564 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
5565 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
5566 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
5567 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
5568 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
5569 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
5570 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
5571
5572 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */
5573 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */
5574 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
5575 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
5576 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
5577 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
5578 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
5579 };
5580
5581 static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
5582 unsigned int pin)
5583 {
5584 const struct sh_pfc_bias_info *info;
5585 u32 reg;
5586 u32 bit;
5587
5588 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
5589 if (!info)
5590 return PIN_CONFIG_BIAS_DISABLE;
5591
5592 reg = info->reg;
5593 bit = BIT(info->bit);
5594
5595 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
5596 return PIN_CONFIG_BIAS_DISABLE;
5597 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
5598 return PIN_CONFIG_BIAS_PULL_UP;
5599 else
5600 return PIN_CONFIG_BIAS_PULL_DOWN;
5601 }
5602
5603 static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5604 unsigned int bias)
5605 {
5606 const struct sh_pfc_bias_info *info;
5607 u32 enable, updown;
5608 u32 reg;
5609 u32 bit;
5610
5611 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
5612 if (!info)
5613 return;
5614
5615 reg = info->reg;
5616 bit = BIT(info->bit);
5617
5618 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
5619 if (bias != PIN_CONFIG_BIAS_DISABLE)
5620 enable |= bit;
5621
5622 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
5623 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5624 updown |= bit;
5625
5626 sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
5627 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
5628 }
5629
5630 static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
5631 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
5632 .get_bias = r8a7795_pinmux_get_bias,
5633 .set_bias = r8a7795_pinmux_set_bias,
5634 };
5635
5636 const struct sh_pfc_soc_info r8a7795_pinmux_info = {
5637 .name = "r8a77950_pfc",
5638 .ops = &r8a7795_pinmux_ops,
5639 .unlock_reg = 0xe6060000, /* PMMR */
5640
5641 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5642
5643 .pins = pinmux_pins,
5644 .nr_pins = ARRAY_SIZE(pinmux_pins),
5645 .groups = pinmux_groups,
5646 .nr_groups = ARRAY_SIZE(pinmux_groups),
5647 .functions = pinmux_functions,
5648 .nr_functions = ARRAY_SIZE(pinmux_functions),
5649
5650 .cfg_regs = pinmux_config_regs,
5651 .drive_regs = pinmux_drive_regs,
5652
5653 .pinmux_data = pinmux_data,
5654 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5655 };
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