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pinctrl: sh-pfc: r8a77965: Use new macros for non-GPIO pins
[mirror_ubuntu-eoan-kernel.git] / drivers / pinctrl / sh-pfc / pfc-r8a77965.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77965 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Copyright (C) 2016-2019 Renesas Electronics Corp.
7 *
8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15 #include <linux/errno.h>
16 #include <linux/kernel.h>
17
18 #include "core.h"
19 #include "sh_pfc.h"
20
21 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
22
23 #define CPU_ALL_GP(fn, sfx) \
24 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
33 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
36
37 #define CPU_ALL_NOGP(fn) \
38 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
57 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
71 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
72 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
73 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
75 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
76 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
77 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
78 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
79 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
80
81 /*
82 * F_() : just information
83 * FM() : macro for FN_xxx / xxx_MARK
84 */
85
86 /* GPSR0 */
87 #define GPSR0_15 F_(D15, IP7_11_8)
88 #define GPSR0_14 F_(D14, IP7_7_4)
89 #define GPSR0_13 F_(D13, IP7_3_0)
90 #define GPSR0_12 F_(D12, IP6_31_28)
91 #define GPSR0_11 F_(D11, IP6_27_24)
92 #define GPSR0_10 F_(D10, IP6_23_20)
93 #define GPSR0_9 F_(D9, IP6_19_16)
94 #define GPSR0_8 F_(D8, IP6_15_12)
95 #define GPSR0_7 F_(D7, IP6_11_8)
96 #define GPSR0_6 F_(D6, IP6_7_4)
97 #define GPSR0_5 F_(D5, IP6_3_0)
98 #define GPSR0_4 F_(D4, IP5_31_28)
99 #define GPSR0_3 F_(D3, IP5_27_24)
100 #define GPSR0_2 F_(D2, IP5_23_20)
101 #define GPSR0_1 F_(D1, IP5_19_16)
102 #define GPSR0_0 F_(D0, IP5_15_12)
103
104 /* GPSR1 */
105 #define GPSR1_28 FM(CLKOUT)
106 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
107 #define GPSR1_26 F_(WE1_N, IP5_7_4)
108 #define GPSR1_25 F_(WE0_N, IP5_3_0)
109 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
110 #define GPSR1_23 F_(RD_N, IP4_27_24)
111 #define GPSR1_22 F_(BS_N, IP4_23_20)
112 #define GPSR1_21 F_(CS1_N, IP4_19_16)
113 #define GPSR1_20 F_(CS0_N, IP4_15_12)
114 #define GPSR1_19 F_(A19, IP4_11_8)
115 #define GPSR1_18 F_(A18, IP4_7_4)
116 #define GPSR1_17 F_(A17, IP4_3_0)
117 #define GPSR1_16 F_(A16, IP3_31_28)
118 #define GPSR1_15 F_(A15, IP3_27_24)
119 #define GPSR1_14 F_(A14, IP3_23_20)
120 #define GPSR1_13 F_(A13, IP3_19_16)
121 #define GPSR1_12 F_(A12, IP3_15_12)
122 #define GPSR1_11 F_(A11, IP3_11_8)
123 #define GPSR1_10 F_(A10, IP3_7_4)
124 #define GPSR1_9 F_(A9, IP3_3_0)
125 #define GPSR1_8 F_(A8, IP2_31_28)
126 #define GPSR1_7 F_(A7, IP2_27_24)
127 #define GPSR1_6 F_(A6, IP2_23_20)
128 #define GPSR1_5 F_(A5, IP2_19_16)
129 #define GPSR1_4 F_(A4, IP2_15_12)
130 #define GPSR1_3 F_(A3, IP2_11_8)
131 #define GPSR1_2 F_(A2, IP2_7_4)
132 #define GPSR1_1 F_(A1, IP2_3_0)
133 #define GPSR1_0 F_(A0, IP1_31_28)
134
135 /* GPSR2 */
136 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
137 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
138 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
139 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
140 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
141 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
142 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
143 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
144 #define GPSR2_6 F_(PWM0, IP1_19_16)
145 #define GPSR2_5 F_(IRQ5, IP1_15_12)
146 #define GPSR2_4 F_(IRQ4, IP1_11_8)
147 #define GPSR2_3 F_(IRQ3, IP1_7_4)
148 #define GPSR2_2 F_(IRQ2, IP1_3_0)
149 #define GPSR2_1 F_(IRQ1, IP0_31_28)
150 #define GPSR2_0 F_(IRQ0, IP0_27_24)
151
152 /* GPSR3 */
153 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
154 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
155 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
156 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
157 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
158 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
159 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
160 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
161 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
162 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
163 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
164 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
165 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
166 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
167 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
168 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
169
170 /* GPSR4 */
171 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
172 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
173 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
174 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
175 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
176 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
177 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
178 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
179 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
180 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
181 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
182 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
183 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
184 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
185 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
186 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
187 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
188 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
189
190 /* GPSR5 */
191 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
192 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
193 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
194 #define GPSR5_22 FM(MSIOF0_RXD)
195 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
196 #define GPSR5_20 FM(MSIOF0_TXD)
197 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
198 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
199 #define GPSR5_17 FM(MSIOF0_SCK)
200 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
201 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
202 #define GPSR5_14 F_(HTX0, IP13_19_16)
203 #define GPSR5_13 F_(HRX0, IP13_15_12)
204 #define GPSR5_12 F_(HSCK0, IP13_11_8)
205 #define GPSR5_11 F_(RX2_A, IP13_7_4)
206 #define GPSR5_10 F_(TX2_A, IP13_3_0)
207 #define GPSR5_9 F_(SCK2, IP12_31_28)
208 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
209 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
210 #define GPSR5_6 F_(TX1_A, IP12_19_16)
211 #define GPSR5_5 F_(RX1_A, IP12_15_12)
212 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
213 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
214 #define GPSR5_2 F_(TX0, IP12_3_0)
215 #define GPSR5_1 F_(RX0, IP11_31_28)
216 #define GPSR5_0 F_(SCK0, IP11_27_24)
217
218 /* GPSR6 */
219 #define GPSR6_31 F_(GP6_31, IP18_7_4)
220 #define GPSR6_30 F_(GP6_30, IP18_3_0)
221 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
222 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
223 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
224 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
225 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
226 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
227 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
228 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
229 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
230 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
231 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
232 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
233 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
234 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
235 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
236 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
237 #define GPSR6_13 FM(SSI_SDATA5)
238 #define GPSR6_12 FM(SSI_WS5)
239 #define GPSR6_11 FM(SSI_SCK5)
240 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
241 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
242 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
243 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
244 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
245 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
246 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
247 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
248 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
249 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
250 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
251
252 /* GPSR7 */
253 #define GPSR7_3 FM(GP7_03)
254 #define GPSR7_2 FM(GP7_02)
255 #define GPSR7_1 FM(AVS2)
256 #define GPSR7_0 FM(AVS1)
257
258
259 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
260 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287
288 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
289 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318
319 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
320 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354
355 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
356 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
377 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384
385 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
386 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
406 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
407 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
408 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
409 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
410 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
411 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
412 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
413
414 #define PINMUX_GPSR \
415 \
416 GPSR6_31 \
417 GPSR6_30 \
418 GPSR6_29 \
419 GPSR1_28 GPSR6_28 \
420 GPSR1_27 GPSR6_27 \
421 GPSR1_26 GPSR6_26 \
422 GPSR1_25 GPSR5_25 GPSR6_25 \
423 GPSR1_24 GPSR5_24 GPSR6_24 \
424 GPSR1_23 GPSR5_23 GPSR6_23 \
425 GPSR1_22 GPSR5_22 GPSR6_22 \
426 GPSR1_21 GPSR5_21 GPSR6_21 \
427 GPSR1_20 GPSR5_20 GPSR6_20 \
428 GPSR1_19 GPSR5_19 GPSR6_19 \
429 GPSR1_18 GPSR5_18 GPSR6_18 \
430 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
431 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
432 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
433 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
434 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
435 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
436 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
437 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
438 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
439 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
440 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
441 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
442 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
443 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
444 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
445 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
446 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
447 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
448
449 #define PINMUX_IPSR \
450 \
451 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
452 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
453 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
454 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
455 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
456 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
457 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
458 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
459 \
460 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
461 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
462 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
463 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
464 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
465 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
466 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
467 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
468 \
469 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
470 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
471 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
472 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
473 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
474 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
475 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
476 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
477 \
478 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
479 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
480 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
481 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
482 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
483 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
484 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
485 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
486 \
487 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
488 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
489 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
490 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
491 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
492 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
493 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
494 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
495
496 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
497 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
498 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
499 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
500 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
501 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
502 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
503 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
504 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
505 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
506 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
507 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
508 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
509 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
510 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
511 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
512 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
513 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
514 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
515
516 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
517 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
518 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
519 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
520 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
521 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
522 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
523 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
524 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
525 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
526 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
527 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
528 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
529 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
530 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
531 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
532 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
533 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
534 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
535 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
536 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
537 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
538 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
539
540 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
541 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
542 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
543 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
544 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
545 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
546 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
547 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
548 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
549 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
550 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
551 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
552 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
553 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
554
555 #define PINMUX_MOD_SELS \
556 \
557 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
558 MOD_SEL2_30 \
559 MOD_SEL1_29_28_27 MOD_SEL2_29 \
560 MOD_SEL0_28_27 MOD_SEL2_28_27 \
561 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
562 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
563 MOD_SEL0_23 MOD_SEL1_23_22_21 \
564 MOD_SEL0_22 MOD_SEL2_22 \
565 MOD_SEL0_21 MOD_SEL2_21 \
566 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
567 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
568 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
569 MOD_SEL2_17 \
570 MOD_SEL0_16 MOD_SEL1_16 \
571 MOD_SEL1_15_14 \
572 MOD_SEL0_14_13 \
573 MOD_SEL1_13 \
574 MOD_SEL0_12 MOD_SEL1_12 \
575 MOD_SEL0_11 MOD_SEL1_11 \
576 MOD_SEL0_10 MOD_SEL1_10 \
577 MOD_SEL0_9_8 MOD_SEL1_9 \
578 MOD_SEL0_7_6 \
579 MOD_SEL1_6 \
580 MOD_SEL0_5 MOD_SEL1_5 \
581 MOD_SEL0_4_3 MOD_SEL1_4 \
582 MOD_SEL1_3 \
583 MOD_SEL1_2 \
584 MOD_SEL1_1 \
585 MOD_SEL1_0 MOD_SEL2_0
586
587 /*
588 * These pins are not able to be muxed but have other properties
589 * that can be set, such as drive-strength or pull-up/pull-down enable.
590 */
591 #define PINMUX_STATIC \
592 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
593 FM(QSPI0_IO2) FM(QSPI0_IO3) \
594 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
595 FM(QSPI1_IO2) FM(QSPI1_IO3) \
596 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
597 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
598 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
599 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
600 FM(PRESETOUT) \
601 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
602 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
603
604 #define PINMUX_PHYS \
605 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
606
607 enum {
608 PINMUX_RESERVED = 0,
609
610 PINMUX_DATA_BEGIN,
611 GP_ALL(DATA),
612 PINMUX_DATA_END,
613
614 #define F_(x, y)
615 #define FM(x) FN_##x,
616 PINMUX_FUNCTION_BEGIN,
617 GP_ALL(FN),
618 PINMUX_GPSR
619 PINMUX_IPSR
620 PINMUX_MOD_SELS
621 PINMUX_FUNCTION_END,
622 #undef F_
623 #undef FM
624
625 #define F_(x, y)
626 #define FM(x) x##_MARK,
627 PINMUX_MARK_BEGIN,
628 PINMUX_GPSR
629 PINMUX_IPSR
630 PINMUX_MOD_SELS
631 PINMUX_STATIC
632 PINMUX_PHYS
633 PINMUX_MARK_END,
634 #undef F_
635 #undef FM
636 };
637
638 static const u16 pinmux_data[] = {
639 PINMUX_DATA_GP_ALL(),
640
641 PINMUX_SINGLE(AVS1),
642 PINMUX_SINGLE(AVS2),
643 PINMUX_SINGLE(CLKOUT),
644 PINMUX_SINGLE(GP7_03),
645 PINMUX_SINGLE(GP7_02),
646 PINMUX_SINGLE(MSIOF0_RXD),
647 PINMUX_SINGLE(MSIOF0_SCK),
648 PINMUX_SINGLE(MSIOF0_TXD),
649 PINMUX_SINGLE(SSI_SCK5),
650 PINMUX_SINGLE(SSI_SDATA5),
651 PINMUX_SINGLE(SSI_WS5),
652
653 /* IPSR0 */
654 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
655 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
656
657 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
658 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
659 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
660
661 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
662 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
663 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
664
665 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
666 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
667 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
668 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
669
670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
671 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
672 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
673 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
674
675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
676 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
677 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
678 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
679
680 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
681 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
682 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
683 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
685 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
686 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
687
688 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
689 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
690 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
691 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
692 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
693 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
694 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
695
696 /* IPSR1 */
697 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
698 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
699 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
700 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
701 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
702 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
703
704 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
705 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
706 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
707 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
708 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
709 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
710
711 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
712 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
713 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
714 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
715 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
716 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
717
718 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
719 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
720 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
721 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
722 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
723 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
724 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
725
726 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
727 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
728 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
729 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
730
731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
732 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
733 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
734 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
735 PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
736
737 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
738 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
739 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
740 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
741
742 PINMUX_IPSR_GPSR(IP1_31_28, A0),
743 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
744 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
745 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
746 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
747 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
748
749 /* IPSR2 */
750 PINMUX_IPSR_GPSR(IP2_3_0, A1),
751 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
752 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
753 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
754 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
755 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
756
757 PINMUX_IPSR_GPSR(IP2_7_4, A2),
758 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
759 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
760 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
761 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
762 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
763
764 PINMUX_IPSR_GPSR(IP2_11_8, A3),
765 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
766 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
767 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
768 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
769 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
770
771 PINMUX_IPSR_GPSR(IP2_15_12, A4),
772 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
773 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
774 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
775 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
776 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
777
778 PINMUX_IPSR_GPSR(IP2_19_16, A5),
779 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
780 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
781 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
782 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
783 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
784 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
785
786 PINMUX_IPSR_GPSR(IP2_23_20, A6),
787 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
788 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
789 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
790 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
791 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
792 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
793
794 PINMUX_IPSR_GPSR(IP2_27_24, A7),
795 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
796 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
797 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
798 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
799 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
800 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
801
802 PINMUX_IPSR_GPSR(IP2_31_28, A8),
803 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
804 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
805 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
806 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
807 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
808 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
809
810 /* IPSR3 */
811 PINMUX_IPSR_GPSR(IP3_3_0, A9),
812 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
813 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
814 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
815
816 PINMUX_IPSR_GPSR(IP3_7_4, A10),
817 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
818 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
819 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
820
821 PINMUX_IPSR_GPSR(IP3_11_8, A11),
822 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
823 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
824 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
825 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
826 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
827 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
828 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
829 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
830
831 PINMUX_IPSR_GPSR(IP3_15_12, A12),
832 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
833 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
834 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
835 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
836 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
837
838 PINMUX_IPSR_GPSR(IP3_19_16, A13),
839 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
840 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
841 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
842 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
843 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
844
845 PINMUX_IPSR_GPSR(IP3_23_20, A14),
846 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
847 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
848 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
849 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
850 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
851
852 PINMUX_IPSR_GPSR(IP3_27_24, A15),
853 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
854 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
855 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
856 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
857 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
858
859 PINMUX_IPSR_GPSR(IP3_31_28, A16),
860 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
861 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
862 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
863
864 /* IPSR4 */
865 PINMUX_IPSR_GPSR(IP4_3_0, A17),
866 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
867 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
868 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
869
870 PINMUX_IPSR_GPSR(IP4_7_4, A18),
871 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
872 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
873 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
874
875 PINMUX_IPSR_GPSR(IP4_11_8, A19),
876 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
877 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
878 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
879
880 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
881 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
882
883 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
884 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
885 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
886
887 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
888 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
889 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
890 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
891 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
892 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
893 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
894 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
895
896 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
897 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
898 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
899 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
900 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
901 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
902
903 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
904 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
905 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
906 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
907 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
908 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
909
910 /* IPSR5 */
911 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
912 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
913 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
914 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
915 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
916 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
917 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
918
919 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
920 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
921 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
922 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
923 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
924 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
925 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
926 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
927
928 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
929 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
930 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
931 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
932
933 PINMUX_IPSR_GPSR(IP5_15_12, D0),
934 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
935 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
936 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
937 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
938
939 PINMUX_IPSR_GPSR(IP5_19_16, D1),
940 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
941 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
942 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
943 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
944
945 PINMUX_IPSR_GPSR(IP5_23_20, D2),
946 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
947 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
948 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
949
950 PINMUX_IPSR_GPSR(IP5_27_24, D3),
951 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
952 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
953 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
954
955 PINMUX_IPSR_GPSR(IP5_31_28, D4),
956 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
957 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
958 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
959
960 /* IPSR6 */
961 PINMUX_IPSR_GPSR(IP6_3_0, D5),
962 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
963 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
964 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
965
966 PINMUX_IPSR_GPSR(IP6_7_4, D6),
967 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
968 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
969 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
970
971 PINMUX_IPSR_GPSR(IP6_11_8, D7),
972 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
973 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
974 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
975
976 PINMUX_IPSR_GPSR(IP6_15_12, D8),
977 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
978 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
979 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
980 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
981 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
982
983 PINMUX_IPSR_GPSR(IP6_19_16, D9),
984 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
985 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
986 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
987 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
988
989 PINMUX_IPSR_GPSR(IP6_23_20, D10),
990 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
991 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
992 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
993 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
994 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
995 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
996
997 PINMUX_IPSR_GPSR(IP6_27_24, D11),
998 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
999 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
1000 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
1001 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
1002 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
1003 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
1004
1005 PINMUX_IPSR_GPSR(IP6_31_28, D12),
1006 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1007 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1008 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1009 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1010 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1011
1012 /* IPSR7 */
1013 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1014 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1015 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1016 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1017 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1018 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1019
1020 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1021 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1022 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1023 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1024 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1025 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1026 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1027
1028 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1029 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1030 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1031 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1032 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1033 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1034 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1035
1036 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1037 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1038 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1039
1040 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1041 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1042 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1043
1044 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1045 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1046 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1047 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1048
1049 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1050 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1051 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1052 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1053
1054 /* IPSR8 */
1055 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1056 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1057 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1058 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1059
1060 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1061 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1062 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1063 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1064
1065 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1066 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1067 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1068
1069 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1070 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1071 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1072 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1073 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1074
1075 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1076 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1077 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1078 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1079 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1080 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1081
1082 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1083 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1084 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1085 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1086 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1087 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1088
1089 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1090 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1091 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1092 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1093 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1094 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1095
1096 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1097 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1098 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1099 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1100 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1101 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1102
1103 /* IPSR9 */
1104 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1105 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1106
1107 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1108 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1109
1110 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1111 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1112
1113 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1114 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1115
1116 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1117 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1118
1119 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1120 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1121
1122 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1123 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1124 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1125
1126 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1127 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1128
1129 /* IPSR10 */
1130 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1131 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1132
1133 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1134 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1135
1136 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1137 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1138
1139 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1140 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1141
1142 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1143 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1144
1145 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1146 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1147 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1148
1149 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1150 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1151 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1152
1153 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1154 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1155 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1156
1157 /* IPSR11 */
1158 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1159 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1160 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1161
1162 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1163 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1164
1165 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1166 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
1167 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1168 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1169
1170 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1171 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
1172 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1173
1174 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1175 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1176 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1177 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
1178
1179 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1180 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1181 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1182 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
1183
1184 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1185 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1186 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1187 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
1188 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1189 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1190 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1191 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1192 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1193 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1194
1195 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1196 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1197 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1198 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1199 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1200
1201 /* IPSR12 */
1202 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1203 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1204 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1205 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1206 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1207
1208 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1209 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1210 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1211 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1212 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1213 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1214 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1215 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1216
1217 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1218 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1219 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1220 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
1221 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1222 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1223 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1224 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1225
1226 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1227 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1228 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1229 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1230 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1231
1232 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1233 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1234 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1235 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1236 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1237
1238 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1239 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1240 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1241 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1242 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1243 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1244 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1245
1246 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1247 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1248 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1249 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1250 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1251 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1252 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1253
1254 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1255 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1256 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1257 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1258 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1259 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1260 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1261
1262 /* IPSR13 */
1263 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1264 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1265 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1266 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1267 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1268 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1269
1270 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1271 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1272 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1273 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1274 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1275 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1276
1277 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1278 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1279 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
1280 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1281 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1282 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1283 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1284 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1285
1286 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1287 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1288 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1289 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1290 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1291 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1292
1293 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1294 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1295 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1296 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1297 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1298 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1299
1300 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1301 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1302 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1303 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1304 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1305 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1306 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1307 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1308
1309 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1310 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1311 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1312 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1313 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1314 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1315 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1316
1317 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1318 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1319 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1320 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1321
1322 /* IPSR14 */
1323 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1324 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1325 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1326 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
1327 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1328 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1329 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1330 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1331
1332 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1333 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1334 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1335 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
1336 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1337 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1338 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1339 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1340
1341 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1342 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1343 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1344
1345 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1346 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1347 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1348 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1349
1350 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1351 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1352 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1353
1354 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1355 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1356
1357 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1358 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1359
1360 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1361 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1362
1363 /* IPSR15 */
1364 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1365
1366 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1367 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1368
1369 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1370 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1371 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1372
1373 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1374 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1375 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1376 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1377
1378 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1379 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1380 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1381 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1382 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1383 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1384 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1385
1386 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1387 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1388 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1389 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1390 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1391 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1392 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1393
1394 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1395 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1396 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1397 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1398 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1399 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1400 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1401
1402 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1403 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1404 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1405 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1406 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1407 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1408 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1409
1410 /* IPSR16 */
1411 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1412 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1413
1414 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1415 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1416
1417 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1418 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1419 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1420
1421 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1422 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1423 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1424 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1425 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1426 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1427 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1428
1429 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1430 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1431 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1432 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1433 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1434 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1435 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1436
1437 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1438 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1439 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1440 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1441 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1442 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1443 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1444 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1445
1446 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1447 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1448 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1449 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1450 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1451 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1452 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1453
1454 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1455 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1456 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1457 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1458 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1459 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1460 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1461 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1462
1463 /* IPSR17 */
1464 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
1465
1466 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
1467 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1468 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1469 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1470 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1471
1472 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1473 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1474 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1475 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1476 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1477 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1478 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1479
1480 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1481 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1482 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1483 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1484 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1485 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1486
1487 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1488 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1489 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1490 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1491 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1492 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1493 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1494 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1495 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1496
1497 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1498 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1499 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1500 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1501 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1502 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1503 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1504 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1505 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1506
1507 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1508 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1509 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1510 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1511 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1512 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1513 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1514 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1515 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1516 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1517 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1518
1519 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1520 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1521 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1522 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1523 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1524 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1525 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1526 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1527 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1528
1529 /* IPSR18 */
1530 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1531 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1532 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1533 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1534 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1535 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1536 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1537 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1538 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1539
1540 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1541 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1542 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1543 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1544 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1545 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1546 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1547 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1548 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1549
1550 /*
1551 * Static pins can not be muxed between different functions but
1552 * still need mark entries in the pinmux list. Add each static
1553 * pin to the list without an associated function. The sh-pfc
1554 * core will do the right thing and skip trying to mux the pin
1555 * while still applying configuration to it.
1556 */
1557 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1558 PINMUX_STATIC
1559 #undef FM
1560 };
1561
1562 /*
1563 * Pins not associated with a GPIO port.
1564 */
1565 enum {
1566 GP_ASSIGN_LAST(),
1567 NOGP_ALL(),
1568 };
1569
1570 static const struct sh_pfc_pin pinmux_pins[] = {
1571 PINMUX_GPIO_GP_ALL(),
1572 PINMUX_NOGP_ALL(),
1573 };
1574
1575 /* - AUDIO CLOCK ------------------------------------------------------------ */
1576 static const unsigned int audio_clk_a_a_pins[] = {
1577 /* CLK A */
1578 RCAR_GP_PIN(6, 22),
1579 };
1580 static const unsigned int audio_clk_a_a_mux[] = {
1581 AUDIO_CLKA_A_MARK,
1582 };
1583 static const unsigned int audio_clk_a_b_pins[] = {
1584 /* CLK A */
1585 RCAR_GP_PIN(5, 4),
1586 };
1587 static const unsigned int audio_clk_a_b_mux[] = {
1588 AUDIO_CLKA_B_MARK,
1589 };
1590 static const unsigned int audio_clk_a_c_pins[] = {
1591 /* CLK A */
1592 RCAR_GP_PIN(5, 19),
1593 };
1594 static const unsigned int audio_clk_a_c_mux[] = {
1595 AUDIO_CLKA_C_MARK,
1596 };
1597 static const unsigned int audio_clk_b_a_pins[] = {
1598 /* CLK B */
1599 RCAR_GP_PIN(5, 12),
1600 };
1601 static const unsigned int audio_clk_b_a_mux[] = {
1602 AUDIO_CLKB_A_MARK,
1603 };
1604 static const unsigned int audio_clk_b_b_pins[] = {
1605 /* CLK B */
1606 RCAR_GP_PIN(6, 23),
1607 };
1608 static const unsigned int audio_clk_b_b_mux[] = {
1609 AUDIO_CLKB_B_MARK,
1610 };
1611 static const unsigned int audio_clk_c_a_pins[] = {
1612 /* CLK C */
1613 RCAR_GP_PIN(5, 21),
1614 };
1615 static const unsigned int audio_clk_c_a_mux[] = {
1616 AUDIO_CLKC_A_MARK,
1617 };
1618 static const unsigned int audio_clk_c_b_pins[] = {
1619 /* CLK C */
1620 RCAR_GP_PIN(5, 0),
1621 };
1622 static const unsigned int audio_clk_c_b_mux[] = {
1623 AUDIO_CLKC_B_MARK,
1624 };
1625 static const unsigned int audio_clkout_a_pins[] = {
1626 /* CLKOUT */
1627 RCAR_GP_PIN(5, 18),
1628 };
1629 static const unsigned int audio_clkout_a_mux[] = {
1630 AUDIO_CLKOUT_A_MARK,
1631 };
1632 static const unsigned int audio_clkout_b_pins[] = {
1633 /* CLKOUT */
1634 RCAR_GP_PIN(6, 28),
1635 };
1636 static const unsigned int audio_clkout_b_mux[] = {
1637 AUDIO_CLKOUT_B_MARK,
1638 };
1639 static const unsigned int audio_clkout_c_pins[] = {
1640 /* CLKOUT */
1641 RCAR_GP_PIN(5, 3),
1642 };
1643 static const unsigned int audio_clkout_c_mux[] = {
1644 AUDIO_CLKOUT_C_MARK,
1645 };
1646 static const unsigned int audio_clkout_d_pins[] = {
1647 /* CLKOUT */
1648 RCAR_GP_PIN(5, 21),
1649 };
1650 static const unsigned int audio_clkout_d_mux[] = {
1651 AUDIO_CLKOUT_D_MARK,
1652 };
1653 static const unsigned int audio_clkout1_a_pins[] = {
1654 /* CLKOUT1 */
1655 RCAR_GP_PIN(5, 15),
1656 };
1657 static const unsigned int audio_clkout1_a_mux[] = {
1658 AUDIO_CLKOUT1_A_MARK,
1659 };
1660 static const unsigned int audio_clkout1_b_pins[] = {
1661 /* CLKOUT1 */
1662 RCAR_GP_PIN(6, 29),
1663 };
1664 static const unsigned int audio_clkout1_b_mux[] = {
1665 AUDIO_CLKOUT1_B_MARK,
1666 };
1667 static const unsigned int audio_clkout2_a_pins[] = {
1668 /* CLKOUT2 */
1669 RCAR_GP_PIN(5, 16),
1670 };
1671 static const unsigned int audio_clkout2_a_mux[] = {
1672 AUDIO_CLKOUT2_A_MARK,
1673 };
1674 static const unsigned int audio_clkout2_b_pins[] = {
1675 /* CLKOUT2 */
1676 RCAR_GP_PIN(6, 30),
1677 };
1678 static const unsigned int audio_clkout2_b_mux[] = {
1679 AUDIO_CLKOUT2_B_MARK,
1680 };
1681
1682 static const unsigned int audio_clkout3_a_pins[] = {
1683 /* CLKOUT3 */
1684 RCAR_GP_PIN(5, 19),
1685 };
1686 static const unsigned int audio_clkout3_a_mux[] = {
1687 AUDIO_CLKOUT3_A_MARK,
1688 };
1689 static const unsigned int audio_clkout3_b_pins[] = {
1690 /* CLKOUT3 */
1691 RCAR_GP_PIN(6, 31),
1692 };
1693 static const unsigned int audio_clkout3_b_mux[] = {
1694 AUDIO_CLKOUT3_B_MARK,
1695 };
1696
1697 /* - EtherAVB --------------------------------------------------------------- */
1698 static const unsigned int avb_link_pins[] = {
1699 /* AVB_LINK */
1700 RCAR_GP_PIN(2, 12),
1701 };
1702 static const unsigned int avb_link_mux[] = {
1703 AVB_LINK_MARK,
1704 };
1705 static const unsigned int avb_magic_pins[] = {
1706 /* AVB_MAGIC_ */
1707 RCAR_GP_PIN(2, 10),
1708 };
1709 static const unsigned int avb_magic_mux[] = {
1710 AVB_MAGIC_MARK,
1711 };
1712 static const unsigned int avb_phy_int_pins[] = {
1713 /* AVB_PHY_INT */
1714 RCAR_GP_PIN(2, 11),
1715 };
1716 static const unsigned int avb_phy_int_mux[] = {
1717 AVB_PHY_INT_MARK,
1718 };
1719 static const unsigned int avb_mdio_pins[] = {
1720 /* AVB_MDC, AVB_MDIO */
1721 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1722 };
1723 static const unsigned int avb_mdio_mux[] = {
1724 AVB_MDC_MARK, AVB_MDIO_MARK,
1725 };
1726 static const unsigned int avb_mii_pins[] = {
1727 /*
1728 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1729 * AVB_TD1, AVB_TD2, AVB_TD3,
1730 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1731 * AVB_RD1, AVB_RD2, AVB_RD3,
1732 * AVB_TXCREFCLK
1733 */
1734 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1735 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1736 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1737 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1738 PIN_AVB_TXCREFCLK,
1739
1740 };
1741 static const unsigned int avb_mii_mux[] = {
1742 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1743 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1744 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1745 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1746 AVB_TXCREFCLK_MARK,
1747 };
1748 static const unsigned int avb_avtp_pps_pins[] = {
1749 /* AVB_AVTP_PPS */
1750 RCAR_GP_PIN(2, 6),
1751 };
1752 static const unsigned int avb_avtp_pps_mux[] = {
1753 AVB_AVTP_PPS_MARK,
1754 };
1755 static const unsigned int avb_avtp_match_a_pins[] = {
1756 /* AVB_AVTP_MATCH_A */
1757 RCAR_GP_PIN(2, 13),
1758 };
1759 static const unsigned int avb_avtp_match_a_mux[] = {
1760 AVB_AVTP_MATCH_A_MARK,
1761 };
1762 static const unsigned int avb_avtp_capture_a_pins[] = {
1763 /* AVB_AVTP_CAPTURE_A */
1764 RCAR_GP_PIN(2, 14),
1765 };
1766 static const unsigned int avb_avtp_capture_a_mux[] = {
1767 AVB_AVTP_CAPTURE_A_MARK,
1768 };
1769 static const unsigned int avb_avtp_match_b_pins[] = {
1770 /* AVB_AVTP_MATCH_B */
1771 RCAR_GP_PIN(1, 8),
1772 };
1773 static const unsigned int avb_avtp_match_b_mux[] = {
1774 AVB_AVTP_MATCH_B_MARK,
1775 };
1776 static const unsigned int avb_avtp_capture_b_pins[] = {
1777 /* AVB_AVTP_CAPTURE_B */
1778 RCAR_GP_PIN(1, 11),
1779 };
1780 static const unsigned int avb_avtp_capture_b_mux[] = {
1781 AVB_AVTP_CAPTURE_B_MARK,
1782 };
1783
1784 /* - CAN ------------------------------------------------------------------ */
1785 static const unsigned int can0_data_a_pins[] = {
1786 /* TX, RX */
1787 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1788 };
1789
1790 static const unsigned int can0_data_a_mux[] = {
1791 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1792 };
1793
1794 static const unsigned int can0_data_b_pins[] = {
1795 /* TX, RX */
1796 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1797 };
1798
1799 static const unsigned int can0_data_b_mux[] = {
1800 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1801 };
1802
1803 static const unsigned int can1_data_pins[] = {
1804 /* TX, RX */
1805 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1806 };
1807
1808 static const unsigned int can1_data_mux[] = {
1809 CAN1_TX_MARK, CAN1_RX_MARK,
1810 };
1811
1812 /* - CAN Clock -------------------------------------------------------------- */
1813 static const unsigned int can_clk_pins[] = {
1814 /* CLK */
1815 RCAR_GP_PIN(1, 25),
1816 };
1817
1818 static const unsigned int can_clk_mux[] = {
1819 CAN_CLK_MARK,
1820 };
1821
1822 /* - CAN FD --------------------------------------------------------------- */
1823 static const unsigned int canfd0_data_a_pins[] = {
1824 /* TX, RX */
1825 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1826 };
1827
1828 static const unsigned int canfd0_data_a_mux[] = {
1829 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1830 };
1831
1832 static const unsigned int canfd0_data_b_pins[] = {
1833 /* TX, RX */
1834 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1835 };
1836
1837 static const unsigned int canfd0_data_b_mux[] = {
1838 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1839 };
1840
1841 static const unsigned int canfd1_data_pins[] = {
1842 /* TX, RX */
1843 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1844 };
1845
1846 static const unsigned int canfd1_data_mux[] = {
1847 CANFD1_TX_MARK, CANFD1_RX_MARK,
1848 };
1849
1850 /* - DRIF0 --------------------------------------------------------------- */
1851 static const unsigned int drif0_ctrl_a_pins[] = {
1852 /* CLK, SYNC */
1853 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1854 };
1855
1856 static const unsigned int drif0_ctrl_a_mux[] = {
1857 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1858 };
1859
1860 static const unsigned int drif0_data0_a_pins[] = {
1861 /* D0 */
1862 RCAR_GP_PIN(6, 10),
1863 };
1864
1865 static const unsigned int drif0_data0_a_mux[] = {
1866 RIF0_D0_A_MARK,
1867 };
1868
1869 static const unsigned int drif0_data1_a_pins[] = {
1870 /* D1 */
1871 RCAR_GP_PIN(6, 7),
1872 };
1873
1874 static const unsigned int drif0_data1_a_mux[] = {
1875 RIF0_D1_A_MARK,
1876 };
1877
1878 static const unsigned int drif0_ctrl_b_pins[] = {
1879 /* CLK, SYNC */
1880 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1881 };
1882
1883 static const unsigned int drif0_ctrl_b_mux[] = {
1884 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1885 };
1886
1887 static const unsigned int drif0_data0_b_pins[] = {
1888 /* D0 */
1889 RCAR_GP_PIN(5, 1),
1890 };
1891
1892 static const unsigned int drif0_data0_b_mux[] = {
1893 RIF0_D0_B_MARK,
1894 };
1895
1896 static const unsigned int drif0_data1_b_pins[] = {
1897 /* D1 */
1898 RCAR_GP_PIN(5, 2),
1899 };
1900
1901 static const unsigned int drif0_data1_b_mux[] = {
1902 RIF0_D1_B_MARK,
1903 };
1904
1905 static const unsigned int drif0_ctrl_c_pins[] = {
1906 /* CLK, SYNC */
1907 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1908 };
1909
1910 static const unsigned int drif0_ctrl_c_mux[] = {
1911 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1912 };
1913
1914 static const unsigned int drif0_data0_c_pins[] = {
1915 /* D0 */
1916 RCAR_GP_PIN(5, 13),
1917 };
1918
1919 static const unsigned int drif0_data0_c_mux[] = {
1920 RIF0_D0_C_MARK,
1921 };
1922
1923 static const unsigned int drif0_data1_c_pins[] = {
1924 /* D1 */
1925 RCAR_GP_PIN(5, 14),
1926 };
1927
1928 static const unsigned int drif0_data1_c_mux[] = {
1929 RIF0_D1_C_MARK,
1930 };
1931
1932 /* - DRIF1 --------------------------------------------------------------- */
1933 static const unsigned int drif1_ctrl_a_pins[] = {
1934 /* CLK, SYNC */
1935 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1936 };
1937
1938 static const unsigned int drif1_ctrl_a_mux[] = {
1939 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1940 };
1941
1942 static const unsigned int drif1_data0_a_pins[] = {
1943 /* D0 */
1944 RCAR_GP_PIN(6, 19),
1945 };
1946
1947 static const unsigned int drif1_data0_a_mux[] = {
1948 RIF1_D0_A_MARK,
1949 };
1950
1951 static const unsigned int drif1_data1_a_pins[] = {
1952 /* D1 */
1953 RCAR_GP_PIN(6, 20),
1954 };
1955
1956 static const unsigned int drif1_data1_a_mux[] = {
1957 RIF1_D1_A_MARK,
1958 };
1959
1960 static const unsigned int drif1_ctrl_b_pins[] = {
1961 /* CLK, SYNC */
1962 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1963 };
1964
1965 static const unsigned int drif1_ctrl_b_mux[] = {
1966 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1967 };
1968
1969 static const unsigned int drif1_data0_b_pins[] = {
1970 /* D0 */
1971 RCAR_GP_PIN(5, 7),
1972 };
1973
1974 static const unsigned int drif1_data0_b_mux[] = {
1975 RIF1_D0_B_MARK,
1976 };
1977
1978 static const unsigned int drif1_data1_b_pins[] = {
1979 /* D1 */
1980 RCAR_GP_PIN(5, 8),
1981 };
1982
1983 static const unsigned int drif1_data1_b_mux[] = {
1984 RIF1_D1_B_MARK,
1985 };
1986
1987 static const unsigned int drif1_ctrl_c_pins[] = {
1988 /* CLK, SYNC */
1989 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1990 };
1991
1992 static const unsigned int drif1_ctrl_c_mux[] = {
1993 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1994 };
1995
1996 static const unsigned int drif1_data0_c_pins[] = {
1997 /* D0 */
1998 RCAR_GP_PIN(5, 6),
1999 };
2000
2001 static const unsigned int drif1_data0_c_mux[] = {
2002 RIF1_D0_C_MARK,
2003 };
2004
2005 static const unsigned int drif1_data1_c_pins[] = {
2006 /* D1 */
2007 RCAR_GP_PIN(5, 10),
2008 };
2009
2010 static const unsigned int drif1_data1_c_mux[] = {
2011 RIF1_D1_C_MARK,
2012 };
2013
2014 /* - DRIF2 --------------------------------------------------------------- */
2015 static const unsigned int drif2_ctrl_a_pins[] = {
2016 /* CLK, SYNC */
2017 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2018 };
2019
2020 static const unsigned int drif2_ctrl_a_mux[] = {
2021 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
2022 };
2023
2024 static const unsigned int drif2_data0_a_pins[] = {
2025 /* D0 */
2026 RCAR_GP_PIN(6, 7),
2027 };
2028
2029 static const unsigned int drif2_data0_a_mux[] = {
2030 RIF2_D0_A_MARK,
2031 };
2032
2033 static const unsigned int drif2_data1_a_pins[] = {
2034 /* D1 */
2035 RCAR_GP_PIN(6, 10),
2036 };
2037
2038 static const unsigned int drif2_data1_a_mux[] = {
2039 RIF2_D1_A_MARK,
2040 };
2041
2042 static const unsigned int drif2_ctrl_b_pins[] = {
2043 /* CLK, SYNC */
2044 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2045 };
2046
2047 static const unsigned int drif2_ctrl_b_mux[] = {
2048 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
2049 };
2050
2051 static const unsigned int drif2_data0_b_pins[] = {
2052 /* D0 */
2053 RCAR_GP_PIN(6, 30),
2054 };
2055
2056 static const unsigned int drif2_data0_b_mux[] = {
2057 RIF2_D0_B_MARK,
2058 };
2059
2060 static const unsigned int drif2_data1_b_pins[] = {
2061 /* D1 */
2062 RCAR_GP_PIN(6, 31),
2063 };
2064
2065 static const unsigned int drif2_data1_b_mux[] = {
2066 RIF2_D1_B_MARK,
2067 };
2068
2069 /* - DRIF3 --------------------------------------------------------------- */
2070 static const unsigned int drif3_ctrl_a_pins[] = {
2071 /* CLK, SYNC */
2072 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2073 };
2074
2075 static const unsigned int drif3_ctrl_a_mux[] = {
2076 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2077 };
2078
2079 static const unsigned int drif3_data0_a_pins[] = {
2080 /* D0 */
2081 RCAR_GP_PIN(6, 19),
2082 };
2083
2084 static const unsigned int drif3_data0_a_mux[] = {
2085 RIF3_D0_A_MARK,
2086 };
2087
2088 static const unsigned int drif3_data1_a_pins[] = {
2089 /* D1 */
2090 RCAR_GP_PIN(6, 20),
2091 };
2092
2093 static const unsigned int drif3_data1_a_mux[] = {
2094 RIF3_D1_A_MARK,
2095 };
2096
2097 static const unsigned int drif3_ctrl_b_pins[] = {
2098 /* CLK, SYNC */
2099 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2100 };
2101
2102 static const unsigned int drif3_ctrl_b_mux[] = {
2103 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2104 };
2105
2106 static const unsigned int drif3_data0_b_pins[] = {
2107 /* D0 */
2108 RCAR_GP_PIN(6, 28),
2109 };
2110
2111 static const unsigned int drif3_data0_b_mux[] = {
2112 RIF3_D0_B_MARK,
2113 };
2114
2115 static const unsigned int drif3_data1_b_pins[] = {
2116 /* D1 */
2117 RCAR_GP_PIN(6, 29),
2118 };
2119
2120 static const unsigned int drif3_data1_b_mux[] = {
2121 RIF3_D1_B_MARK,
2122 };
2123
2124 /* - DU --------------------------------------------------------------------- */
2125 static const unsigned int du_rgb666_pins[] = {
2126 /* R[7:2], G[7:2], B[7:2] */
2127 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2128 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2129 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2130 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2131 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2132 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2133 };
2134
2135 static const unsigned int du_rgb666_mux[] = {
2136 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2137 DU_DR3_MARK, DU_DR2_MARK,
2138 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2139 DU_DG3_MARK, DU_DG2_MARK,
2140 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2141 DU_DB3_MARK, DU_DB2_MARK,
2142 };
2143
2144 static const unsigned int du_rgb888_pins[] = {
2145 /* R[7:0], G[7:0], B[7:0] */
2146 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2147 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2148 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2149 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2150 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2151 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2152 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2153 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2154 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2155 };
2156
2157 static const unsigned int du_rgb888_mux[] = {
2158 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2159 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2160 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2161 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2162 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2163 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2164 };
2165
2166 static const unsigned int du_clk_out_0_pins[] = {
2167 /* CLKOUT */
2168 RCAR_GP_PIN(1, 27),
2169 };
2170
2171 static const unsigned int du_clk_out_0_mux[] = {
2172 DU_DOTCLKOUT0_MARK
2173 };
2174
2175 static const unsigned int du_clk_out_1_pins[] = {
2176 /* CLKOUT */
2177 RCAR_GP_PIN(2, 3),
2178 };
2179
2180 static const unsigned int du_clk_out_1_mux[] = {
2181 DU_DOTCLKOUT1_MARK
2182 };
2183
2184 static const unsigned int du_sync_pins[] = {
2185 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2186 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2187 };
2188
2189 static const unsigned int du_sync_mux[] = {
2190 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2191 };
2192
2193 static const unsigned int du_oddf_pins[] = {
2194 /* EXDISP/EXODDF/EXCDE */
2195 RCAR_GP_PIN(2, 2),
2196 };
2197
2198 static const unsigned int du_oddf_mux[] = {
2199 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2200 };
2201
2202 static const unsigned int du_cde_pins[] = {
2203 /* CDE */
2204 RCAR_GP_PIN(2, 0),
2205 };
2206
2207 static const unsigned int du_cde_mux[] = {
2208 DU_CDE_MARK,
2209 };
2210
2211 static const unsigned int du_disp_pins[] = {
2212 /* DISP */
2213 RCAR_GP_PIN(2, 1),
2214 };
2215
2216 static const unsigned int du_disp_mux[] = {
2217 DU_DISP_MARK,
2218 };
2219
2220 /* - HSCIF0 ----------------------------------------------------------------- */
2221 static const unsigned int hscif0_data_pins[] = {
2222 /* RX, TX */
2223 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2224 };
2225
2226 static const unsigned int hscif0_data_mux[] = {
2227 HRX0_MARK, HTX0_MARK,
2228 };
2229
2230 static const unsigned int hscif0_clk_pins[] = {
2231 /* SCK */
2232 RCAR_GP_PIN(5, 12),
2233 };
2234
2235 static const unsigned int hscif0_clk_mux[] = {
2236 HSCK0_MARK,
2237 };
2238
2239 static const unsigned int hscif0_ctrl_pins[] = {
2240 /* RTS, CTS */
2241 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2242 };
2243
2244 static const unsigned int hscif0_ctrl_mux[] = {
2245 HRTS0_N_MARK, HCTS0_N_MARK,
2246 };
2247
2248 /* - HSCIF1 ----------------------------------------------------------------- */
2249 static const unsigned int hscif1_data_a_pins[] = {
2250 /* RX, TX */
2251 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2252 };
2253
2254 static const unsigned int hscif1_data_a_mux[] = {
2255 HRX1_A_MARK, HTX1_A_MARK,
2256 };
2257
2258 static const unsigned int hscif1_clk_a_pins[] = {
2259 /* SCK */
2260 RCAR_GP_PIN(6, 21),
2261 };
2262
2263 static const unsigned int hscif1_clk_a_mux[] = {
2264 HSCK1_A_MARK,
2265 };
2266
2267 static const unsigned int hscif1_ctrl_a_pins[] = {
2268 /* RTS, CTS */
2269 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2270 };
2271
2272 static const unsigned int hscif1_ctrl_a_mux[] = {
2273 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2274 };
2275
2276 static const unsigned int hscif1_data_b_pins[] = {
2277 /* RX, TX */
2278 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2279 };
2280
2281 static const unsigned int hscif1_data_b_mux[] = {
2282 HRX1_B_MARK, HTX1_B_MARK,
2283 };
2284
2285 static const unsigned int hscif1_clk_b_pins[] = {
2286 /* SCK */
2287 RCAR_GP_PIN(5, 0),
2288 };
2289
2290 static const unsigned int hscif1_clk_b_mux[] = {
2291 HSCK1_B_MARK,
2292 };
2293
2294 static const unsigned int hscif1_ctrl_b_pins[] = {
2295 /* RTS, CTS */
2296 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2297 };
2298
2299 static const unsigned int hscif1_ctrl_b_mux[] = {
2300 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2301 };
2302
2303 /* - HSCIF2 ----------------------------------------------------------------- */
2304 static const unsigned int hscif2_data_a_pins[] = {
2305 /* RX, TX */
2306 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2307 };
2308
2309 static const unsigned int hscif2_data_a_mux[] = {
2310 HRX2_A_MARK, HTX2_A_MARK,
2311 };
2312
2313 static const unsigned int hscif2_clk_a_pins[] = {
2314 /* SCK */
2315 RCAR_GP_PIN(6, 10),
2316 };
2317
2318 static const unsigned int hscif2_clk_a_mux[] = {
2319 HSCK2_A_MARK,
2320 };
2321
2322 static const unsigned int hscif2_ctrl_a_pins[] = {
2323 /* RTS, CTS */
2324 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2325 };
2326
2327 static const unsigned int hscif2_ctrl_a_mux[] = {
2328 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2329 };
2330
2331 static const unsigned int hscif2_data_b_pins[] = {
2332 /* RX, TX */
2333 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2334 };
2335
2336 static const unsigned int hscif2_data_b_mux[] = {
2337 HRX2_B_MARK, HTX2_B_MARK,
2338 };
2339
2340 static const unsigned int hscif2_clk_b_pins[] = {
2341 /* SCK */
2342 RCAR_GP_PIN(6, 21),
2343 };
2344
2345 static const unsigned int hscif2_clk_b_mux[] = {
2346 HSCK2_B_MARK,
2347 };
2348
2349 static const unsigned int hscif2_ctrl_b_pins[] = {
2350 /* RTS, CTS */
2351 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2352 };
2353
2354 static const unsigned int hscif2_ctrl_b_mux[] = {
2355 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2356 };
2357
2358 static const unsigned int hscif2_data_c_pins[] = {
2359 /* RX, TX */
2360 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2361 };
2362
2363 static const unsigned int hscif2_data_c_mux[] = {
2364 HRX2_C_MARK, HTX2_C_MARK,
2365 };
2366
2367 static const unsigned int hscif2_clk_c_pins[] = {
2368 /* SCK */
2369 RCAR_GP_PIN(6, 24),
2370 };
2371
2372 static const unsigned int hscif2_clk_c_mux[] = {
2373 HSCK2_C_MARK,
2374 };
2375
2376 static const unsigned int hscif2_ctrl_c_pins[] = {
2377 /* RTS, CTS */
2378 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2379 };
2380
2381 static const unsigned int hscif2_ctrl_c_mux[] = {
2382 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2383 };
2384
2385 /* - HSCIF3 ----------------------------------------------------------------- */
2386 static const unsigned int hscif3_data_a_pins[] = {
2387 /* RX, TX */
2388 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2389 };
2390
2391 static const unsigned int hscif3_data_a_mux[] = {
2392 HRX3_A_MARK, HTX3_A_MARK,
2393 };
2394
2395 static const unsigned int hscif3_clk_pins[] = {
2396 /* SCK */
2397 RCAR_GP_PIN(1, 22),
2398 };
2399
2400 static const unsigned int hscif3_clk_mux[] = {
2401 HSCK3_MARK,
2402 };
2403
2404 static const unsigned int hscif3_ctrl_pins[] = {
2405 /* RTS, CTS */
2406 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2407 };
2408
2409 static const unsigned int hscif3_ctrl_mux[] = {
2410 HRTS3_N_MARK, HCTS3_N_MARK,
2411 };
2412
2413 static const unsigned int hscif3_data_b_pins[] = {
2414 /* RX, TX */
2415 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2416 };
2417
2418 static const unsigned int hscif3_data_b_mux[] = {
2419 HRX3_B_MARK, HTX3_B_MARK,
2420 };
2421
2422 static const unsigned int hscif3_data_c_pins[] = {
2423 /* RX, TX */
2424 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2425 };
2426
2427 static const unsigned int hscif3_data_c_mux[] = {
2428 HRX3_C_MARK, HTX3_C_MARK,
2429 };
2430
2431 static const unsigned int hscif3_data_d_pins[] = {
2432 /* RX, TX */
2433 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2434 };
2435
2436 static const unsigned int hscif3_data_d_mux[] = {
2437 HRX3_D_MARK, HTX3_D_MARK,
2438 };
2439
2440 /* - HSCIF4 ----------------------------------------------------------------- */
2441 static const unsigned int hscif4_data_a_pins[] = {
2442 /* RX, TX */
2443 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2444 };
2445
2446 static const unsigned int hscif4_data_a_mux[] = {
2447 HRX4_A_MARK, HTX4_A_MARK,
2448 };
2449
2450 static const unsigned int hscif4_clk_pins[] = {
2451 /* SCK */
2452 RCAR_GP_PIN(1, 11),
2453 };
2454
2455 static const unsigned int hscif4_clk_mux[] = {
2456 HSCK4_MARK,
2457 };
2458
2459 static const unsigned int hscif4_ctrl_pins[] = {
2460 /* RTS, CTS */
2461 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2462 };
2463
2464 static const unsigned int hscif4_ctrl_mux[] = {
2465 HRTS4_N_MARK, HCTS4_N_MARK,
2466 };
2467
2468 static const unsigned int hscif4_data_b_pins[] = {
2469 /* RX, TX */
2470 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2471 };
2472
2473 static const unsigned int hscif4_data_b_mux[] = {
2474 HRX4_B_MARK, HTX4_B_MARK,
2475 };
2476
2477 /* - I2C -------------------------------------------------------------------- */
2478 static const unsigned int i2c0_pins[] = {
2479 /* SCL, SDA */
2480 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2481 };
2482
2483 static const unsigned int i2c0_mux[] = {
2484 SCL0_MARK, SDA0_MARK,
2485 };
2486
2487 static const unsigned int i2c1_a_pins[] = {
2488 /* SDA, SCL */
2489 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2490 };
2491
2492 static const unsigned int i2c1_a_mux[] = {
2493 SDA1_A_MARK, SCL1_A_MARK,
2494 };
2495
2496 static const unsigned int i2c1_b_pins[] = {
2497 /* SDA, SCL */
2498 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2499 };
2500
2501 static const unsigned int i2c1_b_mux[] = {
2502 SDA1_B_MARK, SCL1_B_MARK,
2503 };
2504
2505 static const unsigned int i2c2_a_pins[] = {
2506 /* SDA, SCL */
2507 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2508 };
2509
2510 static const unsigned int i2c2_a_mux[] = {
2511 SDA2_A_MARK, SCL2_A_MARK,
2512 };
2513
2514 static const unsigned int i2c2_b_pins[] = {
2515 /* SDA, SCL */
2516 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2517 };
2518
2519 static const unsigned int i2c2_b_mux[] = {
2520 SDA2_B_MARK, SCL2_B_MARK,
2521 };
2522
2523 static const unsigned int i2c3_pins[] = {
2524 /* SCL, SDA */
2525 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2526 };
2527
2528 static const unsigned int i2c3_mux[] = {
2529 SCL3_MARK, SDA3_MARK,
2530 };
2531
2532 static const unsigned int i2c5_pins[] = {
2533 /* SCL, SDA */
2534 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2535 };
2536
2537 static const unsigned int i2c5_mux[] = {
2538 SCL5_MARK, SDA5_MARK,
2539 };
2540
2541 static const unsigned int i2c6_a_pins[] = {
2542 /* SDA, SCL */
2543 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2544 };
2545
2546 static const unsigned int i2c6_a_mux[] = {
2547 SDA6_A_MARK, SCL6_A_MARK,
2548 };
2549
2550 static const unsigned int i2c6_b_pins[] = {
2551 /* SDA, SCL */
2552 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2553 };
2554
2555 static const unsigned int i2c6_b_mux[] = {
2556 SDA6_B_MARK, SCL6_B_MARK,
2557 };
2558
2559 static const unsigned int i2c6_c_pins[] = {
2560 /* SDA, SCL */
2561 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2562 };
2563
2564 static const unsigned int i2c6_c_mux[] = {
2565 SDA6_C_MARK, SCL6_C_MARK,
2566 };
2567
2568 /* - INTC-EX ---------------------------------------------------------------- */
2569 static const unsigned int intc_ex_irq0_pins[] = {
2570 /* IRQ0 */
2571 RCAR_GP_PIN(2, 0),
2572 };
2573 static const unsigned int intc_ex_irq0_mux[] = {
2574 IRQ0_MARK,
2575 };
2576 static const unsigned int intc_ex_irq1_pins[] = {
2577 /* IRQ1 */
2578 RCAR_GP_PIN(2, 1),
2579 };
2580 static const unsigned int intc_ex_irq1_mux[] = {
2581 IRQ1_MARK,
2582 };
2583 static const unsigned int intc_ex_irq2_pins[] = {
2584 /* IRQ2 */
2585 RCAR_GP_PIN(2, 2),
2586 };
2587 static const unsigned int intc_ex_irq2_mux[] = {
2588 IRQ2_MARK,
2589 };
2590 static const unsigned int intc_ex_irq3_pins[] = {
2591 /* IRQ3 */
2592 RCAR_GP_PIN(2, 3),
2593 };
2594 static const unsigned int intc_ex_irq3_mux[] = {
2595 IRQ3_MARK,
2596 };
2597 static const unsigned int intc_ex_irq4_pins[] = {
2598 /* IRQ4 */
2599 RCAR_GP_PIN(2, 4),
2600 };
2601 static const unsigned int intc_ex_irq4_mux[] = {
2602 IRQ4_MARK,
2603 };
2604 static const unsigned int intc_ex_irq5_pins[] = {
2605 /* IRQ5 */
2606 RCAR_GP_PIN(2, 5),
2607 };
2608 static const unsigned int intc_ex_irq5_mux[] = {
2609 IRQ5_MARK,
2610 };
2611
2612 /* - MSIOF0 ----------------------------------------------------------------- */
2613 static const unsigned int msiof0_clk_pins[] = {
2614 /* SCK */
2615 RCAR_GP_PIN(5, 17),
2616 };
2617 static const unsigned int msiof0_clk_mux[] = {
2618 MSIOF0_SCK_MARK,
2619 };
2620 static const unsigned int msiof0_sync_pins[] = {
2621 /* SYNC */
2622 RCAR_GP_PIN(5, 18),
2623 };
2624 static const unsigned int msiof0_sync_mux[] = {
2625 MSIOF0_SYNC_MARK,
2626 };
2627 static const unsigned int msiof0_ss1_pins[] = {
2628 /* SS1 */
2629 RCAR_GP_PIN(5, 19),
2630 };
2631 static const unsigned int msiof0_ss1_mux[] = {
2632 MSIOF0_SS1_MARK,
2633 };
2634 static const unsigned int msiof0_ss2_pins[] = {
2635 /* SS2 */
2636 RCAR_GP_PIN(5, 21),
2637 };
2638 static const unsigned int msiof0_ss2_mux[] = {
2639 MSIOF0_SS2_MARK,
2640 };
2641 static const unsigned int msiof0_txd_pins[] = {
2642 /* TXD */
2643 RCAR_GP_PIN(5, 20),
2644 };
2645 static const unsigned int msiof0_txd_mux[] = {
2646 MSIOF0_TXD_MARK,
2647 };
2648 static const unsigned int msiof0_rxd_pins[] = {
2649 /* RXD */
2650 RCAR_GP_PIN(5, 22),
2651 };
2652 static const unsigned int msiof0_rxd_mux[] = {
2653 MSIOF0_RXD_MARK,
2654 };
2655 /* - MSIOF1 ----------------------------------------------------------------- */
2656 static const unsigned int msiof1_clk_a_pins[] = {
2657 /* SCK */
2658 RCAR_GP_PIN(6, 8),
2659 };
2660 static const unsigned int msiof1_clk_a_mux[] = {
2661 MSIOF1_SCK_A_MARK,
2662 };
2663 static const unsigned int msiof1_sync_a_pins[] = {
2664 /* SYNC */
2665 RCAR_GP_PIN(6, 9),
2666 };
2667 static const unsigned int msiof1_sync_a_mux[] = {
2668 MSIOF1_SYNC_A_MARK,
2669 };
2670 static const unsigned int msiof1_ss1_a_pins[] = {
2671 /* SS1 */
2672 RCAR_GP_PIN(6, 5),
2673 };
2674 static const unsigned int msiof1_ss1_a_mux[] = {
2675 MSIOF1_SS1_A_MARK,
2676 };
2677 static const unsigned int msiof1_ss2_a_pins[] = {
2678 /* SS2 */
2679 RCAR_GP_PIN(6, 6),
2680 };
2681 static const unsigned int msiof1_ss2_a_mux[] = {
2682 MSIOF1_SS2_A_MARK,
2683 };
2684 static const unsigned int msiof1_txd_a_pins[] = {
2685 /* TXD */
2686 RCAR_GP_PIN(6, 7),
2687 };
2688 static const unsigned int msiof1_txd_a_mux[] = {
2689 MSIOF1_TXD_A_MARK,
2690 };
2691 static const unsigned int msiof1_rxd_a_pins[] = {
2692 /* RXD */
2693 RCAR_GP_PIN(6, 10),
2694 };
2695 static const unsigned int msiof1_rxd_a_mux[] = {
2696 MSIOF1_RXD_A_MARK,
2697 };
2698 static const unsigned int msiof1_clk_b_pins[] = {
2699 /* SCK */
2700 RCAR_GP_PIN(5, 9),
2701 };
2702 static const unsigned int msiof1_clk_b_mux[] = {
2703 MSIOF1_SCK_B_MARK,
2704 };
2705 static const unsigned int msiof1_sync_b_pins[] = {
2706 /* SYNC */
2707 RCAR_GP_PIN(5, 3),
2708 };
2709 static const unsigned int msiof1_sync_b_mux[] = {
2710 MSIOF1_SYNC_B_MARK,
2711 };
2712 static const unsigned int msiof1_ss1_b_pins[] = {
2713 /* SS1 */
2714 RCAR_GP_PIN(5, 4),
2715 };
2716 static const unsigned int msiof1_ss1_b_mux[] = {
2717 MSIOF1_SS1_B_MARK,
2718 };
2719 static const unsigned int msiof1_ss2_b_pins[] = {
2720 /* SS2 */
2721 RCAR_GP_PIN(5, 0),
2722 };
2723 static const unsigned int msiof1_ss2_b_mux[] = {
2724 MSIOF1_SS2_B_MARK,
2725 };
2726 static const unsigned int msiof1_txd_b_pins[] = {
2727 /* TXD */
2728 RCAR_GP_PIN(5, 8),
2729 };
2730 static const unsigned int msiof1_txd_b_mux[] = {
2731 MSIOF1_TXD_B_MARK,
2732 };
2733 static const unsigned int msiof1_rxd_b_pins[] = {
2734 /* RXD */
2735 RCAR_GP_PIN(5, 7),
2736 };
2737 static const unsigned int msiof1_rxd_b_mux[] = {
2738 MSIOF1_RXD_B_MARK,
2739 };
2740 static const unsigned int msiof1_clk_c_pins[] = {
2741 /* SCK */
2742 RCAR_GP_PIN(6, 17),
2743 };
2744 static const unsigned int msiof1_clk_c_mux[] = {
2745 MSIOF1_SCK_C_MARK,
2746 };
2747 static const unsigned int msiof1_sync_c_pins[] = {
2748 /* SYNC */
2749 RCAR_GP_PIN(6, 18),
2750 };
2751 static const unsigned int msiof1_sync_c_mux[] = {
2752 MSIOF1_SYNC_C_MARK,
2753 };
2754 static const unsigned int msiof1_ss1_c_pins[] = {
2755 /* SS1 */
2756 RCAR_GP_PIN(6, 21),
2757 };
2758 static const unsigned int msiof1_ss1_c_mux[] = {
2759 MSIOF1_SS1_C_MARK,
2760 };
2761 static const unsigned int msiof1_ss2_c_pins[] = {
2762 /* SS2 */
2763 RCAR_GP_PIN(6, 27),
2764 };
2765 static const unsigned int msiof1_ss2_c_mux[] = {
2766 MSIOF1_SS2_C_MARK,
2767 };
2768 static const unsigned int msiof1_txd_c_pins[] = {
2769 /* TXD */
2770 RCAR_GP_PIN(6, 20),
2771 };
2772 static const unsigned int msiof1_txd_c_mux[] = {
2773 MSIOF1_TXD_C_MARK,
2774 };
2775 static const unsigned int msiof1_rxd_c_pins[] = {
2776 /* RXD */
2777 RCAR_GP_PIN(6, 19),
2778 };
2779 static const unsigned int msiof1_rxd_c_mux[] = {
2780 MSIOF1_RXD_C_MARK,
2781 };
2782 static const unsigned int msiof1_clk_d_pins[] = {
2783 /* SCK */
2784 RCAR_GP_PIN(5, 12),
2785 };
2786 static const unsigned int msiof1_clk_d_mux[] = {
2787 MSIOF1_SCK_D_MARK,
2788 };
2789 static const unsigned int msiof1_sync_d_pins[] = {
2790 /* SYNC */
2791 RCAR_GP_PIN(5, 15),
2792 };
2793 static const unsigned int msiof1_sync_d_mux[] = {
2794 MSIOF1_SYNC_D_MARK,
2795 };
2796 static const unsigned int msiof1_ss1_d_pins[] = {
2797 /* SS1 */
2798 RCAR_GP_PIN(5, 16),
2799 };
2800 static const unsigned int msiof1_ss1_d_mux[] = {
2801 MSIOF1_SS1_D_MARK,
2802 };
2803 static const unsigned int msiof1_ss2_d_pins[] = {
2804 /* SS2 */
2805 RCAR_GP_PIN(5, 21),
2806 };
2807 static const unsigned int msiof1_ss2_d_mux[] = {
2808 MSIOF1_SS2_D_MARK,
2809 };
2810 static const unsigned int msiof1_txd_d_pins[] = {
2811 /* TXD */
2812 RCAR_GP_PIN(5, 14),
2813 };
2814 static const unsigned int msiof1_txd_d_mux[] = {
2815 MSIOF1_TXD_D_MARK,
2816 };
2817 static const unsigned int msiof1_rxd_d_pins[] = {
2818 /* RXD */
2819 RCAR_GP_PIN(5, 13),
2820 };
2821 static const unsigned int msiof1_rxd_d_mux[] = {
2822 MSIOF1_RXD_D_MARK,
2823 };
2824 static const unsigned int msiof1_clk_e_pins[] = {
2825 /* SCK */
2826 RCAR_GP_PIN(3, 0),
2827 };
2828 static const unsigned int msiof1_clk_e_mux[] = {
2829 MSIOF1_SCK_E_MARK,
2830 };
2831 static const unsigned int msiof1_sync_e_pins[] = {
2832 /* SYNC */
2833 RCAR_GP_PIN(3, 1),
2834 };
2835 static const unsigned int msiof1_sync_e_mux[] = {
2836 MSIOF1_SYNC_E_MARK,
2837 };
2838 static const unsigned int msiof1_ss1_e_pins[] = {
2839 /* SS1 */
2840 RCAR_GP_PIN(3, 4),
2841 };
2842 static const unsigned int msiof1_ss1_e_mux[] = {
2843 MSIOF1_SS1_E_MARK,
2844 };
2845 static const unsigned int msiof1_ss2_e_pins[] = {
2846 /* SS2 */
2847 RCAR_GP_PIN(3, 5),
2848 };
2849 static const unsigned int msiof1_ss2_e_mux[] = {
2850 MSIOF1_SS2_E_MARK,
2851 };
2852 static const unsigned int msiof1_txd_e_pins[] = {
2853 /* TXD */
2854 RCAR_GP_PIN(3, 3),
2855 };
2856 static const unsigned int msiof1_txd_e_mux[] = {
2857 MSIOF1_TXD_E_MARK,
2858 };
2859 static const unsigned int msiof1_rxd_e_pins[] = {
2860 /* RXD */
2861 RCAR_GP_PIN(3, 2),
2862 };
2863 static const unsigned int msiof1_rxd_e_mux[] = {
2864 MSIOF1_RXD_E_MARK,
2865 };
2866 static const unsigned int msiof1_clk_f_pins[] = {
2867 /* SCK */
2868 RCAR_GP_PIN(5, 23),
2869 };
2870 static const unsigned int msiof1_clk_f_mux[] = {
2871 MSIOF1_SCK_F_MARK,
2872 };
2873 static const unsigned int msiof1_sync_f_pins[] = {
2874 /* SYNC */
2875 RCAR_GP_PIN(5, 24),
2876 };
2877 static const unsigned int msiof1_sync_f_mux[] = {
2878 MSIOF1_SYNC_F_MARK,
2879 };
2880 static const unsigned int msiof1_ss1_f_pins[] = {
2881 /* SS1 */
2882 RCAR_GP_PIN(6, 1),
2883 };
2884 static const unsigned int msiof1_ss1_f_mux[] = {
2885 MSIOF1_SS1_F_MARK,
2886 };
2887 static const unsigned int msiof1_ss2_f_pins[] = {
2888 /* SS2 */
2889 RCAR_GP_PIN(6, 2),
2890 };
2891 static const unsigned int msiof1_ss2_f_mux[] = {
2892 MSIOF1_SS2_F_MARK,
2893 };
2894 static const unsigned int msiof1_txd_f_pins[] = {
2895 /* TXD */
2896 RCAR_GP_PIN(6, 0),
2897 };
2898 static const unsigned int msiof1_txd_f_mux[] = {
2899 MSIOF1_TXD_F_MARK,
2900 };
2901 static const unsigned int msiof1_rxd_f_pins[] = {
2902 /* RXD */
2903 RCAR_GP_PIN(5, 25),
2904 };
2905 static const unsigned int msiof1_rxd_f_mux[] = {
2906 MSIOF1_RXD_F_MARK,
2907 };
2908 static const unsigned int msiof1_clk_g_pins[] = {
2909 /* SCK */
2910 RCAR_GP_PIN(3, 6),
2911 };
2912 static const unsigned int msiof1_clk_g_mux[] = {
2913 MSIOF1_SCK_G_MARK,
2914 };
2915 static const unsigned int msiof1_sync_g_pins[] = {
2916 /* SYNC */
2917 RCAR_GP_PIN(3, 7),
2918 };
2919 static const unsigned int msiof1_sync_g_mux[] = {
2920 MSIOF1_SYNC_G_MARK,
2921 };
2922 static const unsigned int msiof1_ss1_g_pins[] = {
2923 /* SS1 */
2924 RCAR_GP_PIN(3, 10),
2925 };
2926 static const unsigned int msiof1_ss1_g_mux[] = {
2927 MSIOF1_SS1_G_MARK,
2928 };
2929 static const unsigned int msiof1_ss2_g_pins[] = {
2930 /* SS2 */
2931 RCAR_GP_PIN(3, 11),
2932 };
2933 static const unsigned int msiof1_ss2_g_mux[] = {
2934 MSIOF1_SS2_G_MARK,
2935 };
2936 static const unsigned int msiof1_txd_g_pins[] = {
2937 /* TXD */
2938 RCAR_GP_PIN(3, 9),
2939 };
2940 static const unsigned int msiof1_txd_g_mux[] = {
2941 MSIOF1_TXD_G_MARK,
2942 };
2943 static const unsigned int msiof1_rxd_g_pins[] = {
2944 /* RXD */
2945 RCAR_GP_PIN(3, 8),
2946 };
2947 static const unsigned int msiof1_rxd_g_mux[] = {
2948 MSIOF1_RXD_G_MARK,
2949 };
2950 /* - MSIOF2 ----------------------------------------------------------------- */
2951 static const unsigned int msiof2_clk_a_pins[] = {
2952 /* SCK */
2953 RCAR_GP_PIN(1, 9),
2954 };
2955 static const unsigned int msiof2_clk_a_mux[] = {
2956 MSIOF2_SCK_A_MARK,
2957 };
2958 static const unsigned int msiof2_sync_a_pins[] = {
2959 /* SYNC */
2960 RCAR_GP_PIN(1, 8),
2961 };
2962 static const unsigned int msiof2_sync_a_mux[] = {
2963 MSIOF2_SYNC_A_MARK,
2964 };
2965 static const unsigned int msiof2_ss1_a_pins[] = {
2966 /* SS1 */
2967 RCAR_GP_PIN(1, 6),
2968 };
2969 static const unsigned int msiof2_ss1_a_mux[] = {
2970 MSIOF2_SS1_A_MARK,
2971 };
2972 static const unsigned int msiof2_ss2_a_pins[] = {
2973 /* SS2 */
2974 RCAR_GP_PIN(1, 7),
2975 };
2976 static const unsigned int msiof2_ss2_a_mux[] = {
2977 MSIOF2_SS2_A_MARK,
2978 };
2979 static const unsigned int msiof2_txd_a_pins[] = {
2980 /* TXD */
2981 RCAR_GP_PIN(1, 11),
2982 };
2983 static const unsigned int msiof2_txd_a_mux[] = {
2984 MSIOF2_TXD_A_MARK,
2985 };
2986 static const unsigned int msiof2_rxd_a_pins[] = {
2987 /* RXD */
2988 RCAR_GP_PIN(1, 10),
2989 };
2990 static const unsigned int msiof2_rxd_a_mux[] = {
2991 MSIOF2_RXD_A_MARK,
2992 };
2993 static const unsigned int msiof2_clk_b_pins[] = {
2994 /* SCK */
2995 RCAR_GP_PIN(0, 4),
2996 };
2997 static const unsigned int msiof2_clk_b_mux[] = {
2998 MSIOF2_SCK_B_MARK,
2999 };
3000 static const unsigned int msiof2_sync_b_pins[] = {
3001 /* SYNC */
3002 RCAR_GP_PIN(0, 5),
3003 };
3004 static const unsigned int msiof2_sync_b_mux[] = {
3005 MSIOF2_SYNC_B_MARK,
3006 };
3007 static const unsigned int msiof2_ss1_b_pins[] = {
3008 /* SS1 */
3009 RCAR_GP_PIN(0, 0),
3010 };
3011 static const unsigned int msiof2_ss1_b_mux[] = {
3012 MSIOF2_SS1_B_MARK,
3013 };
3014 static const unsigned int msiof2_ss2_b_pins[] = {
3015 /* SS2 */
3016 RCAR_GP_PIN(0, 1),
3017 };
3018 static const unsigned int msiof2_ss2_b_mux[] = {
3019 MSIOF2_SS2_B_MARK,
3020 };
3021 static const unsigned int msiof2_txd_b_pins[] = {
3022 /* TXD */
3023 RCAR_GP_PIN(0, 7),
3024 };
3025 static const unsigned int msiof2_txd_b_mux[] = {
3026 MSIOF2_TXD_B_MARK,
3027 };
3028 static const unsigned int msiof2_rxd_b_pins[] = {
3029 /* RXD */
3030 RCAR_GP_PIN(0, 6),
3031 };
3032 static const unsigned int msiof2_rxd_b_mux[] = {
3033 MSIOF2_RXD_B_MARK,
3034 };
3035 static const unsigned int msiof2_clk_c_pins[] = {
3036 /* SCK */
3037 RCAR_GP_PIN(2, 12),
3038 };
3039 static const unsigned int msiof2_clk_c_mux[] = {
3040 MSIOF2_SCK_C_MARK,
3041 };
3042 static const unsigned int msiof2_sync_c_pins[] = {
3043 /* SYNC */
3044 RCAR_GP_PIN(2, 11),
3045 };
3046 static const unsigned int msiof2_sync_c_mux[] = {
3047 MSIOF2_SYNC_C_MARK,
3048 };
3049 static const unsigned int msiof2_ss1_c_pins[] = {
3050 /* SS1 */
3051 RCAR_GP_PIN(2, 10),
3052 };
3053 static const unsigned int msiof2_ss1_c_mux[] = {
3054 MSIOF2_SS1_C_MARK,
3055 };
3056 static const unsigned int msiof2_ss2_c_pins[] = {
3057 /* SS2 */
3058 RCAR_GP_PIN(2, 9),
3059 };
3060 static const unsigned int msiof2_ss2_c_mux[] = {
3061 MSIOF2_SS2_C_MARK,
3062 };
3063 static const unsigned int msiof2_txd_c_pins[] = {
3064 /* TXD */
3065 RCAR_GP_PIN(2, 14),
3066 };
3067 static const unsigned int msiof2_txd_c_mux[] = {
3068 MSIOF2_TXD_C_MARK,
3069 };
3070 static const unsigned int msiof2_rxd_c_pins[] = {
3071 /* RXD */
3072 RCAR_GP_PIN(2, 13),
3073 };
3074 static const unsigned int msiof2_rxd_c_mux[] = {
3075 MSIOF2_RXD_C_MARK,
3076 };
3077 static const unsigned int msiof2_clk_d_pins[] = {
3078 /* SCK */
3079 RCAR_GP_PIN(0, 8),
3080 };
3081 static const unsigned int msiof2_clk_d_mux[] = {
3082 MSIOF2_SCK_D_MARK,
3083 };
3084 static const unsigned int msiof2_sync_d_pins[] = {
3085 /* SYNC */
3086 RCAR_GP_PIN(0, 9),
3087 };
3088 static const unsigned int msiof2_sync_d_mux[] = {
3089 MSIOF2_SYNC_D_MARK,
3090 };
3091 static const unsigned int msiof2_ss1_d_pins[] = {
3092 /* SS1 */
3093 RCAR_GP_PIN(0, 12),
3094 };
3095 static const unsigned int msiof2_ss1_d_mux[] = {
3096 MSIOF2_SS1_D_MARK,
3097 };
3098 static const unsigned int msiof2_ss2_d_pins[] = {
3099 /* SS2 */
3100 RCAR_GP_PIN(0, 13),
3101 };
3102 static const unsigned int msiof2_ss2_d_mux[] = {
3103 MSIOF2_SS2_D_MARK,
3104 };
3105 static const unsigned int msiof2_txd_d_pins[] = {
3106 /* TXD */
3107 RCAR_GP_PIN(0, 11),
3108 };
3109 static const unsigned int msiof2_txd_d_mux[] = {
3110 MSIOF2_TXD_D_MARK,
3111 };
3112 static const unsigned int msiof2_rxd_d_pins[] = {
3113 /* RXD */
3114 RCAR_GP_PIN(0, 10),
3115 };
3116 static const unsigned int msiof2_rxd_d_mux[] = {
3117 MSIOF2_RXD_D_MARK,
3118 };
3119 /* - MSIOF3 ----------------------------------------------------------------- */
3120 static const unsigned int msiof3_clk_a_pins[] = {
3121 /* SCK */
3122 RCAR_GP_PIN(0, 0),
3123 };
3124 static const unsigned int msiof3_clk_a_mux[] = {
3125 MSIOF3_SCK_A_MARK,
3126 };
3127 static const unsigned int msiof3_sync_a_pins[] = {
3128 /* SYNC */
3129 RCAR_GP_PIN(0, 1),
3130 };
3131 static const unsigned int msiof3_sync_a_mux[] = {
3132 MSIOF3_SYNC_A_MARK,
3133 };
3134 static const unsigned int msiof3_ss1_a_pins[] = {
3135 /* SS1 */
3136 RCAR_GP_PIN(0, 14),
3137 };
3138 static const unsigned int msiof3_ss1_a_mux[] = {
3139 MSIOF3_SS1_A_MARK,
3140 };
3141 static const unsigned int msiof3_ss2_a_pins[] = {
3142 /* SS2 */
3143 RCAR_GP_PIN(0, 15),
3144 };
3145 static const unsigned int msiof3_ss2_a_mux[] = {
3146 MSIOF3_SS2_A_MARK,
3147 };
3148 static const unsigned int msiof3_txd_a_pins[] = {
3149 /* TXD */
3150 RCAR_GP_PIN(0, 3),
3151 };
3152 static const unsigned int msiof3_txd_a_mux[] = {
3153 MSIOF3_TXD_A_MARK,
3154 };
3155 static const unsigned int msiof3_rxd_a_pins[] = {
3156 /* RXD */
3157 RCAR_GP_PIN(0, 2),
3158 };
3159 static const unsigned int msiof3_rxd_a_mux[] = {
3160 MSIOF3_RXD_A_MARK,
3161 };
3162 static const unsigned int msiof3_clk_b_pins[] = {
3163 /* SCK */
3164 RCAR_GP_PIN(1, 2),
3165 };
3166 static const unsigned int msiof3_clk_b_mux[] = {
3167 MSIOF3_SCK_B_MARK,
3168 };
3169 static const unsigned int msiof3_sync_b_pins[] = {
3170 /* SYNC */
3171 RCAR_GP_PIN(1, 0),
3172 };
3173 static const unsigned int msiof3_sync_b_mux[] = {
3174 MSIOF3_SYNC_B_MARK,
3175 };
3176 static const unsigned int msiof3_ss1_b_pins[] = {
3177 /* SS1 */
3178 RCAR_GP_PIN(1, 4),
3179 };
3180 static const unsigned int msiof3_ss1_b_mux[] = {
3181 MSIOF3_SS1_B_MARK,
3182 };
3183 static const unsigned int msiof3_ss2_b_pins[] = {
3184 /* SS2 */
3185 RCAR_GP_PIN(1, 5),
3186 };
3187 static const unsigned int msiof3_ss2_b_mux[] = {
3188 MSIOF3_SS2_B_MARK,
3189 };
3190 static const unsigned int msiof3_txd_b_pins[] = {
3191 /* TXD */
3192 RCAR_GP_PIN(1, 1),
3193 };
3194 static const unsigned int msiof3_txd_b_mux[] = {
3195 MSIOF3_TXD_B_MARK,
3196 };
3197 static const unsigned int msiof3_rxd_b_pins[] = {
3198 /* RXD */
3199 RCAR_GP_PIN(1, 3),
3200 };
3201 static const unsigned int msiof3_rxd_b_mux[] = {
3202 MSIOF3_RXD_B_MARK,
3203 };
3204 static const unsigned int msiof3_clk_c_pins[] = {
3205 /* SCK */
3206 RCAR_GP_PIN(1, 12),
3207 };
3208 static const unsigned int msiof3_clk_c_mux[] = {
3209 MSIOF3_SCK_C_MARK,
3210 };
3211 static const unsigned int msiof3_sync_c_pins[] = {
3212 /* SYNC */
3213 RCAR_GP_PIN(1, 13),
3214 };
3215 static const unsigned int msiof3_sync_c_mux[] = {
3216 MSIOF3_SYNC_C_MARK,
3217 };
3218 static const unsigned int msiof3_txd_c_pins[] = {
3219 /* TXD */
3220 RCAR_GP_PIN(1, 15),
3221 };
3222 static const unsigned int msiof3_txd_c_mux[] = {
3223 MSIOF3_TXD_C_MARK,
3224 };
3225 static const unsigned int msiof3_rxd_c_pins[] = {
3226 /* RXD */
3227 RCAR_GP_PIN(1, 14),
3228 };
3229 static const unsigned int msiof3_rxd_c_mux[] = {
3230 MSIOF3_RXD_C_MARK,
3231 };
3232 static const unsigned int msiof3_clk_d_pins[] = {
3233 /* SCK */
3234 RCAR_GP_PIN(1, 22),
3235 };
3236 static const unsigned int msiof3_clk_d_mux[] = {
3237 MSIOF3_SCK_D_MARK,
3238 };
3239 static const unsigned int msiof3_sync_d_pins[] = {
3240 /* SYNC */
3241 RCAR_GP_PIN(1, 23),
3242 };
3243 static const unsigned int msiof3_sync_d_mux[] = {
3244 MSIOF3_SYNC_D_MARK,
3245 };
3246 static const unsigned int msiof3_ss1_d_pins[] = {
3247 /* SS1 */
3248 RCAR_GP_PIN(1, 26),
3249 };
3250 static const unsigned int msiof3_ss1_d_mux[] = {
3251 MSIOF3_SS1_D_MARK,
3252 };
3253 static const unsigned int msiof3_txd_d_pins[] = {
3254 /* TXD */
3255 RCAR_GP_PIN(1, 25),
3256 };
3257 static const unsigned int msiof3_txd_d_mux[] = {
3258 MSIOF3_TXD_D_MARK,
3259 };
3260 static const unsigned int msiof3_rxd_d_pins[] = {
3261 /* RXD */
3262 RCAR_GP_PIN(1, 24),
3263 };
3264 static const unsigned int msiof3_rxd_d_mux[] = {
3265 MSIOF3_RXD_D_MARK,
3266 };
3267 static const unsigned int msiof3_clk_e_pins[] = {
3268 /* SCK */
3269 RCAR_GP_PIN(2, 3),
3270 };
3271 static const unsigned int msiof3_clk_e_mux[] = {
3272 MSIOF3_SCK_E_MARK,
3273 };
3274 static const unsigned int msiof3_sync_e_pins[] = {
3275 /* SYNC */
3276 RCAR_GP_PIN(2, 2),
3277 };
3278 static const unsigned int msiof3_sync_e_mux[] = {
3279 MSIOF3_SYNC_E_MARK,
3280 };
3281 static const unsigned int msiof3_ss1_e_pins[] = {
3282 /* SS1 */
3283 RCAR_GP_PIN(2, 1),
3284 };
3285 static const unsigned int msiof3_ss1_e_mux[] = {
3286 MSIOF3_SS1_E_MARK,
3287 };
3288 static const unsigned int msiof3_ss2_e_pins[] = {
3289 /* SS2 */
3290 RCAR_GP_PIN(2, 0),
3291 };
3292 static const unsigned int msiof3_ss2_e_mux[] = {
3293 MSIOF3_SS2_E_MARK,
3294 };
3295 static const unsigned int msiof3_txd_e_pins[] = {
3296 /* TXD */
3297 RCAR_GP_PIN(2, 5),
3298 };
3299 static const unsigned int msiof3_txd_e_mux[] = {
3300 MSIOF3_TXD_E_MARK,
3301 };
3302 static const unsigned int msiof3_rxd_e_pins[] = {
3303 /* RXD */
3304 RCAR_GP_PIN(2, 4),
3305 };
3306 static const unsigned int msiof3_rxd_e_mux[] = {
3307 MSIOF3_RXD_E_MARK,
3308 };
3309
3310 /* - PWM0 --------------------------------------------------------------------*/
3311 static const unsigned int pwm0_pins[] = {
3312 /* PWM */
3313 RCAR_GP_PIN(2, 6),
3314 };
3315 static const unsigned int pwm0_mux[] = {
3316 PWM0_MARK,
3317 };
3318 /* - PWM1 --------------------------------------------------------------------*/
3319 static const unsigned int pwm1_a_pins[] = {
3320 /* PWM */
3321 RCAR_GP_PIN(2, 7),
3322 };
3323 static const unsigned int pwm1_a_mux[] = {
3324 PWM1_A_MARK,
3325 };
3326 static const unsigned int pwm1_b_pins[] = {
3327 /* PWM */
3328 RCAR_GP_PIN(1, 8),
3329 };
3330 static const unsigned int pwm1_b_mux[] = {
3331 PWM1_B_MARK,
3332 };
3333 /* - PWM2 --------------------------------------------------------------------*/
3334 static const unsigned int pwm2_a_pins[] = {
3335 /* PWM */
3336 RCAR_GP_PIN(2, 8),
3337 };
3338 static const unsigned int pwm2_a_mux[] = {
3339 PWM2_A_MARK,
3340 };
3341 static const unsigned int pwm2_b_pins[] = {
3342 /* PWM */
3343 RCAR_GP_PIN(1, 11),
3344 };
3345 static const unsigned int pwm2_b_mux[] = {
3346 PWM2_B_MARK,
3347 };
3348 /* - PWM3 --------------------------------------------------------------------*/
3349 static const unsigned int pwm3_a_pins[] = {
3350 /* PWM */
3351 RCAR_GP_PIN(1, 0),
3352 };
3353 static const unsigned int pwm3_a_mux[] = {
3354 PWM3_A_MARK,
3355 };
3356 static const unsigned int pwm3_b_pins[] = {
3357 /* PWM */
3358 RCAR_GP_PIN(2, 2),
3359 };
3360 static const unsigned int pwm3_b_mux[] = {
3361 PWM3_B_MARK,
3362 };
3363 /* - PWM4 --------------------------------------------------------------------*/
3364 static const unsigned int pwm4_a_pins[] = {
3365 /* PWM */
3366 RCAR_GP_PIN(1, 1),
3367 };
3368 static const unsigned int pwm4_a_mux[] = {
3369 PWM4_A_MARK,
3370 };
3371 static const unsigned int pwm4_b_pins[] = {
3372 /* PWM */
3373 RCAR_GP_PIN(2, 3),
3374 };
3375 static const unsigned int pwm4_b_mux[] = {
3376 PWM4_B_MARK,
3377 };
3378 /* - PWM5 --------------------------------------------------------------------*/
3379 static const unsigned int pwm5_a_pins[] = {
3380 /* PWM */
3381 RCAR_GP_PIN(1, 2),
3382 };
3383 static const unsigned int pwm5_a_mux[] = {
3384 PWM5_A_MARK,
3385 };
3386 static const unsigned int pwm5_b_pins[] = {
3387 /* PWM */
3388 RCAR_GP_PIN(2, 4),
3389 };
3390 static const unsigned int pwm5_b_mux[] = {
3391 PWM5_B_MARK,
3392 };
3393 /* - PWM6 --------------------------------------------------------------------*/
3394 static const unsigned int pwm6_a_pins[] = {
3395 /* PWM */
3396 RCAR_GP_PIN(1, 3),
3397 };
3398 static const unsigned int pwm6_a_mux[] = {
3399 PWM6_A_MARK,
3400 };
3401 static const unsigned int pwm6_b_pins[] = {
3402 /* PWM */
3403 RCAR_GP_PIN(2, 5),
3404 };
3405 static const unsigned int pwm6_b_mux[] = {
3406 PWM6_B_MARK,
3407 };
3408
3409 /* - SATA --------------------------------------------------------------------*/
3410 static const unsigned int sata0_devslp_a_pins[] = {
3411 /* DEVSLP */
3412 RCAR_GP_PIN(6, 16),
3413 };
3414
3415 static const unsigned int sata0_devslp_a_mux[] = {
3416 SATA_DEVSLP_A_MARK,
3417 };
3418
3419 static const unsigned int sata0_devslp_b_pins[] = {
3420 /* DEVSLP */
3421 RCAR_GP_PIN(4, 6),
3422 };
3423
3424 static const unsigned int sata0_devslp_b_mux[] = {
3425 SATA_DEVSLP_B_MARK,
3426 };
3427
3428 /* - SCIF0 ------------------------------------------------------------------ */
3429 static const unsigned int scif0_data_pins[] = {
3430 /* RX, TX */
3431 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3432 };
3433 static const unsigned int scif0_data_mux[] = {
3434 RX0_MARK, TX0_MARK,
3435 };
3436 static const unsigned int scif0_clk_pins[] = {
3437 /* SCK */
3438 RCAR_GP_PIN(5, 0),
3439 };
3440 static const unsigned int scif0_clk_mux[] = {
3441 SCK0_MARK,
3442 };
3443 static const unsigned int scif0_ctrl_pins[] = {
3444 /* RTS, CTS */
3445 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3446 };
3447 static const unsigned int scif0_ctrl_mux[] = {
3448 RTS0_N_MARK, CTS0_N_MARK,
3449 };
3450 /* - SCIF1 ------------------------------------------------------------------ */
3451 static const unsigned int scif1_data_a_pins[] = {
3452 /* RX, TX */
3453 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3454 };
3455 static const unsigned int scif1_data_a_mux[] = {
3456 RX1_A_MARK, TX1_A_MARK,
3457 };
3458 static const unsigned int scif1_clk_pins[] = {
3459 /* SCK */
3460 RCAR_GP_PIN(6, 21),
3461 };
3462 static const unsigned int scif1_clk_mux[] = {
3463 SCK1_MARK,
3464 };
3465 static const unsigned int scif1_ctrl_pins[] = {
3466 /* RTS, CTS */
3467 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3468 };
3469 static const unsigned int scif1_ctrl_mux[] = {
3470 RTS1_N_MARK, CTS1_N_MARK,
3471 };
3472 static const unsigned int scif1_data_b_pins[] = {
3473 /* RX, TX */
3474 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3475 };
3476 static const unsigned int scif1_data_b_mux[] = {
3477 RX1_B_MARK, TX1_B_MARK,
3478 };
3479 /* - SCIF2 ------------------------------------------------------------------ */
3480 static const unsigned int scif2_data_a_pins[] = {
3481 /* RX, TX */
3482 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3483 };
3484 static const unsigned int scif2_data_a_mux[] = {
3485 RX2_A_MARK, TX2_A_MARK,
3486 };
3487 static const unsigned int scif2_clk_pins[] = {
3488 /* SCK */
3489 RCAR_GP_PIN(5, 9),
3490 };
3491 static const unsigned int scif2_clk_mux[] = {
3492 SCK2_MARK,
3493 };
3494 static const unsigned int scif2_data_b_pins[] = {
3495 /* RX, TX */
3496 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3497 };
3498 static const unsigned int scif2_data_b_mux[] = {
3499 RX2_B_MARK, TX2_B_MARK,
3500 };
3501 /* - SCIF3 ------------------------------------------------------------------ */
3502 static const unsigned int scif3_data_a_pins[] = {
3503 /* RX, TX */
3504 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3505 };
3506 static const unsigned int scif3_data_a_mux[] = {
3507 RX3_A_MARK, TX3_A_MARK,
3508 };
3509 static const unsigned int scif3_clk_pins[] = {
3510 /* SCK */
3511 RCAR_GP_PIN(1, 22),
3512 };
3513 static const unsigned int scif3_clk_mux[] = {
3514 SCK3_MARK,
3515 };
3516 static const unsigned int scif3_ctrl_pins[] = {
3517 /* RTS, CTS */
3518 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3519 };
3520 static const unsigned int scif3_ctrl_mux[] = {
3521 RTS3_N_MARK, CTS3_N_MARK,
3522 };
3523 static const unsigned int scif3_data_b_pins[] = {
3524 /* RX, TX */
3525 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3526 };
3527 static const unsigned int scif3_data_b_mux[] = {
3528 RX3_B_MARK, TX3_B_MARK,
3529 };
3530 /* - SCIF4 ------------------------------------------------------------------ */
3531 static const unsigned int scif4_data_a_pins[] = {
3532 /* RX, TX */
3533 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3534 };
3535 static const unsigned int scif4_data_a_mux[] = {
3536 RX4_A_MARK, TX4_A_MARK,
3537 };
3538 static const unsigned int scif4_clk_a_pins[] = {
3539 /* SCK */
3540 RCAR_GP_PIN(2, 10),
3541 };
3542 static const unsigned int scif4_clk_a_mux[] = {
3543 SCK4_A_MARK,
3544 };
3545 static const unsigned int scif4_ctrl_a_pins[] = {
3546 /* RTS, CTS */
3547 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3548 };
3549 static const unsigned int scif4_ctrl_a_mux[] = {
3550 RTS4_N_A_MARK, CTS4_N_A_MARK,
3551 };
3552 static const unsigned int scif4_data_b_pins[] = {
3553 /* RX, TX */
3554 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3555 };
3556 static const unsigned int scif4_data_b_mux[] = {
3557 RX4_B_MARK, TX4_B_MARK,
3558 };
3559 static const unsigned int scif4_clk_b_pins[] = {
3560 /* SCK */
3561 RCAR_GP_PIN(1, 5),
3562 };
3563 static const unsigned int scif4_clk_b_mux[] = {
3564 SCK4_B_MARK,
3565 };
3566 static const unsigned int scif4_ctrl_b_pins[] = {
3567 /* RTS, CTS */
3568 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3569 };
3570 static const unsigned int scif4_ctrl_b_mux[] = {
3571 RTS4_N_B_MARK, CTS4_N_B_MARK,
3572 };
3573 static const unsigned int scif4_data_c_pins[] = {
3574 /* RX, TX */
3575 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3576 };
3577 static const unsigned int scif4_data_c_mux[] = {
3578 RX4_C_MARK, TX4_C_MARK,
3579 };
3580 static const unsigned int scif4_clk_c_pins[] = {
3581 /* SCK */
3582 RCAR_GP_PIN(0, 8),
3583 };
3584 static const unsigned int scif4_clk_c_mux[] = {
3585 SCK4_C_MARK,
3586 };
3587 static const unsigned int scif4_ctrl_c_pins[] = {
3588 /* RTS, CTS */
3589 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3590 };
3591 static const unsigned int scif4_ctrl_c_mux[] = {
3592 RTS4_N_C_MARK, CTS4_N_C_MARK,
3593 };
3594 /* - SCIF5 ------------------------------------------------------------------ */
3595 static const unsigned int scif5_data_a_pins[] = {
3596 /* RX, TX */
3597 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3598 };
3599 static const unsigned int scif5_data_a_mux[] = {
3600 RX5_A_MARK, TX5_A_MARK,
3601 };
3602 static const unsigned int scif5_clk_a_pins[] = {
3603 /* SCK */
3604 RCAR_GP_PIN(6, 21),
3605 };
3606 static const unsigned int scif5_clk_a_mux[] = {
3607 SCK5_A_MARK,
3608 };
3609 static const unsigned int scif5_data_b_pins[] = {
3610 /* RX, TX */
3611 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3612 };
3613 static const unsigned int scif5_data_b_mux[] = {
3614 RX5_B_MARK, TX5_B_MARK,
3615 };
3616 static const unsigned int scif5_clk_b_pins[] = {
3617 /* SCK */
3618 RCAR_GP_PIN(5, 0),
3619 };
3620 static const unsigned int scif5_clk_b_mux[] = {
3621 SCK5_B_MARK,
3622 };
3623 /* - SCIF Clock ------------------------------------------------------------- */
3624 static const unsigned int scif_clk_a_pins[] = {
3625 /* SCIF_CLK */
3626 RCAR_GP_PIN(6, 23),
3627 };
3628 static const unsigned int scif_clk_a_mux[] = {
3629 SCIF_CLK_A_MARK,
3630 };
3631 static const unsigned int scif_clk_b_pins[] = {
3632 /* SCIF_CLK */
3633 RCAR_GP_PIN(5, 9),
3634 };
3635 static const unsigned int scif_clk_b_mux[] = {
3636 SCIF_CLK_B_MARK,
3637 };
3638
3639 /* - SDHI0 ------------------------------------------------------------------ */
3640 static const unsigned int sdhi0_data1_pins[] = {
3641 /* D0 */
3642 RCAR_GP_PIN(3, 2),
3643 };
3644
3645 static const unsigned int sdhi0_data1_mux[] = {
3646 SD0_DAT0_MARK,
3647 };
3648
3649 static const unsigned int sdhi0_data4_pins[] = {
3650 /* D[0:3] */
3651 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3652 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3653 };
3654
3655 static const unsigned int sdhi0_data4_mux[] = {
3656 SD0_DAT0_MARK, SD0_DAT1_MARK,
3657 SD0_DAT2_MARK, SD0_DAT3_MARK,
3658 };
3659
3660 static const unsigned int sdhi0_ctrl_pins[] = {
3661 /* CLK, CMD */
3662 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3663 };
3664
3665 static const unsigned int sdhi0_ctrl_mux[] = {
3666 SD0_CLK_MARK, SD0_CMD_MARK,
3667 };
3668
3669 static const unsigned int sdhi0_cd_pins[] = {
3670 /* CD */
3671 RCAR_GP_PIN(3, 12),
3672 };
3673
3674 static const unsigned int sdhi0_cd_mux[] = {
3675 SD0_CD_MARK,
3676 };
3677
3678 static const unsigned int sdhi0_wp_pins[] = {
3679 /* WP */
3680 RCAR_GP_PIN(3, 13),
3681 };
3682
3683 static const unsigned int sdhi0_wp_mux[] = {
3684 SD0_WP_MARK,
3685 };
3686
3687 /* - SDHI1 ------------------------------------------------------------------ */
3688 static const unsigned int sdhi1_data1_pins[] = {
3689 /* D0 */
3690 RCAR_GP_PIN(3, 8),
3691 };
3692
3693 static const unsigned int sdhi1_data1_mux[] = {
3694 SD1_DAT0_MARK,
3695 };
3696
3697 static const unsigned int sdhi1_data4_pins[] = {
3698 /* D[0:3] */
3699 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3700 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3701 };
3702
3703 static const unsigned int sdhi1_data4_mux[] = {
3704 SD1_DAT0_MARK, SD1_DAT1_MARK,
3705 SD1_DAT2_MARK, SD1_DAT3_MARK,
3706 };
3707
3708 static const unsigned int sdhi1_ctrl_pins[] = {
3709 /* CLK, CMD */
3710 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3711 };
3712
3713 static const unsigned int sdhi1_ctrl_mux[] = {
3714 SD1_CLK_MARK, SD1_CMD_MARK,
3715 };
3716
3717 static const unsigned int sdhi1_cd_pins[] = {
3718 /* CD */
3719 RCAR_GP_PIN(3, 14),
3720 };
3721
3722 static const unsigned int sdhi1_cd_mux[] = {
3723 SD1_CD_MARK,
3724 };
3725
3726 static const unsigned int sdhi1_wp_pins[] = {
3727 /* WP */
3728 RCAR_GP_PIN(3, 15),
3729 };
3730
3731 static const unsigned int sdhi1_wp_mux[] = {
3732 SD1_WP_MARK,
3733 };
3734
3735 /* - SDHI2 ------------------------------------------------------------------ */
3736 static const unsigned int sdhi2_data1_pins[] = {
3737 /* D0 */
3738 RCAR_GP_PIN(4, 2),
3739 };
3740
3741 static const unsigned int sdhi2_data1_mux[] = {
3742 SD2_DAT0_MARK,
3743 };
3744
3745 static const unsigned int sdhi2_data4_pins[] = {
3746 /* D[0:3] */
3747 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3748 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3749 };
3750
3751 static const unsigned int sdhi2_data4_mux[] = {
3752 SD2_DAT0_MARK, SD2_DAT1_MARK,
3753 SD2_DAT2_MARK, SD2_DAT3_MARK,
3754 };
3755
3756 static const unsigned int sdhi2_data8_pins[] = {
3757 /* D[0:7] */
3758 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3759 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3760 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3761 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3762 };
3763
3764 static const unsigned int sdhi2_data8_mux[] = {
3765 SD2_DAT0_MARK, SD2_DAT1_MARK,
3766 SD2_DAT2_MARK, SD2_DAT3_MARK,
3767 SD2_DAT4_MARK, SD2_DAT5_MARK,
3768 SD2_DAT6_MARK, SD2_DAT7_MARK,
3769 };
3770
3771 static const unsigned int sdhi2_ctrl_pins[] = {
3772 /* CLK, CMD */
3773 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3774 };
3775
3776 static const unsigned int sdhi2_ctrl_mux[] = {
3777 SD2_CLK_MARK, SD2_CMD_MARK,
3778 };
3779
3780 static const unsigned int sdhi2_cd_a_pins[] = {
3781 /* CD */
3782 RCAR_GP_PIN(4, 13),
3783 };
3784
3785 static const unsigned int sdhi2_cd_a_mux[] = {
3786 SD2_CD_A_MARK,
3787 };
3788
3789 static const unsigned int sdhi2_cd_b_pins[] = {
3790 /* CD */
3791 RCAR_GP_PIN(5, 10),
3792 };
3793
3794 static const unsigned int sdhi2_cd_b_mux[] = {
3795 SD2_CD_B_MARK,
3796 };
3797
3798 static const unsigned int sdhi2_wp_a_pins[] = {
3799 /* WP */
3800 RCAR_GP_PIN(4, 14),
3801 };
3802
3803 static const unsigned int sdhi2_wp_a_mux[] = {
3804 SD2_WP_A_MARK,
3805 };
3806
3807 static const unsigned int sdhi2_wp_b_pins[] = {
3808 /* WP */
3809 RCAR_GP_PIN(5, 11),
3810 };
3811
3812 static const unsigned int sdhi2_wp_b_mux[] = {
3813 SD2_WP_B_MARK,
3814 };
3815
3816 static const unsigned int sdhi2_ds_pins[] = {
3817 /* DS */
3818 RCAR_GP_PIN(4, 6),
3819 };
3820
3821 static const unsigned int sdhi2_ds_mux[] = {
3822 SD2_DS_MARK,
3823 };
3824
3825 /* - SDHI3 ------------------------------------------------------------------ */
3826 static const unsigned int sdhi3_data1_pins[] = {
3827 /* D0 */
3828 RCAR_GP_PIN(4, 9),
3829 };
3830
3831 static const unsigned int sdhi3_data1_mux[] = {
3832 SD3_DAT0_MARK,
3833 };
3834
3835 static const unsigned int sdhi3_data4_pins[] = {
3836 /* D[0:3] */
3837 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3838 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3839 };
3840
3841 static const unsigned int sdhi3_data4_mux[] = {
3842 SD3_DAT0_MARK, SD3_DAT1_MARK,
3843 SD3_DAT2_MARK, SD3_DAT3_MARK,
3844 };
3845
3846 static const unsigned int sdhi3_data8_pins[] = {
3847 /* D[0:7] */
3848 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3849 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3850 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3851 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3852 };
3853
3854 static const unsigned int sdhi3_data8_mux[] = {
3855 SD3_DAT0_MARK, SD3_DAT1_MARK,
3856 SD3_DAT2_MARK, SD3_DAT3_MARK,
3857 SD3_DAT4_MARK, SD3_DAT5_MARK,
3858 SD3_DAT6_MARK, SD3_DAT7_MARK,
3859 };
3860
3861 static const unsigned int sdhi3_ctrl_pins[] = {
3862 /* CLK, CMD */
3863 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3864 };
3865
3866 static const unsigned int sdhi3_ctrl_mux[] = {
3867 SD3_CLK_MARK, SD3_CMD_MARK,
3868 };
3869
3870 static const unsigned int sdhi3_cd_pins[] = {
3871 /* CD */
3872 RCAR_GP_PIN(4, 15),
3873 };
3874
3875 static const unsigned int sdhi3_cd_mux[] = {
3876 SD3_CD_MARK,
3877 };
3878
3879 static const unsigned int sdhi3_wp_pins[] = {
3880 /* WP */
3881 RCAR_GP_PIN(4, 16),
3882 };
3883
3884 static const unsigned int sdhi3_wp_mux[] = {
3885 SD3_WP_MARK,
3886 };
3887
3888 static const unsigned int sdhi3_ds_pins[] = {
3889 /* DS */
3890 RCAR_GP_PIN(4, 17),
3891 };
3892
3893 static const unsigned int sdhi3_ds_mux[] = {
3894 SD3_DS_MARK,
3895 };
3896
3897 /* - SSI -------------------------------------------------------------------- */
3898 static const unsigned int ssi0_data_pins[] = {
3899 /* SDATA */
3900 RCAR_GP_PIN(6, 2),
3901 };
3902 static const unsigned int ssi0_data_mux[] = {
3903 SSI_SDATA0_MARK,
3904 };
3905 static const unsigned int ssi01239_ctrl_pins[] = {
3906 /* SCK, WS */
3907 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3908 };
3909 static const unsigned int ssi01239_ctrl_mux[] = {
3910 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3911 };
3912 static const unsigned int ssi1_data_a_pins[] = {
3913 /* SDATA */
3914 RCAR_GP_PIN(6, 3),
3915 };
3916 static const unsigned int ssi1_data_a_mux[] = {
3917 SSI_SDATA1_A_MARK,
3918 };
3919 static const unsigned int ssi1_data_b_pins[] = {
3920 /* SDATA */
3921 RCAR_GP_PIN(5, 12),
3922 };
3923 static const unsigned int ssi1_data_b_mux[] = {
3924 SSI_SDATA1_B_MARK,
3925 };
3926 static const unsigned int ssi1_ctrl_a_pins[] = {
3927 /* SCK, WS */
3928 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3929 };
3930 static const unsigned int ssi1_ctrl_a_mux[] = {
3931 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3932 };
3933 static const unsigned int ssi1_ctrl_b_pins[] = {
3934 /* SCK, WS */
3935 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3936 };
3937 static const unsigned int ssi1_ctrl_b_mux[] = {
3938 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3939 };
3940 static const unsigned int ssi2_data_a_pins[] = {
3941 /* SDATA */
3942 RCAR_GP_PIN(6, 4),
3943 };
3944 static const unsigned int ssi2_data_a_mux[] = {
3945 SSI_SDATA2_A_MARK,
3946 };
3947 static const unsigned int ssi2_data_b_pins[] = {
3948 /* SDATA */
3949 RCAR_GP_PIN(5, 13),
3950 };
3951 static const unsigned int ssi2_data_b_mux[] = {
3952 SSI_SDATA2_B_MARK,
3953 };
3954 static const unsigned int ssi2_ctrl_a_pins[] = {
3955 /* SCK, WS */
3956 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3957 };
3958 static const unsigned int ssi2_ctrl_a_mux[] = {
3959 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3960 };
3961 static const unsigned int ssi2_ctrl_b_pins[] = {
3962 /* SCK, WS */
3963 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3964 };
3965 static const unsigned int ssi2_ctrl_b_mux[] = {
3966 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3967 };
3968 static const unsigned int ssi3_data_pins[] = {
3969 /* SDATA */
3970 RCAR_GP_PIN(6, 7),
3971 };
3972 static const unsigned int ssi3_data_mux[] = {
3973 SSI_SDATA3_MARK,
3974 };
3975 static const unsigned int ssi349_ctrl_pins[] = {
3976 /* SCK, WS */
3977 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3978 };
3979 static const unsigned int ssi349_ctrl_mux[] = {
3980 SSI_SCK349_MARK, SSI_WS349_MARK,
3981 };
3982 static const unsigned int ssi4_data_pins[] = {
3983 /* SDATA */
3984 RCAR_GP_PIN(6, 10),
3985 };
3986 static const unsigned int ssi4_data_mux[] = {
3987 SSI_SDATA4_MARK,
3988 };
3989 static const unsigned int ssi4_ctrl_pins[] = {
3990 /* SCK, WS */
3991 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3992 };
3993 static const unsigned int ssi4_ctrl_mux[] = {
3994 SSI_SCK4_MARK, SSI_WS4_MARK,
3995 };
3996 static const unsigned int ssi5_data_pins[] = {
3997 /* SDATA */
3998 RCAR_GP_PIN(6, 13),
3999 };
4000 static const unsigned int ssi5_data_mux[] = {
4001 SSI_SDATA5_MARK,
4002 };
4003 static const unsigned int ssi5_ctrl_pins[] = {
4004 /* SCK, WS */
4005 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
4006 };
4007 static const unsigned int ssi5_ctrl_mux[] = {
4008 SSI_SCK5_MARK, SSI_WS5_MARK,
4009 };
4010 static const unsigned int ssi6_data_pins[] = {
4011 /* SDATA */
4012 RCAR_GP_PIN(6, 16),
4013 };
4014 static const unsigned int ssi6_data_mux[] = {
4015 SSI_SDATA6_MARK,
4016 };
4017 static const unsigned int ssi6_ctrl_pins[] = {
4018 /* SCK, WS */
4019 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
4020 };
4021 static const unsigned int ssi6_ctrl_mux[] = {
4022 SSI_SCK6_MARK, SSI_WS6_MARK,
4023 };
4024 static const unsigned int ssi7_data_pins[] = {
4025 /* SDATA */
4026 RCAR_GP_PIN(6, 19),
4027 };
4028 static const unsigned int ssi7_data_mux[] = {
4029 SSI_SDATA7_MARK,
4030 };
4031 static const unsigned int ssi78_ctrl_pins[] = {
4032 /* SCK, WS */
4033 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
4034 };
4035 static const unsigned int ssi78_ctrl_mux[] = {
4036 SSI_SCK78_MARK, SSI_WS78_MARK,
4037 };
4038 static const unsigned int ssi8_data_pins[] = {
4039 /* SDATA */
4040 RCAR_GP_PIN(6, 20),
4041 };
4042 static const unsigned int ssi8_data_mux[] = {
4043 SSI_SDATA8_MARK,
4044 };
4045 static const unsigned int ssi9_data_a_pins[] = {
4046 /* SDATA */
4047 RCAR_GP_PIN(6, 21),
4048 };
4049 static const unsigned int ssi9_data_a_mux[] = {
4050 SSI_SDATA9_A_MARK,
4051 };
4052 static const unsigned int ssi9_data_b_pins[] = {
4053 /* SDATA */
4054 RCAR_GP_PIN(5, 14),
4055 };
4056 static const unsigned int ssi9_data_b_mux[] = {
4057 SSI_SDATA9_B_MARK,
4058 };
4059 static const unsigned int ssi9_ctrl_a_pins[] = {
4060 /* SCK, WS */
4061 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
4062 };
4063 static const unsigned int ssi9_ctrl_a_mux[] = {
4064 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
4065 };
4066 static const unsigned int ssi9_ctrl_b_pins[] = {
4067 /* SCK, WS */
4068 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
4069 };
4070 static const unsigned int ssi9_ctrl_b_mux[] = {
4071 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4072 };
4073
4074 /* - TMU -------------------------------------------------------------------- */
4075 static const unsigned int tmu_tclk1_a_pins[] = {
4076 /* TCLK */
4077 RCAR_GP_PIN(6, 23),
4078 };
4079
4080 static const unsigned int tmu_tclk1_a_mux[] = {
4081 TCLK1_A_MARK,
4082 };
4083
4084 static const unsigned int tmu_tclk1_b_pins[] = {
4085 /* TCLK */
4086 RCAR_GP_PIN(5, 19),
4087 };
4088
4089 static const unsigned int tmu_tclk1_b_mux[] = {
4090 TCLK1_B_MARK,
4091 };
4092
4093 static const unsigned int tmu_tclk2_a_pins[] = {
4094 /* TCLK */
4095 RCAR_GP_PIN(6, 19),
4096 };
4097
4098 static const unsigned int tmu_tclk2_a_mux[] = {
4099 TCLK2_A_MARK,
4100 };
4101
4102 static const unsigned int tmu_tclk2_b_pins[] = {
4103 /* TCLK */
4104 RCAR_GP_PIN(6, 28),
4105 };
4106
4107 static const unsigned int tmu_tclk2_b_mux[] = {
4108 TCLK2_B_MARK,
4109 };
4110
4111 /* - TPU ------------------------------------------------------------------- */
4112 static const unsigned int tpu_to0_pins[] = {
4113 /* TPU0TO0 */
4114 RCAR_GP_PIN(6, 28),
4115 };
4116 static const unsigned int tpu_to0_mux[] = {
4117 TPU0TO0_MARK,
4118 };
4119 static const unsigned int tpu_to1_pins[] = {
4120 /* TPU0TO1 */
4121 RCAR_GP_PIN(6, 29),
4122 };
4123 static const unsigned int tpu_to1_mux[] = {
4124 TPU0TO1_MARK,
4125 };
4126 static const unsigned int tpu_to2_pins[] = {
4127 /* TPU0TO2 */
4128 RCAR_GP_PIN(6, 30),
4129 };
4130 static const unsigned int tpu_to2_mux[] = {
4131 TPU0TO2_MARK,
4132 };
4133 static const unsigned int tpu_to3_pins[] = {
4134 /* TPU0TO3 */
4135 RCAR_GP_PIN(6, 31),
4136 };
4137 static const unsigned int tpu_to3_mux[] = {
4138 TPU0TO3_MARK,
4139 };
4140
4141 /* - USB0 ------------------------------------------------------------------- */
4142 static const unsigned int usb0_pins[] = {
4143 /* PWEN, OVC */
4144 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4145 };
4146
4147 static const unsigned int usb0_mux[] = {
4148 USB0_PWEN_MARK, USB0_OVC_MARK,
4149 };
4150
4151 /* - USB1 ------------------------------------------------------------------- */
4152 static const unsigned int usb1_pins[] = {
4153 /* PWEN, OVC */
4154 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4155 };
4156
4157 static const unsigned int usb1_mux[] = {
4158 USB1_PWEN_MARK, USB1_OVC_MARK,
4159 };
4160
4161 /* - USB30 ------------------------------------------------------------------ */
4162 static const unsigned int usb30_pins[] = {
4163 /* PWEN, OVC */
4164 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4165 };
4166
4167 static const unsigned int usb30_mux[] = {
4168 USB30_PWEN_MARK, USB30_OVC_MARK,
4169 };
4170
4171 /* - VIN4 ------------------------------------------------------------------- */
4172 static const unsigned int vin4_data18_a_pins[] = {
4173 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4174 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4175 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4176 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4177 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4178 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4179 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4180 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4181 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4182 };
4183
4184 static const unsigned int vin4_data18_a_mux[] = {
4185 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4186 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4187 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4188 VI4_DATA10_MARK, VI4_DATA11_MARK,
4189 VI4_DATA12_MARK, VI4_DATA13_MARK,
4190 VI4_DATA14_MARK, VI4_DATA15_MARK,
4191 VI4_DATA18_MARK, VI4_DATA19_MARK,
4192 VI4_DATA20_MARK, VI4_DATA21_MARK,
4193 VI4_DATA22_MARK, VI4_DATA23_MARK,
4194 };
4195
4196 static const union vin_data vin4_data_a_pins = {
4197 .data24 = {
4198 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4199 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4200 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4201 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4202 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4203 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4204 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4205 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4206 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4207 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4208 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4209 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4210 },
4211 };
4212
4213 static const union vin_data vin4_data_a_mux = {
4214 .data24 = {
4215 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4216 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4217 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4218 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4219 VI4_DATA8_MARK, VI4_DATA9_MARK,
4220 VI4_DATA10_MARK, VI4_DATA11_MARK,
4221 VI4_DATA12_MARK, VI4_DATA13_MARK,
4222 VI4_DATA14_MARK, VI4_DATA15_MARK,
4223 VI4_DATA16_MARK, VI4_DATA17_MARK,
4224 VI4_DATA18_MARK, VI4_DATA19_MARK,
4225 VI4_DATA20_MARK, VI4_DATA21_MARK,
4226 VI4_DATA22_MARK, VI4_DATA23_MARK,
4227 },
4228 };
4229
4230 static const unsigned int vin4_data18_b_pins[] = {
4231 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4232 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4233 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4234 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4235 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4236 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4237 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4238 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4239 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4240 };
4241
4242 static const unsigned int vin4_data18_b_mux[] = {
4243 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4244 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4245 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4246 VI4_DATA10_MARK, VI4_DATA11_MARK,
4247 VI4_DATA12_MARK, VI4_DATA13_MARK,
4248 VI4_DATA14_MARK, VI4_DATA15_MARK,
4249 VI4_DATA18_MARK, VI4_DATA19_MARK,
4250 VI4_DATA20_MARK, VI4_DATA21_MARK,
4251 VI4_DATA22_MARK, VI4_DATA23_MARK,
4252 };
4253
4254 static const union vin_data vin4_data_b_pins = {
4255 .data24 = {
4256 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4257 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4258 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4259 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4260 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4261 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4262 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4263 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4264 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4265 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4266 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4267 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4268 },
4269 };
4270
4271 static const union vin_data vin4_data_b_mux = {
4272 .data24 = {
4273 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4274 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4275 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4276 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4277 VI4_DATA8_MARK, VI4_DATA9_MARK,
4278 VI4_DATA10_MARK, VI4_DATA11_MARK,
4279 VI4_DATA12_MARK, VI4_DATA13_MARK,
4280 VI4_DATA14_MARK, VI4_DATA15_MARK,
4281 VI4_DATA16_MARK, VI4_DATA17_MARK,
4282 VI4_DATA18_MARK, VI4_DATA19_MARK,
4283 VI4_DATA20_MARK, VI4_DATA21_MARK,
4284 VI4_DATA22_MARK, VI4_DATA23_MARK,
4285 },
4286 };
4287
4288 static const unsigned int vin4_sync_pins[] = {
4289 /* VSYNC_N, HSYNC_N */
4290 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
4291 };
4292
4293 static const unsigned int vin4_sync_mux[] = {
4294 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4295 };
4296
4297 static const unsigned int vin4_field_pins[] = {
4298 RCAR_GP_PIN(1, 16),
4299 };
4300
4301 static const unsigned int vin4_field_mux[] = {
4302 VI4_FIELD_MARK,
4303 };
4304
4305 static const unsigned int vin4_clkenb_pins[] = {
4306 RCAR_GP_PIN(1, 19),
4307 };
4308
4309 static const unsigned int vin4_clkenb_mux[] = {
4310 VI4_CLKENB_MARK,
4311 };
4312
4313 static const unsigned int vin4_clk_pins[] = {
4314 RCAR_GP_PIN(1, 27),
4315 };
4316
4317 static const unsigned int vin4_clk_mux[] = {
4318 VI4_CLK_MARK,
4319 };
4320
4321 /* - VIN5 ------------------------------------------------------------------- */
4322 static const union vin_data16 vin5_data_pins = {
4323 .data16 = {
4324 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4325 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4326 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4327 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4328 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4329 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4330 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4331 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4332 },
4333 };
4334
4335 static const union vin_data16 vin5_data_mux = {
4336 .data16 = {
4337 VI5_DATA0_MARK, VI5_DATA1_MARK,
4338 VI5_DATA2_MARK, VI5_DATA3_MARK,
4339 VI5_DATA4_MARK, VI5_DATA5_MARK,
4340 VI5_DATA6_MARK, VI5_DATA7_MARK,
4341 VI5_DATA8_MARK, VI5_DATA9_MARK,
4342 VI5_DATA10_MARK, VI5_DATA11_MARK,
4343 VI5_DATA12_MARK, VI5_DATA13_MARK,
4344 VI5_DATA14_MARK, VI5_DATA15_MARK,
4345 },
4346 };
4347
4348 static const unsigned int vin5_sync_pins[] = {
4349 /* VSYNC_N, HSYNC_N */
4350 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
4351 };
4352
4353 static const unsigned int vin5_sync_mux[] = {
4354 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4355 };
4356
4357 static const unsigned int vin5_field_pins[] = {
4358 RCAR_GP_PIN(1, 11),
4359 };
4360
4361 static const unsigned int vin5_field_mux[] = {
4362 VI5_FIELD_MARK,
4363 };
4364
4365 static const unsigned int vin5_clkenb_pins[] = {
4366 RCAR_GP_PIN(1, 20),
4367 };
4368
4369 static const unsigned int vin5_clkenb_mux[] = {
4370 VI5_CLKENB_MARK,
4371 };
4372
4373 static const unsigned int vin5_clk_pins[] = {
4374 RCAR_GP_PIN(1, 21),
4375 };
4376
4377 static const unsigned int vin5_clk_mux[] = {
4378 VI5_CLK_MARK,
4379 };
4380
4381 static const struct sh_pfc_pin_group pinmux_groups[] = {
4382 SH_PFC_PIN_GROUP(audio_clk_a_a),
4383 SH_PFC_PIN_GROUP(audio_clk_a_b),
4384 SH_PFC_PIN_GROUP(audio_clk_a_c),
4385 SH_PFC_PIN_GROUP(audio_clk_b_a),
4386 SH_PFC_PIN_GROUP(audio_clk_b_b),
4387 SH_PFC_PIN_GROUP(audio_clk_c_a),
4388 SH_PFC_PIN_GROUP(audio_clk_c_b),
4389 SH_PFC_PIN_GROUP(audio_clkout_a),
4390 SH_PFC_PIN_GROUP(audio_clkout_b),
4391 SH_PFC_PIN_GROUP(audio_clkout_c),
4392 SH_PFC_PIN_GROUP(audio_clkout_d),
4393 SH_PFC_PIN_GROUP(audio_clkout1_a),
4394 SH_PFC_PIN_GROUP(audio_clkout1_b),
4395 SH_PFC_PIN_GROUP(audio_clkout2_a),
4396 SH_PFC_PIN_GROUP(audio_clkout2_b),
4397 SH_PFC_PIN_GROUP(audio_clkout3_a),
4398 SH_PFC_PIN_GROUP(audio_clkout3_b),
4399 SH_PFC_PIN_GROUP(avb_link),
4400 SH_PFC_PIN_GROUP(avb_magic),
4401 SH_PFC_PIN_GROUP(avb_phy_int),
4402 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4403 SH_PFC_PIN_GROUP(avb_mdio),
4404 SH_PFC_PIN_GROUP(avb_mii),
4405 SH_PFC_PIN_GROUP(avb_avtp_pps),
4406 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4407 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4408 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4409 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4410 SH_PFC_PIN_GROUP(can0_data_a),
4411 SH_PFC_PIN_GROUP(can0_data_b),
4412 SH_PFC_PIN_GROUP(can1_data),
4413 SH_PFC_PIN_GROUP(can_clk),
4414 SH_PFC_PIN_GROUP(canfd0_data_a),
4415 SH_PFC_PIN_GROUP(canfd0_data_b),
4416 SH_PFC_PIN_GROUP(canfd1_data),
4417 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4418 SH_PFC_PIN_GROUP(drif0_data0_a),
4419 SH_PFC_PIN_GROUP(drif0_data1_a),
4420 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4421 SH_PFC_PIN_GROUP(drif0_data0_b),
4422 SH_PFC_PIN_GROUP(drif0_data1_b),
4423 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4424 SH_PFC_PIN_GROUP(drif0_data0_c),
4425 SH_PFC_PIN_GROUP(drif0_data1_c),
4426 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4427 SH_PFC_PIN_GROUP(drif1_data0_a),
4428 SH_PFC_PIN_GROUP(drif1_data1_a),
4429 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4430 SH_PFC_PIN_GROUP(drif1_data0_b),
4431 SH_PFC_PIN_GROUP(drif1_data1_b),
4432 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4433 SH_PFC_PIN_GROUP(drif1_data0_c),
4434 SH_PFC_PIN_GROUP(drif1_data1_c),
4435 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4436 SH_PFC_PIN_GROUP(drif2_data0_a),
4437 SH_PFC_PIN_GROUP(drif2_data1_a),
4438 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4439 SH_PFC_PIN_GROUP(drif2_data0_b),
4440 SH_PFC_PIN_GROUP(drif2_data1_b),
4441 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4442 SH_PFC_PIN_GROUP(drif3_data0_a),
4443 SH_PFC_PIN_GROUP(drif3_data1_a),
4444 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4445 SH_PFC_PIN_GROUP(drif3_data0_b),
4446 SH_PFC_PIN_GROUP(drif3_data1_b),
4447 SH_PFC_PIN_GROUP(du_rgb666),
4448 SH_PFC_PIN_GROUP(du_rgb888),
4449 SH_PFC_PIN_GROUP(du_clk_out_0),
4450 SH_PFC_PIN_GROUP(du_clk_out_1),
4451 SH_PFC_PIN_GROUP(du_sync),
4452 SH_PFC_PIN_GROUP(du_oddf),
4453 SH_PFC_PIN_GROUP(du_cde),
4454 SH_PFC_PIN_GROUP(du_disp),
4455 SH_PFC_PIN_GROUP(hscif0_data),
4456 SH_PFC_PIN_GROUP(hscif0_clk),
4457 SH_PFC_PIN_GROUP(hscif0_ctrl),
4458 SH_PFC_PIN_GROUP(hscif1_data_a),
4459 SH_PFC_PIN_GROUP(hscif1_clk_a),
4460 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4461 SH_PFC_PIN_GROUP(hscif1_data_b),
4462 SH_PFC_PIN_GROUP(hscif1_clk_b),
4463 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4464 SH_PFC_PIN_GROUP(hscif2_data_a),
4465 SH_PFC_PIN_GROUP(hscif2_clk_a),
4466 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4467 SH_PFC_PIN_GROUP(hscif2_data_b),
4468 SH_PFC_PIN_GROUP(hscif2_clk_b),
4469 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4470 SH_PFC_PIN_GROUP(hscif2_data_c),
4471 SH_PFC_PIN_GROUP(hscif2_clk_c),
4472 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4473 SH_PFC_PIN_GROUP(hscif3_data_a),
4474 SH_PFC_PIN_GROUP(hscif3_clk),
4475 SH_PFC_PIN_GROUP(hscif3_ctrl),
4476 SH_PFC_PIN_GROUP(hscif3_data_b),
4477 SH_PFC_PIN_GROUP(hscif3_data_c),
4478 SH_PFC_PIN_GROUP(hscif3_data_d),
4479 SH_PFC_PIN_GROUP(hscif4_data_a),
4480 SH_PFC_PIN_GROUP(hscif4_clk),
4481 SH_PFC_PIN_GROUP(hscif4_ctrl),
4482 SH_PFC_PIN_GROUP(hscif4_data_b),
4483 SH_PFC_PIN_GROUP(i2c0),
4484 SH_PFC_PIN_GROUP(i2c1_a),
4485 SH_PFC_PIN_GROUP(i2c1_b),
4486 SH_PFC_PIN_GROUP(i2c2_a),
4487 SH_PFC_PIN_GROUP(i2c2_b),
4488 SH_PFC_PIN_GROUP(i2c3),
4489 SH_PFC_PIN_GROUP(i2c5),
4490 SH_PFC_PIN_GROUP(i2c6_a),
4491 SH_PFC_PIN_GROUP(i2c6_b),
4492 SH_PFC_PIN_GROUP(i2c6_c),
4493 SH_PFC_PIN_GROUP(intc_ex_irq0),
4494 SH_PFC_PIN_GROUP(intc_ex_irq1),
4495 SH_PFC_PIN_GROUP(intc_ex_irq2),
4496 SH_PFC_PIN_GROUP(intc_ex_irq3),
4497 SH_PFC_PIN_GROUP(intc_ex_irq4),
4498 SH_PFC_PIN_GROUP(intc_ex_irq5),
4499 SH_PFC_PIN_GROUP(msiof0_clk),
4500 SH_PFC_PIN_GROUP(msiof0_sync),
4501 SH_PFC_PIN_GROUP(msiof0_ss1),
4502 SH_PFC_PIN_GROUP(msiof0_ss2),
4503 SH_PFC_PIN_GROUP(msiof0_txd),
4504 SH_PFC_PIN_GROUP(msiof0_rxd),
4505 SH_PFC_PIN_GROUP(msiof1_clk_a),
4506 SH_PFC_PIN_GROUP(msiof1_sync_a),
4507 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4508 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4509 SH_PFC_PIN_GROUP(msiof1_txd_a),
4510 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4511 SH_PFC_PIN_GROUP(msiof1_clk_b),
4512 SH_PFC_PIN_GROUP(msiof1_sync_b),
4513 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4514 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4515 SH_PFC_PIN_GROUP(msiof1_txd_b),
4516 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4517 SH_PFC_PIN_GROUP(msiof1_clk_c),
4518 SH_PFC_PIN_GROUP(msiof1_sync_c),
4519 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4520 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4521 SH_PFC_PIN_GROUP(msiof1_txd_c),
4522 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4523 SH_PFC_PIN_GROUP(msiof1_clk_d),
4524 SH_PFC_PIN_GROUP(msiof1_sync_d),
4525 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4526 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4527 SH_PFC_PIN_GROUP(msiof1_txd_d),
4528 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4529 SH_PFC_PIN_GROUP(msiof1_clk_e),
4530 SH_PFC_PIN_GROUP(msiof1_sync_e),
4531 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4532 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4533 SH_PFC_PIN_GROUP(msiof1_txd_e),
4534 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4535 SH_PFC_PIN_GROUP(msiof1_clk_f),
4536 SH_PFC_PIN_GROUP(msiof1_sync_f),
4537 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4538 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4539 SH_PFC_PIN_GROUP(msiof1_txd_f),
4540 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4541 SH_PFC_PIN_GROUP(msiof1_clk_g),
4542 SH_PFC_PIN_GROUP(msiof1_sync_g),
4543 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4544 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4545 SH_PFC_PIN_GROUP(msiof1_txd_g),
4546 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4547 SH_PFC_PIN_GROUP(msiof2_clk_a),
4548 SH_PFC_PIN_GROUP(msiof2_sync_a),
4549 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4550 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4551 SH_PFC_PIN_GROUP(msiof2_txd_a),
4552 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4553 SH_PFC_PIN_GROUP(msiof2_clk_b),
4554 SH_PFC_PIN_GROUP(msiof2_sync_b),
4555 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4556 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4557 SH_PFC_PIN_GROUP(msiof2_txd_b),
4558 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4559 SH_PFC_PIN_GROUP(msiof2_clk_c),
4560 SH_PFC_PIN_GROUP(msiof2_sync_c),
4561 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4562 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4563 SH_PFC_PIN_GROUP(msiof2_txd_c),
4564 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4565 SH_PFC_PIN_GROUP(msiof2_clk_d),
4566 SH_PFC_PIN_GROUP(msiof2_sync_d),
4567 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4568 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4569 SH_PFC_PIN_GROUP(msiof2_txd_d),
4570 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4571 SH_PFC_PIN_GROUP(msiof3_clk_a),
4572 SH_PFC_PIN_GROUP(msiof3_sync_a),
4573 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4574 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4575 SH_PFC_PIN_GROUP(msiof3_txd_a),
4576 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4577 SH_PFC_PIN_GROUP(msiof3_clk_b),
4578 SH_PFC_PIN_GROUP(msiof3_sync_b),
4579 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4580 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4581 SH_PFC_PIN_GROUP(msiof3_txd_b),
4582 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4583 SH_PFC_PIN_GROUP(msiof3_clk_c),
4584 SH_PFC_PIN_GROUP(msiof3_sync_c),
4585 SH_PFC_PIN_GROUP(msiof3_txd_c),
4586 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4587 SH_PFC_PIN_GROUP(msiof3_clk_d),
4588 SH_PFC_PIN_GROUP(msiof3_sync_d),
4589 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4590 SH_PFC_PIN_GROUP(msiof3_txd_d),
4591 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4592 SH_PFC_PIN_GROUP(msiof3_clk_e),
4593 SH_PFC_PIN_GROUP(msiof3_sync_e),
4594 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4595 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4596 SH_PFC_PIN_GROUP(msiof3_txd_e),
4597 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4598 SH_PFC_PIN_GROUP(pwm0),
4599 SH_PFC_PIN_GROUP(pwm1_a),
4600 SH_PFC_PIN_GROUP(pwm1_b),
4601 SH_PFC_PIN_GROUP(pwm2_a),
4602 SH_PFC_PIN_GROUP(pwm2_b),
4603 SH_PFC_PIN_GROUP(pwm3_a),
4604 SH_PFC_PIN_GROUP(pwm3_b),
4605 SH_PFC_PIN_GROUP(pwm4_a),
4606 SH_PFC_PIN_GROUP(pwm4_b),
4607 SH_PFC_PIN_GROUP(pwm5_a),
4608 SH_PFC_PIN_GROUP(pwm5_b),
4609 SH_PFC_PIN_GROUP(pwm6_a),
4610 SH_PFC_PIN_GROUP(pwm6_b),
4611 SH_PFC_PIN_GROUP(sata0_devslp_a),
4612 SH_PFC_PIN_GROUP(sata0_devslp_b),
4613 SH_PFC_PIN_GROUP(scif0_data),
4614 SH_PFC_PIN_GROUP(scif0_clk),
4615 SH_PFC_PIN_GROUP(scif0_ctrl),
4616 SH_PFC_PIN_GROUP(scif1_data_a),
4617 SH_PFC_PIN_GROUP(scif1_clk),
4618 SH_PFC_PIN_GROUP(scif1_ctrl),
4619 SH_PFC_PIN_GROUP(scif1_data_b),
4620 SH_PFC_PIN_GROUP(scif2_data_a),
4621 SH_PFC_PIN_GROUP(scif2_clk),
4622 SH_PFC_PIN_GROUP(scif2_data_b),
4623 SH_PFC_PIN_GROUP(scif3_data_a),
4624 SH_PFC_PIN_GROUP(scif3_clk),
4625 SH_PFC_PIN_GROUP(scif3_ctrl),
4626 SH_PFC_PIN_GROUP(scif3_data_b),
4627 SH_PFC_PIN_GROUP(scif4_data_a),
4628 SH_PFC_PIN_GROUP(scif4_clk_a),
4629 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4630 SH_PFC_PIN_GROUP(scif4_data_b),
4631 SH_PFC_PIN_GROUP(scif4_clk_b),
4632 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4633 SH_PFC_PIN_GROUP(scif4_data_c),
4634 SH_PFC_PIN_GROUP(scif4_clk_c),
4635 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4636 SH_PFC_PIN_GROUP(scif5_data_a),
4637 SH_PFC_PIN_GROUP(scif5_clk_a),
4638 SH_PFC_PIN_GROUP(scif5_data_b),
4639 SH_PFC_PIN_GROUP(scif5_clk_b),
4640 SH_PFC_PIN_GROUP(scif_clk_a),
4641 SH_PFC_PIN_GROUP(scif_clk_b),
4642 SH_PFC_PIN_GROUP(sdhi0_data1),
4643 SH_PFC_PIN_GROUP(sdhi0_data4),
4644 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4645 SH_PFC_PIN_GROUP(sdhi0_cd),
4646 SH_PFC_PIN_GROUP(sdhi0_wp),
4647 SH_PFC_PIN_GROUP(sdhi1_data1),
4648 SH_PFC_PIN_GROUP(sdhi1_data4),
4649 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4650 SH_PFC_PIN_GROUP(sdhi1_cd),
4651 SH_PFC_PIN_GROUP(sdhi1_wp),
4652 SH_PFC_PIN_GROUP(sdhi2_data1),
4653 SH_PFC_PIN_GROUP(sdhi2_data4),
4654 SH_PFC_PIN_GROUP(sdhi2_data8),
4655 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4656 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4657 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4658 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4659 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4660 SH_PFC_PIN_GROUP(sdhi2_ds),
4661 SH_PFC_PIN_GROUP(sdhi3_data1),
4662 SH_PFC_PIN_GROUP(sdhi3_data4),
4663 SH_PFC_PIN_GROUP(sdhi3_data8),
4664 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4665 SH_PFC_PIN_GROUP(sdhi3_cd),
4666 SH_PFC_PIN_GROUP(sdhi3_wp),
4667 SH_PFC_PIN_GROUP(sdhi3_ds),
4668 SH_PFC_PIN_GROUP(ssi0_data),
4669 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4670 SH_PFC_PIN_GROUP(ssi1_data_a),
4671 SH_PFC_PIN_GROUP(ssi1_data_b),
4672 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4673 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4674 SH_PFC_PIN_GROUP(ssi2_data_a),
4675 SH_PFC_PIN_GROUP(ssi2_data_b),
4676 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4677 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4678 SH_PFC_PIN_GROUP(ssi3_data),
4679 SH_PFC_PIN_GROUP(ssi349_ctrl),
4680 SH_PFC_PIN_GROUP(ssi4_data),
4681 SH_PFC_PIN_GROUP(ssi4_ctrl),
4682 SH_PFC_PIN_GROUP(ssi5_data),
4683 SH_PFC_PIN_GROUP(ssi5_ctrl),
4684 SH_PFC_PIN_GROUP(ssi6_data),
4685 SH_PFC_PIN_GROUP(ssi6_ctrl),
4686 SH_PFC_PIN_GROUP(ssi7_data),
4687 SH_PFC_PIN_GROUP(ssi78_ctrl),
4688 SH_PFC_PIN_GROUP(ssi8_data),
4689 SH_PFC_PIN_GROUP(ssi9_data_a),
4690 SH_PFC_PIN_GROUP(ssi9_data_b),
4691 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4692 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4693 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4694 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4695 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4696 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4697 SH_PFC_PIN_GROUP(tpu_to0),
4698 SH_PFC_PIN_GROUP(tpu_to1),
4699 SH_PFC_PIN_GROUP(tpu_to2),
4700 SH_PFC_PIN_GROUP(tpu_to3),
4701 SH_PFC_PIN_GROUP(usb0),
4702 SH_PFC_PIN_GROUP(usb1),
4703 SH_PFC_PIN_GROUP(usb30),
4704 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4705 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4706 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4707 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4708 SH_PFC_PIN_GROUP(vin4_data18_a),
4709 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4710 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4711 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4712 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4713 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4714 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4715 SH_PFC_PIN_GROUP(vin4_data18_b),
4716 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4717 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4718 SH_PFC_PIN_GROUP(vin4_sync),
4719 SH_PFC_PIN_GROUP(vin4_field),
4720 SH_PFC_PIN_GROUP(vin4_clkenb),
4721 SH_PFC_PIN_GROUP(vin4_clk),
4722 VIN_DATA_PIN_GROUP(vin5_data, 8),
4723 VIN_DATA_PIN_GROUP(vin5_data, 10),
4724 VIN_DATA_PIN_GROUP(vin5_data, 12),
4725 VIN_DATA_PIN_GROUP(vin5_data, 16),
4726 SH_PFC_PIN_GROUP(vin5_sync),
4727 SH_PFC_PIN_GROUP(vin5_field),
4728 SH_PFC_PIN_GROUP(vin5_clkenb),
4729 SH_PFC_PIN_GROUP(vin5_clk),
4730 };
4731
4732 static const char * const audio_clk_groups[] = {
4733 "audio_clk_a_a",
4734 "audio_clk_a_b",
4735 "audio_clk_a_c",
4736 "audio_clk_b_a",
4737 "audio_clk_b_b",
4738 "audio_clk_c_a",
4739 "audio_clk_c_b",
4740 "audio_clkout_a",
4741 "audio_clkout_b",
4742 "audio_clkout_c",
4743 "audio_clkout_d",
4744 "audio_clkout1_a",
4745 "audio_clkout1_b",
4746 "audio_clkout2_a",
4747 "audio_clkout2_b",
4748 "audio_clkout3_a",
4749 "audio_clkout3_b",
4750 };
4751
4752 static const char * const avb_groups[] = {
4753 "avb_link",
4754 "avb_magic",
4755 "avb_phy_int",
4756 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4757 "avb_mdio",
4758 "avb_mii",
4759 "avb_avtp_pps",
4760 "avb_avtp_match_a",
4761 "avb_avtp_capture_a",
4762 "avb_avtp_match_b",
4763 "avb_avtp_capture_b",
4764 };
4765
4766 static const char * const can0_groups[] = {
4767 "can0_data_a",
4768 "can0_data_b",
4769 };
4770
4771 static const char * const can1_groups[] = {
4772 "can1_data",
4773 };
4774
4775 static const char * const can_clk_groups[] = {
4776 "can_clk",
4777 };
4778
4779 static const char * const canfd0_groups[] = {
4780 "canfd0_data_a",
4781 "canfd0_data_b",
4782 };
4783
4784 static const char * const canfd1_groups[] = {
4785 "canfd1_data",
4786 };
4787
4788 static const char * const drif0_groups[] = {
4789 "drif0_ctrl_a",
4790 "drif0_data0_a",
4791 "drif0_data1_a",
4792 "drif0_ctrl_b",
4793 "drif0_data0_b",
4794 "drif0_data1_b",
4795 "drif0_ctrl_c",
4796 "drif0_data0_c",
4797 "drif0_data1_c",
4798 };
4799
4800 static const char * const drif1_groups[] = {
4801 "drif1_ctrl_a",
4802 "drif1_data0_a",
4803 "drif1_data1_a",
4804 "drif1_ctrl_b",
4805 "drif1_data0_b",
4806 "drif1_data1_b",
4807 "drif1_ctrl_c",
4808 "drif1_data0_c",
4809 "drif1_data1_c",
4810 };
4811
4812 static const char * const drif2_groups[] = {
4813 "drif2_ctrl_a",
4814 "drif2_data0_a",
4815 "drif2_data1_a",
4816 "drif2_ctrl_b",
4817 "drif2_data0_b",
4818 "drif2_data1_b",
4819 };
4820
4821 static const char * const drif3_groups[] = {
4822 "drif3_ctrl_a",
4823 "drif3_data0_a",
4824 "drif3_data1_a",
4825 "drif3_ctrl_b",
4826 "drif3_data0_b",
4827 "drif3_data1_b",
4828 };
4829
4830 static const char * const du_groups[] = {
4831 "du_rgb666",
4832 "du_rgb888",
4833 "du_clk_out_0",
4834 "du_clk_out_1",
4835 "du_sync",
4836 "du_oddf",
4837 "du_cde",
4838 "du_disp",
4839 };
4840
4841 static const char * const hscif0_groups[] = {
4842 "hscif0_data",
4843 "hscif0_clk",
4844 "hscif0_ctrl",
4845 };
4846
4847 static const char * const hscif1_groups[] = {
4848 "hscif1_data_a",
4849 "hscif1_clk_a",
4850 "hscif1_ctrl_a",
4851 "hscif1_data_b",
4852 "hscif1_clk_b",
4853 "hscif1_ctrl_b",
4854 };
4855
4856 static const char * const hscif2_groups[] = {
4857 "hscif2_data_a",
4858 "hscif2_clk_a",
4859 "hscif2_ctrl_a",
4860 "hscif2_data_b",
4861 "hscif2_clk_b",
4862 "hscif2_ctrl_b",
4863 "hscif2_data_c",
4864 "hscif2_clk_c",
4865 "hscif2_ctrl_c",
4866 };
4867
4868 static const char * const hscif3_groups[] = {
4869 "hscif3_data_a",
4870 "hscif3_clk",
4871 "hscif3_ctrl",
4872 "hscif3_data_b",
4873 "hscif3_data_c",
4874 "hscif3_data_d",
4875 };
4876
4877 static const char * const hscif4_groups[] = {
4878 "hscif4_data_a",
4879 "hscif4_clk",
4880 "hscif4_ctrl",
4881 "hscif4_data_b",
4882 };
4883
4884 static const char * const i2c0_groups[] = {
4885 "i2c0",
4886 };
4887
4888 static const char * const i2c1_groups[] = {
4889 "i2c1_a",
4890 "i2c1_b",
4891 };
4892
4893 static const char * const i2c2_groups[] = {
4894 "i2c2_a",
4895 "i2c2_b",
4896 };
4897
4898 static const char * const i2c3_groups[] = {
4899 "i2c3",
4900 };
4901
4902 static const char * const i2c5_groups[] = {
4903 "i2c5",
4904 };
4905
4906 static const char * const i2c6_groups[] = {
4907 "i2c6_a",
4908 "i2c6_b",
4909 "i2c6_c",
4910 };
4911
4912 static const char * const intc_ex_groups[] = {
4913 "intc_ex_irq0",
4914 "intc_ex_irq1",
4915 "intc_ex_irq2",
4916 "intc_ex_irq3",
4917 "intc_ex_irq4",
4918 "intc_ex_irq5",
4919 };
4920
4921 static const char * const msiof0_groups[] = {
4922 "msiof0_clk",
4923 "msiof0_sync",
4924 "msiof0_ss1",
4925 "msiof0_ss2",
4926 "msiof0_txd",
4927 "msiof0_rxd",
4928 };
4929
4930 static const char * const msiof1_groups[] = {
4931 "msiof1_clk_a",
4932 "msiof1_sync_a",
4933 "msiof1_ss1_a",
4934 "msiof1_ss2_a",
4935 "msiof1_txd_a",
4936 "msiof1_rxd_a",
4937 "msiof1_clk_b",
4938 "msiof1_sync_b",
4939 "msiof1_ss1_b",
4940 "msiof1_ss2_b",
4941 "msiof1_txd_b",
4942 "msiof1_rxd_b",
4943 "msiof1_clk_c",
4944 "msiof1_sync_c",
4945 "msiof1_ss1_c",
4946 "msiof1_ss2_c",
4947 "msiof1_txd_c",
4948 "msiof1_rxd_c",
4949 "msiof1_clk_d",
4950 "msiof1_sync_d",
4951 "msiof1_ss1_d",
4952 "msiof1_ss2_d",
4953 "msiof1_txd_d",
4954 "msiof1_rxd_d",
4955 "msiof1_clk_e",
4956 "msiof1_sync_e",
4957 "msiof1_ss1_e",
4958 "msiof1_ss2_e",
4959 "msiof1_txd_e",
4960 "msiof1_rxd_e",
4961 "msiof1_clk_f",
4962 "msiof1_sync_f",
4963 "msiof1_ss1_f",
4964 "msiof1_ss2_f",
4965 "msiof1_txd_f",
4966 "msiof1_rxd_f",
4967 "msiof1_clk_g",
4968 "msiof1_sync_g",
4969 "msiof1_ss1_g",
4970 "msiof1_ss2_g",
4971 "msiof1_txd_g",
4972 "msiof1_rxd_g",
4973 };
4974
4975 static const char * const msiof2_groups[] = {
4976 "msiof2_clk_a",
4977 "msiof2_sync_a",
4978 "msiof2_ss1_a",
4979 "msiof2_ss2_a",
4980 "msiof2_txd_a",
4981 "msiof2_rxd_a",
4982 "msiof2_clk_b",
4983 "msiof2_sync_b",
4984 "msiof2_ss1_b",
4985 "msiof2_ss2_b",
4986 "msiof2_txd_b",
4987 "msiof2_rxd_b",
4988 "msiof2_clk_c",
4989 "msiof2_sync_c",
4990 "msiof2_ss1_c",
4991 "msiof2_ss2_c",
4992 "msiof2_txd_c",
4993 "msiof2_rxd_c",
4994 "msiof2_clk_d",
4995 "msiof2_sync_d",
4996 "msiof2_ss1_d",
4997 "msiof2_ss2_d",
4998 "msiof2_txd_d",
4999 "msiof2_rxd_d",
5000 };
5001
5002 static const char * const msiof3_groups[] = {
5003 "msiof3_clk_a",
5004 "msiof3_sync_a",
5005 "msiof3_ss1_a",
5006 "msiof3_ss2_a",
5007 "msiof3_txd_a",
5008 "msiof3_rxd_a",
5009 "msiof3_clk_b",
5010 "msiof3_sync_b",
5011 "msiof3_ss1_b",
5012 "msiof3_ss2_b",
5013 "msiof3_txd_b",
5014 "msiof3_rxd_b",
5015 "msiof3_clk_c",
5016 "msiof3_sync_c",
5017 "msiof3_txd_c",
5018 "msiof3_rxd_c",
5019 "msiof3_clk_d",
5020 "msiof3_sync_d",
5021 "msiof3_ss1_d",
5022 "msiof3_txd_d",
5023 "msiof3_rxd_d",
5024 "msiof3_clk_e",
5025 "msiof3_sync_e",
5026 "msiof3_ss1_e",
5027 "msiof3_ss2_e",
5028 "msiof3_txd_e",
5029 "msiof3_rxd_e",
5030 };
5031
5032 static const char * const pwm0_groups[] = {
5033 "pwm0",
5034 };
5035
5036 static const char * const pwm1_groups[] = {
5037 "pwm1_a",
5038 "pwm1_b",
5039 };
5040
5041 static const char * const pwm2_groups[] = {
5042 "pwm2_a",
5043 "pwm2_b",
5044 };
5045
5046 static const char * const pwm3_groups[] = {
5047 "pwm3_a",
5048 "pwm3_b",
5049 };
5050
5051 static const char * const pwm4_groups[] = {
5052 "pwm4_a",
5053 "pwm4_b",
5054 };
5055
5056 static const char * const pwm5_groups[] = {
5057 "pwm5_a",
5058 "pwm5_b",
5059 };
5060
5061 static const char * const pwm6_groups[] = {
5062 "pwm6_a",
5063 "pwm6_b",
5064 };
5065
5066 static const char * const sata0_groups[] = {
5067 "sata0_devslp_a",
5068 "sata0_devslp_b",
5069 };
5070
5071 static const char * const scif0_groups[] = {
5072 "scif0_data",
5073 "scif0_clk",
5074 "scif0_ctrl",
5075 };
5076
5077 static const char * const scif1_groups[] = {
5078 "scif1_data_a",
5079 "scif1_clk",
5080 "scif1_ctrl",
5081 "scif1_data_b",
5082 };
5083 static const char * const scif2_groups[] = {
5084 "scif2_data_a",
5085 "scif2_clk",
5086 "scif2_data_b",
5087 };
5088
5089 static const char * const scif3_groups[] = {
5090 "scif3_data_a",
5091 "scif3_clk",
5092 "scif3_ctrl",
5093 "scif3_data_b",
5094 };
5095
5096 static const char * const scif4_groups[] = {
5097 "scif4_data_a",
5098 "scif4_clk_a",
5099 "scif4_ctrl_a",
5100 "scif4_data_b",
5101 "scif4_clk_b",
5102 "scif4_ctrl_b",
5103 "scif4_data_c",
5104 "scif4_clk_c",
5105 "scif4_ctrl_c",
5106 };
5107
5108 static const char * const scif5_groups[] = {
5109 "scif5_data_a",
5110 "scif5_clk_a",
5111 "scif5_data_b",
5112 "scif5_clk_b",
5113 };
5114
5115 static const char * const scif_clk_groups[] = {
5116 "scif_clk_a",
5117 "scif_clk_b",
5118 };
5119
5120 static const char * const sdhi0_groups[] = {
5121 "sdhi0_data1",
5122 "sdhi0_data4",
5123 "sdhi0_ctrl",
5124 "sdhi0_cd",
5125 "sdhi0_wp",
5126 };
5127
5128 static const char * const sdhi1_groups[] = {
5129 "sdhi1_data1",
5130 "sdhi1_data4",
5131 "sdhi1_ctrl",
5132 "sdhi1_cd",
5133 "sdhi1_wp",
5134 };
5135
5136 static const char * const sdhi2_groups[] = {
5137 "sdhi2_data1",
5138 "sdhi2_data4",
5139 "sdhi2_data8",
5140 "sdhi2_ctrl",
5141 "sdhi2_cd_a",
5142 "sdhi2_wp_a",
5143 "sdhi2_cd_b",
5144 "sdhi2_wp_b",
5145 "sdhi2_ds",
5146 };
5147
5148 static const char * const sdhi3_groups[] = {
5149 "sdhi3_data1",
5150 "sdhi3_data4",
5151 "sdhi3_data8",
5152 "sdhi3_ctrl",
5153 "sdhi3_cd",
5154 "sdhi3_wp",
5155 "sdhi3_ds",
5156 };
5157
5158 static const char * const ssi_groups[] = {
5159 "ssi0_data",
5160 "ssi01239_ctrl",
5161 "ssi1_data_a",
5162 "ssi1_data_b",
5163 "ssi1_ctrl_a",
5164 "ssi1_ctrl_b",
5165 "ssi2_data_a",
5166 "ssi2_data_b",
5167 "ssi2_ctrl_a",
5168 "ssi2_ctrl_b",
5169 "ssi3_data",
5170 "ssi349_ctrl",
5171 "ssi4_data",
5172 "ssi4_ctrl",
5173 "ssi5_data",
5174 "ssi5_ctrl",
5175 "ssi6_data",
5176 "ssi6_ctrl",
5177 "ssi7_data",
5178 "ssi78_ctrl",
5179 "ssi8_data",
5180 "ssi9_data_a",
5181 "ssi9_data_b",
5182 "ssi9_ctrl_a",
5183 "ssi9_ctrl_b",
5184 };
5185
5186 static const char * const tmu_groups[] = {
5187 "tmu_tclk1_a",
5188 "tmu_tclk1_b",
5189 "tmu_tclk2_a",
5190 "tmu_tclk2_b",
5191 };
5192
5193 static const char * const tpu_groups[] = {
5194 "tpu_to0",
5195 "tpu_to1",
5196 "tpu_to2",
5197 "tpu_to3",
5198 };
5199
5200 static const char * const usb0_groups[] = {
5201 "usb0",
5202 };
5203
5204 static const char * const usb1_groups[] = {
5205 "usb1",
5206 };
5207
5208 static const char * const usb30_groups[] = {
5209 "usb30",
5210 };
5211
5212 static const char * const vin4_groups[] = {
5213 "vin4_data8_a",
5214 "vin4_data10_a",
5215 "vin4_data12_a",
5216 "vin4_data16_a",
5217 "vin4_data18_a",
5218 "vin4_data20_a",
5219 "vin4_data24_a",
5220 "vin4_data8_b",
5221 "vin4_data10_b",
5222 "vin4_data12_b",
5223 "vin4_data16_b",
5224 "vin4_data18_b",
5225 "vin4_data20_b",
5226 "vin4_data24_b",
5227 "vin4_sync",
5228 "vin4_field",
5229 "vin4_clkenb",
5230 "vin4_clk",
5231 };
5232
5233 static const char * const vin5_groups[] = {
5234 "vin5_data8",
5235 "vin5_data10",
5236 "vin5_data12",
5237 "vin5_data16",
5238 "vin5_sync",
5239 "vin5_field",
5240 "vin5_clkenb",
5241 "vin5_clk",
5242 };
5243
5244 static const struct sh_pfc_function pinmux_functions[] = {
5245 SH_PFC_FUNCTION(audio_clk),
5246 SH_PFC_FUNCTION(avb),
5247 SH_PFC_FUNCTION(can0),
5248 SH_PFC_FUNCTION(can1),
5249 SH_PFC_FUNCTION(can_clk),
5250 SH_PFC_FUNCTION(canfd0),
5251 SH_PFC_FUNCTION(canfd1),
5252 SH_PFC_FUNCTION(drif0),
5253 SH_PFC_FUNCTION(drif1),
5254 SH_PFC_FUNCTION(drif2),
5255 SH_PFC_FUNCTION(drif3),
5256 SH_PFC_FUNCTION(du),
5257 SH_PFC_FUNCTION(hscif0),
5258 SH_PFC_FUNCTION(hscif1),
5259 SH_PFC_FUNCTION(hscif2),
5260 SH_PFC_FUNCTION(hscif3),
5261 SH_PFC_FUNCTION(hscif4),
5262 SH_PFC_FUNCTION(i2c0),
5263 SH_PFC_FUNCTION(i2c1),
5264 SH_PFC_FUNCTION(i2c2),
5265 SH_PFC_FUNCTION(i2c3),
5266 SH_PFC_FUNCTION(i2c5),
5267 SH_PFC_FUNCTION(i2c6),
5268 SH_PFC_FUNCTION(intc_ex),
5269 SH_PFC_FUNCTION(msiof0),
5270 SH_PFC_FUNCTION(msiof1),
5271 SH_PFC_FUNCTION(msiof2),
5272 SH_PFC_FUNCTION(msiof3),
5273 SH_PFC_FUNCTION(pwm0),
5274 SH_PFC_FUNCTION(pwm1),
5275 SH_PFC_FUNCTION(pwm2),
5276 SH_PFC_FUNCTION(pwm3),
5277 SH_PFC_FUNCTION(pwm4),
5278 SH_PFC_FUNCTION(pwm5),
5279 SH_PFC_FUNCTION(pwm6),
5280 SH_PFC_FUNCTION(sata0),
5281 SH_PFC_FUNCTION(scif0),
5282 SH_PFC_FUNCTION(scif1),
5283 SH_PFC_FUNCTION(scif2),
5284 SH_PFC_FUNCTION(scif3),
5285 SH_PFC_FUNCTION(scif4),
5286 SH_PFC_FUNCTION(scif5),
5287 SH_PFC_FUNCTION(scif_clk),
5288 SH_PFC_FUNCTION(sdhi0),
5289 SH_PFC_FUNCTION(sdhi1),
5290 SH_PFC_FUNCTION(sdhi2),
5291 SH_PFC_FUNCTION(sdhi3),
5292 SH_PFC_FUNCTION(ssi),
5293 SH_PFC_FUNCTION(tmu),
5294 SH_PFC_FUNCTION(tpu),
5295 SH_PFC_FUNCTION(usb0),
5296 SH_PFC_FUNCTION(usb1),
5297 SH_PFC_FUNCTION(usb30),
5298 SH_PFC_FUNCTION(vin4),
5299 SH_PFC_FUNCTION(vin5),
5300 };
5301
5302 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5303 #define F_(x, y) FN_##y
5304 #define FM(x) FN_##x
5305 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5306 0, 0,
5307 0, 0,
5308 0, 0,
5309 0, 0,
5310 0, 0,
5311 0, 0,
5312 0, 0,
5313 0, 0,
5314 0, 0,
5315 0, 0,
5316 0, 0,
5317 0, 0,
5318 0, 0,
5319 0, 0,
5320 0, 0,
5321 0, 0,
5322 GP_0_15_FN, GPSR0_15,
5323 GP_0_14_FN, GPSR0_14,
5324 GP_0_13_FN, GPSR0_13,
5325 GP_0_12_FN, GPSR0_12,
5326 GP_0_11_FN, GPSR0_11,
5327 GP_0_10_FN, GPSR0_10,
5328 GP_0_9_FN, GPSR0_9,
5329 GP_0_8_FN, GPSR0_8,
5330 GP_0_7_FN, GPSR0_7,
5331 GP_0_6_FN, GPSR0_6,
5332 GP_0_5_FN, GPSR0_5,
5333 GP_0_4_FN, GPSR0_4,
5334 GP_0_3_FN, GPSR0_3,
5335 GP_0_2_FN, GPSR0_2,
5336 GP_0_1_FN, GPSR0_1,
5337 GP_0_0_FN, GPSR0_0, ))
5338 },
5339 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5340 0, 0,
5341 0, 0,
5342 0, 0,
5343 GP_1_28_FN, GPSR1_28,
5344 GP_1_27_FN, GPSR1_27,
5345 GP_1_26_FN, GPSR1_26,
5346 GP_1_25_FN, GPSR1_25,
5347 GP_1_24_FN, GPSR1_24,
5348 GP_1_23_FN, GPSR1_23,
5349 GP_1_22_FN, GPSR1_22,
5350 GP_1_21_FN, GPSR1_21,
5351 GP_1_20_FN, GPSR1_20,
5352 GP_1_19_FN, GPSR1_19,
5353 GP_1_18_FN, GPSR1_18,
5354 GP_1_17_FN, GPSR1_17,
5355 GP_1_16_FN, GPSR1_16,
5356 GP_1_15_FN, GPSR1_15,
5357 GP_1_14_FN, GPSR1_14,
5358 GP_1_13_FN, GPSR1_13,
5359 GP_1_12_FN, GPSR1_12,
5360 GP_1_11_FN, GPSR1_11,
5361 GP_1_10_FN, GPSR1_10,
5362 GP_1_9_FN, GPSR1_9,
5363 GP_1_8_FN, GPSR1_8,
5364 GP_1_7_FN, GPSR1_7,
5365 GP_1_6_FN, GPSR1_6,
5366 GP_1_5_FN, GPSR1_5,
5367 GP_1_4_FN, GPSR1_4,
5368 GP_1_3_FN, GPSR1_3,
5369 GP_1_2_FN, GPSR1_2,
5370 GP_1_1_FN, GPSR1_1,
5371 GP_1_0_FN, GPSR1_0, ))
5372 },
5373 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5374 0, 0,
5375 0, 0,
5376 0, 0,
5377 0, 0,
5378 0, 0,
5379 0, 0,
5380 0, 0,
5381 0, 0,
5382 0, 0,
5383 0, 0,
5384 0, 0,
5385 0, 0,
5386 0, 0,
5387 0, 0,
5388 0, 0,
5389 0, 0,
5390 0, 0,
5391 GP_2_14_FN, GPSR2_14,
5392 GP_2_13_FN, GPSR2_13,
5393 GP_2_12_FN, GPSR2_12,
5394 GP_2_11_FN, GPSR2_11,
5395 GP_2_10_FN, GPSR2_10,
5396 GP_2_9_FN, GPSR2_9,
5397 GP_2_8_FN, GPSR2_8,
5398 GP_2_7_FN, GPSR2_7,
5399 GP_2_6_FN, GPSR2_6,
5400 GP_2_5_FN, GPSR2_5,
5401 GP_2_4_FN, GPSR2_4,
5402 GP_2_3_FN, GPSR2_3,
5403 GP_2_2_FN, GPSR2_2,
5404 GP_2_1_FN, GPSR2_1,
5405 GP_2_0_FN, GPSR2_0, ))
5406 },
5407 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5408 0, 0,
5409 0, 0,
5410 0, 0,
5411 0, 0,
5412 0, 0,
5413 0, 0,
5414 0, 0,
5415 0, 0,
5416 0, 0,
5417 0, 0,
5418 0, 0,
5419 0, 0,
5420 0, 0,
5421 0, 0,
5422 0, 0,
5423 0, 0,
5424 GP_3_15_FN, GPSR3_15,
5425 GP_3_14_FN, GPSR3_14,
5426 GP_3_13_FN, GPSR3_13,
5427 GP_3_12_FN, GPSR3_12,
5428 GP_3_11_FN, GPSR3_11,
5429 GP_3_10_FN, GPSR3_10,
5430 GP_3_9_FN, GPSR3_9,
5431 GP_3_8_FN, GPSR3_8,
5432 GP_3_7_FN, GPSR3_7,
5433 GP_3_6_FN, GPSR3_6,
5434 GP_3_5_FN, GPSR3_5,
5435 GP_3_4_FN, GPSR3_4,
5436 GP_3_3_FN, GPSR3_3,
5437 GP_3_2_FN, GPSR3_2,
5438 GP_3_1_FN, GPSR3_1,
5439 GP_3_0_FN, GPSR3_0, ))
5440 },
5441 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5442 0, 0,
5443 0, 0,
5444 0, 0,
5445 0, 0,
5446 0, 0,
5447 0, 0,
5448 0, 0,
5449 0, 0,
5450 0, 0,
5451 0, 0,
5452 0, 0,
5453 0, 0,
5454 0, 0,
5455 0, 0,
5456 GP_4_17_FN, GPSR4_17,
5457 GP_4_16_FN, GPSR4_16,
5458 GP_4_15_FN, GPSR4_15,
5459 GP_4_14_FN, GPSR4_14,
5460 GP_4_13_FN, GPSR4_13,
5461 GP_4_12_FN, GPSR4_12,
5462 GP_4_11_FN, GPSR4_11,
5463 GP_4_10_FN, GPSR4_10,
5464 GP_4_9_FN, GPSR4_9,
5465 GP_4_8_FN, GPSR4_8,
5466 GP_4_7_FN, GPSR4_7,
5467 GP_4_6_FN, GPSR4_6,
5468 GP_4_5_FN, GPSR4_5,
5469 GP_4_4_FN, GPSR4_4,
5470 GP_4_3_FN, GPSR4_3,
5471 GP_4_2_FN, GPSR4_2,
5472 GP_4_1_FN, GPSR4_1,
5473 GP_4_0_FN, GPSR4_0, ))
5474 },
5475 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5476 0, 0,
5477 0, 0,
5478 0, 0,
5479 0, 0,
5480 0, 0,
5481 0, 0,
5482 GP_5_25_FN, GPSR5_25,
5483 GP_5_24_FN, GPSR5_24,
5484 GP_5_23_FN, GPSR5_23,
5485 GP_5_22_FN, GPSR5_22,
5486 GP_5_21_FN, GPSR5_21,
5487 GP_5_20_FN, GPSR5_20,
5488 GP_5_19_FN, GPSR5_19,
5489 GP_5_18_FN, GPSR5_18,
5490 GP_5_17_FN, GPSR5_17,
5491 GP_5_16_FN, GPSR5_16,
5492 GP_5_15_FN, GPSR5_15,
5493 GP_5_14_FN, GPSR5_14,
5494 GP_5_13_FN, GPSR5_13,
5495 GP_5_12_FN, GPSR5_12,
5496 GP_5_11_FN, GPSR5_11,
5497 GP_5_10_FN, GPSR5_10,
5498 GP_5_9_FN, GPSR5_9,
5499 GP_5_8_FN, GPSR5_8,
5500 GP_5_7_FN, GPSR5_7,
5501 GP_5_6_FN, GPSR5_6,
5502 GP_5_5_FN, GPSR5_5,
5503 GP_5_4_FN, GPSR5_4,
5504 GP_5_3_FN, GPSR5_3,
5505 GP_5_2_FN, GPSR5_2,
5506 GP_5_1_FN, GPSR5_1,
5507 GP_5_0_FN, GPSR5_0, ))
5508 },
5509 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5510 GP_6_31_FN, GPSR6_31,
5511 GP_6_30_FN, GPSR6_30,
5512 GP_6_29_FN, GPSR6_29,
5513 GP_6_28_FN, GPSR6_28,
5514 GP_6_27_FN, GPSR6_27,
5515 GP_6_26_FN, GPSR6_26,
5516 GP_6_25_FN, GPSR6_25,
5517 GP_6_24_FN, GPSR6_24,
5518 GP_6_23_FN, GPSR6_23,
5519 GP_6_22_FN, GPSR6_22,
5520 GP_6_21_FN, GPSR6_21,
5521 GP_6_20_FN, GPSR6_20,
5522 GP_6_19_FN, GPSR6_19,
5523 GP_6_18_FN, GPSR6_18,
5524 GP_6_17_FN, GPSR6_17,
5525 GP_6_16_FN, GPSR6_16,
5526 GP_6_15_FN, GPSR6_15,
5527 GP_6_14_FN, GPSR6_14,
5528 GP_6_13_FN, GPSR6_13,
5529 GP_6_12_FN, GPSR6_12,
5530 GP_6_11_FN, GPSR6_11,
5531 GP_6_10_FN, GPSR6_10,
5532 GP_6_9_FN, GPSR6_9,
5533 GP_6_8_FN, GPSR6_8,
5534 GP_6_7_FN, GPSR6_7,
5535 GP_6_6_FN, GPSR6_6,
5536 GP_6_5_FN, GPSR6_5,
5537 GP_6_4_FN, GPSR6_4,
5538 GP_6_3_FN, GPSR6_3,
5539 GP_6_2_FN, GPSR6_2,
5540 GP_6_1_FN, GPSR6_1,
5541 GP_6_0_FN, GPSR6_0, ))
5542 },
5543 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5544 0, 0,
5545 0, 0,
5546 0, 0,
5547 0, 0,
5548 0, 0,
5549 0, 0,
5550 0, 0,
5551 0, 0,
5552 0, 0,
5553 0, 0,
5554 0, 0,
5555 0, 0,
5556 0, 0,
5557 0, 0,
5558 0, 0,
5559 0, 0,
5560 0, 0,
5561 0, 0,
5562 0, 0,
5563 0, 0,
5564 0, 0,
5565 0, 0,
5566 0, 0,
5567 0, 0,
5568 0, 0,
5569 0, 0,
5570 0, 0,
5571 0, 0,
5572 GP_7_3_FN, GPSR7_3,
5573 GP_7_2_FN, GPSR7_2,
5574 GP_7_1_FN, GPSR7_1,
5575 GP_7_0_FN, GPSR7_0, ))
5576 },
5577 #undef F_
5578 #undef FM
5579
5580 #define F_(x, y) x,
5581 #define FM(x) FN_##x,
5582 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5583 IP0_31_28
5584 IP0_27_24
5585 IP0_23_20
5586 IP0_19_16
5587 IP0_15_12
5588 IP0_11_8
5589 IP0_7_4
5590 IP0_3_0 ))
5591 },
5592 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5593 IP1_31_28
5594 IP1_27_24
5595 IP1_23_20
5596 IP1_19_16
5597 IP1_15_12
5598 IP1_11_8
5599 IP1_7_4
5600 IP1_3_0 ))
5601 },
5602 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5603 IP2_31_28
5604 IP2_27_24
5605 IP2_23_20
5606 IP2_19_16
5607 IP2_15_12
5608 IP2_11_8
5609 IP2_7_4
5610 IP2_3_0 ))
5611 },
5612 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5613 IP3_31_28
5614 IP3_27_24
5615 IP3_23_20
5616 IP3_19_16
5617 IP3_15_12
5618 IP3_11_8
5619 IP3_7_4
5620 IP3_3_0 ))
5621 },
5622 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5623 IP4_31_28
5624 IP4_27_24
5625 IP4_23_20
5626 IP4_19_16
5627 IP4_15_12
5628 IP4_11_8
5629 IP4_7_4
5630 IP4_3_0 ))
5631 },
5632 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5633 IP5_31_28
5634 IP5_27_24
5635 IP5_23_20
5636 IP5_19_16
5637 IP5_15_12
5638 IP5_11_8
5639 IP5_7_4
5640 IP5_3_0 ))
5641 },
5642 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5643 IP6_31_28
5644 IP6_27_24
5645 IP6_23_20
5646 IP6_19_16
5647 IP6_15_12
5648 IP6_11_8
5649 IP6_7_4
5650 IP6_3_0 ))
5651 },
5652 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5653 IP7_31_28
5654 IP7_27_24
5655 IP7_23_20
5656 IP7_19_16
5657 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5658 IP7_11_8
5659 IP7_7_4
5660 IP7_3_0 ))
5661 },
5662 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5663 IP8_31_28
5664 IP8_27_24
5665 IP8_23_20
5666 IP8_19_16
5667 IP8_15_12
5668 IP8_11_8
5669 IP8_7_4
5670 IP8_3_0 ))
5671 },
5672 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5673 IP9_31_28
5674 IP9_27_24
5675 IP9_23_20
5676 IP9_19_16
5677 IP9_15_12
5678 IP9_11_8
5679 IP9_7_4
5680 IP9_3_0 ))
5681 },
5682 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5683 IP10_31_28
5684 IP10_27_24
5685 IP10_23_20
5686 IP10_19_16
5687 IP10_15_12
5688 IP10_11_8
5689 IP10_7_4
5690 IP10_3_0 ))
5691 },
5692 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5693 IP11_31_28
5694 IP11_27_24
5695 IP11_23_20
5696 IP11_19_16
5697 IP11_15_12
5698 IP11_11_8
5699 IP11_7_4
5700 IP11_3_0 ))
5701 },
5702 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5703 IP12_31_28
5704 IP12_27_24
5705 IP12_23_20
5706 IP12_19_16
5707 IP12_15_12
5708 IP12_11_8
5709 IP12_7_4
5710 IP12_3_0 ))
5711 },
5712 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5713 IP13_31_28
5714 IP13_27_24
5715 IP13_23_20
5716 IP13_19_16
5717 IP13_15_12
5718 IP13_11_8
5719 IP13_7_4
5720 IP13_3_0 ))
5721 },
5722 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5723 IP14_31_28
5724 IP14_27_24
5725 IP14_23_20
5726 IP14_19_16
5727 IP14_15_12
5728 IP14_11_8
5729 IP14_7_4
5730 IP14_3_0 ))
5731 },
5732 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5733 IP15_31_28
5734 IP15_27_24
5735 IP15_23_20
5736 IP15_19_16
5737 IP15_15_12
5738 IP15_11_8
5739 IP15_7_4
5740 IP15_3_0 ))
5741 },
5742 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5743 IP16_31_28
5744 IP16_27_24
5745 IP16_23_20
5746 IP16_19_16
5747 IP16_15_12
5748 IP16_11_8
5749 IP16_7_4
5750 IP16_3_0 ))
5751 },
5752 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5753 IP17_31_28
5754 IP17_27_24
5755 IP17_23_20
5756 IP17_19_16
5757 IP17_15_12
5758 IP17_11_8
5759 IP17_7_4
5760 IP17_3_0 ))
5761 },
5762 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
5763 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5764 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5765 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5766 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5767 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5768 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5769 IP18_7_4
5770 IP18_3_0 ))
5771 },
5772 #undef F_
5773 #undef FM
5774
5775 #define F_(x, y) x,
5776 #define FM(x) FN_##x,
5777 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5778 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5779 1, 1, 1, 2, 2, 1, 2, 3),
5780 GROUP(
5781 MOD_SEL0_31_30_29
5782 MOD_SEL0_28_27
5783 MOD_SEL0_26_25_24
5784 MOD_SEL0_23
5785 MOD_SEL0_22
5786 MOD_SEL0_21
5787 MOD_SEL0_20
5788 MOD_SEL0_19
5789 MOD_SEL0_18_17
5790 MOD_SEL0_16
5791 0, 0, /* RESERVED 15 */
5792 MOD_SEL0_14_13
5793 MOD_SEL0_12
5794 MOD_SEL0_11
5795 MOD_SEL0_10
5796 MOD_SEL0_9_8
5797 MOD_SEL0_7_6
5798 MOD_SEL0_5
5799 MOD_SEL0_4_3
5800 /* RESERVED 2, 1, 0 */
5801 0, 0, 0, 0, 0, 0, 0, 0 ))
5802 },
5803 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5804 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5805 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5806 GROUP(
5807 MOD_SEL1_31_30
5808 MOD_SEL1_29_28_27
5809 MOD_SEL1_26
5810 MOD_SEL1_25_24
5811 MOD_SEL1_23_22_21
5812 MOD_SEL1_20
5813 MOD_SEL1_19
5814 MOD_SEL1_18_17
5815 MOD_SEL1_16
5816 MOD_SEL1_15_14
5817 MOD_SEL1_13
5818 MOD_SEL1_12
5819 MOD_SEL1_11
5820 MOD_SEL1_10
5821 MOD_SEL1_9
5822 0, 0, 0, 0, /* RESERVED 8, 7 */
5823 MOD_SEL1_6
5824 MOD_SEL1_5
5825 MOD_SEL1_4
5826 MOD_SEL1_3
5827 MOD_SEL1_2
5828 MOD_SEL1_1
5829 MOD_SEL1_0 ))
5830 },
5831 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5832 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5833 1, 4, 4, 4, 3, 1),
5834 GROUP(
5835 MOD_SEL2_31
5836 MOD_SEL2_30
5837 MOD_SEL2_29
5838 MOD_SEL2_28_27
5839 MOD_SEL2_26
5840 MOD_SEL2_25_24_23
5841 MOD_SEL2_22
5842 MOD_SEL2_21
5843 MOD_SEL2_20
5844 MOD_SEL2_19
5845 MOD_SEL2_18
5846 MOD_SEL2_17
5847 /* RESERVED 16 */
5848 0, 0,
5849 /* RESERVED 15, 14, 13, 12 */
5850 0, 0, 0, 0, 0, 0, 0, 0,
5851 0, 0, 0, 0, 0, 0, 0, 0,
5852 /* RESERVED 11, 10, 9, 8 */
5853 0, 0, 0, 0, 0, 0, 0, 0,
5854 0, 0, 0, 0, 0, 0, 0, 0,
5855 /* RESERVED 7, 6, 5, 4 */
5856 0, 0, 0, 0, 0, 0, 0, 0,
5857 0, 0, 0, 0, 0, 0, 0, 0,
5858 /* RESERVED 3, 2, 1 */
5859 0, 0, 0, 0, 0, 0, 0, 0,
5860 MOD_SEL2_0 ))
5861 },
5862 { },
5863 };
5864
5865 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5866 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5867 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5868 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5869 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5870 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5871 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5872 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5873 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5874 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
5875 } },
5876 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5877 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5878 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5879 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5880 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5881 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5882 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5883 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5884 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
5885 } },
5886 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5887 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5888 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5889 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5890 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5891 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5892 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5893 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5894 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
5895 } },
5896 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5897 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5898 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5899 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5900 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5901 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5902 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5903 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5904 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5905 } },
5906 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5907 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5908 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5909 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5910 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5911 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5912 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5913 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5914 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5915 } },
5916 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5917 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5918 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5919 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5920 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5921 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5922 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5923 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5924 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5925 } },
5926 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5927 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5928 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5929 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5930 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5931 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5932 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5933 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5934 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5935 } },
5936 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5937 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5938 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5939 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5940 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5941 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5942 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5943 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5944 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5945 } },
5946 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5947 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5948 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5949 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5950 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5951 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5952 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5953 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5954 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5955 } },
5956 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5957 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5958 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
5959 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5960 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5961 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5962 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5963 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5964 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5965 } },
5966 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5967 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5968 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5969 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5970 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5971 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5972 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5973 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5974 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5975 } },
5976 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5977 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5978 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5979 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5980 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5981 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5982 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5983 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5984 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
5985 } },
5986 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5987 { PIN_DU_DOTCLKIN3, 28, 2 }, /* DU_DOTCLKIN3 */
5988 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
5989 { PIN_TMS, 4, 2 }, /* TMS */
5990 } },
5991 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5992 { PIN_TDO, 28, 2 }, /* TDO */
5993 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5994 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5995 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5996 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5997 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5998 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5999 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
6000 } },
6001 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
6002 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
6003 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
6004 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
6005 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
6006 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
6007 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
6008 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
6009 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
6010 } },
6011 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
6012 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
6013 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
6014 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
6015 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
6016 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
6017 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
6018 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
6019 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
6020 } },
6021 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
6022 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
6023 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
6024 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
6025 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
6026 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
6027 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
6028 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
6029 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
6030 } },
6031 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
6032 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
6033 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
6034 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
6035 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
6036 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
6037 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
6038 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
6039 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
6040 } },
6041 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
6042 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
6043 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
6044 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
6045 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
6046 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
6047 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
6048 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
6049 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
6050 } },
6051 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
6052 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
6053 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
6054 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
6055 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
6056 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
6057 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
6058 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
6059 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
6060 } },
6061 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
6062 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
6063 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
6064 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
6065 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
6066 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
6067 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
6068 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
6069 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
6070 } },
6071 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
6072 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
6073 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
6074 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
6075 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
6076 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
6077 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
6078 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
6079 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
6080 } },
6081 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
6082 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
6083 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
6084 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
6085 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
6086 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
6087 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
6088 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
6089 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
6090 } },
6091 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
6092 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
6093 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
6094 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
6095 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
6096 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
6097 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
6098 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
6099 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
6100 } },
6101 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
6102 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
6103 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
6104 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
6105 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
6106 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
6107 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
6108 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
6109 } },
6110 { },
6111 };
6112
6113 enum ioctrl_regs {
6114 POCCTRL,
6115 TDSELCTRL,
6116 };
6117
6118 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
6119 [POCCTRL] = { 0xe6060380, },
6120 [TDSELCTRL] = { 0xe60603c0, },
6121 { /* sentinel */ },
6122 };
6123
6124 static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6125 {
6126 int bit = -EINVAL;
6127
6128 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
6129
6130 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
6131 bit = pin & 0x1f;
6132
6133 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
6134 bit = (pin & 0x1f) + 12;
6135
6136 return bit;
6137 }
6138
6139 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6140 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
6141 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
6142 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
6143 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
6144 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
6145 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
6146 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
6147 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
6148 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
6149 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
6150 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
6151 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
6152 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
6153 [12] = PIN_RPC_INT_N, /* RPC_INT# */
6154 [13] = PIN_RPC_WP_N, /* RPC_WP# */
6155 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
6156 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
6157 [16] = PIN_AVB_RXC, /* AVB_RXC */
6158 [17] = PIN_AVB_RD0, /* AVB_RD0 */
6159 [18] = PIN_AVB_RD1, /* AVB_RD1 */
6160 [19] = PIN_AVB_RD2, /* AVB_RD2 */
6161 [20] = PIN_AVB_RD3, /* AVB_RD3 */
6162 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
6163 [22] = PIN_AVB_TXC, /* AVB_TXC */
6164 [23] = PIN_AVB_TD0, /* AVB_TD0 */
6165 [24] = PIN_AVB_TD1, /* AVB_TD1 */
6166 [25] = PIN_AVB_TD2, /* AVB_TD2 */
6167 [26] = PIN_AVB_TD3, /* AVB_TD3 */
6168 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
6169 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
6170 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
6171 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
6172 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
6173 } },
6174 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6175 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
6176 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
6177 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
6178 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
6179 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
6180 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
6181 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
6182 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
6183 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
6184 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
6185 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
6186 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
6187 [12] = RCAR_GP_PIN(1, 0), /* A0 */
6188 [13] = RCAR_GP_PIN(1, 1), /* A1 */
6189 [14] = RCAR_GP_PIN(1, 2), /* A2 */
6190 [15] = RCAR_GP_PIN(1, 3), /* A3 */
6191 [16] = RCAR_GP_PIN(1, 4), /* A4 */
6192 [17] = RCAR_GP_PIN(1, 5), /* A5 */
6193 [18] = RCAR_GP_PIN(1, 6), /* A6 */
6194 [19] = RCAR_GP_PIN(1, 7), /* A7 */
6195 [20] = RCAR_GP_PIN(1, 8), /* A8 */
6196 [21] = RCAR_GP_PIN(1, 9), /* A9 */
6197 [22] = RCAR_GP_PIN(1, 10), /* A10 */
6198 [23] = RCAR_GP_PIN(1, 11), /* A11 */
6199 [24] = RCAR_GP_PIN(1, 12), /* A12 */
6200 [25] = RCAR_GP_PIN(1, 13), /* A13 */
6201 [26] = RCAR_GP_PIN(1, 14), /* A14 */
6202 [27] = RCAR_GP_PIN(1, 15), /* A15 */
6203 [28] = RCAR_GP_PIN(1, 16), /* A16 */
6204 [29] = RCAR_GP_PIN(1, 17), /* A17 */
6205 [30] = RCAR_GP_PIN(1, 18), /* A18 */
6206 [31] = RCAR_GP_PIN(1, 19), /* A19 */
6207 } },
6208 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6209 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6210 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
6211 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
6212 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
6213 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
6214 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
6215 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
6216 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
6217 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
6218 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
6219 [10] = RCAR_GP_PIN(0, 0), /* D0 */
6220 [11] = RCAR_GP_PIN(0, 1), /* D1 */
6221 [12] = RCAR_GP_PIN(0, 2), /* D2 */
6222 [13] = RCAR_GP_PIN(0, 3), /* D3 */
6223 [14] = RCAR_GP_PIN(0, 4), /* D4 */
6224 [15] = RCAR_GP_PIN(0, 5), /* D5 */
6225 [16] = RCAR_GP_PIN(0, 6), /* D6 */
6226 [17] = RCAR_GP_PIN(0, 7), /* D7 */
6227 [18] = RCAR_GP_PIN(0, 8), /* D8 */
6228 [19] = RCAR_GP_PIN(0, 9), /* D9 */
6229 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6230 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6231 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6232 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6233 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6234 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6235 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6236 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
6237 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
6238 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
6239 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
6240 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
6241 } },
6242 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6243 [ 0] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
6244 [ 1] = SH_PFC_PIN_NONE,
6245 [ 2] = PIN_FSCLKST, /* FSCLKST */
6246 [ 3] = PIN_EXTALR, /* EXTALR*/
6247 [ 4] = PIN_TRST_N, /* TRST# */
6248 [ 5] = PIN_TCK, /* TCK */
6249 [ 6] = PIN_TMS, /* TMS */
6250 [ 7] = PIN_TDI, /* TDI */
6251 [ 8] = SH_PFC_PIN_NONE,
6252 [ 9] = PIN_ASEBRK, /* ASEBRK */
6253 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6254 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6255 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6256 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6257 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6258 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6259 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6260 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6261 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6262 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6263 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6264 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6265 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6266 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6267 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6268 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6269 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6270 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6271 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6272 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6273 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6274 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6275 } },
6276 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6277 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6278 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6279 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6280 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6281 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6282 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6283 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6284 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6285 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6286 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6287 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6288 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6289 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6290 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6291 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6292 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6293 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6294 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6295 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6296 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6297 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6298 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6299 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6300 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6301 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6302 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6303 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6304 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6305 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6306 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6307 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6308 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6309 } },
6310 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6311 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6312 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6313 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6314 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6315 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6316 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6317 [ 6] = PIN_MLB_REF, /* MLB_REF */
6318 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6319 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6320 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6321 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6322 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6323 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6324 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6325 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6326 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6327 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6328 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6329 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6330 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6331 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6332 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6333 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6334 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6335 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6336 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6337 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6338 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6339 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6340 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6341 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6342 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6343 } },
6344 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6345 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6346 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6347 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6348 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6349 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6350 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6351 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
6352 [ 7] = SH_PFC_PIN_NONE,
6353 [ 8] = SH_PFC_PIN_NONE,
6354 [ 9] = SH_PFC_PIN_NONE,
6355 [10] = SH_PFC_PIN_NONE,
6356 [11] = SH_PFC_PIN_NONE,
6357 [12] = SH_PFC_PIN_NONE,
6358 [13] = SH_PFC_PIN_NONE,
6359 [14] = SH_PFC_PIN_NONE,
6360 [15] = SH_PFC_PIN_NONE,
6361 [16] = SH_PFC_PIN_NONE,
6362 [17] = SH_PFC_PIN_NONE,
6363 [18] = SH_PFC_PIN_NONE,
6364 [19] = SH_PFC_PIN_NONE,
6365 [20] = SH_PFC_PIN_NONE,
6366 [21] = SH_PFC_PIN_NONE,
6367 [22] = SH_PFC_PIN_NONE,
6368 [23] = SH_PFC_PIN_NONE,
6369 [24] = SH_PFC_PIN_NONE,
6370 [25] = SH_PFC_PIN_NONE,
6371 [26] = SH_PFC_PIN_NONE,
6372 [27] = SH_PFC_PIN_NONE,
6373 [28] = SH_PFC_PIN_NONE,
6374 [29] = SH_PFC_PIN_NONE,
6375 [30] = SH_PFC_PIN_NONE,
6376 [31] = SH_PFC_PIN_NONE,
6377 } },
6378 { /* sentinel */ },
6379 };
6380
6381 static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
6382 unsigned int pin)
6383 {
6384 const struct pinmux_bias_reg *reg;
6385 unsigned int bit;
6386
6387 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6388 if (!reg)
6389 return PIN_CONFIG_BIAS_DISABLE;
6390
6391 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6392 return PIN_CONFIG_BIAS_DISABLE;
6393 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6394 return PIN_CONFIG_BIAS_PULL_UP;
6395 else
6396 return PIN_CONFIG_BIAS_PULL_DOWN;
6397 }
6398
6399 static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6400 unsigned int bias)
6401 {
6402 const struct pinmux_bias_reg *reg;
6403 u32 enable, updown;
6404 unsigned int bit;
6405
6406 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6407 if (!reg)
6408 return;
6409
6410 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6411 if (bias != PIN_CONFIG_BIAS_DISABLE)
6412 enable |= BIT(bit);
6413
6414 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6415 if (bias == PIN_CONFIG_BIAS_PULL_UP)
6416 updown |= BIT(bit);
6417
6418 sh_pfc_write(pfc, reg->pud, updown);
6419 sh_pfc_write(pfc, reg->puen, enable);
6420 }
6421
6422 static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
6423 .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
6424 .get_bias = r8a77965_pinmux_get_bias,
6425 .set_bias = r8a77965_pinmux_set_bias,
6426 };
6427
6428 const struct sh_pfc_soc_info r8a77965_pinmux_info = {
6429 .name = "r8a77965_pfc",
6430 .ops = &r8a77965_pinmux_ops,
6431 .unlock_reg = 0xe6060000, /* PMMR */
6432
6433 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6434
6435 .pins = pinmux_pins,
6436 .nr_pins = ARRAY_SIZE(pinmux_pins),
6437 .groups = pinmux_groups,
6438 .nr_groups = ARRAY_SIZE(pinmux_groups),
6439 .functions = pinmux_functions,
6440 .nr_functions = ARRAY_SIZE(pinmux_functions),
6441
6442 .cfg_regs = pinmux_config_regs,
6443 .drive_regs = pinmux_drive_regs,
6444 .bias_regs = pinmux_bias_regs,
6445 .ioctrl_regs = pinmux_ioctrl_regs,
6446
6447 .pinmux_data = pinmux_data,
6448 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6449 };
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