drivers/pinctrl/sh-pfc/pfc-sh73a0.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * sh73a0 processor support - PFC hardware block
   4  *
   5  * Copyright (C) 2010 Renesas Solutions Corp.
   6  * Copyright (C) 2010 NISHIMOTO Hiroki
   7  */
   8 #include <linux/io.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/pinctrl/pinconf-generic.h>
  12 #include <linux/regulator/driver.h>
  13 #include <linux/regulator/machine.h>
  14 #include <linux/slab.h>
  15
  16 #include "core.h"
  17 #include "sh_pfc.h"
  18
  19 #define CPU_ALL_PORT(fn, pfx, sfx)                                      \
  20         PORT_10(0,  fn, pfx, sfx), PORT_90(0, fn, pfx, sfx),            \
  21         PORT_10(100, fn, pfx##10, sfx),                                 \
  22         PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \
  23         PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \
  24         PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \
  25         PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \
  26         PORT_1(118, fn, pfx##118, sfx),                                 \
  27         PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
  28         PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \
  29         PORT_10(150, fn, pfx##15, sfx),                                 \
  30         PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \
  31         PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \
  32         PORT_1(164, fn, pfx##164, sfx),                                 \
  33         PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
  34         PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
  35         PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
  36         PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
  37         PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx), \
  38         PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx), \
  39         PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx), \
  40         PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx), \
  41         PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
  42         PORT_1(282, fn, pfx##282, sfx),                                 \
  43         PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
  44         PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)
  45
  46 enum {
  47         PINMUX_RESERVED = 0,
  48
  49         PINMUX_DATA_BEGIN,
  50         PORT_ALL(DATA),                 /* PORT0_DATA -> PORT309_DATA */
  51         PINMUX_DATA_END,
  52
  53         PINMUX_INPUT_BEGIN,
  54         PORT_ALL(IN),                   /* PORT0_IN -> PORT309_IN */
  55         PINMUX_INPUT_END,
  56
  57         PINMUX_OUTPUT_BEGIN,
  58         PORT_ALL(OUT),                  /* PORT0_OUT -> PORT309_OUT */
  59         PINMUX_OUTPUT_END,
  60
  61         PINMUX_FUNCTION_BEGIN,
  62         PORT_ALL(FN_IN),                /* PORT0_FN_IN -> PORT309_FN_IN */
  63         PORT_ALL(FN_OUT),               /* PORT0_FN_OUT -> PORT309_FN_OUT */
  64         PORT_ALL(FN0),                  /* PORT0_FN0 -> PORT309_FN0 */
  65         PORT_ALL(FN1),                  /* PORT0_FN1 -> PORT309_FN1 */
  66         PORT_ALL(FN2),                  /* PORT0_FN2 -> PORT309_FN2 */
  67         PORT_ALL(FN3),                  /* PORT0_FN3 -> PORT309_FN3 */
  68         PORT_ALL(FN4),                  /* PORT0_FN4 -> PORT309_FN4 */
  69         PORT_ALL(FN5),                  /* PORT0_FN5 -> PORT309_FN5 */
  70         PORT_ALL(FN6),                  /* PORT0_FN6 -> PORT309_FN6 */
  71         PORT_ALL(FN7),                  /* PORT0_FN7 -> PORT309_FN7 */
  72
  73         MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
  74         MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
  75         MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
  76         MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
  77         MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
  78         MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
  79         MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
  80         MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
  81         MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
  82         MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
  83         MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
  84         MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
  85         MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
  86         MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
  87         MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
  88         MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
  89         MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
  90         MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
  91         MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
  92         MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
  93         MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
  94         MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
  95         MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
  96         MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
  97         MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
  98         MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
  99         MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
 100         MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
 101         MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
 102         MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
 103         MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
 104         MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
 105         MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
 106         MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
 107         MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
 108         MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
 109         MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
 110         MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
 111         MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
 112         MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
 113         MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
 114         MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
 115         PINMUX_FUNCTION_END,
 116
 117         PINMUX_MARK_BEGIN,
 118         /* Hardware manual Table 25-1 (Function 0-7) */
 119         VBUS_0_MARK,
 120         GPI0_MARK,
 121         GPI1_MARK,
 122         GPI2_MARK,
 123         GPI3_MARK,
 124         GPI4_MARK,
 125         GPI5_MARK,
 126         GPI6_MARK,
 127         GPI7_MARK,
 128         SCIFA7_RXD_MARK,
 129         SCIFA7_CTS__MARK,
 130         GPO7_MARK, MFG0_OUT2_MARK,
 131         GPO6_MARK, MFG1_OUT2_MARK,
 132         GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
 133         SCIFA0_TXD_MARK,
 134         SCIFA7_TXD_MARK,
 135         SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
 136         GPO0_MARK,
 137         GPO1_MARK,
 138         GPO2_MARK, STATUS0_MARK,
 139         GPO3_MARK, STATUS1_MARK,
 140         GPO4_MARK, STATUS2_MARK,
 141         VINT_MARK,
 142         TCKON_MARK,
 143         XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
 144         MFG0_OUT1_MARK, PORT27_IROUT_MARK,
 145         XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
 146         PORT28_TPU1TO1_MARK,
 147         SIM_RST_MARK, PORT29_TPU1TO1_MARK,
 148         SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
 149         SIM_D_MARK, PORT31_IROUT_MARK,
 150         SCIFA4_TXD_MARK,
 151         SCIFA4_RXD_MARK, XWUP_MARK,
 152         SCIFA4_RTS__MARK,
 153         SCIFA4_CTS__MARK,
 154         FSIBOBT_MARK, FSIBIBT_MARK,
 155         FSIBOLR_MARK, FSIBILR_MARK,
 156         FSIBOSLD_MARK,
 157         FSIBISLD_MARK,
 158         VACK_MARK,
 159         XTAL1L_MARK,
 160         SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
 161         SCIFA0_RXD_MARK,
 162         SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
 163         FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
 164         FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
 165         FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
 166         FSICISLD_MARK, FSIDISLD_MARK,
 167         FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
 168         FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
 169
 170         FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
 171         FSIAOSLD_MARK, BBIF2_TXD2_MARK,
 172         FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
 173         PORT53_FSICSPDIF_MARK,
 174         FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
 175         FSICCK_MARK, FSICOMC_MARK,
 176         FSIAISLD_MARK, TPU0TO0_MARK,
 177         A0_MARK, BS__MARK,
 178         A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
 179         A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
 180         A14_MARK, KEYOUT5_MARK,
 181         A15_MARK, KEYOUT4_MARK,
 182         A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
 183         A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
 184         A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
 185         A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
 186         A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
 187         A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
 188         A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
 189         A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
 190         A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
 191         A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
 192         A26_MARK, KEYIN6_MARK,
 193         KEYIN7_MARK,
 194         D0_NAF0_MARK,
 195         D1_NAF1_MARK,
 196         D2_NAF2_MARK,
 197         D3_NAF3_MARK,
 198         D4_NAF4_MARK,
 199         D5_NAF5_MARK,
 200         D6_NAF6_MARK,
 201         D7_NAF7_MARK,
 202         D8_NAF8_MARK,
 203         D9_NAF9_MARK,
 204         D10_NAF10_MARK,
 205         D11_NAF11_MARK,
 206         D12_NAF12_MARK,
 207         D13_NAF13_MARK,
 208         D14_NAF14_MARK,
 209         D15_NAF15_MARK,
 210         CS4__MARK,
 211         CS5A__MARK, PORT91_RDWR_MARK,
 212         CS5B__MARK, FCE1__MARK,
 213         CS6B__MARK, DACK0_MARK,
 214         FCE0__MARK, CS6A__MARK,
 215         WAIT__MARK, DREQ0_MARK,
 216         RD__FSC_MARK,
 217         WE0__FWE_MARK, RDWR_FWE_MARK,
 218         WE1__MARK,
 219         FRB_MARK,
 220         CKO_MARK,
 221         NBRSTOUT__MARK,
 222         NBRST__MARK,
 223         BBIF2_TXD_MARK,
 224         BBIF2_RXD_MARK,
 225         BBIF2_SYNC_MARK,
 226         BBIF2_SCK_MARK,
 227         SCIFA3_CTS__MARK, MFG3_IN2_MARK,
 228         SCIFA3_RXD_MARK, MFG3_IN1_MARK,
 229         BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
 230         SCIFA3_TXD_MARK,
 231         HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
 232         HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
 233         HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
 234         HSI_TX_READY_MARK, BBIF1_TXD_MARK,
 235         HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
 236         PORT115_I2C_SCL3_MARK,
 237         HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
 238         PORT116_I2C_SDA3_MARK,
 239         HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
 240         HSI_TX_FLAG_MARK,
 241         VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
 242
 243         VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
 244         VIO2_HD_MARK, LCD2D1_MARK,
 245         VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
 246         VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
 247         PORT131_KEYOUT11_MARK, LCD2D11_MARK,
 248         VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
 249         PORT132_KEYOUT10_MARK, LCD2D12_MARK,
 250         VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
 251         VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
 252         VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
 253         VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
 254         VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
 255         VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
 256         VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
 257         VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
 258         VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
 259         VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
 260         VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
 261         VIO2_D5_MARK, LCD2D3_MARK,
 262         VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
 263         VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
 264         PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
 265         VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
 266         LCD2D18_MARK,
 267         VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
 268         VIO_CKO_MARK,
 269         A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
 270         MFG0_IN2_MARK,
 271         TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
 272         TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
 273         TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
 274         SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
 275         SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
 276         SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
 277         SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
 278         DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
 279         PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
 280         PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
 281         PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
 282         PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
 283         PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
 284         LCDD0_MARK,
 285         LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
 286         LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
 287         LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
 288         LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
 289         LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
 290         LCDD6_MARK,
 291         LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
 292         LCDD8_MARK, D16_MARK,
 293         LCDD9_MARK, D17_MARK,
 294         LCDD10_MARK, D18_MARK,
 295         LCDD11_MARK, D19_MARK,
 296         LCDD12_MARK, D20_MARK,
 297         LCDD13_MARK, D21_MARK,
 298         LCDD14_MARK, D22_MARK,
 299         LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
 300         LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
 301         LCDD17_MARK, D25_MARK,
 302         LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
 303         LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
 304         LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
 305         LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
 306         LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
 307         LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
 308         LCDDCK_MARK, LCDWR__MARK,
 309         LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
 310         VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
 311         LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
 312         PORT218_VIO_CKOR_MARK,
 313         LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
 314         MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
 315         LCDVSYN_MARK, LCDVSYN2_MARK,
 316         LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
 317         MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
 318         LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
 319         VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
 320
 321         SCIFA1_TXD_MARK, OVCN2_MARK,
 322         EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
 323         SCIFA1_RTS__MARK, IDIN_MARK,
 324         SCIFA1_RXD_MARK,
 325         SCIFA1_CTS__MARK, MFG1_IN1_MARK,
 326         MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
 327         MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
 328         MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
 329         MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
 330         MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
 331         MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
 332         MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
 333         MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
 334         MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
 335         MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
 336         SCIFA6_TXD_MARK,
 337         PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
 338         PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
 339         PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
 340         PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
 341         MSIOF2R_RXD_MARK,
 342         PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
 343         MSIOF2R_TXD_MARK,
 344         PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
 345         TPU1TO0_MARK,
 346         PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
 347         TPU3TO1_MARK,
 348         PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
 349         TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
 350         PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
 351         MSIOF2R_TSYNC_MARK,
 352         SDHICLK0_MARK,
 353         SDHICD0_MARK,
 354         SDHID0_0_MARK,
 355         SDHID0_1_MARK,
 356         SDHID0_2_MARK,
 357         SDHID0_3_MARK,
 358         SDHICMD0_MARK,
 359         SDHIWP0_MARK,
 360         SDHICLK1_MARK,
 361         SDHID1_0_MARK, TS_SPSYNC2_MARK,
 362         SDHID1_1_MARK, TS_SDAT2_MARK,
 363         SDHID1_2_MARK, TS_SDEN2_MARK,
 364         SDHID1_3_MARK, TS_SCK2_MARK,
 365         SDHICMD1_MARK,
 366         SDHICLK2_MARK,
 367         SDHID2_0_MARK, TS_SPSYNC4_MARK,
 368         SDHID2_1_MARK, TS_SDAT4_MARK,
 369         SDHID2_2_MARK, TS_SDEN4_MARK,
 370         SDHID2_3_MARK, TS_SCK4_MARK,
 371         SDHICMD2_MARK,
 372         MMCCLK0_MARK,
 373         MMCD0_0_MARK,
 374         MMCD0_1_MARK,
 375         MMCD0_2_MARK,
 376         MMCD0_3_MARK,
 377         MMCD0_4_MARK, TS_SPSYNC5_MARK,
 378         MMCD0_5_MARK, TS_SDAT5_MARK,
 379         MMCD0_6_MARK, TS_SDEN5_MARK,
 380         MMCD0_7_MARK, TS_SCK5_MARK,
 381         MMCCMD0_MARK,
 382         RESETOUTS__MARK, EXTAL2OUT_MARK,
 383         MCP_WAIT__MCP_FRB_MARK,
 384         MCP_CKO_MARK, MMCCLK1_MARK,
 385         MCP_D15_MCP_NAF15_MARK,
 386         MCP_D14_MCP_NAF14_MARK,
 387         MCP_D13_MCP_NAF13_MARK,
 388         MCP_D12_MCP_NAF12_MARK,
 389         MCP_D11_MCP_NAF11_MARK,
 390         MCP_D10_MCP_NAF10_MARK,
 391         MCP_D9_MCP_NAF9_MARK,
 392         MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
 393         MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
 394
 395         MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
 396         MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
 397         MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
 398         MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
 399         MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
 400         MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
 401         MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
 402         MCP_NBRSTOUT__MARK,
 403         MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
 404
 405         /* MSEL2 special cases */
 406         TSIF2_TS_XX1_MARK,
 407         TSIF2_TS_XX2_MARK,
 408         TSIF2_TS_XX3_MARK,
 409         TSIF2_TS_XX4_MARK,
 410         TSIF2_TS_XX5_MARK,
 411         TSIF1_TS_XX1_MARK,
 412         TSIF1_TS_XX2_MARK,
 413         TSIF1_TS_XX3_MARK,
 414         TSIF1_TS_XX4_MARK,
 415         TSIF1_TS_XX5_MARK,
 416         TSIF0_TS_XX1_MARK,
 417         TSIF0_TS_XX2_MARK,
 418         TSIF0_TS_XX3_MARK,
 419         TSIF0_TS_XX4_MARK,
 420         TSIF0_TS_XX5_MARK,
 421         MST1_TS_XX1_MARK,
 422         MST1_TS_XX2_MARK,
 423         MST1_TS_XX3_MARK,
 424         MST1_TS_XX4_MARK,
 425         MST1_TS_XX5_MARK,
 426         MST0_TS_XX1_MARK,
 427         MST0_TS_XX2_MARK,
 428         MST0_TS_XX3_MARK,
 429         MST0_TS_XX4_MARK,
 430         MST0_TS_XX5_MARK,
 431
 432         /* MSEL3 special cases */
 433         SDHI0_VCCQ_MC0_ON_MARK,
 434         SDHI0_VCCQ_MC0_OFF_MARK,
 435         DEBUG_MON_VIO_MARK,
 436         DEBUG_MON_LCDD_MARK,
 437         LCDC_LCDC0_MARK,
 438         LCDC_LCDC1_MARK,
 439
 440         /* MSEL4 special cases */
 441         IRQ9_MEM_INT_MARK,
 442         IRQ9_MCP_INT_MARK,
 443         A11_MARK,
 444         KEYOUT8_MARK,
 445         TPU4TO3_MARK,
 446         RESETA_N_PU_ON_MARK,
 447         RESETA_N_PU_OFF_MARK,
 448         EDBGREQ_PD_MARK,
 449         EDBGREQ_PU_MARK,
 450
 451         PINMUX_MARK_END,
 452 };
 453
 454 static const u16 pinmux_data[] = {
 455         /* specify valid pin states for each pin in GPIO mode */
 456         PINMUX_DATA_ALL(),
 457
 458         /* Table 25-1 (Function 0-7) */
 459         PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
 460         PINMUX_DATA(GPI0_MARK, PORT1_FN1),
 461         PINMUX_DATA(GPI1_MARK, PORT2_FN1),
 462         PINMUX_DATA(GPI2_MARK, PORT3_FN1),
 463         PINMUX_DATA(GPI3_MARK, PORT4_FN1),
 464         PINMUX_DATA(GPI4_MARK, PORT5_FN1),
 465         PINMUX_DATA(GPI5_MARK, PORT6_FN1),
 466         PINMUX_DATA(GPI6_MARK, PORT7_FN1),
 467         PINMUX_DATA(GPI7_MARK, PORT8_FN1),
 468         PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
 469         PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
 470         PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
 471         PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
 472         PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
 473         PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
 474         PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
 475         PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
 476         PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
 477         PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
 478         PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
 479         PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
 480         PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
 481         PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
 482         PINMUX_DATA(GPO0_MARK, PORT20_FN1),
 483         PINMUX_DATA(GPO1_MARK, PORT21_FN1),
 484         PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
 485         PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
 486         PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
 487         PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
 488         PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
 489         PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
 490         PINMUX_DATA(VINT_MARK, PORT25_FN1),
 491         PINMUX_DATA(TCKON_MARK, PORT26_FN1),
 492         PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
 493         PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
 494                 MSEL2CR_MSEL16_1), \
 495         PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
 496                 MSEL2CR_MSEL18_1), \
 497         PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
 498         PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
 499         PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
 500         PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
 501                 MSEL2CR_MSEL16_1), \
 502         PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
 503                 MSEL2CR_MSEL18_1), \
 504         PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
 505         PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
 506         PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
 507         PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
 508         PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
 509         PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
 510         PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
 511         PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
 512         PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
 513         PINMUX_DATA(XWUP_MARK, PORT33_FN3),
 514         PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
 515         PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
 516         PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
 517         PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
 518         PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
 519         PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
 520         PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
 521         PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
 522         PINMUX_DATA(VACK_MARK, PORT40_FN1),
 523         PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
 524         PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
 525         PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
 526         PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
 527         PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
 528         PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
 529         PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
 530         PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
 531         PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
 532         PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
 533         PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
 534         PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
 535         PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
 536         PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
 537         PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
 538         PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
 539         PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
 540         PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
 541         PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
 542         PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
 543         PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
 544         PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
 545         PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
 546         PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
 547         PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
 548         PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
 549
 550         PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
 551         PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
 552         PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
 553         PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
 554         PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
 555         PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
 556         PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
 557         PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
 558         PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
 559         PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
 560         PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
 561         PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
 562         PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
 563         PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
 564         PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
 565         PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
 566         PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
 567         PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
 568         PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
 569         PINMUX_DATA(A0_MARK, PORT57_FN1), \
 570         PINMUX_DATA(BS__MARK, PORT57_FN2),
 571         PINMUX_DATA(A12_MARK, PORT58_FN1), \
 572         PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
 573         PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
 574         PINMUX_DATA(A13_MARK, PORT59_FN1), \
 575         PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
 576         PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
 577         PINMUX_DATA(A14_MARK, PORT60_FN1), \
 578         PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
 579         PINMUX_DATA(A15_MARK, PORT61_FN1), \
 580         PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
 581         PINMUX_DATA(A16_MARK, PORT62_FN1), \
 582         PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
 583         PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
 584         PINMUX_DATA(A17_MARK, PORT63_FN1), \
 585         PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
 586         PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
 587         PINMUX_DATA(A18_MARK, PORT64_FN1), \
 588         PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
 589         PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
 590         PINMUX_DATA(A19_MARK, PORT65_FN1), \
 591         PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
 592         PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
 593         PINMUX_DATA(A20_MARK, PORT66_FN1), \
 594         PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
 595         PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
 596         PINMUX_DATA(A21_MARK, PORT67_FN1), \
 597         PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
 598         PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
 599         PINMUX_DATA(A22_MARK, PORT68_FN1), \
 600         PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
 601         PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
 602         PINMUX_DATA(A23_MARK, PORT69_FN1), \
 603         PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
 604         PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
 605         PINMUX_DATA(A24_MARK, PORT70_FN1), \
 606         PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
 607         PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
 608         PINMUX_DATA(A25_MARK, PORT71_FN1), \
 609         PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
 610         PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
 611         PINMUX_DATA(A26_MARK, PORT72_FN1), \
 612         PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
 613         PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
 614         PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
 615         PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
 616         PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
 617         PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
 618         PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
 619         PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
 620         PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
 621         PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
 622         PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
 623         PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
 624         PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
 625         PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
 626         PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
 627         PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
 628         PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
 629         PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
 630         PINMUX_DATA(CS4__MARK, PORT90_FN1),
 631         PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
 632         PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
 633         PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
 634         PINMUX_DATA(FCE1__MARK, PORT92_FN2),
 635         PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
 636         PINMUX_DATA(DACK0_MARK, PORT93_FN4),
 637         PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
 638         PINMUX_DATA(CS6A__MARK, PORT94_FN2),
 639         PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
 640         PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
 641         PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
 642         PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
 643         PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
 644         PINMUX_DATA(WE1__MARK, PORT98_FN1),
 645         PINMUX_DATA(FRB_MARK, PORT99_FN1),
 646         PINMUX_DATA(CKO_MARK, PORT100_FN1),
 647         PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
 648         PINMUX_DATA(NBRST__MARK, PORT102_FN1),
 649         PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
 650         PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
 651         PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
 652         PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
 653         PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
 654         PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
 655         PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
 656         PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
 657         PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
 658         PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
 659         PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
 660         PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
 661         PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
 662         PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
 663         PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
 664         PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
 665         PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
 666         PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
 667         PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
 668         PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
 669         PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
 670         PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
 671         PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
 672         PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
 673         PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
 674         PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
 675         PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
 676         PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
 677         PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
 678         PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
 679         PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
 680         PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
 681         PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
 682         PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
 683         PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
 684         PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
 685
 686         PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
 687         PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
 688         PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
 689         PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
 690         PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
 691         PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
 692         PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
 693                 MSEL4CR_MSEL10_1), \
 694         PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
 695         PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
 696         PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
 697         PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
 698         PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
 699         PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
 700         PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
 701         PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
 702         PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
 703         PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
 704         PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
 705         PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
 706         PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
 707         PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
 708         PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
 709         PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
 710         PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
 711         PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
 712         PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
 713         PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
 714         PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
 715         PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
 716         PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
 717         PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
 718         PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
 719         PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
 720         PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
 721         PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
 722         PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
 723         PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
 724         PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
 725         PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
 726         PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
 727         PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
 728         PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
 729         PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
 730         PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
 731         PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
 732         PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
 733         PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
 734         PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
 735         PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
 736         PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
 737         PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
 738         PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
 739         PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
 740         PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
 741         PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
 742         PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
 743         PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
 744         PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
 745         PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
 746         PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
 747         PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
 748         PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
 749         PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
 750         PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
 751         PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
 752         PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
 753         PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
 754         PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
 755         PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
 756         PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
 757         PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
 758         PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
 759         PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
 760         PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
 761         PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
 762         PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
 763         PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
 764         PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
 765         PINMUX_DATA(A27_MARK, PORT149_FN1), \
 766         PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
 767         PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
 768         PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
 769         PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
 770         PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
 771         PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
 772         PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
 773         PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
 774         PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
 775         PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
 776         PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
 777         PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
 778         PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
 779         PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
 780         PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
 781         PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
 782         PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
 783         PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
 784         PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
 785                 MSEL4CR_MSEL10_0),
 786         PINMUX_DATA(DINT__MARK, PORT158_FN1), \
 787         PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
 788         PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
 789         PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
 790         PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
 791         PINMUX_DATA(NMI_MARK, PORT159_FN3),
 792         PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
 793         PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
 794         PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
 795         PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
 796         PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
 797         PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
 798         PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
 799         PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
 800         PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
 801         PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
 802         PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
 803         PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
 804                 MSEL4CR_MSEL20_1), \
 805         PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
 806         PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
 807         PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
 808                 MSEL4CR_MSEL20_1), \
 809         PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
 810         PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
 811         PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
 812                 MSEL4CR_MSEL20_1), \
 813         PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
 814         PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
 815         PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
 816                 MSEL4CR_MSEL20_1),
 817         PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
 818         PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
 819                 MSEL4CR_MSEL20_1), \
 820         PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
 821         PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
 822         PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
 823         PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
 824         PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
 825         PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
 826         PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
 827         PINMUX_DATA(D16_MARK, PORT200_FN6),
 828         PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
 829         PINMUX_DATA(D17_MARK, PORT201_FN6),
 830         PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
 831         PINMUX_DATA(D18_MARK, PORT202_FN6),
 832         PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
 833         PINMUX_DATA(D19_MARK, PORT203_FN6),
 834         PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
 835         PINMUX_DATA(D20_MARK, PORT204_FN6),
 836         PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
 837         PINMUX_DATA(D21_MARK, PORT205_FN6),
 838         PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
 839         PINMUX_DATA(D22_MARK, PORT206_FN6),
 840         PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
 841         PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
 842         PINMUX_DATA(D23_MARK, PORT207_FN6),
 843         PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
 844         PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
 845         PINMUX_DATA(D24_MARK, PORT208_FN6),
 846         PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
 847         PINMUX_DATA(D25_MARK, PORT209_FN6),
 848         PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
 849         PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
 850         PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
 851         PINMUX_DATA(D26_MARK, PORT210_FN6),
 852         PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
 853         PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
 854         PINMUX_DATA(D27_MARK, PORT211_FN6),
 855         PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
 856         PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
 857         PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
 858         PINMUX_DATA(D28_MARK, PORT212_FN6),
 859         PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
 860         PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
 861         PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
 862         PINMUX_DATA(D29_MARK, PORT213_FN6),
 863         PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
 864         PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
 865         PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
 866         PINMUX_DATA(D30_MARK, PORT214_FN6),
 867         PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
 868         PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
 869         PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
 870         PINMUX_DATA(D31_MARK, PORT215_FN6),
 871         PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
 872         PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
 873         PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
 874         PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
 875         PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
 876         PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
 877         PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
 878                 MSEL4CR_MSEL26_1), \
 879         PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
 880         PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
 881         PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
 882         PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
 883         PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
 884         PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
 885         PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
 886         PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
 887         PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
 888         PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
 889         PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
 890         PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
 891                 MSEL4CR_MSEL26_1), \
 892         PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
 893         PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
 894         PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
 895         PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
 896         PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
 897         PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
 898         PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
 899         PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
 900         PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
 901                 MSEL4CR_MSEL26_1), \
 902         PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
 903         PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
 904         PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
 905         PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
 906         PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
 907         PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
 908         PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
 909                 MSEL4CR_MSEL26_1), \
 910         PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
 911
 912         PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
 913         PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
 914         PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
 915         PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
 916         PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
 917         PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
 918         PINMUX_DATA(IDIN_MARK, PORT227_FN4),
 919         PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
 920         PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
 921         PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
 922         PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
 923         PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
 924         PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
 925         PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
 926         PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
 927         PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
 928         PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
 929         PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
 930         PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
 931         PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
 932         PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
 933                 MSEL4CR_MSEL26_0), \
 934         PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
 935         PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
 936         PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
 937         PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
 938                 MSEL4CR_MSEL26_0), \
 939         PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
 940         PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
 941         PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
 942                 MSEL2CR_MSEL16_0),
 943         PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
 944         PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
 945                 MSEL2CR_MSEL16_0),
 946         PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
 947         PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
 948                 MSEL4CR_MSEL26_0), \
 949         PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
 950         PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
 951         PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
 952                 MSEL4CR_MSEL26_0), \
 953         PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
 954         PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
 955         PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
 956         PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
 957         PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
 958         PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
 959         PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
 960         PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
 961         PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
 962         PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
 963         PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
 964                 MSEL4CR_MSEL20_0), \
 965         PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
 966         PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
 967         PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
 968         PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
 969                 MSEL4CR_MSEL20_0), \
 970         PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
 971         PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
 972         PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
 973         PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
 974                 MSEL4CR_MSEL20_0), \
 975         PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
 976         PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
 977         PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
 978         PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
 979                 MSEL4CR_MSEL20_0), \
 980         PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
 981         PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
 982         PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
 983         PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
 984                 MSEL4CR_MSEL20_0), \
 985         PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
 986         PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
 987         PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
 988         PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
 989                 MSEL2CR_MSEL18_0), \
 990         PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
 991         PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
 992         PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
 993         PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
 994                 MSEL2CR_MSEL18_0), \
 995         PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
 996         PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
 997         PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
 998         PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
 999         PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
1000         PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
1001         PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
1002         PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
1003         PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
1004         PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
1005         PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
1006         PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
1007         PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
1008         PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
1009         PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
1010         PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
1011         PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
1012         PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
1013         PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
1014         PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
1015         PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
1016         PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
1017         PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
1018         PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
1019         PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
1020         PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
1021         PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
1022         PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
1023         PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
1024         PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
1025         PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
1026         PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
1027         PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
1028         PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
1029         PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
1030         PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
1031         PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
1032         PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
1033         PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
1034         PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
1035         PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
1036         PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
1037         PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
1038         PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
1039         PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
1040         PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
1041         PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
1042         PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
1043         PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
1044         PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
1045         PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
1046         PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
1047         PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
1048         PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
1049         PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
1050         PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
1051         PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
1052         PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
1053         PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
1054
1055         PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
1056         PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
1057         PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
1058         PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
1059         PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
1060         PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
1061         PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
1062         PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
1063         PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
1064         PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
1065         PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
1066         PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
1067         PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
1068         PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
1069         PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
1070         PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
1071         PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
1072
1073         /* MSEL2 special cases */
1074         PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1075                 MSEL2CR_MSEL12_0),
1076         PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1077                 MSEL2CR_MSEL12_1),
1078         PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1079                 MSEL2CR_MSEL12_0),
1080         PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1081                 MSEL2CR_MSEL12_1),
1082         PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
1083                 MSEL2CR_MSEL12_0),
1084         PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1085                 MSEL2CR_MSEL9_0),
1086         PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1087                 MSEL2CR_MSEL9_1),
1088         PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1089                 MSEL2CR_MSEL9_0),
1090         PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1091                 MSEL2CR_MSEL9_1),
1092         PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
1093                 MSEL2CR_MSEL9_0),
1094         PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1095                 MSEL2CR_MSEL6_0),
1096         PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1097                 MSEL2CR_MSEL6_1),
1098         PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1099                 MSEL2CR_MSEL6_0),
1100         PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1101                 MSEL2CR_MSEL6_1),
1102         PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
1103                 MSEL2CR_MSEL6_0),
1104         PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1105                 MSEL2CR_MSEL3_0),
1106         PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1107                 MSEL2CR_MSEL3_1),
1108         PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1109                 MSEL2CR_MSEL3_0),
1110         PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1111                 MSEL2CR_MSEL3_1),
1112         PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
1113                 MSEL2CR_MSEL3_0),
1114         PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1115                 MSEL2CR_MSEL0_0),
1116         PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1117                 MSEL2CR_MSEL0_1),
1118         PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1119                 MSEL2CR_MSEL0_0),
1120         PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1121                 MSEL2CR_MSEL0_1),
1122         PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
1123                 MSEL2CR_MSEL0_0),
1124
1125         /* MSEL3 special cases */
1126         PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
1127         PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
1128         PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
1129         PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
1130         PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
1131         PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
1132
1133         /* MSEL4 special cases */
1134         PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
1135         PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
1136         PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
1137         PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
1138         PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
1139         PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
1140         PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
1141         PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
1142         PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
1143 };
1144
1145 #define __I             (SH_PFC_PIN_CFG_INPUT)
1146 #define __O             (SH_PFC_PIN_CFG_OUTPUT)
1147 #define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1148 #define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
1149 #define __PU            (SH_PFC_PIN_CFG_PULL_UP)
1150 #define __PUD           (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1151
1152 #define SH73A0_PIN_I_PD(pin)            SH_PFC_PIN_CFG(pin, __I | __PD)
1153 #define SH73A0_PIN_I_PU(pin)            SH_PFC_PIN_CFG(pin, __I | __PU)
1154 #define SH73A0_PIN_I_PU_PD(pin)         SH_PFC_PIN_CFG(pin, __I | __PUD)
1155 #define SH73A0_PIN_IO(pin)              SH_PFC_PIN_CFG(pin, __IO)
1156 #define SH73A0_PIN_IO_PD(pin)           SH_PFC_PIN_CFG(pin, __IO | __PD)
1157 #define SH73A0_PIN_IO_PU(pin)           SH_PFC_PIN_CFG(pin, __IO | __PU)
1158 #define SH73A0_PIN_IO_PU_PD(pin)        SH_PFC_PIN_CFG(pin, __IO | __PUD)
1159 #define SH73A0_PIN_O(pin)               SH_PFC_PIN_CFG(pin, __O)
1160
1161 /* Pin numbers for pins without a corresponding GPIO port number are computed
1162  * from the row and column numbers with a 1000 offset to avoid collisions with
1163  * GPIO port numbers.
1164  */
1165 #define PIN_NUMBER(row, col)            (1000+((row)-1)*34+(col)-1)
1166
1167 static const struct sh_pfc_pin pinmux_pins[] = {
1168         /* Table 25-1 (I/O and Pull U/D) */
1169         SH73A0_PIN_I_PD(0),
1170         SH73A0_PIN_I_PU(1),
1171         SH73A0_PIN_I_PU(2),
1172         SH73A0_PIN_I_PU(3),
1173         SH73A0_PIN_I_PU(4),
1174         SH73A0_PIN_I_PU(5),
1175         SH73A0_PIN_I_PU(6),
1176         SH73A0_PIN_I_PU(7),
1177         SH73A0_PIN_I_PU(8),
1178         SH73A0_PIN_I_PD(9),
1179         SH73A0_PIN_I_PD(10),
1180         SH73A0_PIN_I_PU_PD(11),
1181         SH73A0_PIN_IO_PU_PD(12),
1182         SH73A0_PIN_IO_PU_PD(13),
1183         SH73A0_PIN_IO_PU_PD(14),
1184         SH73A0_PIN_IO_PU_PD(15),
1185         SH73A0_PIN_IO_PD(16),
1186         SH73A0_PIN_IO_PD(17),
1187         SH73A0_PIN_IO_PU(18),
1188         SH73A0_PIN_IO_PU(19),
1189         SH73A0_PIN_O(20),
1190         SH73A0_PIN_O(21),
1191         SH73A0_PIN_O(22),
1192         SH73A0_PIN_O(23),
1193         SH73A0_PIN_O(24),
1194         SH73A0_PIN_I_PD(25),
1195         SH73A0_PIN_I_PD(26),
1196         SH73A0_PIN_IO_PU(27),
1197         SH73A0_PIN_IO_PU(28),
1198         SH73A0_PIN_IO_PD(29),
1199         SH73A0_PIN_IO_PD(30),
1200         SH73A0_PIN_IO_PU(31),
1201         SH73A0_PIN_IO_PD(32),
1202         SH73A0_PIN_I_PU_PD(33),
1203         SH73A0_PIN_IO_PD(34),
1204         SH73A0_PIN_I_PU_PD(35),
1205         SH73A0_PIN_IO_PD(36),
1206         SH73A0_PIN_IO(37),
1207         SH73A0_PIN_O(38),
1208         SH73A0_PIN_I_PU(39),
1209         SH73A0_PIN_I_PU_PD(40),
1210         SH73A0_PIN_O(41),
1211         SH73A0_PIN_IO_PD(42),
1212         SH73A0_PIN_IO_PU_PD(43),
1213         SH73A0_PIN_IO_PU_PD(44),
1214         SH73A0_PIN_IO_PD(45),
1215         SH73A0_PIN_IO_PD(46),
1216         SH73A0_PIN_IO_PD(47),
1217         SH73A0_PIN_I_PD(48),
1218         SH73A0_PIN_IO_PU_PD(49),
1219         SH73A0_PIN_IO_PD(50),
1220         SH73A0_PIN_IO_PD(51),
1221         SH73A0_PIN_O(52),
1222         SH73A0_PIN_IO_PU_PD(53),
1223         SH73A0_PIN_IO_PU_PD(54),
1224         SH73A0_PIN_IO_PD(55),
1225         SH73A0_PIN_I_PU_PD(56),
1226         SH73A0_PIN_IO(57),
1227         SH73A0_PIN_IO(58),
1228         SH73A0_PIN_IO(59),
1229         SH73A0_PIN_IO(60),
1230         SH73A0_PIN_IO(61),
1231         SH73A0_PIN_IO_PD(62),
1232         SH73A0_PIN_IO_PD(63),
1233         SH73A0_PIN_IO_PU_PD(64),
1234         SH73A0_PIN_IO_PD(65),
1235         SH73A0_PIN_IO_PU_PD(66),
1236         SH73A0_PIN_IO_PU_PD(67),
1237         SH73A0_PIN_IO_PU_PD(68),
1238         SH73A0_PIN_IO_PU_PD(69),
1239         SH73A0_PIN_IO_PU_PD(70),
1240         SH73A0_PIN_IO_PU_PD(71),
1241         SH73A0_PIN_IO_PU_PD(72),
1242         SH73A0_PIN_I_PU_PD(73),
1243         SH73A0_PIN_IO_PU(74),
1244         SH73A0_PIN_IO_PU(75),
1245         SH73A0_PIN_IO_PU(76),
1246         SH73A0_PIN_IO_PU(77),
1247         SH73A0_PIN_IO_PU(78),
1248         SH73A0_PIN_IO_PU(79),
1249         SH73A0_PIN_IO_PU(80),
1250         SH73A0_PIN_IO_PU(81),
1251         SH73A0_PIN_IO_PU(82),
1252         SH73A0_PIN_IO_PU(83),
1253         SH73A0_PIN_IO_PU(84),
1254         SH73A0_PIN_IO_PU(85),
1255         SH73A0_PIN_IO_PU(86),
1256         SH73A0_PIN_IO_PU(87),
1257         SH73A0_PIN_IO_PU(88),
1258         SH73A0_PIN_IO_PU(89),
1259         SH73A0_PIN_O(90),
1260         SH73A0_PIN_IO_PU(91),
1261         SH73A0_PIN_O(92),
1262         SH73A0_PIN_IO_PU(93),
1263         SH73A0_PIN_O(94),
1264         SH73A0_PIN_I_PU_PD(95),
1265         SH73A0_PIN_IO(96),
1266         SH73A0_PIN_IO(97),
1267         SH73A0_PIN_IO(98),
1268         SH73A0_PIN_I_PU(99),
1269         SH73A0_PIN_O(100),
1270         SH73A0_PIN_O(101),
1271         SH73A0_PIN_I_PU(102),
1272         SH73A0_PIN_IO_PD(103),
1273         SH73A0_PIN_I_PU_PD(104),
1274         SH73A0_PIN_I_PD(105),
1275         SH73A0_PIN_I_PD(106),
1276         SH73A0_PIN_I_PU_PD(107),
1277         SH73A0_PIN_I_PU_PD(108),
1278         SH73A0_PIN_IO_PD(109),
1279         SH73A0_PIN_IO_PD(110),
1280         SH73A0_PIN_IO_PU_PD(111),
1281         SH73A0_PIN_IO_PU_PD(112),
1282         SH73A0_PIN_IO_PU_PD(113),
1283         SH73A0_PIN_IO_PD(114),
1284         SH73A0_PIN_IO_PU(115),
1285         SH73A0_PIN_IO_PU(116),
1286         SH73A0_PIN_IO_PU_PD(117),
1287         SH73A0_PIN_IO_PU_PD(118),
1288         SH73A0_PIN_IO_PD(128),
1289         SH73A0_PIN_IO_PD(129),
1290         SH73A0_PIN_IO_PU_PD(130),
1291         SH73A0_PIN_IO_PD(131),
1292         SH73A0_PIN_IO_PD(132),
1293         SH73A0_PIN_IO_PD(133),
1294         SH73A0_PIN_IO_PU_PD(134),
1295         SH73A0_PIN_IO_PU_PD(135),
1296         SH73A0_PIN_IO_PU_PD(136),
1297         SH73A0_PIN_IO_PU_PD(137),
1298         SH73A0_PIN_IO_PD(138),
1299         SH73A0_PIN_IO_PD(139),
1300         SH73A0_PIN_IO_PD(140),
1301         SH73A0_PIN_IO_PD(141),
1302         SH73A0_PIN_IO_PD(142),
1303         SH73A0_PIN_IO_PD(143),
1304         SH73A0_PIN_IO_PU_PD(144),
1305         SH73A0_PIN_IO_PD(145),
1306         SH73A0_PIN_IO_PU_PD(146),
1307         SH73A0_PIN_IO_PU_PD(147),
1308         SH73A0_PIN_IO_PU_PD(148),
1309         SH73A0_PIN_IO_PU_PD(149),
1310         SH73A0_PIN_I_PU_PD(150),
1311         SH73A0_PIN_IO_PU_PD(151),
1312         SH73A0_PIN_IO_PU_PD(152),
1313         SH73A0_PIN_IO_PD(153),
1314         SH73A0_PIN_IO_PD(154),
1315         SH73A0_PIN_I_PU_PD(155),
1316         SH73A0_PIN_IO_PU_PD(156),
1317         SH73A0_PIN_I_PD(157),
1318         SH73A0_PIN_IO_PD(158),
1319         SH73A0_PIN_IO_PU_PD(159),
1320         SH73A0_PIN_IO_PU_PD(160),
1321         SH73A0_PIN_I_PU_PD(161),
1322         SH73A0_PIN_I_PU_PD(162),
1323         SH73A0_PIN_IO_PU_PD(163),
1324         SH73A0_PIN_I_PU_PD(164),
1325         SH73A0_PIN_IO_PD(192),
1326         SH73A0_PIN_IO_PU_PD(193),
1327         SH73A0_PIN_IO_PD(194),
1328         SH73A0_PIN_IO_PU_PD(195),
1329         SH73A0_PIN_IO_PD(196),
1330         SH73A0_PIN_IO_PD(197),
1331         SH73A0_PIN_IO_PD(198),
1332         SH73A0_PIN_IO_PD(199),
1333         SH73A0_PIN_IO_PU_PD(200),
1334         SH73A0_PIN_IO_PU_PD(201),
1335         SH73A0_PIN_IO_PU_PD(202),
1336         SH73A0_PIN_IO_PU_PD(203),
1337         SH73A0_PIN_IO_PU_PD(204),
1338         SH73A0_PIN_IO_PU_PD(205),
1339         SH73A0_PIN_IO_PU_PD(206),
1340         SH73A0_PIN_IO_PD(207),
1341         SH73A0_PIN_IO_PD(208),
1342         SH73A0_PIN_IO_PD(209),
1343         SH73A0_PIN_IO_PD(210),
1344         SH73A0_PIN_IO_PD(211),
1345         SH73A0_PIN_IO_PD(212),
1346         SH73A0_PIN_IO_PD(213),
1347         SH73A0_PIN_IO_PU_PD(214),
1348         SH73A0_PIN_IO_PU_PD(215),
1349         SH73A0_PIN_IO_PD(216),
1350         SH73A0_PIN_IO_PD(217),
1351         SH73A0_PIN_O(218),
1352         SH73A0_PIN_IO_PD(219),
1353         SH73A0_PIN_IO_PD(220),
1354         SH73A0_PIN_IO_PU_PD(221),
1355         SH73A0_PIN_IO_PU_PD(222),
1356         SH73A0_PIN_I_PU_PD(223),
1357         SH73A0_PIN_I_PU_PD(224),
1358         SH73A0_PIN_IO_PU_PD(225),
1359         SH73A0_PIN_O(226),
1360         SH73A0_PIN_IO_PU_PD(227),
1361         SH73A0_PIN_I_PU_PD(228),
1362         SH73A0_PIN_I_PD(229),
1363         SH73A0_PIN_IO(230),
1364         SH73A0_PIN_IO_PU_PD(231),
1365         SH73A0_PIN_IO_PU_PD(232),
1366         SH73A0_PIN_I_PU_PD(233),
1367         SH73A0_PIN_IO_PU_PD(234),
1368         SH73A0_PIN_IO_PU_PD(235),
1369         SH73A0_PIN_IO_PU_PD(236),
1370         SH73A0_PIN_IO_PD(237),
1371         SH73A0_PIN_IO_PU_PD(238),
1372         SH73A0_PIN_IO_PU_PD(239),
1373         SH73A0_PIN_IO_PU_PD(240),
1374         SH73A0_PIN_O(241),
1375         SH73A0_PIN_I_PD(242),
1376         SH73A0_PIN_IO_PU_PD(243),
1377         SH73A0_PIN_IO_PU_PD(244),
1378         SH73A0_PIN_IO_PU_PD(245),
1379         SH73A0_PIN_IO_PU_PD(246),
1380         SH73A0_PIN_IO_PU_PD(247),
1381         SH73A0_PIN_IO_PU_PD(248),
1382         SH73A0_PIN_IO_PU_PD(249),
1383         SH73A0_PIN_IO_PU_PD(250),
1384         SH73A0_PIN_IO_PU_PD(251),
1385         SH73A0_PIN_IO_PU_PD(252),
1386         SH73A0_PIN_IO_PU_PD(253),
1387         SH73A0_PIN_IO_PU_PD(254),
1388         SH73A0_PIN_IO_PU_PD(255),
1389         SH73A0_PIN_IO_PU_PD(256),
1390         SH73A0_PIN_IO_PU_PD(257),
1391         SH73A0_PIN_IO_PU_PD(258),
1392         SH73A0_PIN_IO_PU_PD(259),
1393         SH73A0_PIN_IO_PU_PD(260),
1394         SH73A0_PIN_IO_PU_PD(261),
1395         SH73A0_PIN_IO_PU_PD(262),
1396         SH73A0_PIN_IO_PU_PD(263),
1397         SH73A0_PIN_IO_PU_PD(264),
1398         SH73A0_PIN_IO_PU_PD(265),
1399         SH73A0_PIN_IO_PU_PD(266),
1400         SH73A0_PIN_IO_PU_PD(267),
1401         SH73A0_PIN_IO_PU_PD(268),
1402         SH73A0_PIN_IO_PU_PD(269),
1403         SH73A0_PIN_IO_PU_PD(270),
1404         SH73A0_PIN_IO_PU_PD(271),
1405         SH73A0_PIN_IO_PU_PD(272),
1406         SH73A0_PIN_IO_PU_PD(273),
1407         SH73A0_PIN_IO_PU_PD(274),
1408         SH73A0_PIN_IO_PU_PD(275),
1409         SH73A0_PIN_IO_PU_PD(276),
1410         SH73A0_PIN_IO_PU_PD(277),
1411         SH73A0_PIN_IO_PU_PD(278),
1412         SH73A0_PIN_IO_PU_PD(279),
1413         SH73A0_PIN_IO_PU_PD(280),
1414         SH73A0_PIN_O(281),
1415         SH73A0_PIN_O(282),
1416         SH73A0_PIN_I_PU(288),
1417         SH73A0_PIN_IO_PU_PD(289),
1418         SH73A0_PIN_IO_PU_PD(290),
1419         SH73A0_PIN_IO_PU_PD(291),
1420         SH73A0_PIN_IO_PU_PD(292),
1421         SH73A0_PIN_IO_PU_PD(293),
1422         SH73A0_PIN_IO_PU_PD(294),
1423         SH73A0_PIN_IO_PU_PD(295),
1424         SH73A0_PIN_IO_PU_PD(296),
1425         SH73A0_PIN_IO_PU_PD(297),
1426         SH73A0_PIN_IO_PU_PD(298),
1427         SH73A0_PIN_IO_PU_PD(299),
1428         SH73A0_PIN_IO_PU_PD(300),
1429         SH73A0_PIN_IO_PU_PD(301),
1430         SH73A0_PIN_IO_PU_PD(302),
1431         SH73A0_PIN_IO_PU_PD(303),
1432         SH73A0_PIN_IO_PU_PD(304),
1433         SH73A0_PIN_IO_PU_PD(305),
1434         SH73A0_PIN_O(306),
1435         SH73A0_PIN_O(307),
1436         SH73A0_PIN_I_PU(308),
1437         SH73A0_PIN_O(309),
1438
1439         /* Pins not associated with a GPIO port */
1440         SH_PFC_PIN_NAMED(6, 26, F26),
1441 };
1442
1443 /* - BSC -------------------------------------------------------------------- */
1444 static const unsigned int bsc_data_0_7_pins[] = {
1445         /* D[0:7] */
1446         74, 75, 76, 77, 78, 79, 80, 81,
1447 };
1448 static const unsigned int bsc_data_0_7_mux[] = {
1449         D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1450         D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1451 };
1452 static const unsigned int bsc_data_8_15_pins[] = {
1453         /* D[8:15] */
1454         82, 83, 84, 85, 86, 87, 88, 89,
1455 };
1456 static const unsigned int bsc_data_8_15_mux[] = {
1457         D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1458         D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1459 };
1460 static const unsigned int bsc_cs4_pins[] = {
1461         /* CS */
1462         90,
1463 };
1464 static const unsigned int bsc_cs4_mux[] = {
1465         CS4__MARK,
1466 };
1467 static const unsigned int bsc_cs5_a_pins[] = {
1468         /* CS */
1469         91,
1470 };
1471 static const unsigned int bsc_cs5_a_mux[] = {
1472         CS5A__MARK,
1473 };
1474 static const unsigned int bsc_cs5_b_pins[] = {
1475         /* CS */
1476         92,
1477 };
1478 static const unsigned int bsc_cs5_b_mux[] = {
1479         CS5B__MARK,
1480 };
1481 static const unsigned int bsc_cs6_a_pins[] = {
1482         /* CS */
1483         94,
1484 };
1485 static const unsigned int bsc_cs6_a_mux[] = {
1486         CS6A__MARK,
1487 };
1488 static const unsigned int bsc_cs6_b_pins[] = {
1489         /* CS */
1490         93,
1491 };
1492 static const unsigned int bsc_cs6_b_mux[] = {
1493         CS6B__MARK,
1494 };
1495 static const unsigned int bsc_rd_pins[] = {
1496         /* RD */
1497         96,
1498 };
1499 static const unsigned int bsc_rd_mux[] = {
1500         RD__FSC_MARK,
1501 };
1502 static const unsigned int bsc_rdwr_0_pins[] = {
1503         /* RDWR */
1504         91,
1505 };
1506 static const unsigned int bsc_rdwr_0_mux[] = {
1507         PORT91_RDWR_MARK,
1508 };
1509 static const unsigned int bsc_rdwr_1_pins[] = {
1510         /* RDWR */
1511         97,
1512 };
1513 static const unsigned int bsc_rdwr_1_mux[] = {
1514         RDWR_FWE_MARK,
1515 };
1516 static const unsigned int bsc_rdwr_2_pins[] = {
1517         /* RDWR */
1518         149,
1519 };
1520 static const unsigned int bsc_rdwr_2_mux[] = {
1521         PORT149_RDWR_MARK,
1522 };
1523 static const unsigned int bsc_we0_pins[] = {
1524         /* WE0 */
1525         97,
1526 };
1527 static const unsigned int bsc_we0_mux[] = {
1528         WE0__FWE_MARK,
1529 };
1530 static const unsigned int bsc_we1_pins[] = {
1531         /* WE1 */
1532         98,
1533 };
1534 static const unsigned int bsc_we1_mux[] = {
1535         WE1__MARK,
1536 };
1537 /* - FSIA ------------------------------------------------------------------- */
1538 static const unsigned int fsia_mclk_in_pins[] = {
1539         /* CK */
1540         49,
1541 };
1542 static const unsigned int fsia_mclk_in_mux[] = {
1543         FSIACK_MARK,
1544 };
1545 static const unsigned int fsia_mclk_out_pins[] = {
1546         /* OMC */
1547         49,
1548 };
1549 static const unsigned int fsia_mclk_out_mux[] = {
1550         FSIAOMC_MARK,
1551 };
1552 static const unsigned int fsia_sclk_in_pins[] = {
1553         /* ILR, IBT */
1554         50, 51,
1555 };
1556 static const unsigned int fsia_sclk_in_mux[] = {
1557         FSIAILR_MARK, FSIAIBT_MARK,
1558 };
1559 static const unsigned int fsia_sclk_out_pins[] = {
1560         /* OLR, OBT */
1561         50, 51,
1562 };
1563 static const unsigned int fsia_sclk_out_mux[] = {
1564         FSIAOLR_MARK, FSIAOBT_MARK,
1565 };
1566 static const unsigned int fsia_data_in_pins[] = {
1567         /* ISLD */
1568         55,
1569 };
1570 static const unsigned int fsia_data_in_mux[] = {
1571         FSIAISLD_MARK,
1572 };
1573 static const unsigned int fsia_data_out_pins[] = {
1574         /* OSLD */
1575         52,
1576 };
1577 static const unsigned int fsia_data_out_mux[] = {
1578         FSIAOSLD_MARK,
1579 };
1580 static const unsigned int fsia_spdif_pins[] = {
1581         /* SPDIF */
1582         53,
1583 };
1584 static const unsigned int fsia_spdif_mux[] = {
1585         FSIASPDIF_MARK,
1586 };
1587 /* - FSIB ------------------------------------------------------------------- */
1588 static const unsigned int fsib_mclk_in_pins[] = {
1589         /* CK */
1590         54,
1591 };
1592 static const unsigned int fsib_mclk_in_mux[] = {
1593         FSIBCK_MARK,
1594 };
1595 static const unsigned int fsib_mclk_out_pins[] = {
1596         /* OMC */
1597         54,
1598 };
1599 static const unsigned int fsib_mclk_out_mux[] = {
1600         FSIBOMC_MARK,
1601 };
1602 static const unsigned int fsib_sclk_in_pins[] = {
1603         /* ILR, IBT */
1604         37, 36,
1605 };
1606 static const unsigned int fsib_sclk_in_mux[] = {
1607         FSIBILR_MARK, FSIBIBT_MARK,
1608 };
1609 static const unsigned int fsib_sclk_out_pins[] = {
1610         /* OLR, OBT */
1611         37, 36,
1612 };
1613 static const unsigned int fsib_sclk_out_mux[] = {
1614         FSIBOLR_MARK, FSIBOBT_MARK,
1615 };
1616 static const unsigned int fsib_data_in_pins[] = {
1617         /* ISLD */
1618         39,
1619 };
1620 static const unsigned int fsib_data_in_mux[] = {
1621         FSIBISLD_MARK,
1622 };
1623 static const unsigned int fsib_data_out_pins[] = {
1624         /* OSLD */
1625         38,
1626 };
1627 static const unsigned int fsib_data_out_mux[] = {
1628         FSIBOSLD_MARK,
1629 };
1630 static const unsigned int fsib_spdif_pins[] = {
1631         /* SPDIF */
1632         53,
1633 };
1634 static const unsigned int fsib_spdif_mux[] = {
1635         FSIBSPDIF_MARK,
1636 };
1637 /* - FSIC ------------------------------------------------------------------- */
1638 static const unsigned int fsic_mclk_in_pins[] = {
1639         /* CK */
1640         54,
1641 };
1642 static const unsigned int fsic_mclk_in_mux[] = {
1643         FSICCK_MARK,
1644 };
1645 static const unsigned int fsic_mclk_out_pins[] = {
1646         /* OMC */
1647         54,
1648 };
1649 static const unsigned int fsic_mclk_out_mux[] = {
1650         FSICOMC_MARK,
1651 };
1652 static const unsigned int fsic_sclk_in_pins[] = {
1653         /* ILR, IBT */
1654         46, 45,
1655 };
1656 static const unsigned int fsic_sclk_in_mux[] = {
1657         FSICILR_MARK, FSICIBT_MARK,
1658 };
1659 static const unsigned int fsic_sclk_out_pins[] = {
1660         /* OLR, OBT */
1661         46, 45,
1662 };
1663 static const unsigned int fsic_sclk_out_mux[] = {
1664         FSICOLR_MARK, FSICOBT_MARK,
1665 };
1666 static const unsigned int fsic_data_in_pins[] = {
1667         /* ISLD */
1668         48,
1669 };
1670 static const unsigned int fsic_data_in_mux[] = {
1671         FSICISLD_MARK,
1672 };
1673 static const unsigned int fsic_data_out_pins[] = {
1674         /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
1675         47, 44, 42, 16,
1676 };
1677 static const unsigned int fsic_data_out_mux[] = {
1678         FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
1679 };
1680 static const unsigned int fsic_spdif_0_pins[] = {
1681         /* SPDIF */
1682         53,
1683 };
1684 static const unsigned int fsic_spdif_0_mux[] = {
1685         PORT53_FSICSPDIF_MARK,
1686 };
1687 static const unsigned int fsic_spdif_1_pins[] = {
1688         /* SPDIF */
1689         47,
1690 };
1691 static const unsigned int fsic_spdif_1_mux[] = {
1692         PORT47_FSICSPDIF_MARK,
1693 };
1694 /* - FSID ------------------------------------------------------------------- */
1695 static const unsigned int fsid_sclk_in_pins[] = {
1696         /* ILR, IBT */
1697         46, 45,
1698 };
1699 static const unsigned int fsid_sclk_in_mux[] = {
1700         FSIDILR_MARK, FSIDIBT_MARK,
1701 };
1702 static const unsigned int fsid_sclk_out_pins[] = {
1703         /* OLR, OBT */
1704         46, 45,
1705 };
1706 static const unsigned int fsid_sclk_out_mux[] = {
1707         FSIDOLR_MARK, FSIDOBT_MARK,
1708 };
1709 static const unsigned int fsid_data_in_pins[] = {
1710         /* ISLD */
1711         48,
1712 };
1713 static const unsigned int fsid_data_in_mux[] = {
1714         FSIDISLD_MARK,
1715 };
1716 /* - I2C2 ------------------------------------------------------------------- */
1717 static const unsigned int i2c2_0_pins[] = {
1718         /* SCL, SDA */
1719         237, 236,
1720 };
1721 static const unsigned int i2c2_0_mux[] = {
1722         PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
1723 };
1724 static const unsigned int i2c2_1_pins[] = {
1725         /* SCL, SDA */
1726         27, 28,
1727 };
1728 static const unsigned int i2c2_1_mux[] = {
1729         PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
1730 };
1731 static const unsigned int i2c2_2_pins[] = {
1732         /* SCL, SDA */
1733         115, 116,
1734 };
1735 static const unsigned int i2c2_2_mux[] = {
1736         PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
1737 };
1738 /* - I2C3 ------------------------------------------------------------------- */
1739 static const unsigned int i2c3_0_pins[] = {
1740         /* SCL, SDA */
1741         248, 249,
1742 };
1743 static const unsigned int i2c3_0_mux[] = {
1744         PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
1745 };
1746 static const unsigned int i2c3_1_pins[] = {
1747         /* SCL, SDA */
1748         27, 28,
1749 };
1750 static const unsigned int i2c3_1_mux[] = {
1751         PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
1752 };
1753 static const unsigned int i2c3_2_pins[] = {
1754         /* SCL, SDA */
1755         115, 116,
1756 };
1757 static const unsigned int i2c3_2_mux[] = {
1758         PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
1759 };
1760 /* - IrDA ------------------------------------------------------------------- */
1761 static const unsigned int irda_0_pins[] = {
1762         /* OUT, IN, FIRSEL */
1763         241, 242, 243,
1764 };
1765 static const unsigned int irda_0_mux[] = {
1766         PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
1767 };
1768 static const unsigned int irda_1_pins[] = {
1769         /* OUT, IN, FIRSEL */
1770         49, 53, 54,
1771 };
1772 static const unsigned int irda_1_mux[] = {
1773         PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
1774 };
1775 /* - KEYSC ------------------------------------------------------------------ */
1776 static const unsigned int keysc_in5_pins[] = {
1777         /* KEYIN[0:4] */
1778         66, 67, 68, 69, 70,
1779 };
1780 static const unsigned int keysc_in5_mux[] = {
1781         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1782         KEYIN4_MARK,
1783 };
1784 static const unsigned int keysc_in6_pins[] = {
1785         /* KEYIN[0:5] */
1786         66, 67, 68, 69, 70, 71,
1787 };
1788 static const unsigned int keysc_in6_mux[] = {
1789         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1790         KEYIN4_MARK, KEYIN5_MARK,
1791 };
1792 static const unsigned int keysc_in7_pins[] = {
1793         /* KEYIN[0:6] */
1794         66, 67, 68, 69, 70, 71, 72,
1795 };
1796 static const unsigned int keysc_in7_mux[] = {
1797         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1798         KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
1799 };
1800 static const unsigned int keysc_in8_pins[] = {
1801         /* KEYIN[0:7] */
1802         66, 67, 68, 69, 70, 71, 72, 73,
1803 };
1804 static const unsigned int keysc_in8_mux[] = {
1805         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1806         KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
1807 };
1808 static const unsigned int keysc_out04_pins[] = {
1809         /* KEYOUT[0:4] */
1810         65, 64, 63, 62, 61,
1811 };
1812 static const unsigned int keysc_out04_mux[] = {
1813         KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
1814 };
1815 static const unsigned int keysc_out5_pins[] = {
1816         /* KEYOUT5 */
1817         60,
1818 };
1819 static const unsigned int keysc_out5_mux[] = {
1820         KEYOUT5_MARK,
1821 };
1822 static const unsigned int keysc_out6_0_pins[] = {
1823         /* KEYOUT6 */
1824         59,
1825 };
1826 static const unsigned int keysc_out6_0_mux[] = {
1827         PORT59_KEYOUT6_MARK,
1828 };
1829 static const unsigned int keysc_out6_1_pins[] = {
1830         /* KEYOUT6 */
1831         131,
1832 };
1833 static const unsigned int keysc_out6_1_mux[] = {
1834         PORT131_KEYOUT6_MARK,
1835 };
1836 static const unsigned int keysc_out6_2_pins[] = {
1837         /* KEYOUT6 */
1838         143,
1839 };
1840 static const unsigned int keysc_out6_2_mux[] = {
1841         PORT143_KEYOUT6_MARK,
1842 };
1843 static const unsigned int keysc_out7_0_pins[] = {
1844         /* KEYOUT7 */
1845         58,
1846 };
1847 static const unsigned int keysc_out7_0_mux[] = {
1848         PORT58_KEYOUT7_MARK,
1849 };
1850 static const unsigned int keysc_out7_1_pins[] = {
1851         /* KEYOUT7 */
1852         132,
1853 };
1854 static const unsigned int keysc_out7_1_mux[] = {
1855         PORT132_KEYOUT7_MARK,
1856 };
1857 static const unsigned int keysc_out7_2_pins[] = {
1858         /* KEYOUT7 */
1859         144,
1860 };
1861 static const unsigned int keysc_out7_2_mux[] = {
1862         PORT144_KEYOUT7_MARK,
1863 };
1864 static const unsigned int keysc_out8_0_pins[] = {
1865         /* KEYOUT8 */
1866         PIN_NUMBER(6, 26),
1867 };
1868 static const unsigned int keysc_out8_0_mux[] = {
1869         KEYOUT8_MARK,
1870 };
1871 static const unsigned int keysc_out8_1_pins[] = {
1872         /* KEYOUT8 */
1873         136,
1874 };
1875 static const unsigned int keysc_out8_1_mux[] = {
1876         PORT136_KEYOUT8_MARK,
1877 };
1878 static const unsigned int keysc_out8_2_pins[] = {
1879         /* KEYOUT8 */
1880         138,
1881 };
1882 static const unsigned int keysc_out8_2_mux[] = {
1883         PORT138_KEYOUT8_MARK,
1884 };
1885 static const unsigned int keysc_out9_0_pins[] = {
1886         /* KEYOUT9 */
1887         137,
1888 };
1889 static const unsigned int keysc_out9_0_mux[] = {
1890         PORT137_KEYOUT9_MARK,
1891 };
1892 static const unsigned int keysc_out9_1_pins[] = {
1893         /* KEYOUT9 */
1894         139,
1895 };
1896 static const unsigned int keysc_out9_1_mux[] = {
1897         PORT139_KEYOUT9_MARK,
1898 };
1899 static const unsigned int keysc_out9_2_pins[] = {
1900         /* KEYOUT9 */
1901         149,
1902 };
1903 static const unsigned int keysc_out9_2_mux[] = {
1904         PORT149_KEYOUT9_MARK,
1905 };
1906 static const unsigned int keysc_out10_0_pins[] = {
1907         /* KEYOUT10 */
1908         132,
1909 };
1910 static const unsigned int keysc_out10_0_mux[] = {
1911         PORT132_KEYOUT10_MARK,
1912 };
1913 static const unsigned int keysc_out10_1_pins[] = {
1914         /* KEYOUT10 */
1915         142,
1916 };
1917 static const unsigned int keysc_out10_1_mux[] = {
1918         PORT142_KEYOUT10_MARK,
1919 };
1920 static const unsigned int keysc_out11_0_pins[] = {
1921         /* KEYOUT11 */
1922         131,
1923 };
1924 static const unsigned int keysc_out11_0_mux[] = {
1925         PORT131_KEYOUT11_MARK,
1926 };
1927 static const unsigned int keysc_out11_1_pins[] = {
1928         /* KEYOUT11 */
1929         143,
1930 };
1931 static const unsigned int keysc_out11_1_mux[] = {
1932         PORT143_KEYOUT11_MARK,
1933 };
1934 /* - LCD -------------------------------------------------------------------- */
1935 static const unsigned int lcd_data8_pins[] = {
1936         /* D[0:7] */
1937         192, 193, 194, 195, 196, 197, 198, 199,
1938 };
1939 static const unsigned int lcd_data8_mux[] = {
1940         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1941         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1942 };
1943 static const unsigned int lcd_data9_pins[] = {
1944         /* D[0:8] */
1945         192, 193, 194, 195, 196, 197, 198, 199,
1946         200,
1947 };
1948 static const unsigned int lcd_data9_mux[] = {
1949         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1950         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1951         LCDD8_MARK,
1952 };
1953 static const unsigned int lcd_data12_pins[] = {
1954         /* D[0:11] */
1955         192, 193, 194, 195, 196, 197, 198, 199,
1956         200, 201, 202, 203,
1957 };
1958 static const unsigned int lcd_data12_mux[] = {
1959         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1960         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1961         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1962 };
1963 static const unsigned int lcd_data16_pins[] = {
1964         /* D[0:15] */
1965         192, 193, 194, 195, 196, 197, 198, 199,
1966         200, 201, 202, 203, 204, 205, 206, 207,
1967 };
1968 static const unsigned int lcd_data16_mux[] = {
1969         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1970         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1971         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1972         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1973 };
1974 static const unsigned int lcd_data18_pins[] = {
1975         /* D[0:17] */
1976         192, 193, 194, 195, 196, 197, 198, 199,
1977         200, 201, 202, 203, 204, 205, 206, 207,
1978         208, 209,
1979 };
1980 static const unsigned int lcd_data18_mux[] = {
1981         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1982         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1983         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1984         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1985         LCDD16_MARK, LCDD17_MARK,
1986 };
1987 static const unsigned int lcd_data24_pins[] = {
1988         /* D[0:23] */
1989         192, 193, 194, 195, 196, 197, 198, 199,
1990         200, 201, 202, 203, 204, 205, 206, 207,
1991         208, 209, 210, 211, 212, 213, 214, 215
1992 };
1993 static const unsigned int lcd_data24_mux[] = {
1994         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1995         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1996         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1997         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1998         LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
1999         LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
2000 };
2001 static const unsigned int lcd_display_pins[] = {
2002         /* DON */
2003         222,
2004 };
2005 static const unsigned int lcd_display_mux[] = {
2006         LCDDON_MARK,
2007 };
2008 static const unsigned int lcd_lclk_pins[] = {
2009         /* LCLK */
2010         221,
2011 };
2012 static const unsigned int lcd_lclk_mux[] = {
2013         LCDLCLK_MARK,
2014 };
2015 static const unsigned int lcd_sync_pins[] = {
2016         /* VSYN, HSYN, DCK, DISP */
2017         220, 218, 216, 219,
2018 };
2019 static const unsigned int lcd_sync_mux[] = {
2020         LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
2021 };
2022 static const unsigned int lcd_sys_pins[] = {
2023         /* CS, WR, RD, RS */
2024         218, 216, 217, 219,
2025 };
2026 static const unsigned int lcd_sys_mux[] = {
2027         LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
2028 };
2029 /* - LCD2 ------------------------------------------------------------------- */
2030 static const unsigned int lcd2_data8_pins[] = {
2031         /* D[0:7] */
2032         128, 129, 142, 143, 144, 145, 138, 139,
2033 };
2034 static const unsigned int lcd2_data8_mux[] = {
2035         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2036         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2037 };
2038 static const unsigned int lcd2_data9_pins[] = {
2039         /* D[0:8] */
2040         128, 129, 142, 143, 144, 145, 138, 139,
2041         140,
2042 };
2043 static const unsigned int lcd2_data9_mux[] = {
2044         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2045         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2046         LCD2D8_MARK,
2047 };
2048 static const unsigned int lcd2_data12_pins[] = {
2049         /* D[0:11] */
2050         128, 129, 142, 143, 144, 145, 138, 139,
2051         140, 141, 130, 131,
2052 };
2053 static const unsigned int lcd2_data12_mux[] = {
2054         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2055         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2056         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2057 };
2058 static const unsigned int lcd2_data16_pins[] = {
2059         /* D[0:15] */
2060         128, 129, 142, 143, 144, 145, 138, 139,
2061         140, 141, 130, 131, 132, 133, 134, 135,
2062 };
2063 static const unsigned int lcd2_data16_mux[] = {
2064         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2065         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2066         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2067         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2068 };
2069 static const unsigned int lcd2_data18_pins[] = {
2070         /* D[0:17] */
2071         128, 129, 142, 143, 144, 145, 138, 139,
2072         140, 141, 130, 131, 132, 133, 134, 135,
2073         136, 137,
2074 };
2075 static const unsigned int lcd2_data18_mux[] = {
2076         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2077         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2078         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2079         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2080         LCD2D16_MARK, LCD2D17_MARK,
2081 };
2082 static const unsigned int lcd2_data24_pins[] = {
2083         /* D[0:23] */
2084         128, 129, 142, 143, 144, 145, 138, 139,
2085         140, 141, 130, 131, 132, 133, 134, 135,
2086         136, 137, 146, 147, 234, 235, 238, 239
2087 };
2088 static const unsigned int lcd2_data24_mux[] = {
2089         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2090         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2091         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2092         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2093         LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
2094         LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
2095 };
2096 static const unsigned int lcd2_sync_0_pins[] = {
2097         /* VSYN, HSYN, DCK, DISP */
2098         128, 129, 146, 145,
2099 };
2100 static const unsigned int lcd2_sync_0_mux[] = {
2101         PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
2102         LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
2103 };
2104 static const unsigned int lcd2_sync_1_pins[] = {
2105         /* VSYN, HSYN, DCK, DISP */
2106         222, 221, 219, 217,
2107 };
2108 static const unsigned int lcd2_sync_1_mux[] = {
2109         PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
2110         LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
2111 };
2112 static const unsigned int lcd2_sys_0_pins[] = {
2113         /* CS, WR, RD, RS */
2114         129, 146, 147, 145,
2115 };
2116 static const unsigned int lcd2_sys_0_mux[] = {
2117         PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
2118         LCD2RD__MARK, PORT145_LCD2RS_MARK,
2119 };
2120 static const unsigned int lcd2_sys_1_pins[] = {
2121         /* CS, WR, RD, RS */
2122         221, 219, 147, 217,
2123 };
2124 static const unsigned int lcd2_sys_1_mux[] = {
2125         PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
2126         LCD2RD__MARK, PORT217_LCD2RS_MARK,
2127 };
2128 /* - MMCIF ------------------------------------------------------------------ */
2129 static const unsigned int mmc0_data1_0_pins[] = {
2130         /* D[0] */
2131         271,
2132 };
2133 static const unsigned int mmc0_data1_0_mux[] = {
2134         MMCD0_0_MARK,
2135 };
2136 static const unsigned int mmc0_data4_0_pins[] = {
2137         /* D[0:3] */
2138         271, 272, 273, 274,
2139 };
2140 static const unsigned int mmc0_data4_0_mux[] = {
2141         MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2142 };
2143 static const unsigned int mmc0_data8_0_pins[] = {
2144         /* D[0:7] */
2145         271, 272, 273, 274, 275, 276, 277, 278,
2146 };
2147 static const unsigned int mmc0_data8_0_mux[] = {
2148         MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2149         MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
2150 };
2151 static const unsigned int mmc0_ctrl_0_pins[] = {
2152         /* CMD, CLK */
2153         279, 270,
2154 };
2155 static const unsigned int mmc0_ctrl_0_mux[] = {
2156         MMCCMD0_MARK, MMCCLK0_MARK,
2157 };
2158
2159 static const unsigned int mmc0_data1_1_pins[] = {
2160         /* D[0] */
2161         305,
2162 };
2163 static const unsigned int mmc0_data1_1_mux[] = {
2164         MMCD1_0_MARK,
2165 };
2166 static const unsigned int mmc0_data4_1_pins[] = {
2167         /* D[0:3] */
2168         305, 304, 303, 302,
2169 };
2170 static const unsigned int mmc0_data4_1_mux[] = {
2171         MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2172 };
2173 static const unsigned int mmc0_data8_1_pins[] = {
2174         /* D[0:7] */
2175         305, 304, 303, 302, 301, 300, 299, 298,
2176 };
2177 static const unsigned int mmc0_data8_1_mux[] = {
2178         MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2179         MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
2180 };
2181 static const unsigned int mmc0_ctrl_1_pins[] = {
2182         /* CMD, CLK */
2183         297, 289,
2184 };
2185 static const unsigned int mmc0_ctrl_1_mux[] = {
2186         MMCCMD1_MARK, MMCCLK1_MARK,
2187 };
2188 /* - MSIOF0 ----------------------------------------------------------------- */
2189 static const unsigned int msiof0_rsck_pins[] = {
2190         /* RSCK */
2191         66,
2192 };
2193 static const unsigned int msiof0_rsck_mux[] = {
2194         MSIOF0_RSCK_MARK,
2195 };
2196 static const unsigned int msiof0_tsck_pins[] = {
2197         /* TSCK */
2198         64,
2199 };
2200 static const unsigned int msiof0_tsck_mux[] = {
2201         MSIOF0_TSCK_MARK,
2202 };
2203 static const unsigned int msiof0_rsync_pins[] = {
2204         /* RSYNC */
2205         67,
2206 };
2207 static const unsigned int msiof0_rsync_mux[] = {
2208         MSIOF0_RSYNC_MARK,
2209 };
2210 static const unsigned int msiof0_tsync_pins[] = {
2211         /* TSYNC */
2212         63,
2213 };
2214 static const unsigned int msiof0_tsync_mux[] = {
2215         MSIOF0_TSYNC_MARK,
2216 };
2217 static const unsigned int msiof0_ss1_pins[] = {
2218         /* SS1 */
2219         62,
2220 };
2221 static const unsigned int msiof0_ss1_mux[] = {
2222         MSIOF0_SS1_MARK,
2223 };
2224 static const unsigned int msiof0_ss2_pins[] = {
2225         /* SS2 */
2226         71,
2227 };
2228 static const unsigned int msiof0_ss2_mux[] = {
2229         MSIOF0_SS2_MARK,
2230 };
2231 static const unsigned int msiof0_rxd_pins[] = {
2232         /* RXD */
2233         70,
2234 };
2235 static const unsigned int msiof0_rxd_mux[] = {
2236         MSIOF0_RXD_MARK,
2237 };
2238 static const unsigned int msiof0_txd_pins[] = {
2239         /* TXD */
2240         65,
2241 };
2242 static const unsigned int msiof0_txd_mux[] = {
2243         MSIOF0_TXD_MARK,
2244 };
2245 static const unsigned int msiof0_mck0_pins[] = {
2246         /* MSCK0 */
2247         68,
2248 };
2249 static const unsigned int msiof0_mck0_mux[] = {
2250         MSIOF0_MCK0_MARK,
2251 };
2252
2253 static const unsigned int msiof0_mck1_pins[] = {
2254         /* MSCK1 */
2255         69,
2256 };
2257 static const unsigned int msiof0_mck1_mux[] = {
2258         MSIOF0_MCK1_MARK,
2259 };
2260
2261 static const unsigned int msiof0l_rsck_pins[] = {
2262         /* RSCK */
2263         214,
2264 };
2265 static const unsigned int msiof0l_rsck_mux[] = {
2266         MSIOF0L_RSCK_MARK,
2267 };
2268 static const unsigned int msiof0l_tsck_pins[] = {
2269         /* TSCK */
2270         219,
2271 };
2272 static const unsigned int msiof0l_tsck_mux[] = {
2273         MSIOF0L_TSCK_MARK,
2274 };
2275 static const unsigned int msiof0l_rsync_pins[] = {
2276         /* RSYNC */
2277         215,
2278 };
2279 static const unsigned int msiof0l_rsync_mux[] = {
2280         MSIOF0L_RSYNC_MARK,
2281 };
2282 static const unsigned int msiof0l_tsync_pins[] = {
2283         /* TSYNC */
2284         217,
2285 };
2286 static const unsigned int msiof0l_tsync_mux[] = {
2287         MSIOF0L_TSYNC_MARK,
2288 };
2289 static const unsigned int msiof0l_ss1_a_pins[] = {
2290         /* SS1 */
2291         207,
2292 };
2293 static const unsigned int msiof0l_ss1_a_mux[] = {
2294         PORT207_MSIOF0L_SS1_MARK,
2295 };
2296 static const unsigned int msiof0l_ss1_b_pins[] = {
2297         /* SS1 */
2298         210,
2299 };
2300 static const unsigned int msiof0l_ss1_b_mux[] = {
2301         PORT210_MSIOF0L_SS1_MARK,
2302 };
2303 static const unsigned int msiof0l_ss2_a_pins[] = {
2304         /* SS2 */
2305         208,
2306 };
2307 static const unsigned int msiof0l_ss2_a_mux[] = {
2308         PORT208_MSIOF0L_SS2_MARK,
2309 };
2310 static const unsigned int msiof0l_ss2_b_pins[] = {
2311         /* SS2 */
2312         211,
2313 };
2314 static const unsigned int msiof0l_ss2_b_mux[] = {
2315         PORT211_MSIOF0L_SS2_MARK,
2316 };
2317 static const unsigned int msiof0l_rxd_pins[] = {
2318         /* RXD */
2319         221,
2320 };
2321 static const unsigned int msiof0l_rxd_mux[] = {
2322         MSIOF0L_RXD_MARK,
2323 };
2324 static const unsigned int msiof0l_txd_pins[] = {
2325         /* TXD */
2326         222,
2327 };
2328 static const unsigned int msiof0l_txd_mux[] = {
2329         MSIOF0L_TXD_MARK,
2330 };
2331 static const unsigned int msiof0l_mck0_pins[] = {
2332         /* MSCK0 */
2333         212,
2334 };
2335 static const unsigned int msiof0l_mck0_mux[] = {
2336         MSIOF0L_MCK0_MARK,
2337 };
2338 static const unsigned int msiof0l_mck1_pins[] = {
2339         /* MSCK1 */
2340         213,
2341 };
2342 static const unsigned int msiof0l_mck1_mux[] = {
2343         MSIOF0L_MCK1_MARK,
2344 };
2345 /* - MSIOF1 ----------------------------------------------------------------- */
2346 static const unsigned int msiof1_rsck_pins[] = {
2347         /* RSCK */
2348         234,
2349 };
2350 static const unsigned int msiof1_rsck_mux[] = {
2351         MSIOF1_RSCK_MARK,
2352 };
2353 static const unsigned int msiof1_tsck_pins[] = {
2354         /* TSCK */
2355         232,
2356 };
2357 static const unsigned int msiof1_tsck_mux[] = {
2358         MSIOF1_TSCK_MARK,
2359 };
2360 static const unsigned int msiof1_rsync_pins[] = {
2361         /* RSYNC */
2362         235,
2363 };
2364 static const unsigned int msiof1_rsync_mux[] = {
2365         MSIOF1_RSYNC_MARK,
2366 };
2367 static const unsigned int msiof1_tsync_pins[] = {
2368         /* TSYNC */
2369         231,
2370 };
2371 static const unsigned int msiof1_tsync_mux[] = {
2372         MSIOF1_TSYNC_MARK,
2373 };
2374 static const unsigned int msiof1_ss1_pins[] = {
2375         /* SS1 */
2376         238,
2377 };
2378 static const unsigned int msiof1_ss1_mux[] = {
2379         MSIOF1_SS1_MARK,
2380 };
2381 static const unsigned int msiof1_ss2_pins[] = {
2382         /* SS2 */
2383         239,
2384 };
2385 static const unsigned int msiof1_ss2_mux[] = {
2386         MSIOF1_SS2_MARK,
2387 };
2388 static const unsigned int msiof1_rxd_pins[] = {
2389         /* RXD */
2390         233,
2391 };
2392 static const unsigned int msiof1_rxd_mux[] = {
2393         MSIOF1_RXD_MARK,
2394 };
2395 static const unsigned int msiof1_txd_pins[] = {
2396         /* TXD */
2397         230,
2398 };
2399 static const unsigned int msiof1_txd_mux[] = {
2400         MSIOF1_TXD_MARK,
2401 };
2402 static const unsigned int msiof1_mck0_pins[] = {
2403         /* MSCK0 */
2404         236,
2405 };
2406 static const unsigned int msiof1_mck0_mux[] = {
2407         MSIOF1_MCK0_MARK,
2408 };
2409 static const unsigned int msiof1_mck1_pins[] = {
2410         /* MSCK1 */
2411         237,
2412 };
2413 static const unsigned int msiof1_mck1_mux[] = {
2414         MSIOF1_MCK1_MARK,
2415 };
2416 /* - MSIOF2 ----------------------------------------------------------------- */
2417 static const unsigned int msiof2_rsck_pins[] = {
2418         /* RSCK */
2419         151,
2420 };
2421 static const unsigned int msiof2_rsck_mux[] = {
2422         MSIOF2_RSCK_MARK,
2423 };
2424 static const unsigned int msiof2_tsck_pins[] = {
2425         /* TSCK */
2426         135,
2427 };
2428 static const unsigned int msiof2_tsck_mux[] = {
2429         MSIOF2_TSCK_MARK,
2430 };
2431 static const unsigned int msiof2_rsync_pins[] = {
2432         /* RSYNC */
2433         152,
2434 };
2435 static const unsigned int msiof2_rsync_mux[] = {
2436         MSIOF2_RSYNC_MARK,
2437 };
2438 static const unsigned int msiof2_tsync_pins[] = {
2439         /* TSYNC */
2440         133,
2441 };
2442 static const unsigned int msiof2_tsync_mux[] = {
2443         MSIOF2_TSYNC_MARK,
2444 };
2445 static const unsigned int msiof2_ss1_a_pins[] = {
2446         /* SS1 */
2447         131,
2448 };
2449 static const unsigned int msiof2_ss1_a_mux[] = {
2450         PORT131_MSIOF2_SS1_MARK,
2451 };
2452 static const unsigned int msiof2_ss1_b_pins[] = {
2453         /* SS1 */
2454         153,
2455 };
2456 static const unsigned int msiof2_ss1_b_mux[] = {
2457         PORT153_MSIOF2_SS1_MARK,
2458 };
2459 static const unsigned int msiof2_ss2_a_pins[] = {
2460         /* SS2 */
2461         132,
2462 };
2463 static const unsigned int msiof2_ss2_a_mux[] = {
2464         PORT132_MSIOF2_SS2_MARK,
2465 };
2466 static const unsigned int msiof2_ss2_b_pins[] = {
2467         /* SS2 */
2468         156,
2469 };
2470 static const unsigned int msiof2_ss2_b_mux[] = {
2471         PORT156_MSIOF2_SS2_MARK,
2472 };
2473 static const unsigned int msiof2_rxd_a_pins[] = {
2474         /* RXD */
2475         130,
2476 };
2477 static const unsigned int msiof2_rxd_a_mux[] = {
2478         PORT130_MSIOF2_RXD_MARK,
2479 };
2480 static const unsigned int msiof2_rxd_b_pins[] = {
2481         /* RXD */
2482         157,
2483 };
2484 static const unsigned int msiof2_rxd_b_mux[] = {
2485         PORT157_MSIOF2_RXD_MARK,
2486 };
2487 static const unsigned int msiof2_txd_pins[] = {
2488         /* TXD */
2489         134,
2490 };
2491 static const unsigned int msiof2_txd_mux[] = {
2492         MSIOF2_TXD_MARK,
2493 };
2494 static const unsigned int msiof2_mck0_pins[] = {
2495         /* MSCK0 */
2496         154,
2497 };
2498 static const unsigned int msiof2_mck0_mux[] = {
2499         MSIOF2_MCK0_MARK,
2500 };
2501 static const unsigned int msiof2_mck1_pins[] = {
2502         /* MSCK1 */
2503         155,
2504 };
2505 static const unsigned int msiof2_mck1_mux[] = {
2506         MSIOF2_MCK1_MARK,
2507 };
2508
2509 static const unsigned int msiof2r_tsck_pins[] = {
2510         /* TSCK */
2511         248,
2512 };
2513 static const unsigned int msiof2r_tsck_mux[] = {
2514         MSIOF2R_TSCK_MARK,
2515 };
2516 static const unsigned int msiof2r_tsync_pins[] = {
2517         /* TSYNC */
2518         249,
2519 };
2520 static const unsigned int msiof2r_tsync_mux[] = {
2521         MSIOF2R_TSYNC_MARK,
2522 };
2523 static const unsigned int msiof2r_rxd_pins[] = {
2524         /* RXD */
2525         244,
2526 };
2527 static const unsigned int msiof2r_rxd_mux[] = {
2528         MSIOF2R_RXD_MARK,
2529 };
2530 static const unsigned int msiof2r_txd_pins[] = {
2531         /* TXD */
2532         245,
2533 };
2534 static const unsigned int msiof2r_txd_mux[] = {
2535         MSIOF2R_TXD_MARK,
2536 };
2537 /* - MSIOF3 (Pin function name of MSIOF3 is named BBIF1) -------------------- */
2538 static const unsigned int msiof3_rsck_pins[] = {
2539         /* RSCK */
2540         115,
2541 };
2542 static const unsigned int msiof3_rsck_mux[] = {
2543         BBIF1_RSCK_MARK,
2544 };
2545 static const unsigned int msiof3_tsck_pins[] = {
2546         /* TSCK */
2547         112,
2548 };
2549 static const unsigned int msiof3_tsck_mux[] = {
2550         BBIF1_TSCK_MARK,
2551 };
2552 static const unsigned int msiof3_rsync_pins[] = {
2553         /* RSYNC */
2554         116,
2555 };
2556 static const unsigned int msiof3_rsync_mux[] = {
2557         BBIF1_RSYNC_MARK,
2558 };
2559 static const unsigned int msiof3_tsync_pins[] = {
2560         /* TSYNC */
2561         113,
2562 };
2563 static const unsigned int msiof3_tsync_mux[] = {
2564         BBIF1_TSYNC_MARK,
2565 };
2566 static const unsigned int msiof3_ss1_pins[] = {
2567         /* SS1 */
2568         117,
2569 };
2570 static const unsigned int msiof3_ss1_mux[] = {
2571         BBIF1_SS1_MARK,
2572 };
2573 static const unsigned int msiof3_ss2_pins[] = {
2574         /* SS2 */
2575         109,
2576 };
2577 static const unsigned int msiof3_ss2_mux[] = {
2578         BBIF1_SS2_MARK,
2579 };
2580 static const unsigned int msiof3_rxd_pins[] = {
2581         /* RXD */
2582         111,
2583 };
2584 static const unsigned int msiof3_rxd_mux[] = {
2585         BBIF1_RXD_MARK,
2586 };
2587 static const unsigned int msiof3_txd_pins[] = {
2588         /* TXD */
2589         114,
2590 };
2591 static const unsigned int msiof3_txd_mux[] = {
2592         BBIF1_TXD_MARK,
2593 };
2594 static const unsigned int msiof3_flow_pins[] = {
2595         /* FLOW */
2596         117,
2597 };
2598 static const unsigned int msiof3_flow_mux[] = {
2599         BBIF1_FLOW_MARK,
2600 };
2601
2602 /* - SCIFA0 ----------------------------------------------------------------- */
2603 static const unsigned int scifa0_data_pins[] = {
2604         /* RXD, TXD */
2605         43, 17,
2606 };
2607 static const unsigned int scifa0_data_mux[] = {
2608         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2609 };
2610 static const unsigned int scifa0_clk_pins[] = {
2611         /* SCK */
2612         16,
2613 };
2614 static const unsigned int scifa0_clk_mux[] = {
2615         SCIFA0_SCK_MARK,
2616 };
2617 static const unsigned int scifa0_ctrl_pins[] = {
2618         /* RTS, CTS */
2619         42, 44,
2620 };
2621 static const unsigned int scifa0_ctrl_mux[] = {
2622         SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
2623 };
2624 /* - SCIFA1 ----------------------------------------------------------------- */
2625 static const unsigned int scifa1_data_pins[] = {
2626         /* RXD, TXD */
2627         228, 225,
2628 };
2629 static const unsigned int scifa1_data_mux[] = {
2630         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2631 };
2632 static const unsigned int scifa1_clk_pins[] = {
2633         /* SCK */
2634         226,
2635 };
2636 static const unsigned int scifa1_clk_mux[] = {
2637         SCIFA1_SCK_MARK,
2638 };
2639 static const unsigned int scifa1_ctrl_pins[] = {
2640         /* RTS, CTS */
2641         227, 229,
2642 };
2643 static const unsigned int scifa1_ctrl_mux[] = {
2644         SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
2645 };
2646 /* - SCIFA2 ----------------------------------------------------------------- */
2647 static const unsigned int scifa2_data_0_pins[] = {
2648         /* RXD, TXD */
2649         155, 154,
2650 };
2651 static const unsigned int scifa2_data_0_mux[] = {
2652         SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
2653 };
2654 static const unsigned int scifa2_clk_0_pins[] = {
2655         /* SCK */
2656         158,
2657 };
2658 static const unsigned int scifa2_clk_0_mux[] = {
2659         SCIFA2_SCK1_MARK,
2660 };
2661 static const unsigned int scifa2_ctrl_0_pins[] = {
2662         /* RTS, CTS */
2663         156, 157,
2664 };
2665 static const unsigned int scifa2_ctrl_0_mux[] = {
2666         SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
2667 };
2668 static const unsigned int scifa2_data_1_pins[] = {
2669         /* RXD, TXD */
2670         233, 230,
2671 };
2672 static const unsigned int scifa2_data_1_mux[] = {
2673         SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
2674 };
2675 static const unsigned int scifa2_clk_1_pins[] = {
2676         /* SCK */
2677         232,
2678 };
2679 static const unsigned int scifa2_clk_1_mux[] = {
2680         SCIFA2_SCK2_MARK,
2681 };
2682 static const unsigned int scifa2_ctrl_1_pins[] = {
2683         /* RTS, CTS */
2684         234, 231,
2685 };
2686 static const unsigned int scifa2_ctrl_1_mux[] = {
2687         SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
2688 };
2689 /* - SCIFA3 ----------------------------------------------------------------- */
2690 static const unsigned int scifa3_data_pins[] = {
2691         /* RXD, TXD */
2692         108, 110,
2693 };
2694 static const unsigned int scifa3_data_mux[] = {
2695         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2696 };
2697 static const unsigned int scifa3_ctrl_pins[] = {
2698         /* RTS, CTS */
2699         109, 107,
2700 };
2701 static const unsigned int scifa3_ctrl_mux[] = {
2702         SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
2703 };
2704 /* - SCIFA4 ----------------------------------------------------------------- */
2705 static const unsigned int scifa4_data_pins[] = {
2706         /* RXD, TXD */
2707         33, 32,
2708 };
2709 static const unsigned int scifa4_data_mux[] = {
2710         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2711 };
2712 static const unsigned int scifa4_ctrl_pins[] = {
2713         /* RTS, CTS */
2714         34, 35,
2715 };
2716 static const unsigned int scifa4_ctrl_mux[] = {
2717         SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
2718 };
2719 /* - SCIFA5 ----------------------------------------------------------------- */
2720 static const unsigned int scifa5_data_0_pins[] = {
2721         /* RXD, TXD */
2722         246, 247,
2723 };
2724 static const unsigned int scifa5_data_0_mux[] = {
2725         PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
2726 };
2727 static const unsigned int scifa5_clk_0_pins[] = {
2728         /* SCK */
2729         248,
2730 };
2731 static const unsigned int scifa5_clk_0_mux[] = {
2732         PORT248_SCIFA5_SCK_MARK,
2733 };
2734 static const unsigned int scifa5_ctrl_0_pins[] = {
2735         /* RTS, CTS */
2736         245, 244,
2737 };
2738 static const unsigned int scifa5_ctrl_0_mux[] = {
2739         PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
2740 };
2741 static const unsigned int scifa5_data_1_pins[] = {
2742         /* RXD, TXD */
2743         195, 196,
2744 };
2745 static const unsigned int scifa5_data_1_mux[] = {
2746         PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
2747 };
2748 static const unsigned int scifa5_clk_1_pins[] = {
2749         /* SCK */
2750         197,
2751 };
2752 static const unsigned int scifa5_clk_1_mux[] = {
2753         PORT197_SCIFA5_SCK_MARK,
2754 };
2755 static const unsigned int scifa5_ctrl_1_pins[] = {
2756         /* RTS, CTS */
2757         194, 193,
2758 };
2759 static const unsigned int scifa5_ctrl_1_mux[] = {
2760         PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
2761 };
2762 static const unsigned int scifa5_data_2_pins[] = {
2763         /* RXD, TXD */
2764         162, 160,
2765 };
2766 static const unsigned int scifa5_data_2_mux[] = {
2767         PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
2768 };
2769 static const unsigned int scifa5_clk_2_pins[] = {
2770         /* SCK */
2771         159,
2772 };
2773 static const unsigned int scifa5_clk_2_mux[] = {
2774         PORT159_SCIFA5_SCK_MARK,
2775 };
2776 static const unsigned int scifa5_ctrl_2_pins[] = {
2777         /* RTS, CTS */
2778         163, 161,
2779 };
2780 static const unsigned int scifa5_ctrl_2_mux[] = {
2781         PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
2782 };
2783 /* - SCIFA6 ----------------------------------------------------------------- */
2784 static const unsigned int scifa6_pins[] = {
2785         /* TXD */
2786         240,
2787 };
2788 static const unsigned int scifa6_mux[] = {
2789         SCIFA6_TXD_MARK,
2790 };
2791 /* - SCIFA7 ----------------------------------------------------------------- */
2792 static const unsigned int scifa7_data_pins[] = {
2793         /* RXD, TXD */
2794         12, 18,
2795 };
2796 static const unsigned int scifa7_data_mux[] = {
2797         SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2798 };
2799 static const unsigned int scifa7_ctrl_pins[] = {
2800         /* RTS, CTS */
2801         19, 13,
2802 };
2803 static const unsigned int scifa7_ctrl_mux[] = {
2804         SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
2805 };
2806 /* - SCIFB ------------------------------------------------------------------ */
2807 static const unsigned int scifb_data_0_pins[] = {
2808         /* RXD, TXD */
2809         162, 160,
2810 };
2811 static const unsigned int scifb_data_0_mux[] = {
2812         PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
2813 };
2814 static const unsigned int scifb_clk_0_pins[] = {
2815         /* SCK */
2816         159,
2817 };
2818 static const unsigned int scifb_clk_0_mux[] = {
2819         PORT159_SCIFB_SCK_MARK,
2820 };
2821 static const unsigned int scifb_ctrl_0_pins[] = {
2822         /* RTS, CTS */
2823         163, 161,
2824 };
2825 static const unsigned int scifb_ctrl_0_mux[] = {
2826         PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
2827 };
2828 static const unsigned int scifb_data_1_pins[] = {
2829         /* RXD, TXD */
2830         246, 247,
2831 };
2832 static const unsigned int scifb_data_1_mux[] = {
2833         PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
2834 };
2835 static const unsigned int scifb_clk_1_pins[] = {
2836         /* SCK */
2837         248,
2838 };
2839 static const unsigned int scifb_clk_1_mux[] = {
2840         PORT248_SCIFB_SCK_MARK,
2841 };
2842 static const unsigned int scifb_ctrl_1_pins[] = {
2843         /* RTS, CTS */
2844         245, 244,
2845 };
2846 static const unsigned int scifb_ctrl_1_mux[] = {
2847         PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
2848 };
2849 /* - SDHI0 ------------------------------------------------------------------ */
2850 static const unsigned int sdhi0_data1_pins[] = {
2851         /* D0 */
2852         252,
2853 };
2854 static const unsigned int sdhi0_data1_mux[] = {
2855         SDHID0_0_MARK,
2856 };
2857 static const unsigned int sdhi0_data4_pins[] = {
2858         /* D[0:3] */
2859         252, 253, 254, 255,
2860 };
2861 static const unsigned int sdhi0_data4_mux[] = {
2862         SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
2863 };
2864 static const unsigned int sdhi0_ctrl_pins[] = {
2865         /* CMD, CLK */
2866         256, 250,
2867 };
2868 static const unsigned int sdhi0_ctrl_mux[] = {
2869         SDHICMD0_MARK, SDHICLK0_MARK,
2870 };
2871 static const unsigned int sdhi0_cd_pins[] = {
2872         /* CD */
2873         251,
2874 };
2875 static const unsigned int sdhi0_cd_mux[] = {
2876         SDHICD0_MARK,
2877 };
2878 static const unsigned int sdhi0_wp_pins[] = {
2879         /* WP */
2880         257,
2881 };
2882 static const unsigned int sdhi0_wp_mux[] = {
2883         SDHIWP0_MARK,
2884 };
2885 /* - SDHI1 ------------------------------------------------------------------ */
2886 static const unsigned int sdhi1_data1_pins[] = {
2887         /* D0 */
2888         259,
2889 };
2890 static const unsigned int sdhi1_data1_mux[] = {
2891         SDHID1_0_MARK,
2892 };
2893 static const unsigned int sdhi1_data4_pins[] = {
2894         /* D[0:3] */
2895         259, 260, 261, 262,
2896 };
2897 static const unsigned int sdhi1_data4_mux[] = {
2898         SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
2899 };
2900 static const unsigned int sdhi1_ctrl_pins[] = {
2901         /* CMD, CLK */
2902         263, 258,
2903 };
2904 static const unsigned int sdhi1_ctrl_mux[] = {
2905         SDHICMD1_MARK, SDHICLK1_MARK,
2906 };
2907 /* - SDHI2 ------------------------------------------------------------------ */
2908 static const unsigned int sdhi2_data1_pins[] = {
2909         /* D0 */
2910         265,
2911 };
2912 static const unsigned int sdhi2_data1_mux[] = {
2913         SDHID2_0_MARK,
2914 };
2915 static const unsigned int sdhi2_data4_pins[] = {
2916         /* D[0:3] */
2917         265, 266, 267, 268,
2918 };
2919 static const unsigned int sdhi2_data4_mux[] = {
2920         SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
2921 };
2922 static const unsigned int sdhi2_ctrl_pins[] = {
2923         /* CMD, CLK */
2924         269, 264,
2925 };
2926 static const unsigned int sdhi2_ctrl_mux[] = {
2927         SDHICMD2_MARK, SDHICLK2_MARK,
2928 };
2929 /* - TPU0 ------------------------------------------------------------------- */
2930 static const unsigned int tpu0_to0_pins[] = {
2931         /* TO */
2932         55,
2933 };
2934 static const unsigned int tpu0_to0_mux[] = {
2935         TPU0TO0_MARK,
2936 };
2937 static const unsigned int tpu0_to1_pins[] = {
2938         /* TO */
2939         59,
2940 };
2941 static const unsigned int tpu0_to1_mux[] = {
2942         TPU0TO1_MARK,
2943 };
2944 static const unsigned int tpu0_to2_pins[] = {
2945         /* TO */
2946         140,
2947 };
2948 static const unsigned int tpu0_to2_mux[] = {
2949         TPU0TO2_MARK,
2950 };
2951 static const unsigned int tpu0_to3_pins[] = {
2952         /* TO */
2953         141,
2954 };
2955 static const unsigned int tpu0_to3_mux[] = {
2956         TPU0TO3_MARK,
2957 };
2958 /* - TPU1 ------------------------------------------------------------------- */
2959 static const unsigned int tpu1_to0_pins[] = {
2960         /* TO */
2961         246,
2962 };
2963 static const unsigned int tpu1_to0_mux[] = {
2964         TPU1TO0_MARK,
2965 };
2966 static const unsigned int tpu1_to1_0_pins[] = {
2967         /* TO */
2968         28,
2969 };
2970 static const unsigned int tpu1_to1_0_mux[] = {
2971         PORT28_TPU1TO1_MARK,
2972 };
2973 static const unsigned int tpu1_to1_1_pins[] = {
2974         /* TO */
2975         29,
2976 };
2977 static const unsigned int tpu1_to1_1_mux[] = {
2978         PORT29_TPU1TO1_MARK,
2979 };
2980 static const unsigned int tpu1_to2_pins[] = {
2981         /* TO */
2982         153,
2983 };
2984 static const unsigned int tpu1_to2_mux[] = {
2985         TPU1TO2_MARK,
2986 };
2987 static const unsigned int tpu1_to3_pins[] = {
2988         /* TO */
2989         145,
2990 };
2991 static const unsigned int tpu1_to3_mux[] = {
2992         TPU1TO3_MARK,
2993 };
2994 /* - TPU2 ------------------------------------------------------------------- */
2995 static const unsigned int tpu2_to0_pins[] = {
2996         /* TO */
2997         248,
2998 };
2999 static const unsigned int tpu2_to0_mux[] = {
3000         TPU2TO0_MARK,
3001 };
3002 static const unsigned int tpu2_to1_pins[] = {
3003         /* TO */
3004         197,
3005 };
3006 static const unsigned int tpu2_to1_mux[] = {
3007         TPU2TO1_MARK,
3008 };
3009 static const unsigned int tpu2_to2_pins[] = {
3010         /* TO */
3011         50,
3012 };
3013 static const unsigned int tpu2_to2_mux[] = {
3014         TPU2TO2_MARK,
3015 };
3016 static const unsigned int tpu2_to3_pins[] = {
3017         /* TO */
3018         51,
3019 };
3020 static const unsigned int tpu2_to3_mux[] = {
3021         TPU2TO3_MARK,
3022 };
3023 /* - TPU3 ------------------------------------------------------------------- */
3024 static const unsigned int tpu3_to0_pins[] = {
3025         /* TO */
3026         163,
3027 };
3028 static const unsigned int tpu3_to0_mux[] = {
3029         TPU3TO0_MARK,
3030 };
3031 static const unsigned int tpu3_to1_pins[] = {
3032         /* TO */
3033         247,
3034 };
3035 static const unsigned int tpu3_to1_mux[] = {
3036         TPU3TO1_MARK,
3037 };
3038 static const unsigned int tpu3_to2_pins[] = {
3039         /* TO */
3040         54,
3041 };
3042 static const unsigned int tpu3_to2_mux[] = {
3043         TPU3TO2_MARK,
3044 };
3045 static const unsigned int tpu3_to3_pins[] = {
3046         /* TO */
3047         53,
3048 };
3049 static const unsigned int tpu3_to3_mux[] = {
3050         TPU3TO3_MARK,
3051 };
3052 /* - TPU4 ------------------------------------------------------------------- */
3053 static const unsigned int tpu4_to0_pins[] = {
3054         /* TO */
3055         241,
3056 };
3057 static const unsigned int tpu4_to0_mux[] = {
3058         TPU4TO0_MARK,
3059 };
3060 static const unsigned int tpu4_to1_pins[] = {
3061         /* TO */
3062         199,
3063 };
3064 static const unsigned int tpu4_to1_mux[] = {
3065         TPU4TO1_MARK,
3066 };
3067 static const unsigned int tpu4_to2_pins[] = {
3068         /* TO */
3069         58,
3070 };
3071 static const unsigned int tpu4_to2_mux[] = {
3072         TPU4TO2_MARK,
3073 };
3074 static const unsigned int tpu4_to3_pins[] = {
3075         /* TO */
3076 };
3077 static const unsigned int tpu4_to3_mux[] = {
3078         TPU4TO3_MARK,
3079 };
3080 /* - USB -------------------------------------------------------------------- */
3081 static const unsigned int usb_vbus_pins[] = {
3082         /* VBUS */
3083         0,
3084 };
3085 static const unsigned int usb_vbus_mux[] = {
3086         VBUS_0_MARK,
3087 };
3088
3089 static const struct sh_pfc_pin_group pinmux_groups[] = {
3090         SH_PFC_PIN_GROUP(bsc_data_0_7),
3091         SH_PFC_PIN_GROUP(bsc_data_8_15),
3092         SH_PFC_PIN_GROUP(bsc_cs4),
3093         SH_PFC_PIN_GROUP(bsc_cs5_a),
3094         SH_PFC_PIN_GROUP(bsc_cs5_b),
3095         SH_PFC_PIN_GROUP(bsc_cs6_a),
3096         SH_PFC_PIN_GROUP(bsc_cs6_b),
3097         SH_PFC_PIN_GROUP(bsc_rd),
3098         SH_PFC_PIN_GROUP(bsc_rdwr_0),
3099         SH_PFC_PIN_GROUP(bsc_rdwr_1),
3100         SH_PFC_PIN_GROUP(bsc_rdwr_2),
3101         SH_PFC_PIN_GROUP(bsc_we0),
3102         SH_PFC_PIN_GROUP(bsc_we1),
3103         SH_PFC_PIN_GROUP(fsia_mclk_in),
3104         SH_PFC_PIN_GROUP(fsia_mclk_out),
3105         SH_PFC_PIN_GROUP(fsia_sclk_in),
3106         SH_PFC_PIN_GROUP(fsia_sclk_out),
3107         SH_PFC_PIN_GROUP(fsia_data_in),
3108         SH_PFC_PIN_GROUP(fsia_data_out),
3109         SH_PFC_PIN_GROUP(fsia_spdif),
3110         SH_PFC_PIN_GROUP(fsib_mclk_in),
3111         SH_PFC_PIN_GROUP(fsib_mclk_out),
3112         SH_PFC_PIN_GROUP(fsib_sclk_in),
3113         SH_PFC_PIN_GROUP(fsib_sclk_out),
3114         SH_PFC_PIN_GROUP(fsib_data_in),
3115         SH_PFC_PIN_GROUP(fsib_data_out),
3116         SH_PFC_PIN_GROUP(fsib_spdif),
3117         SH_PFC_PIN_GROUP(fsic_mclk_in),
3118         SH_PFC_PIN_GROUP(fsic_mclk_out),
3119         SH_PFC_PIN_GROUP(fsic_sclk_in),
3120         SH_PFC_PIN_GROUP(fsic_sclk_out),
3121         SH_PFC_PIN_GROUP(fsic_data_in),
3122         SH_PFC_PIN_GROUP(fsic_data_out),
3123         SH_PFC_PIN_GROUP(fsic_spdif_0),
3124         SH_PFC_PIN_GROUP(fsic_spdif_1),
3125         SH_PFC_PIN_GROUP(fsid_sclk_in),
3126         SH_PFC_PIN_GROUP(fsid_sclk_out),
3127         SH_PFC_PIN_GROUP(fsid_data_in),
3128         SH_PFC_PIN_GROUP(i2c2_0),
3129         SH_PFC_PIN_GROUP(i2c2_1),
3130         SH_PFC_PIN_GROUP(i2c2_2),
3131         SH_PFC_PIN_GROUP(i2c3_0),
3132         SH_PFC_PIN_GROUP(i2c3_1),
3133         SH_PFC_PIN_GROUP(i2c3_2),
3134         SH_PFC_PIN_GROUP(irda_0),
3135         SH_PFC_PIN_GROUP(irda_1),
3136         SH_PFC_PIN_GROUP(keysc_in5),
3137         SH_PFC_PIN_GROUP(keysc_in6),
3138         SH_PFC_PIN_GROUP(keysc_in7),
3139         SH_PFC_PIN_GROUP(keysc_in8),
3140         SH_PFC_PIN_GROUP(keysc_out04),
3141         SH_PFC_PIN_GROUP(keysc_out5),
3142         SH_PFC_PIN_GROUP(keysc_out6_0),
3143         SH_PFC_PIN_GROUP(keysc_out6_1),
3144         SH_PFC_PIN_GROUP(keysc_out6_2),
3145         SH_PFC_PIN_GROUP(keysc_out7_0),
3146         SH_PFC_PIN_GROUP(keysc_out7_1),
3147         SH_PFC_PIN_GROUP(keysc_out7_2),
3148         SH_PFC_PIN_GROUP(keysc_out8_0),
3149         SH_PFC_PIN_GROUP(keysc_out8_1),
3150         SH_PFC_PIN_GROUP(keysc_out8_2),
3151         SH_PFC_PIN_GROUP(keysc_out9_0),
3152         SH_PFC_PIN_GROUP(keysc_out9_1),
3153         SH_PFC_PIN_GROUP(keysc_out9_2),
3154         SH_PFC_PIN_GROUP(keysc_out10_0),
3155         SH_PFC_PIN_GROUP(keysc_out10_1),
3156         SH_PFC_PIN_GROUP(keysc_out11_0),
3157         SH_PFC_PIN_GROUP(keysc_out11_1),
3158         SH_PFC_PIN_GROUP(lcd_data8),
3159         SH_PFC_PIN_GROUP(lcd_data9),
3160         SH_PFC_PIN_GROUP(lcd_data12),
3161         SH_PFC_PIN_GROUP(lcd_data16),
3162         SH_PFC_PIN_GROUP(lcd_data18),
3163         SH_PFC_PIN_GROUP(lcd_data24),
3164         SH_PFC_PIN_GROUP(lcd_display),
3165         SH_PFC_PIN_GROUP(lcd_lclk),
3166         SH_PFC_PIN_GROUP(lcd_sync),
3167         SH_PFC_PIN_GROUP(lcd_sys),
3168         SH_PFC_PIN_GROUP(lcd2_data8),
3169         SH_PFC_PIN_GROUP(lcd2_data9),
3170         SH_PFC_PIN_GROUP(lcd2_data12),
3171         SH_PFC_PIN_GROUP(lcd2_data16),
3172         SH_PFC_PIN_GROUP(lcd2_data18),
3173         SH_PFC_PIN_GROUP(lcd2_data24),
3174         SH_PFC_PIN_GROUP(lcd2_sync_0),
3175         SH_PFC_PIN_GROUP(lcd2_sync_1),
3176         SH_PFC_PIN_GROUP(lcd2_sys_0),
3177         SH_PFC_PIN_GROUP(lcd2_sys_1),
3178         SH_PFC_PIN_GROUP(mmc0_data1_0),
3179         SH_PFC_PIN_GROUP(mmc0_data4_0),
3180         SH_PFC_PIN_GROUP(mmc0_data8_0),
3181         SH_PFC_PIN_GROUP(mmc0_ctrl_0),
3182         SH_PFC_PIN_GROUP(mmc0_data1_1),
3183         SH_PFC_PIN_GROUP(mmc0_data4_1),
3184         SH_PFC_PIN_GROUP(mmc0_data8_1),
3185         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
3186         SH_PFC_PIN_GROUP(msiof0_rsck),
3187         SH_PFC_PIN_GROUP(msiof0_tsck),
3188         SH_PFC_PIN_GROUP(msiof0_rsync),
3189         SH_PFC_PIN_GROUP(msiof0_tsync),
3190         SH_PFC_PIN_GROUP(msiof0_ss1),
3191         SH_PFC_PIN_GROUP(msiof0_ss2),
3192         SH_PFC_PIN_GROUP(msiof0_rxd),
3193         SH_PFC_PIN_GROUP(msiof0_txd),
3194         SH_PFC_PIN_GROUP(msiof0_mck0),
3195         SH_PFC_PIN_GROUP(msiof0_mck1),
3196         SH_PFC_PIN_GROUP(msiof0l_rsck),
3197         SH_PFC_PIN_GROUP(msiof0l_tsck),
3198         SH_PFC_PIN_GROUP(msiof0l_rsync),
3199         SH_PFC_PIN_GROUP(msiof0l_tsync),
3200         SH_PFC_PIN_GROUP(msiof0l_ss1_a),
3201         SH_PFC_PIN_GROUP(msiof0l_ss1_b),
3202         SH_PFC_PIN_GROUP(msiof0l_ss2_a),
3203         SH_PFC_PIN_GROUP(msiof0l_ss2_b),
3204         SH_PFC_PIN_GROUP(msiof0l_rxd),
3205         SH_PFC_PIN_GROUP(msiof0l_txd),
3206         SH_PFC_PIN_GROUP(msiof0l_mck0),
3207         SH_PFC_PIN_GROUP(msiof0l_mck1),
3208         SH_PFC_PIN_GROUP(msiof1_rsck),
3209         SH_PFC_PIN_GROUP(msiof1_tsck),
3210         SH_PFC_PIN_GROUP(msiof1_rsync),
3211         SH_PFC_PIN_GROUP(msiof1_tsync),
3212         SH_PFC_PIN_GROUP(msiof1_ss1),
3213         SH_PFC_PIN_GROUP(msiof1_ss2),
3214         SH_PFC_PIN_GROUP(msiof1_rxd),
3215         SH_PFC_PIN_GROUP(msiof1_txd),
3216         SH_PFC_PIN_GROUP(msiof1_mck0),
3217         SH_PFC_PIN_GROUP(msiof1_mck1),
3218         SH_PFC_PIN_GROUP(msiof2_rsck),
3219         SH_PFC_PIN_GROUP(msiof2_tsck),
3220         SH_PFC_PIN_GROUP(msiof2_rsync),
3221         SH_PFC_PIN_GROUP(msiof2_tsync),
3222         SH_PFC_PIN_GROUP(msiof2_ss1_a),
3223         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3224         SH_PFC_PIN_GROUP(msiof2_ss2_a),
3225         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3226         SH_PFC_PIN_GROUP(msiof2_rxd_a),
3227         SH_PFC_PIN_GROUP(msiof2_rxd_b),
3228         SH_PFC_PIN_GROUP(msiof2_txd),
3229         SH_PFC_PIN_GROUP(msiof2_mck0),
3230         SH_PFC_PIN_GROUP(msiof2_mck1),
3231         SH_PFC_PIN_GROUP(msiof2r_tsck),
3232         SH_PFC_PIN_GROUP(msiof2r_tsync),
3233         SH_PFC_PIN_GROUP(msiof2r_rxd),
3234         SH_PFC_PIN_GROUP(msiof2r_txd),
3235         SH_PFC_PIN_GROUP(msiof3_rsck),
3236         SH_PFC_PIN_GROUP(msiof3_tsck),
3237         SH_PFC_PIN_GROUP(msiof3_rsync),
3238         SH_PFC_PIN_GROUP(msiof3_tsync),
3239         SH_PFC_PIN_GROUP(msiof3_ss1),
3240         SH_PFC_PIN_GROUP(msiof3_ss2),
3241         SH_PFC_PIN_GROUP(msiof3_rxd),
3242         SH_PFC_PIN_GROUP(msiof3_txd),
3243         SH_PFC_PIN_GROUP(msiof3_flow),
3244         SH_PFC_PIN_GROUP(scifa0_data),
3245         SH_PFC_PIN_GROUP(scifa0_clk),
3246         SH_PFC_PIN_GROUP(scifa0_ctrl),
3247         SH_PFC_PIN_GROUP(scifa1_data),
3248         SH_PFC_PIN_GROUP(scifa1_clk),
3249         SH_PFC_PIN_GROUP(scifa1_ctrl),
3250         SH_PFC_PIN_GROUP(scifa2_data_0),
3251         SH_PFC_PIN_GROUP(scifa2_clk_0),
3252         SH_PFC_PIN_GROUP(scifa2_ctrl_0),
3253         SH_PFC_PIN_GROUP(scifa2_data_1),
3254         SH_PFC_PIN_GROUP(scifa2_clk_1),
3255         SH_PFC_PIN_GROUP(scifa2_ctrl_1),
3256         SH_PFC_PIN_GROUP(scifa3_data),
3257         SH_PFC_PIN_GROUP(scifa3_ctrl),
3258         SH_PFC_PIN_GROUP(scifa4_data),
3259         SH_PFC_PIN_GROUP(scifa4_ctrl),
3260         SH_PFC_PIN_GROUP(scifa5_data_0),
3261         SH_PFC_PIN_GROUP(scifa5_clk_0),
3262         SH_PFC_PIN_GROUP(scifa5_ctrl_0),
3263         SH_PFC_PIN_GROUP(scifa5_data_1),
3264         SH_PFC_PIN_GROUP(scifa5_clk_1),
3265         SH_PFC_PIN_GROUP(scifa5_ctrl_1),
3266         SH_PFC_PIN_GROUP(scifa5_data_2),
3267         SH_PFC_PIN_GROUP(scifa5_clk_2),
3268         SH_PFC_PIN_GROUP(scifa5_ctrl_2),
3269         SH_PFC_PIN_GROUP(scifa6),
3270         SH_PFC_PIN_GROUP(scifa7_data),
3271         SH_PFC_PIN_GROUP(scifa7_ctrl),
3272         SH_PFC_PIN_GROUP(scifb_data_0),
3273         SH_PFC_PIN_GROUP(scifb_clk_0),
3274         SH_PFC_PIN_GROUP(scifb_ctrl_0),
3275         SH_PFC_PIN_GROUP(scifb_data_1),
3276         SH_PFC_PIN_GROUP(scifb_clk_1),
3277         SH_PFC_PIN_GROUP(scifb_ctrl_1),
3278         SH_PFC_PIN_GROUP(sdhi0_data1),
3279         SH_PFC_PIN_GROUP(sdhi0_data4),
3280         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3281         SH_PFC_PIN_GROUP(sdhi0_cd),
3282         SH_PFC_PIN_GROUP(sdhi0_wp),
3283         SH_PFC_PIN_GROUP(sdhi1_data1),
3284         SH_PFC_PIN_GROUP(sdhi1_data4),
3285         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3286         SH_PFC_PIN_GROUP(sdhi2_data1),
3287         SH_PFC_PIN_GROUP(sdhi2_data4),
3288         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3289         SH_PFC_PIN_GROUP(tpu0_to0),
3290         SH_PFC_PIN_GROUP(tpu0_to1),
3291         SH_PFC_PIN_GROUP(tpu0_to2),
3292         SH_PFC_PIN_GROUP(tpu0_to3),
3293         SH_PFC_PIN_GROUP(tpu1_to0),
3294         SH_PFC_PIN_GROUP(tpu1_to1_0),
3295         SH_PFC_PIN_GROUP(tpu1_to1_1),
3296         SH_PFC_PIN_GROUP(tpu1_to2),
3297         SH_PFC_PIN_GROUP(tpu1_to3),
3298         SH_PFC_PIN_GROUP(tpu2_to0),
3299         SH_PFC_PIN_GROUP(tpu2_to1),
3300         SH_PFC_PIN_GROUP(tpu2_to2),
3301         SH_PFC_PIN_GROUP(tpu2_to3),
3302         SH_PFC_PIN_GROUP(tpu3_to0),
3303         SH_PFC_PIN_GROUP(tpu3_to1),
3304         SH_PFC_PIN_GROUP(tpu3_to2),
3305         SH_PFC_PIN_GROUP(tpu3_to3),
3306         SH_PFC_PIN_GROUP(tpu4_to0),
3307         SH_PFC_PIN_GROUP(tpu4_to1),
3308         SH_PFC_PIN_GROUP(tpu4_to2),
3309         SH_PFC_PIN_GROUP(tpu4_to3),
3310         SH_PFC_PIN_GROUP(usb_vbus),
3311 };
3312
3313 static const char * const bsc_groups[] = {
3314         "bsc_data_0_7",
3315         "bsc_data_8_15",
3316         "bsc_cs4",
3317         "bsc_cs5_a",
3318         "bsc_cs5_b",
3319         "bsc_cs6_a",
3320         "bsc_cs6_b",
3321         "bsc_rd",
3322         "bsc_rdwr_0",
3323         "bsc_rdwr_1",
3324         "bsc_rdwr_2",
3325         "bsc_we0",
3326         "bsc_we1",
3327 };
3328
3329 static const char * const fsia_groups[] = {
3330         "fsia_mclk_in",
3331         "fsia_mclk_out",
3332         "fsia_sclk_in",
3333         "fsia_sclk_out",
3334         "fsia_data_in",
3335         "fsia_data_out",
3336         "fsia_spdif",
3337 };
3338
3339 static const char * const fsib_groups[] = {
3340         "fsib_mclk_in",
3341         "fsib_mclk_out",
3342         "fsib_sclk_in",
3343         "fsib_sclk_out",
3344         "fsib_data_in",
3345         "fsib_data_out",
3346         "fsib_spdif",
3347 };
3348
3349 static const char * const fsic_groups[] = {
3350         "fsic_mclk_in",
3351         "fsic_mclk_out",
3352         "fsic_sclk_in",
3353         "fsic_sclk_out",
3354         "fsic_data_in",
3355         "fsic_data_out",
3356         "fsic_spdif",
3357 };
3358
3359 static const char * const fsid_groups[] = {
3360         "fsid_sclk_in",
3361         "fsid_sclk_out",
3362         "fsid_data_in",
3363 };
3364
3365 static const char * const i2c2_groups[] = {
3366         "i2c2_0",
3367         "i2c2_1",
3368         "i2c2_2",
3369 };
3370
3371 static const char * const i2c3_groups[] = {
3372         "i2c3_0",
3373         "i2c3_1",
3374         "i2c3_2",
3375 };
3376
3377 static const char * const irda_groups[] = {
3378         "irda_0",
3379         "irda_1",
3380 };
3381
3382 static const char * const keysc_groups[] = {
3383         "keysc_in5",
3384         "keysc_in6",
3385         "keysc_in7",
3386         "keysc_in8",
3387         "keysc_out04",
3388         "keysc_out5",
3389         "keysc_out6_0",
3390         "keysc_out6_1",
3391         "keysc_out6_2",
3392         "keysc_out7_0",
3393         "keysc_out7_1",
3394         "keysc_out7_2",
3395         "keysc_out8_0",
3396         "keysc_out8_1",
3397         "keysc_out8_2",
3398         "keysc_out9_0",
3399         "keysc_out9_1",
3400         "keysc_out9_2",
3401         "keysc_out10_0",
3402         "keysc_out10_1",
3403         "keysc_out11_0",
3404         "keysc_out11_1",
3405 };
3406
3407 static const char * const lcd_groups[] = {
3408         "lcd_data8",
3409         "lcd_data9",
3410         "lcd_data12",
3411         "lcd_data16",
3412         "lcd_data18",
3413         "lcd_data24",
3414         "lcd_display",
3415         "lcd_lclk",
3416         "lcd_sync",
3417         "lcd_sys",
3418 };
3419
3420 static const char * const lcd2_groups[] = {
3421         "lcd2_data8",
3422         "lcd2_data9",
3423         "lcd2_data12",
3424         "lcd2_data16",
3425         "lcd2_data18",
3426         "lcd2_data24",
3427         "lcd2_sync_0",
3428         "lcd2_sync_1",
3429         "lcd2_sys_0",
3430         "lcd2_sys_1",
3431 };
3432
3433 static const char * const mmc0_groups[] = {
3434         "mmc0_data1_0",
3435         "mmc0_data4_0",
3436         "mmc0_data8_0",
3437         "mmc0_ctrl_0",
3438         "mmc0_data1_1",
3439         "mmc0_data4_1",
3440         "mmc0_data8_1",
3441         "mmc0_ctrl_1",
3442 };
3443
3444 static const char * const msiof0_groups[] = {
3445         "msiof0_rsck",
3446         "msiof0_tsck",
3447         "msiof0_rsync",
3448         "msiof0_tsync",
3449         "msiof0_ss1",
3450         "msiof0_ss2",
3451         "msiof0_rxd",
3452         "msiof0_txd",
3453         "msiof0_mck0",
3454         "msiof0_mck1",
3455         "msiof0l_rsck",
3456         "msiof0l_tsck",
3457         "msiof0l_rsync",
3458         "msiof0l_tsync",
3459         "msiof0l_ss1_a",
3460         "msiof0l_ss1_b",
3461         "msiof0l_ss2_a",
3462         "msiof0l_ss2_b",
3463         "msiof0l_rxd",
3464         "msiof0l_txd",
3465         "msiof0l_mck0",
3466         "msiof0l_mck1",
3467 };
3468
3469 static const char * const msiof1_groups[] = {
3470         "msiof1_rsck",
3471         "msiof1_tsck",
3472         "msiof1_rsync",
3473         "msiof1_tsync",
3474         "msiof1_ss1",
3475         "msiof1_ss2",
3476         "msiof1_rxd",
3477         "msiof1_txd",
3478         "msiof1_mck0",
3479         "msiof1_mck1",
3480 };
3481
3482 static const char * const msiof2_groups[] = {
3483         "msiof2_rsck",
3484         "msiof2_tsck",
3485         "msiof2_rsync",
3486         "msiof2_tsync",
3487         "msiof2_ss1_a",
3488         "msiof2_ss1_b",
3489         "msiof2_ss2_a",
3490         "msiof2_ss2_b",
3491         "msiof2_rxd_a",
3492         "msiof2_rxd_b",
3493         "msiof2_txd",
3494         "msiof2_mck0",
3495         "msiof2_mck1",
3496         "msiof2r_tsck",
3497         "msiof2r_tsync",
3498         "msiof2r_rxd",
3499         "msiof2r_txd",
3500 };
3501
3502 static const char * const msiof3_groups[] = {
3503         "msiof3_rsck",
3504         "msiof3_tsck",
3505         "msiof3_rsync",
3506         "msiof3_tsync",
3507         "msiof3_ss1",
3508         "msiof3_ss2",
3509         "msiof3_rxd",
3510         "msiof3_txd",
3511         "msiof3_flow",
3512 };
3513
3514 static const char * const scifa0_groups[] = {
3515         "scifa0_data",
3516         "scifa0_clk",
3517         "scifa0_ctrl",
3518 };
3519
3520 static const char * const scifa1_groups[] = {
3521         "scifa1_data",
3522         "scifa1_clk",
3523         "scifa1_ctrl",
3524 };
3525
3526 static const char * const scifa2_groups[] = {
3527         "scifa2_data_0",
3528         "scifa2_clk_0",
3529         "scifa2_ctrl_0",
3530         "scifa2_data_1",
3531         "scifa2_clk_1",
3532         "scifa2_ctrl_1",
3533 };
3534
3535 static const char * const scifa3_groups[] = {
3536         "scifa3_data",
3537         "scifa3_ctrl",
3538 };
3539
3540 static const char * const scifa4_groups[] = {
3541         "scifa4_data",
3542         "scifa4_ctrl",
3543 };
3544
3545 static const char * const scifa5_groups[] = {
3546         "scifa5_data_0",
3547         "scifa5_clk_0",
3548         "scifa5_ctrl_0",
3549         "scifa5_data_1",
3550         "scifa5_clk_1",
3551         "scifa5_ctrl_1",
3552         "scifa5_data_2",
3553         "scifa5_clk_2",
3554         "scifa5_ctrl_2",
3555 };
3556
3557 static const char * const scifa6_groups[] = {
3558         "scifa6",
3559 };
3560
3561 static const char * const scifa7_groups[] = {
3562         "scifa7_data",
3563         "scifa7_ctrl",
3564 };
3565
3566 static const char * const scifb_groups[] = {
3567         "scifb_data_0",
3568         "scifb_clk_0",
3569         "scifb_ctrl_0",
3570         "scifb_data_1",
3571         "scifb_clk_1",
3572         "scifb_ctrl_1",
3573 };
3574
3575 static const char * const sdhi0_groups[] = {
3576         "sdhi0_data1",
3577         "sdhi0_data4",
3578         "sdhi0_ctrl",
3579         "sdhi0_cd",
3580         "sdhi0_wp",
3581 };
3582
3583 static const char * const sdhi1_groups[] = {
3584         "sdhi1_data1",
3585         "sdhi1_data4",
3586         "sdhi1_ctrl",
3587 };
3588
3589 static const char * const sdhi2_groups[] = {
3590         "sdhi2_data1",
3591         "sdhi2_data4",
3592         "sdhi2_ctrl",
3593 };
3594
3595 static const char * const usb_groups[] = {
3596         "usb_vbus",
3597 };
3598
3599 static const char * const tpu0_groups[] = {
3600         "tpu0_to0",
3601         "tpu0_to1",
3602         "tpu0_to2",
3603         "tpu0_to3",
3604 };
3605
3606 static const char * const tpu1_groups[] = {
3607         "tpu1_to0",
3608         "tpu1_to1_0",
3609         "tpu1_to1_1",
3610         "tpu1_to2",
3611         "tpu1_to3",
3612 };
3613
3614 static const char * const tpu2_groups[] = {
3615         "tpu2_to0",
3616         "tpu2_to1",
3617         "tpu2_to2",
3618         "tpu2_to3",
3619 };
3620
3621 static const char * const tpu3_groups[] = {
3622         "tpu3_to0",
3623         "tpu3_to1",
3624         "tpu3_to2",
3625         "tpu3_to3",
3626 };
3627
3628 static const char * const tpu4_groups[] = {
3629         "tpu4_to0",
3630         "tpu4_to1",
3631         "tpu4_to2",
3632         "tpu4_to3",
3633 };
3634
3635 static const struct sh_pfc_function pinmux_functions[] = {
3636         SH_PFC_FUNCTION(bsc),
3637         SH_PFC_FUNCTION(fsia),
3638         SH_PFC_FUNCTION(fsib),
3639         SH_PFC_FUNCTION(fsic),
3640         SH_PFC_FUNCTION(fsid),
3641         SH_PFC_FUNCTION(i2c2),
3642         SH_PFC_FUNCTION(i2c3),
3643         SH_PFC_FUNCTION(irda),
3644         SH_PFC_FUNCTION(keysc),
3645         SH_PFC_FUNCTION(lcd),
3646         SH_PFC_FUNCTION(lcd2),
3647         SH_PFC_FUNCTION(mmc0),
3648         SH_PFC_FUNCTION(msiof0),
3649         SH_PFC_FUNCTION(msiof1),
3650         SH_PFC_FUNCTION(msiof2),
3651         SH_PFC_FUNCTION(msiof3),
3652         SH_PFC_FUNCTION(scifa0),
3653         SH_PFC_FUNCTION(scifa1),
3654         SH_PFC_FUNCTION(scifa2),
3655         SH_PFC_FUNCTION(scifa3),
3656         SH_PFC_FUNCTION(scifa4),
3657         SH_PFC_FUNCTION(scifa5),
3658         SH_PFC_FUNCTION(scifa6),
3659         SH_PFC_FUNCTION(scifa7),
3660         SH_PFC_FUNCTION(scifb),
3661         SH_PFC_FUNCTION(sdhi0),
3662         SH_PFC_FUNCTION(sdhi1),
3663         SH_PFC_FUNCTION(sdhi2),
3664         SH_PFC_FUNCTION(tpu0),
3665         SH_PFC_FUNCTION(tpu1),
3666         SH_PFC_FUNCTION(tpu2),
3667         SH_PFC_FUNCTION(tpu3),
3668         SH_PFC_FUNCTION(tpu4),
3669         SH_PFC_FUNCTION(usb),
3670 };
3671
3672 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3673         PORTCR(0, 0xe6050000), /* PORT0CR */
3674         PORTCR(1, 0xe6050001), /* PORT1CR */
3675         PORTCR(2, 0xe6050002), /* PORT2CR */
3676         PORTCR(3, 0xe6050003), /* PORT3CR */
3677         PORTCR(4, 0xe6050004), /* PORT4CR */
3678         PORTCR(5, 0xe6050005), /* PORT5CR */
3679         PORTCR(6, 0xe6050006), /* PORT6CR */
3680         PORTCR(7, 0xe6050007), /* PORT7CR */
3681         PORTCR(8, 0xe6050008), /* PORT8CR */
3682         PORTCR(9, 0xe6050009), /* PORT9CR */
3683
3684         PORTCR(10, 0xe605000a), /* PORT10CR */
3685         PORTCR(11, 0xe605000b), /* PORT11CR */
3686         PORTCR(12, 0xe605000c), /* PORT12CR */
3687         PORTCR(13, 0xe605000d), /* PORT13CR */
3688         PORTCR(14, 0xe605000e), /* PORT14CR */
3689         PORTCR(15, 0xe605000f), /* PORT15CR */
3690         PORTCR(16, 0xe6050010), /* PORT16CR */
3691         PORTCR(17, 0xe6050011), /* PORT17CR */
3692         PORTCR(18, 0xe6050012), /* PORT18CR */
3693         PORTCR(19, 0xe6050013), /* PORT19CR */
3694
3695         PORTCR(20, 0xe6050014), /* PORT20CR */
3696         PORTCR(21, 0xe6050015), /* PORT21CR */
3697         PORTCR(22, 0xe6050016), /* PORT22CR */
3698         PORTCR(23, 0xe6050017), /* PORT23CR */
3699         PORTCR(24, 0xe6050018), /* PORT24CR */
3700         PORTCR(25, 0xe6050019), /* PORT25CR */
3701         PORTCR(26, 0xe605001a), /* PORT26CR */
3702         PORTCR(27, 0xe605001b), /* PORT27CR */
3703         PORTCR(28, 0xe605001c), /* PORT28CR */
3704         PORTCR(29, 0xe605001d), /* PORT29CR */
3705
3706         PORTCR(30, 0xe605001e), /* PORT30CR */
3707         PORTCR(31, 0xe605001f), /* PORT31CR */
3708         PORTCR(32, 0xe6051020), /* PORT32CR */
3709         PORTCR(33, 0xe6051021), /* PORT33CR */
3710         PORTCR(34, 0xe6051022), /* PORT34CR */
3711         PORTCR(35, 0xe6051023), /* PORT35CR */
3712         PORTCR(36, 0xe6051024), /* PORT36CR */
3713         PORTCR(37, 0xe6051025), /* PORT37CR */
3714         PORTCR(38, 0xe6051026), /* PORT38CR */
3715         PORTCR(39, 0xe6051027), /* PORT39CR */
3716
3717         PORTCR(40, 0xe6051028), /* PORT40CR */
3718         PORTCR(41, 0xe6051029), /* PORT41CR */
3719         PORTCR(42, 0xe605102a), /* PORT42CR */
3720         PORTCR(43, 0xe605102b), /* PORT43CR */
3721         PORTCR(44, 0xe605102c), /* PORT44CR */
3722         PORTCR(45, 0xe605102d), /* PORT45CR */
3723         PORTCR(46, 0xe605102e), /* PORT46CR */
3724         PORTCR(47, 0xe605102f), /* PORT47CR */
3725         PORTCR(48, 0xe6051030), /* PORT48CR */
3726         PORTCR(49, 0xe6051031), /* PORT49CR */
3727
3728         PORTCR(50, 0xe6051032), /* PORT50CR */
3729         PORTCR(51, 0xe6051033), /* PORT51CR */
3730         PORTCR(52, 0xe6051034), /* PORT52CR */
3731         PORTCR(53, 0xe6051035), /* PORT53CR */
3732         PORTCR(54, 0xe6051036), /* PORT54CR */
3733         PORTCR(55, 0xe6051037), /* PORT55CR */
3734         PORTCR(56, 0xe6051038), /* PORT56CR */
3735         PORTCR(57, 0xe6051039), /* PORT57CR */
3736         PORTCR(58, 0xe605103a), /* PORT58CR */
3737         PORTCR(59, 0xe605103b), /* PORT59CR */
3738
3739         PORTCR(60, 0xe605103c), /* PORT60CR */
3740         PORTCR(61, 0xe605103d), /* PORT61CR */
3741         PORTCR(62, 0xe605103e), /* PORT62CR */
3742         PORTCR(63, 0xe605103f), /* PORT63CR */
3743         PORTCR(64, 0xe6051040), /* PORT64CR */
3744         PORTCR(65, 0xe6051041), /* PORT65CR */
3745         PORTCR(66, 0xe6051042), /* PORT66CR */
3746         PORTCR(67, 0xe6051043), /* PORT67CR */
3747         PORTCR(68, 0xe6051044), /* PORT68CR */
3748         PORTCR(69, 0xe6051045), /* PORT69CR */
3749
3750         PORTCR(70, 0xe6051046), /* PORT70CR */
3751         PORTCR(71, 0xe6051047), /* PORT71CR */
3752         PORTCR(72, 0xe6051048), /* PORT72CR */
3753         PORTCR(73, 0xe6051049), /* PORT73CR */
3754         PORTCR(74, 0xe605104a), /* PORT74CR */
3755         PORTCR(75, 0xe605104b), /* PORT75CR */
3756         PORTCR(76, 0xe605104c), /* PORT76CR */
3757         PORTCR(77, 0xe605104d), /* PORT77CR */
3758         PORTCR(78, 0xe605104e), /* PORT78CR */
3759         PORTCR(79, 0xe605104f), /* PORT79CR */
3760
3761         PORTCR(80, 0xe6051050), /* PORT80CR */
3762         PORTCR(81, 0xe6051051), /* PORT81CR */
3763         PORTCR(82, 0xe6051052), /* PORT82CR */
3764         PORTCR(83, 0xe6051053), /* PORT83CR */
3765         PORTCR(84, 0xe6051054), /* PORT84CR */
3766         PORTCR(85, 0xe6051055), /* PORT85CR */
3767         PORTCR(86, 0xe6051056), /* PORT86CR */
3768         PORTCR(87, 0xe6051057), /* PORT87CR */
3769         PORTCR(88, 0xe6051058), /* PORT88CR */
3770         PORTCR(89, 0xe6051059), /* PORT89CR */
3771
3772         PORTCR(90, 0xe605105a), /* PORT90CR */
3773         PORTCR(91, 0xe605105b), /* PORT91CR */
3774         PORTCR(92, 0xe605105c), /* PORT92CR */
3775         PORTCR(93, 0xe605105d), /* PORT93CR */
3776         PORTCR(94, 0xe605105e), /* PORT94CR */
3777         PORTCR(95, 0xe605105f), /* PORT95CR */
3778         PORTCR(96, 0xe6052060), /* PORT96CR */
3779         PORTCR(97, 0xe6052061), /* PORT97CR */
3780         PORTCR(98, 0xe6052062), /* PORT98CR */
3781         PORTCR(99, 0xe6052063), /* PORT99CR */
3782
3783         PORTCR(100, 0xe6052064), /* PORT100CR */
3784         PORTCR(101, 0xe6052065), /* PORT101CR */
3785         PORTCR(102, 0xe6052066), /* PORT102CR */
3786         PORTCR(103, 0xe6052067), /* PORT103CR */
3787         PORTCR(104, 0xe6052068), /* PORT104CR */
3788         PORTCR(105, 0xe6052069), /* PORT105CR */
3789         PORTCR(106, 0xe605206a), /* PORT106CR */
3790         PORTCR(107, 0xe605206b), /* PORT107CR */
3791         PORTCR(108, 0xe605206c), /* PORT108CR */
3792         PORTCR(109, 0xe605206d), /* PORT109CR */
3793
3794         PORTCR(110, 0xe605206e), /* PORT110CR */
3795         PORTCR(111, 0xe605206f), /* PORT111CR */
3796         PORTCR(112, 0xe6052070), /* PORT112CR */
3797         PORTCR(113, 0xe6052071), /* PORT113CR */
3798         PORTCR(114, 0xe6052072), /* PORT114CR */
3799         PORTCR(115, 0xe6052073), /* PORT115CR */
3800         PORTCR(116, 0xe6052074), /* PORT116CR */
3801         PORTCR(117, 0xe6052075), /* PORT117CR */
3802         PORTCR(118, 0xe6052076), /* PORT118CR */
3803
3804         PORTCR(128, 0xe6052080), /* PORT128CR */
3805         PORTCR(129, 0xe6052081), /* PORT129CR */
3806
3807         PORTCR(130, 0xe6052082), /* PORT130CR */
3808         PORTCR(131, 0xe6052083), /* PORT131CR */
3809         PORTCR(132, 0xe6052084), /* PORT132CR */
3810         PORTCR(133, 0xe6052085), /* PORT133CR */
3811         PORTCR(134, 0xe6052086), /* PORT134CR */
3812         PORTCR(135, 0xe6052087), /* PORT135CR */
3813         PORTCR(136, 0xe6052088), /* PORT136CR */
3814         PORTCR(137, 0xe6052089), /* PORT137CR */
3815         PORTCR(138, 0xe605208a), /* PORT138CR */
3816         PORTCR(139, 0xe605208b), /* PORT139CR */
3817
3818         PORTCR(140, 0xe605208c), /* PORT140CR */
3819         PORTCR(141, 0xe605208d), /* PORT141CR */
3820         PORTCR(142, 0xe605208e), /* PORT142CR */
3821         PORTCR(143, 0xe605208f), /* PORT143CR */
3822         PORTCR(144, 0xe6052090), /* PORT144CR */
3823         PORTCR(145, 0xe6052091), /* PORT145CR */
3824         PORTCR(146, 0xe6052092), /* PORT146CR */
3825         PORTCR(147, 0xe6052093), /* PORT147CR */
3826         PORTCR(148, 0xe6052094), /* PORT148CR */
3827         PORTCR(149, 0xe6052095), /* PORT149CR */
3828
3829         PORTCR(150, 0xe6052096), /* PORT150CR */
3830         PORTCR(151, 0xe6052097), /* PORT151CR */
3831         PORTCR(152, 0xe6052098), /* PORT152CR */
3832         PORTCR(153, 0xe6052099), /* PORT153CR */
3833         PORTCR(154, 0xe605209a), /* PORT154CR */
3834         PORTCR(155, 0xe605209b), /* PORT155CR */
3835         PORTCR(156, 0xe605209c), /* PORT156CR */
3836         PORTCR(157, 0xe605209d), /* PORT157CR */
3837         PORTCR(158, 0xe605209e), /* PORT158CR */
3838         PORTCR(159, 0xe605209f), /* PORT159CR */
3839
3840         PORTCR(160, 0xe60520a0), /* PORT160CR */
3841         PORTCR(161, 0xe60520a1), /* PORT161CR */
3842         PORTCR(162, 0xe60520a2), /* PORT162CR */
3843         PORTCR(163, 0xe60520a3), /* PORT163CR */
3844         PORTCR(164, 0xe60520a4), /* PORT164CR */
3845
3846         PORTCR(192, 0xe60520c0), /* PORT192CR */
3847         PORTCR(193, 0xe60520c1), /* PORT193CR */
3848         PORTCR(194, 0xe60520c2), /* PORT194CR */
3849         PORTCR(195, 0xe60520c3), /* PORT195CR */
3850         PORTCR(196, 0xe60520c4), /* PORT196CR */
3851         PORTCR(197, 0xe60520c5), /* PORT197CR */
3852         PORTCR(198, 0xe60520c6), /* PORT198CR */
3853         PORTCR(199, 0xe60520c7), /* PORT199CR */
3854
3855         PORTCR(200, 0xe60520c8), /* PORT200CR */
3856         PORTCR(201, 0xe60520c9), /* PORT201CR */
3857         PORTCR(202, 0xe60520ca), /* PORT202CR */
3858         PORTCR(203, 0xe60520cb), /* PORT203CR */
3859         PORTCR(204, 0xe60520cc), /* PORT204CR */
3860         PORTCR(205, 0xe60520cd), /* PORT205CR */
3861         PORTCR(206, 0xe60520ce), /* PORT206CR */
3862         PORTCR(207, 0xe60520cf), /* PORT207CR */
3863         PORTCR(208, 0xe60520d0), /* PORT208CR */
3864         PORTCR(209, 0xe60520d1), /* PORT209CR */
3865
3866         PORTCR(210, 0xe60520d2), /* PORT210CR */
3867         PORTCR(211, 0xe60520d3), /* PORT211CR */
3868         PORTCR(212, 0xe60520d4), /* PORT212CR */
3869         PORTCR(213, 0xe60520d5), /* PORT213CR */
3870         PORTCR(214, 0xe60520d6), /* PORT214CR */
3871         PORTCR(215, 0xe60520d7), /* PORT215CR */
3872         PORTCR(216, 0xe60520d8), /* PORT216CR */
3873         PORTCR(217, 0xe60520d9), /* PORT217CR */
3874         PORTCR(218, 0xe60520da), /* PORT218CR */
3875         PORTCR(219, 0xe60520db), /* PORT219CR */
3876
3877         PORTCR(220, 0xe60520dc), /* PORT220CR */
3878         PORTCR(221, 0xe60520dd), /* PORT221CR */
3879         PORTCR(222, 0xe60520de), /* PORT222CR */
3880         PORTCR(223, 0xe60520df), /* PORT223CR */
3881         PORTCR(224, 0xe60530e0), /* PORT224CR */
3882         PORTCR(225, 0xe60530e1), /* PORT225CR */
3883         PORTCR(226, 0xe60530e2), /* PORT226CR */
3884         PORTCR(227, 0xe60530e3), /* PORT227CR */
3885         PORTCR(228, 0xe60530e4), /* PORT228CR */
3886         PORTCR(229, 0xe60530e5), /* PORT229CR */
3887
3888         PORTCR(230, 0xe60530e6), /* PORT230CR */
3889         PORTCR(231, 0xe60530e7), /* PORT231CR */
3890         PORTCR(232, 0xe60530e8), /* PORT232CR */
3891         PORTCR(233, 0xe60530e9), /* PORT233CR */
3892         PORTCR(234, 0xe60530ea), /* PORT234CR */
3893         PORTCR(235, 0xe60530eb), /* PORT235CR */
3894         PORTCR(236, 0xe60530ec), /* PORT236CR */
3895         PORTCR(237, 0xe60530ed), /* PORT237CR */
3896         PORTCR(238, 0xe60530ee), /* PORT238CR */
3897         PORTCR(239, 0xe60530ef), /* PORT239CR */
3898
3899         PORTCR(240, 0xe60530f0), /* PORT240CR */
3900         PORTCR(241, 0xe60530f1), /* PORT241CR */
3901         PORTCR(242, 0xe60530f2), /* PORT242CR */
3902         PORTCR(243, 0xe60530f3), /* PORT243CR */
3903         PORTCR(244, 0xe60530f4), /* PORT244CR */
3904         PORTCR(245, 0xe60530f5), /* PORT245CR */
3905         PORTCR(246, 0xe60530f6), /* PORT246CR */
3906         PORTCR(247, 0xe60530f7), /* PORT247CR */
3907         PORTCR(248, 0xe60530f8), /* PORT248CR */
3908         PORTCR(249, 0xe60530f9), /* PORT249CR */
3909
3910         PORTCR(250, 0xe60530fa), /* PORT250CR */
3911         PORTCR(251, 0xe60530fb), /* PORT251CR */
3912         PORTCR(252, 0xe60530fc), /* PORT252CR */
3913         PORTCR(253, 0xe60530fd), /* PORT253CR */
3914         PORTCR(254, 0xe60530fe), /* PORT254CR */
3915         PORTCR(255, 0xe60530ff), /* PORT255CR */
3916         PORTCR(256, 0xe6053100), /* PORT256CR */
3917         PORTCR(257, 0xe6053101), /* PORT257CR */
3918         PORTCR(258, 0xe6053102), /* PORT258CR */
3919         PORTCR(259, 0xe6053103), /* PORT259CR */
3920
3921         PORTCR(260, 0xe6053104), /* PORT260CR */
3922         PORTCR(261, 0xe6053105), /* PORT261CR */
3923         PORTCR(262, 0xe6053106), /* PORT262CR */
3924         PORTCR(263, 0xe6053107), /* PORT263CR */
3925         PORTCR(264, 0xe6053108), /* PORT264CR */
3926         PORTCR(265, 0xe6053109), /* PORT265CR */
3927         PORTCR(266, 0xe605310a), /* PORT266CR */
3928         PORTCR(267, 0xe605310b), /* PORT267CR */
3929         PORTCR(268, 0xe605310c), /* PORT268CR */
3930         PORTCR(269, 0xe605310d), /* PORT269CR */
3931
3932         PORTCR(270, 0xe605310e), /* PORT270CR */
3933         PORTCR(271, 0xe605310f), /* PORT271CR */
3934         PORTCR(272, 0xe6053110), /* PORT272CR */
3935         PORTCR(273, 0xe6053111), /* PORT273CR */
3936         PORTCR(274, 0xe6053112), /* PORT274CR */
3937         PORTCR(275, 0xe6053113), /* PORT275CR */
3938         PORTCR(276, 0xe6053114), /* PORT276CR */
3939         PORTCR(277, 0xe6053115), /* PORT277CR */
3940         PORTCR(278, 0xe6053116), /* PORT278CR */
3941         PORTCR(279, 0xe6053117), /* PORT279CR */
3942
3943         PORTCR(280, 0xe6053118), /* PORT280CR */
3944         PORTCR(281, 0xe6053119), /* PORT281CR */
3945         PORTCR(282, 0xe605311a), /* PORT282CR */
3946
3947         PORTCR(288, 0xe6052120), /* PORT288CR */
3948         PORTCR(289, 0xe6052121), /* PORT289CR */
3949
3950         PORTCR(290, 0xe6052122), /* PORT290CR */
3951         PORTCR(291, 0xe6052123), /* PORT291CR */
3952         PORTCR(292, 0xe6052124), /* PORT292CR */
3953         PORTCR(293, 0xe6052125), /* PORT293CR */
3954         PORTCR(294, 0xe6052126), /* PORT294CR */
3955         PORTCR(295, 0xe6052127), /* PORT295CR */
3956         PORTCR(296, 0xe6052128), /* PORT296CR */
3957         PORTCR(297, 0xe6052129), /* PORT297CR */
3958         PORTCR(298, 0xe605212a), /* PORT298CR */
3959         PORTCR(299, 0xe605212b), /* PORT299CR */
3960
3961         PORTCR(300, 0xe605212c), /* PORT300CR */
3962         PORTCR(301, 0xe605212d), /* PORT301CR */
3963         PORTCR(302, 0xe605212e), /* PORT302CR */
3964         PORTCR(303, 0xe605212f), /* PORT303CR */
3965         PORTCR(304, 0xe6052130), /* PORT304CR */
3966         PORTCR(305, 0xe6052131), /* PORT305CR */
3967         PORTCR(306, 0xe6052132), /* PORT306CR */
3968         PORTCR(307, 0xe6052133), /* PORT307CR */
3969         PORTCR(308, 0xe6052134), /* PORT308CR */
3970         PORTCR(309, 0xe6052135), /* PORT309CR */
3971
3972         { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
3973                         0, 0,
3974                         0, 0,
3975                         0, 0,
3976                         0, 0,
3977                         0, 0,
3978                         0, 0,
3979                         0, 0,
3980                         0, 0,
3981                         0, 0,
3982                         0, 0,
3983                         0, 0,
3984                         0, 0,
3985                         MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
3986                         MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
3987                         MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
3988                         MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
3989                         0, 0,
3990                         MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
3991                         MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
3992                         MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
3993                         MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
3994                         MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
3995                         MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
3996                         MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
3997                         MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
3998                         MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
3999                         MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
4000                         MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
4001                         MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
4002                         MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
4003                         MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
4004                         MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
4005                 }
4006         },
4007         { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
4008                         0, 0,
4009                         0, 0,
4010                         0, 0,
4011                         MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
4012                         0, 0,
4013                         0, 0,
4014                         0, 0,
4015                         0, 0,
4016                         0, 0,
4017                         0, 0,
4018                         0, 0,
4019                         0, 0,
4020                         0, 0,
4021                         0, 0,
4022                         0, 0,
4023                         0, 0,
4024                         MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
4025                         0, 0,
4026                         0, 0,
4027                         0, 0,
4028                         MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
4029                         0, 0,
4030                         MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
4031                         0, 0,
4032                         0, 0,
4033                         MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
4034                         0, 0,
4035                         0, 0,
4036                         0, 0,
4037                         MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
4038                         0, 0,
4039                         0, 0,
4040                 }
4041         },
4042         { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
4043                         0, 0,
4044                         0, 0,
4045                         MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
4046                         0, 0,
4047                         MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
4048                         MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
4049                         0, 0,
4050                         0, 0,
4051                         0, 0,
4052                         MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
4053                         MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
4054                         MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
4055                         MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
4056                         0, 0,
4057                         0, 0,
4058                         0, 0,
4059                         MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
4060                         0, 0,
4061                         MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
4062                         MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
4063                         MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
4064                         MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
4065                         MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
4066                         MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
4067                         MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
4068                         0, 0,
4069                         0, 0,
4070                         MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
4071                         0, 0,
4072                         0, 0,
4073                         MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
4074                         0, 0,
4075                 }
4076         },
4077         { },
4078 };
4079
4080 static const struct pinmux_data_reg pinmux_data_regs[] = {
4081         { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
4082                         PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
4083                         PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
4084                         PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
4085                         PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
4086                         PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
4087                         PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
4088                         PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
4089                         PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
4090         },
4091         { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
4092                         PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
4093                         PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
4094                         PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
4095                         PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
4096                         PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
4097                         PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
4098                         PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
4099                         PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
4100         },
4101         { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
4102                         PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
4103                         PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
4104                         PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
4105                         PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
4106                         PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
4107                         PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
4108                         PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
4109                         PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
4110         },
4111         { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
4112                         0, 0, 0, 0,
4113                         0, 0, 0, 0,
4114                         0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
4115                         PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
4116                         PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
4117                         PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
4118                         PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
4119                         PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
4120         },
4121         { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
4122                         PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
4123                         PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
4124                         PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
4125                         PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
4126                         PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
4127                         PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
4128                         PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
4129                         PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
4130         },
4131         { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
4132                         0, 0, 0, 0,
4133                         0, 0, 0, 0,
4134                         0, 0, 0, 0,
4135                         0, 0, 0, 0,
4136                         0, 0, 0, 0,
4137                         0, 0, 0, 0,
4138                         0, 0, 0, PORT164_DATA,
4139                         PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
4140         },
4141         { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
4142                         PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
4143                         PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
4144                         PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
4145                         PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
4146                         PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
4147                         PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
4148                         PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
4149                         PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
4150         },
4151         { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
4152                         PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
4153                         PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
4154                         PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
4155                         PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
4156                         PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
4157                         PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
4158                         PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
4159                         PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
4160         },
4161         { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
4162                         0, 0, 0, 0,
4163                         0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
4164                         PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
4165                         PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
4166                         PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
4167                         PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
4168                         PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
4169                         PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
4170         },
4171         { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
4172                         0, 0, 0, 0,
4173                         0, 0, 0, 0,
4174                         0, 0, PORT309_DATA, PORT308_DATA,
4175                         PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
4176                         PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
4177                         PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
4178                         PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
4179                         PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
4180         },
4181         { },
4182 };
4183
4184 static const struct pinmux_irq pinmux_irqs[] = {
4185         PINMUX_IRQ(11),         /* IRQ0 */
4186         PINMUX_IRQ(10),         /* IRQ1 */
4187         PINMUX_IRQ(149),        /* IRQ2 */
4188         PINMUX_IRQ(224),        /* IRQ3 */
4189         PINMUX_IRQ(159),        /* IRQ4 */
4190         PINMUX_IRQ(227),        /* IRQ5 */
4191         PINMUX_IRQ(147),        /* IRQ6 */
4192         PINMUX_IRQ(150),        /* IRQ7 */
4193         PINMUX_IRQ(223),        /* IRQ8 */
4194         PINMUX_IRQ(56, 308),    /* IRQ9 */
4195         PINMUX_IRQ(54),         /* IRQ10 */
4196         PINMUX_IRQ(238),        /* IRQ11 */
4197         PINMUX_IRQ(156),        /* IRQ12 */
4198         PINMUX_IRQ(239),        /* IRQ13 */
4199         PINMUX_IRQ(251),        /* IRQ14 */
4200         PINMUX_IRQ(0),          /* IRQ15 */
4201         PINMUX_IRQ(249),        /* IRQ16 */
4202         PINMUX_IRQ(234),        /* IRQ17 */
4203         PINMUX_IRQ(13),         /* IRQ18 */
4204         PINMUX_IRQ(9),          /* IRQ19 */
4205         PINMUX_IRQ(14),         /* IRQ20 */
4206         PINMUX_IRQ(15),         /* IRQ21 */
4207         PINMUX_IRQ(40),         /* IRQ22 */
4208         PINMUX_IRQ(53),         /* IRQ23 */
4209         PINMUX_IRQ(118),        /* IRQ24 */
4210         PINMUX_IRQ(164),        /* IRQ25 */
4211         PINMUX_IRQ(115),        /* IRQ26 */
4212         PINMUX_IRQ(116),        /* IRQ27 */
4213         PINMUX_IRQ(117),        /* IRQ28 */
4214         PINMUX_IRQ(28),         /* IRQ29 */
4215         PINMUX_IRQ(27),         /* IRQ30 */
4216         PINMUX_IRQ(26),         /* IRQ31 */
4217 };
4218
4219 /* -----------------------------------------------------------------------------
4220  * VCCQ MC0 regulator
4221  */
4222
4223 static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
4224 {
4225         struct sh_pfc *pfc = reg->reg_data;
4226         void __iomem *addr = pfc->windows[1].virt + 4;
4227         unsigned long flags;
4228         u32 value;
4229
4230         spin_lock_irqsave(&pfc->lock, flags);
4231
4232         value = ioread32(addr);
4233
4234         if (enable)
4235                 value |= BIT(28);
4236         else
4237                 value &= ~BIT(28);
4238
4239         iowrite32(value, addr);
4240
4241         spin_unlock_irqrestore(&pfc->lock, flags);
4242 }
4243
4244 static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
4245 {
4246         sh73a0_vccq_mc0_endisable(reg, true);
4247         return 0;
4248 }
4249
4250 static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
4251 {
4252         sh73a0_vccq_mc0_endisable(reg, false);
4253         return 0;
4254 }
4255
4256 static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
4257 {
4258         struct sh_pfc *pfc = reg->reg_data;
4259         void __iomem *addr = pfc->windows[1].virt + 4;
4260         unsigned long flags;
4261         u32 value;
4262
4263         spin_lock_irqsave(&pfc->lock, flags);
4264         value = ioread32(addr);
4265         spin_unlock_irqrestore(&pfc->lock, flags);
4266
4267         return !!(value & BIT(28));
4268 }
4269
4270 static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
4271 {
4272         return 3300000;
4273 }
4274
4275 static struct regulator_ops sh73a0_vccq_mc0_ops = {
4276         .enable = sh73a0_vccq_mc0_enable,
4277         .disable = sh73a0_vccq_mc0_disable,
4278         .is_enabled = sh73a0_vccq_mc0_is_enabled,
4279         .get_voltage = sh73a0_vccq_mc0_get_voltage,
4280 };
4281
4282 static const struct regulator_desc sh73a0_vccq_mc0_desc = {
4283         .owner = THIS_MODULE,
4284         .name = "vccq_mc0",
4285         .type = REGULATOR_VOLTAGE,
4286         .ops = &sh73a0_vccq_mc0_ops,
4287 };
4288
4289 static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
4290         REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
4291         REGULATOR_SUPPLY("vqmmc", "ee100000.sdhi"),
4292 };
4293
4294 static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
4295         .constraints = {
4296                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
4297         },
4298         .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
4299         .consumer_supplies = sh73a0_vccq_mc0_consumers,
4300 };
4301
4302 /* -----------------------------------------------------------------------------
4303  * Pin bias
4304  */
4305
4306 #define PORTnCR_PULMD_OFF       (0 << 6)
4307 #define PORTnCR_PULMD_DOWN      (2 << 6)
4308 #define PORTnCR_PULMD_UP        (3 << 6)
4309 #define PORTnCR_PULMD_MASK      (3 << 6)
4310
4311 static const unsigned int sh73a0_portcr_offsets[] = {
4312         0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
4313         0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
4314 };
4315
4316 static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
4317 {
4318         void __iomem *addr = pfc->windows->virt
4319                            + sh73a0_portcr_offsets[pin >> 5] + pin;
4320         u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
4321
4322         switch (value) {
4323         case PORTnCR_PULMD_UP:
4324                 return PIN_CONFIG_BIAS_PULL_UP;
4325         case PORTnCR_PULMD_DOWN:
4326                 return PIN_CONFIG_BIAS_PULL_DOWN;
4327         case PORTnCR_PULMD_OFF:
4328         default:
4329                 return PIN_CONFIG_BIAS_DISABLE;
4330         }
4331 }
4332
4333 static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
4334                                    unsigned int bias)
4335 {
4336         void __iomem *addr = pfc->windows->virt
4337                            + sh73a0_portcr_offsets[pin >> 5] + pin;
4338         u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
4339
4340         switch (bias) {
4341         case PIN_CONFIG_BIAS_PULL_UP:
4342                 value |= PORTnCR_PULMD_UP;
4343                 break;
4344         case PIN_CONFIG_BIAS_PULL_DOWN:
4345                 value |= PORTnCR_PULMD_DOWN;
4346                 break;
4347         }
4348
4349         iowrite8(value, addr);
4350 }
4351
4352 /* -----------------------------------------------------------------------------
4353  * SoC information
4354  */
4355
4356 static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
4357 {
4358         struct regulator_config cfg = { };
4359         struct regulator_dev *vccq;
4360         int ret;
4361
4362         cfg.dev = pfc->dev;
4363         cfg.init_data = &sh73a0_vccq_mc0_init_data;
4364         cfg.driver_data = pfc;
4365
4366         vccq = devm_regulator_register(pfc->dev, &sh73a0_vccq_mc0_desc, &cfg);
4367         if (IS_ERR(vccq)) {
4368                 ret = PTR_ERR(vccq);
4369                 dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
4370                         ret);
4371                 return ret;
4372         }
4373
4374         return 0;
4375 }
4376
4377 static const struct sh_pfc_soc_operations sh73a0_pfc_ops = {
4378         .init = sh73a0_pinmux_soc_init,
4379         .get_bias = sh73a0_pinmux_get_bias,
4380         .set_bias = sh73a0_pinmux_set_bias,
4381 };
4382
4383 const struct sh_pfc_soc_info sh73a0_pinmux_info = {
4384         .name = "sh73a0_pfc",
4385         .ops = &sh73a0_pfc_ops,
4386
4387         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
4388         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
4389         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4390
4391         .pins = pinmux_pins,
4392         .nr_pins = ARRAY_SIZE(pinmux_pins),
4393         .groups = pinmux_groups,
4394         .nr_groups = ARRAY_SIZE(pinmux_groups),
4395         .functions = pinmux_functions,
4396         .nr_functions = ARRAY_SIZE(pinmux_functions),
4397
4398         .cfg_regs = pinmux_config_regs,
4399         .data_regs = pinmux_data_regs,
4400
4401         .pinmux_data = pinmux_data,
4402         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
4403
4404         .gpio_irq = pinmux_irqs,
4405         .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
4406 };