drivers/pinctrl/sh-pfc/sh_pfc.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * SuperH Pin Function Controller Support
   4  *
   5  * Copyright (c) 2008 Magnus Damm
   6  */
   7
   8 #ifndef __SH_PFC_H
   9 #define __SH_PFC_H
  10
  11 #include <linux/bug.h>
  12 #include <linux/pinctrl/pinconf-generic.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/stringify.h>
  15
  16 enum {
  17         PINMUX_TYPE_NONE,
  18         PINMUX_TYPE_FUNCTION,
  19         PINMUX_TYPE_GPIO,
  20         PINMUX_TYPE_OUTPUT,
  21         PINMUX_TYPE_INPUT,
  22 };
  23
  24 #define SH_PFC_PIN_CFG_INPUT            (1 << 0)
  25 #define SH_PFC_PIN_CFG_OUTPUT           (1 << 1)
  26 #define SH_PFC_PIN_CFG_PULL_UP          (1 << 2)
  27 #define SH_PFC_PIN_CFG_PULL_DOWN        (1 << 3)
  28 #define SH_PFC_PIN_CFG_IO_VOLTAGE       (1 << 4)
  29 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH   (1 << 5)
  30 #define SH_PFC_PIN_CFG_NO_GPIO          (1 << 31)
  31
  32 struct sh_pfc_pin {
  33         u16 pin;
  34         u16 enum_id;
  35         const char *name;
  36         unsigned int configs;
  37 };
  38
  39 #define SH_PFC_PIN_GROUP_ALIAS(alias, n)                \
  40         {                                               \
  41                 .name = #alias,                         \
  42                 .pins = n##_pins,                       \
  43                 .mux = n##_mux,                         \
  44                 .nr_pins = ARRAY_SIZE(n##_pins) +       \
  45                 BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
  46         }
  47 #define SH_PFC_PIN_GROUP(n)     SH_PFC_PIN_GROUP_ALIAS(n, n)
  48
  49 struct sh_pfc_pin_group {
  50         const char *name;
  51         const unsigned int *pins;
  52         const unsigned int *mux;
  53         unsigned int nr_pins;
  54 };
  55
  56 /*
  57  * Using union vin_data{,12,16} saves memory occupied by the VIN data pins.
  58  * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
  59  * in this case. It accepts an optional 'version' argument used when the
  60  * same group can appear on a different set of pins.
  61  */
  62 #define VIN_DATA_PIN_GROUP(n, s, ...)                                   \
  63         {                                                               \
  64                 .name = #n#s#__VA_ARGS__,                               \
  65                 .pins = n##__VA_ARGS__##_pins.data##s,                  \
  66                 .mux = n##__VA_ARGS__##_mux.data##s,                    \
  67                 .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s),   \
  68         }
  69
  70 union vin_data12 {
  71         unsigned int data12[12];
  72         unsigned int data10[10];
  73         unsigned int data8[8];
  74 };
  75
  76 union vin_data16 {
  77         unsigned int data16[16];
  78         unsigned int data12[12];
  79         unsigned int data10[10];
  80         unsigned int data8[8];
  81 };
  82
  83 union vin_data {
  84         unsigned int data24[24];
  85         unsigned int data20[20];
  86         unsigned int data16[16];
  87         unsigned int data12[12];
  88         unsigned int data10[10];
  89         unsigned int data8[8];
  90         unsigned int data4[4];
  91 };
  92
  93 #define SH_PFC_FUNCTION(n)                              \
  94         {                                               \
  95                 .name = #n,                             \
  96                 .groups = n##_groups,                   \
  97                 .nr_groups = ARRAY_SIZE(n##_groups),    \
  98         }
  99
 100 struct sh_pfc_function {
 101         const char *name;
 102         const char * const *groups;
 103         unsigned int nr_groups;
 104 };
 105
 106 struct pinmux_func {
 107         u16 enum_id;
 108         const char *name;
 109 };
 110
 111 struct pinmux_cfg_reg {
 112         u32 reg;
 113         u8 reg_width, field_width;
 114         const u16 *enum_ids;
 115         const u8 *var_field_width;
 116 };
 117
 118 /*
 119  * Describe a config register consisting of several fields of the same width
 120  *   - name: Register name (unused, for documentation purposes only)
 121  *   - r: Physical register address
 122  *   - r_width: Width of the register (in bits)
 123  *   - f_width: Width of the fixed-width register fields (in bits)
 124  * This macro must be followed by initialization data: For each register field
 125  * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
 126  * one for each possible combination of the register field bit values.
 127  */
 128 #define PINMUX_CFG_REG(name, r, r_width, f_width) \
 129         .reg = r, .reg_width = r_width, .field_width = f_width,         \
 130         .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
 131
 132 /*
 133  * Describe a config register consisting of several fields of different widths
 134  *   - name: Register name (unused, for documentation purposes only)
 135  *   - r: Physical register address
 136  *   - r_width: Width of the register (in bits)
 137  *   - var_fw0, var_fwn...: List of widths of the register fields (in bits),
 138  *                          From left to right (i.e. MSB to LSB)
 139  * This macro must be followed by initialization data: For each register field
 140  * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
 141  * one for each possible combination of the register field bit values.
 142  */
 143 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
 144         .reg = r, .reg_width = r_width, \
 145         .var_field_width = (const u8 []) { var_fw0, var_fwn, 0 }, \
 146         .enum_ids = (const u16 [])
 147
 148 struct pinmux_drive_reg_field {
 149         u16 pin;
 150         u8 offset;
 151         u8 size;
 152 };
 153
 154 struct pinmux_drive_reg {
 155         u32 reg;
 156         const struct pinmux_drive_reg_field fields[8];
 157 };
 158
 159 #define PINMUX_DRIVE_REG(name, r) \
 160         .reg = r, \
 161         .fields =
 162
 163 struct pinmux_bias_reg {
 164         u32 puen;               /* Pull-enable or pull-up control register */
 165         u32 pud;                /* Pull-up/down control register (optional) */
 166         const u16 pins[32];
 167 };
 168
 169 #define PINMUX_BIAS_REG(name1, r1, name2, r2) \
 170         .puen = r1,     \
 171         .pud = r2,      \
 172         .pins =
 173
 174 struct pinmux_ioctrl_reg {
 175         u32 reg;
 176 };
 177
 178 struct pinmux_data_reg {
 179         u32 reg;
 180         u8 reg_width;
 181         const u16 *enum_ids;
 182 };
 183
 184 /*
 185  * Describe a data register
 186  *   - name: Register name (unused, for documentation purposes only)
 187  *   - r: Physical register address
 188  *   - r_width: Width of the register (in bits)
 189  * This macro must be followed by initialization data: For each register bit
 190  * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
 191  */
 192 #define PINMUX_DATA_REG(name, r, r_width) \
 193         .reg = r, .reg_width = r_width, \
 194         .enum_ids = (const u16 [r_width]) \
 195
 196 struct pinmux_irq {
 197         const short *gpios;
 198 };
 199
 200 /*
 201  * Describe the mapping from GPIOs to a single IRQ
 202  *   - ids...: List of GPIOs that are mapped to the same IRQ
 203  */
 204 #define PINMUX_IRQ(ids...)                         \
 205         { .gpios = (const short []) { ids, -1 } }
 206
 207 struct pinmux_range {
 208         u16 begin;
 209         u16 end;
 210         u16 force;
 211 };
 212
 213 struct sh_pfc_window {
 214         phys_addr_t phys;
 215         void __iomem *virt;
 216         unsigned long size;
 217 };
 218
 219 struct sh_pfc_pin_range;
 220
 221 struct sh_pfc {
 222         struct device *dev;
 223         const struct sh_pfc_soc_info *info;
 224         spinlock_t lock;
 225
 226         unsigned int num_windows;
 227         struct sh_pfc_window *windows;
 228         unsigned int num_irqs;
 229         unsigned int *irqs;
 230
 231         struct sh_pfc_pin_range *ranges;
 232         unsigned int nr_ranges;
 233
 234         unsigned int nr_gpio_pins;
 235
 236         struct sh_pfc_chip *gpio;
 237         u32 *saved_regs;
 238 };
 239
 240 struct sh_pfc_soc_operations {
 241         int (*init)(struct sh_pfc *pfc);
 242         unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
 243         void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
 244                          unsigned int bias);
 245         int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
 246 };
 247
 248 struct sh_pfc_soc_info {
 249         const char *name;
 250         const struct sh_pfc_soc_operations *ops;
 251
 252         struct pinmux_range input;
 253         struct pinmux_range output;
 254         struct pinmux_range function;
 255
 256         const struct sh_pfc_pin *pins;
 257         unsigned int nr_pins;
 258         const struct sh_pfc_pin_group *groups;
 259         unsigned int nr_groups;
 260         const struct sh_pfc_function *functions;
 261         unsigned int nr_functions;
 262
 263 #ifdef CONFIG_SUPERH
 264         const struct pinmux_func *func_gpios;
 265         unsigned int nr_func_gpios;
 266 #endif
 267
 268         const struct pinmux_cfg_reg *cfg_regs;
 269         const struct pinmux_drive_reg *drive_regs;
 270         const struct pinmux_bias_reg *bias_regs;
 271         const struct pinmux_ioctrl_reg *ioctrl_regs;
 272         const struct pinmux_data_reg *data_regs;
 273
 274         const u16 *pinmux_data;
 275         unsigned int pinmux_data_size;
 276
 277         const struct pinmux_irq *gpio_irq;
 278         unsigned int gpio_irq_size;
 279
 280         u32 unlock_reg;
 281 };
 282
 283 extern const struct sh_pfc_soc_info emev2_pinmux_info;
 284 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
 285 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
 286 extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
 287 extern const struct sh_pfc_soc_info r8a7744_pinmux_info;
 288 extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
 289 extern const struct sh_pfc_soc_info r8a77470_pinmux_info;
 290 extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
 291 extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
 292 extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
 293 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
 294 extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
 295 extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
 296 extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
 297 extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
 298 extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
 299 extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
 300 extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
 301 extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
 302 extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
 303 extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
 304 extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
 305 extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
 306 extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
 307 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
 308 extern const struct sh_pfc_soc_info sh7264_pinmux_info;
 309 extern const struct sh_pfc_soc_info sh7269_pinmux_info;
 310 extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
 311 extern const struct sh_pfc_soc_info sh7720_pinmux_info;
 312 extern const struct sh_pfc_soc_info sh7722_pinmux_info;
 313 extern const struct sh_pfc_soc_info sh7723_pinmux_info;
 314 extern const struct sh_pfc_soc_info sh7724_pinmux_info;
 315 extern const struct sh_pfc_soc_info sh7734_pinmux_info;
 316 extern const struct sh_pfc_soc_info sh7757_pinmux_info;
 317 extern const struct sh_pfc_soc_info sh7785_pinmux_info;
 318 extern const struct sh_pfc_soc_info sh7786_pinmux_info;
 319 extern const struct sh_pfc_soc_info shx3_pinmux_info;
 320
 321 /* -----------------------------------------------------------------------------
 322  * Helper macros to create pin and port lists
 323  */
 324
 325 /*
 326  * sh_pfc_soc_info pinmux_data array macros
 327  */
 328
 329 /*
 330  * Describe generic pinmux data
 331  *   - data_or_mark: *_DATA or *_MARK enum ID
 332  *   - ids...: List of enum IDs to associate with data_or_mark
 333  */
 334 #define PINMUX_DATA(data_or_mark, ids...)       data_or_mark, ids, 0
 335
 336 /*
 337  * Describe a pinmux configuration without GPIO function that needs
 338  * configuration in a Peripheral Function Select Register (IPSR)
 339  *   - ipsr: IPSR field (unused, for documentation purposes only)
 340  *   - fn: Function name, referring to a field in the IPSR
 341  */
 342 #define PINMUX_IPSR_NOGP(ipsr, fn)                                      \
 343         PINMUX_DATA(fn##_MARK, FN_##fn)
 344
 345 /*
 346  * Describe a pinmux configuration with GPIO function that needs configuration
 347  * in both a Peripheral Function Select Register (IPSR) and in a
 348  * GPIO/Peripheral Function Select Register (GPSR)
 349  *   - ipsr: IPSR field
 350  *   - fn: Function name, also referring to the IPSR field
 351  */
 352 #define PINMUX_IPSR_GPSR(ipsr, fn)                                      \
 353         PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
 354
 355 /*
 356  * Describe a pinmux configuration without GPIO function that needs
 357  * configuration in a Peripheral Function Select Register (IPSR), and where the
 358  * pinmux function has a representation in a Module Select Register (MOD_SEL).
 359  *   - ipsr: IPSR field (unused, for documentation purposes only)
 360  *   - fn: Function name, also referring to the IPSR field
 361  *   - msel: Module selector
 362  */
 363 #define PINMUX_IPSR_NOGM(ipsr, fn, msel)                                \
 364         PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
 365
 366 /*
 367  * Describe a pinmux configuration with GPIO function where the pinmux function
 368  * has no representation in a Peripheral Function Select Register (IPSR), but
 369  * instead solely depends on a group selection.
 370  *   - gpsr: GPSR field
 371  *   - fn: Function name, also referring to the GPSR field
 372  *   - gsel: Group selector
 373  */
 374 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel)                                \
 375         PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
 376
 377 /*
 378  * Describe a pinmux configuration with GPIO function that needs configuration
 379  * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
 380  * Function Select Register (GPSR), and where the pinmux function has a
 381  * representation in a Module Select Register (MOD_SEL).
 382  *   - ipsr: IPSR field
 383  *   - fn: Function name, also referring to the IPSR field
 384  *   - msel: Module selector
 385  */
 386 #define PINMUX_IPSR_MSEL(ipsr, fn, msel)                                \
 387         PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
 388
 389 /*
 390  * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
 391  * an additional select register that controls physical multiplexing
 392  * with another pin.
 393  *   - ipsr: IPSR field
 394  *   - fn: Function name, also referring to the IPSR field
 395  *   - psel: Physical multiplexing selector
 396  *   - msel: Module selector
 397  */
 398 #define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
 399         PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
 400
 401 /*
 402  * Describe a pinmux configuration in which a pin is physically multiplexed
 403  * with other pins.
 404  *   - ipsr: IPSR field
 405  *   - fn: Function name, also referring to the IPSR field
 406  *   - psel: Physical multiplexing selector
 407  */
 408 #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
 409         PINMUX_DATA(fn##_MARK, FN_##psel)
 410
 411 /*
 412  * Describe a pinmux configuration for a single-function pin with GPIO
 413  * capability.
 414  *   - fn: Function name
 415  */
 416 #define PINMUX_SINGLE(fn)                                               \
 417         PINMUX_DATA(fn##_MARK, FN_##fn)
 418
 419 /*
 420  * GP port style (32 ports banks)
 421  */
 422
 423 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg)                          \
 424         fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
 425 #define PORT_GP_1(bank, pin, fn, sfx)   PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
 426
 427 #define PORT_GP_CFG_4(bank, fn, sfx, cfg)                               \
 428         PORT_GP_CFG_1(bank, 0,  fn, sfx, cfg),                          \
 429         PORT_GP_CFG_1(bank, 1,  fn, sfx, cfg),                          \
 430         PORT_GP_CFG_1(bank, 2,  fn, sfx, cfg),                          \
 431         PORT_GP_CFG_1(bank, 3,  fn, sfx, cfg)
 432 #define PORT_GP_4(bank, fn, sfx)        PORT_GP_CFG_4(bank, fn, sfx, 0)
 433
 434 #define PORT_GP_CFG_6(bank, fn, sfx, cfg)                               \
 435         PORT_GP_CFG_4(bank, fn, sfx, cfg),                              \
 436         PORT_GP_CFG_1(bank, 4,  fn, sfx, cfg),                          \
 437         PORT_GP_CFG_1(bank, 5,  fn, sfx, cfg)
 438 #define PORT_GP_6(bank, fn, sfx)        PORT_GP_CFG_6(bank, fn, sfx, 0)
 439
 440 #define PORT_GP_CFG_8(bank, fn, sfx, cfg)                               \
 441         PORT_GP_CFG_6(bank, fn, sfx, cfg),                              \
 442         PORT_GP_CFG_1(bank, 6,  fn, sfx, cfg),                          \
 443         PORT_GP_CFG_1(bank, 7,  fn, sfx, cfg)
 444 #define PORT_GP_8(bank, fn, sfx)        PORT_GP_CFG_8(bank, fn, sfx, 0)
 445
 446 #define PORT_GP_CFG_9(bank, fn, sfx, cfg)                               \
 447         PORT_GP_CFG_8(bank, fn, sfx, cfg),                              \
 448         PORT_GP_CFG_1(bank, 8,  fn, sfx, cfg)
 449 #define PORT_GP_9(bank, fn, sfx)        PORT_GP_CFG_9(bank, fn, sfx, 0)
 450
 451 #define PORT_GP_CFG_10(bank, fn, sfx, cfg)                              \
 452         PORT_GP_CFG_9(bank, fn, sfx, cfg),                              \
 453         PORT_GP_CFG_1(bank, 9,  fn, sfx, cfg)
 454 #define PORT_GP_10(bank, fn, sfx)       PORT_GP_CFG_10(bank, fn, sfx, 0)
 455
 456 #define PORT_GP_CFG_11(bank, fn, sfx, cfg)                              \
 457         PORT_GP_CFG_10(bank, fn, sfx, cfg),                             \
 458         PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
 459 #define PORT_GP_11(bank, fn, sfx)       PORT_GP_CFG_11(bank, fn, sfx, 0)
 460
 461 #define PORT_GP_CFG_12(bank, fn, sfx, cfg)                              \
 462         PORT_GP_CFG_11(bank, fn, sfx, cfg),                             \
 463         PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
 464 #define PORT_GP_12(bank, fn, sfx)       PORT_GP_CFG_12(bank, fn, sfx, 0)
 465
 466 #define PORT_GP_CFG_14(bank, fn, sfx, cfg)                              \
 467         PORT_GP_CFG_12(bank, fn, sfx, cfg),                             \
 468         PORT_GP_CFG_1(bank, 12, fn, sfx, cfg),                          \
 469         PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
 470 #define PORT_GP_14(bank, fn, sfx)       PORT_GP_CFG_14(bank, fn, sfx, 0)
 471
 472 #define PORT_GP_CFG_15(bank, fn, sfx, cfg)                              \
 473         PORT_GP_CFG_14(bank, fn, sfx, cfg),                             \
 474         PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
 475 #define PORT_GP_15(bank, fn, sfx)       PORT_GP_CFG_15(bank, fn, sfx, 0)
 476
 477 #define PORT_GP_CFG_16(bank, fn, sfx, cfg)                              \
 478         PORT_GP_CFG_15(bank, fn, sfx, cfg),                             \
 479         PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
 480 #define PORT_GP_16(bank, fn, sfx)       PORT_GP_CFG_16(bank, fn, sfx, 0)
 481
 482 #define PORT_GP_CFG_17(bank, fn, sfx, cfg)                              \
 483         PORT_GP_CFG_16(bank, fn, sfx, cfg),                             \
 484         PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
 485 #define PORT_GP_17(bank, fn, sfx)       PORT_GP_CFG_17(bank, fn, sfx, 0)
 486
 487 #define PORT_GP_CFG_18(bank, fn, sfx, cfg)                              \
 488         PORT_GP_CFG_17(bank, fn, sfx, cfg),                             \
 489         PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
 490 #define PORT_GP_18(bank, fn, sfx)       PORT_GP_CFG_18(bank, fn, sfx, 0)
 491
 492 #define PORT_GP_CFG_20(bank, fn, sfx, cfg)                              \
 493         PORT_GP_CFG_18(bank, fn, sfx, cfg),                             \
 494         PORT_GP_CFG_1(bank, 18, fn, sfx, cfg),                          \
 495         PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
 496 #define PORT_GP_20(bank, fn, sfx)       PORT_GP_CFG_20(bank, fn, sfx, 0)
 497
 498 #define PORT_GP_CFG_21(bank, fn, sfx, cfg)                              \
 499         PORT_GP_CFG_20(bank, fn, sfx, cfg),                             \
 500         PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
 501 #define PORT_GP_21(bank, fn, sfx)       PORT_GP_CFG_21(bank, fn, sfx, 0)
 502
 503 #define PORT_GP_CFG_22(bank, fn, sfx, cfg)                              \
 504         PORT_GP_CFG_21(bank, fn, sfx, cfg),                             \
 505         PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
 506 #define PORT_GP_22(bank, fn, sfx)       PORT_GP_CFG_22(bank, fn, sfx, 0)
 507
 508 #define PORT_GP_CFG_23(bank, fn, sfx, cfg)                              \
 509         PORT_GP_CFG_22(bank, fn, sfx, cfg),                             \
 510         PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
 511 #define PORT_GP_23(bank, fn, sfx)       PORT_GP_CFG_23(bank, fn, sfx, 0)
 512
 513 #define PORT_GP_CFG_24(bank, fn, sfx, cfg)                              \
 514         PORT_GP_CFG_23(bank, fn, sfx, cfg),                             \
 515         PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
 516 #define PORT_GP_24(bank, fn, sfx)       PORT_GP_CFG_24(bank, fn, sfx, 0)
 517
 518 #define PORT_GP_CFG_25(bank, fn, sfx, cfg)                              \
 519         PORT_GP_CFG_24(bank, fn, sfx, cfg),                             \
 520         PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
 521 #define PORT_GP_25(bank, fn, sfx)       PORT_GP_CFG_25(bank, fn, sfx, 0)
 522
 523 #define PORT_GP_CFG_26(bank, fn, sfx, cfg)                              \
 524         PORT_GP_CFG_25(bank, fn, sfx, cfg),                             \
 525         PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
 526 #define PORT_GP_26(bank, fn, sfx)       PORT_GP_CFG_26(bank, fn, sfx, 0)
 527
 528 #define PORT_GP_CFG_28(bank, fn, sfx, cfg)                              \
 529         PORT_GP_CFG_26(bank, fn, sfx, cfg),                             \
 530         PORT_GP_CFG_1(bank, 26, fn, sfx, cfg),                          \
 531         PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
 532 #define PORT_GP_28(bank, fn, sfx)       PORT_GP_CFG_28(bank, fn, sfx, 0)
 533
 534 #define PORT_GP_CFG_29(bank, fn, sfx, cfg)                              \
 535         PORT_GP_CFG_28(bank, fn, sfx, cfg),                             \
 536         PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
 537 #define PORT_GP_29(bank, fn, sfx)       PORT_GP_CFG_29(bank, fn, sfx, 0)
 538
 539 #define PORT_GP_CFG_30(bank, fn, sfx, cfg)                              \
 540         PORT_GP_CFG_29(bank, fn, sfx, cfg),                             \
 541         PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
 542 #define PORT_GP_30(bank, fn, sfx)       PORT_GP_CFG_30(bank, fn, sfx, 0)
 543
 544 #define PORT_GP_CFG_32(bank, fn, sfx, cfg)                              \
 545         PORT_GP_CFG_30(bank, fn, sfx, cfg),                             \
 546         PORT_GP_CFG_1(bank, 30, fn, sfx, cfg),                          \
 547         PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
 548 #define PORT_GP_32(bank, fn, sfx)       PORT_GP_CFG_32(bank, fn, sfx, 0)
 549
 550 #define PORT_GP_32_REV(bank, fn, sfx)                                   \
 551         PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),     \
 552         PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),     \
 553         PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),     \
 554         PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),     \
 555         PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),     \
 556         PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),     \
 557         PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),     \
 558         PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),     \
 559         PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),     \
 560         PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),     \
 561         PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),     \
 562         PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),     \
 563         PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),     \
 564         PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),     \
 565         PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),     \
 566         PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
 567
 568 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
 569 #define _GP_ALL(bank, pin, name, sfx, cfg)      name##_##sfx
 570 #define GP_ALL(str)                     CPU_ALL_PORT(_GP_ALL, str)
 571
 572 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
 573 #define _GP_GPIO(bank, _pin, _name, sfx, cfg)                           \
 574         {                                                               \
 575                 .pin = (bank * 32) + _pin,                              \
 576                 .name = __stringify(_name),                             \
 577                 .enum_id = _name##_DATA,                                \
 578                 .configs = cfg,                                         \
 579         }
 580 #define PINMUX_GPIO_GP_ALL()            CPU_ALL_PORT(_GP_GPIO, unused)
 581
 582 /* PINMUX_DATA_GP_ALL -  Expand to a list of name_DATA, name_FN marks */
 583 #define _GP_DATA(bank, pin, name, sfx, cfg)     PINMUX_DATA(name##_DATA, name##_FN)
 584 #define PINMUX_DATA_GP_ALL()            CPU_ALL_PORT(_GP_DATA, unused)
 585
 586 /*
 587  * PORT style (linear pin space)
 588  */
 589
 590 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
 591
 592 #define PORT_10(pn, fn, pfx, sfx)                                         \
 593         PORT_1(pn,   fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx),     \
 594         PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx),     \
 595         PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx),     \
 596         PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx),     \
 597         PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
 598
 599 #define PORT_90(pn, fn, pfx, sfx)                                         \
 600         PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
 601         PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
 602         PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
 603         PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
 604         PORT_10(pn+90, fn, pfx##9, sfx)
 605
 606 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
 607 #define _PORT_ALL(pn, pfx, sfx)         pfx##_##sfx
 608 #define PORT_ALL(str)                   CPU_ALL_PORT(_PORT_ALL, PORT, str)
 609
 610 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
 611 #define PINMUX_GPIO(_pin)                                               \
 612         [GPIO_##_pin] = {                                               \
 613                 .pin = (u16)-1,                                         \
 614                 .name = __stringify(GPIO_##_pin),                       \
 615                 .enum_id = _pin##_DATA,                                 \
 616         }
 617
 618 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
 619 #define SH_PFC_PIN_CFG(_pin, cfgs)                                      \
 620         {                                                               \
 621                 .pin = _pin,                                            \
 622                 .name = __stringify(PORT##_pin),                        \
 623                 .enum_id = PORT##_pin##_DATA,                           \
 624                 .configs = cfgs,                                        \
 625         }
 626
 627 /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
 628 #define SH_PFC_PIN_NAMED(row, col, _name)                               \
 629         {                                                               \
 630                 .pin = PIN_NUMBER(row, col),                            \
 631                 .name = __stringify(PIN_##_name),                       \
 632                 .configs = SH_PFC_PIN_CFG_NO_GPIO,                      \
 633         }
 634
 635 /* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
 636 #define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs)                     \
 637         {                                                               \
 638                 .pin = PIN_NUMBER(row, col),                            \
 639                 .name = __stringify(PIN_##_name),                       \
 640                 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs,               \
 641         }
 642
 643 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
 644  *                   PORT_name_OUT, PORT_name_IN marks
 645  */
 646 #define _PORT_DATA(pn, pfx, sfx)                                        \
 647         PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0,                  \
 648                     PORT##pfx##_OUT, PORT##pfx##_IN)
 649 #define PINMUX_DATA_ALL()               CPU_ALL_PORT(_PORT_DATA, , unused)
 650
 651 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
 652 #define PINMUX_GPIO_FN(gpio, base, data_or_mark)                        \
 653         [gpio - (base)] = {                                             \
 654                 .name = __stringify(gpio),                              \
 655                 .enum_id = data_or_mark,                                \
 656         }
 657 #define GPIO_FN(str)                                                    \
 658         PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
 659
 660 /*
 661  * PORTnCR helper macro for SH-Mobile/R-Mobile
 662  */
 663 #define PORTCR(nr, reg)                                                 \
 664         {                                                               \
 665                 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
 666                         /* PULMD[1:0], handled by .set_bias() */        \
 667                         0, 0, 0, 0,                                     \
 668                         /* IE and OE */                                 \
 669                         0, PORT##nr##_OUT, PORT##nr##_IN, 0,            \
 670                         /* SEC, not supported */                        \
 671                         0, 0,                                           \
 672                         /* PTMD[2:0] */                                 \
 673                         PORT##nr##_FN0, PORT##nr##_FN1,                 \
 674                         PORT##nr##_FN2, PORT##nr##_FN3,                 \
 675                         PORT##nr##_FN4, PORT##nr##_FN5,                 \
 676                         PORT##nr##_FN6, PORT##nr##_FN7                  \
 677                 }                                                       \
 678         }
 679
 680 /*
 681  * GPIO number helper macro for R-Car
 682  */
 683 #define RCAR_GP_PIN(bank, pin)          (((bank) * 32) + (pin))
 684
 685 #endif /* __SH_PFC_H */