2 * SuperH Pin Function Controller Support
4 * Copyright (c) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/bug.h>
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include <linux/spinlock.h>
17 #include <linux/stringify.h>
27 #define SH_PFC_PIN_CFG_INPUT (1 << 0)
28 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
29 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
30 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
31 #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
32 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
33 #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
42 #define SH_PFC_PIN_GROUP(n) \
47 .nr_pins = ARRAY_SIZE(n##_pins), \
50 struct sh_pfc_pin_group
{
52 const unsigned int *pins
;
53 const unsigned int *mux
;
58 * Using union vin_data saves memory occupied by the VIN data pins.
59 * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
62 #define VIN_DATA_PIN_GROUP(n, s) \
65 .pins = n##_pins.data##s, \
66 .mux = n##_mux.data##s, \
67 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
71 unsigned int data24
[24];
72 unsigned int data20
[20];
73 unsigned int data16
[16];
74 unsigned int data12
[12];
75 unsigned int data10
[10];
76 unsigned int data8
[8];
77 unsigned int data4
[4];
80 #define SH_PFC_FUNCTION(n) \
83 .groups = n##_groups, \
84 .nr_groups = ARRAY_SIZE(n##_groups), \
87 struct sh_pfc_function
{
89 const char * const *groups
;
90 unsigned int nr_groups
;
98 struct pinmux_cfg_reg
{
100 u8 reg_width
, field_width
;
102 const u8
*var_field_width
;
106 * Describe a config register consisting of several fields of the same width
107 * - name: Register name (unused, for documentation purposes only)
108 * - r: Physical register address
109 * - r_width: Width of the register (in bits)
110 * - f_width: Width of the fixed-width register fields (in bits)
111 * This macro must be followed by initialization data: For each register field
112 * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
113 * one for each possible combination of the register field bit values.
115 #define PINMUX_CFG_REG(name, r, r_width, f_width) \
116 .reg = r, .reg_width = r_width, .field_width = f_width, \
117 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
120 * Describe a config register consisting of several fields of different widths
121 * - name: Register name (unused, for documentation purposes only)
122 * - r: Physical register address
123 * - r_width: Width of the register (in bits)
124 * - var_fw0, var_fwn...: List of widths of the register fields (in bits),
125 * From left to right (i.e. MSB to LSB)
126 * This macro must be followed by initialization data: For each register field
127 * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
128 * one for each possible combination of the register field bit values.
130 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
131 .reg = r, .reg_width = r_width, \
132 .var_field_width = (const u8 [r_width]) \
133 { var_fw0, var_fwn, 0 }, \
134 .enum_ids = (const u16 [])
136 struct pinmux_drive_reg_field
{
142 struct pinmux_drive_reg
{
144 const struct pinmux_drive_reg_field fields
[8];
147 #define PINMUX_DRIVE_REG(name, r) \
151 struct pinmux_data_reg
{
158 * Describe a data register
159 * - name: Register name (unused, for documentation purposes only)
160 * - r: Physical register address
161 * - r_width: Width of the register (in bits)
162 * This macro must be followed by initialization data: For each register bit
163 * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
165 #define PINMUX_DATA_REG(name, r, r_width) \
166 .reg = r, .reg_width = r_width, \
167 .enum_ids = (const u16 [r_width]) \
174 * Describe the mapping from GPIOs to a single IRQ
175 * - ids...: List of GPIOs that are mapped to the same IRQ
177 #define PINMUX_IRQ(ids...) \
178 { .gpios = (const short []) { ids, -1 } }
180 struct pinmux_range
{
186 struct sh_pfc_window
{
192 struct sh_pfc_pin_range
;
196 const struct sh_pfc_soc_info
*info
;
199 unsigned int num_windows
;
200 struct sh_pfc_window
*windows
;
201 unsigned int num_irqs
;
204 struct sh_pfc_pin_range
*ranges
;
205 unsigned int nr_ranges
;
207 unsigned int nr_gpio_pins
;
209 struct sh_pfc_chip
*gpio
;
212 struct sh_pfc_soc_operations
{
213 int (*init
)(struct sh_pfc
*pfc
);
214 unsigned int (*get_bias
)(struct sh_pfc
*pfc
, unsigned int pin
);
215 void (*set_bias
)(struct sh_pfc
*pfc
, unsigned int pin
,
217 int (*pin_to_pocctrl
)(struct sh_pfc
*pfc
, unsigned int pin
, u32
*pocctrl
);
220 struct sh_pfc_soc_info
{
222 const struct sh_pfc_soc_operations
*ops
;
224 struct pinmux_range input
;
225 struct pinmux_range output
;
226 struct pinmux_range function
;
228 const struct sh_pfc_pin
*pins
;
229 unsigned int nr_pins
;
230 const struct sh_pfc_pin_group
*groups
;
231 unsigned int nr_groups
;
232 const struct sh_pfc_function
*functions
;
233 unsigned int nr_functions
;
236 const struct pinmux_func
*func_gpios
;
237 unsigned int nr_func_gpios
;
240 const struct pinmux_cfg_reg
*cfg_regs
;
241 const struct pinmux_drive_reg
*drive_regs
;
242 const struct pinmux_data_reg
*data_regs
;
244 const u16
*pinmux_data
;
245 unsigned int pinmux_data_size
;
247 const struct pinmux_irq
*gpio_irq
;
248 unsigned int gpio_irq_size
;
253 extern const struct sh_pfc_soc_info emev2_pinmux_info
;
254 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info
;
255 extern const struct sh_pfc_soc_info r8a7740_pinmux_info
;
256 extern const struct sh_pfc_soc_info r8a7778_pinmux_info
;
257 extern const struct sh_pfc_soc_info r8a7779_pinmux_info
;
258 extern const struct sh_pfc_soc_info r8a7790_pinmux_info
;
259 extern const struct sh_pfc_soc_info r8a7791_pinmux_info
;
260 extern const struct sh_pfc_soc_info r8a7792_pinmux_info
;
261 extern const struct sh_pfc_soc_info r8a7793_pinmux_info
;
262 extern const struct sh_pfc_soc_info r8a7794_pinmux_info
;
263 extern const struct sh_pfc_soc_info r8a7795_pinmux_info
;
264 extern const struct sh_pfc_soc_info r8a7796_pinmux_info
;
265 extern const struct sh_pfc_soc_info sh7203_pinmux_info
;
266 extern const struct sh_pfc_soc_info sh7264_pinmux_info
;
267 extern const struct sh_pfc_soc_info sh7269_pinmux_info
;
268 extern const struct sh_pfc_soc_info sh73a0_pinmux_info
;
269 extern const struct sh_pfc_soc_info sh7720_pinmux_info
;
270 extern const struct sh_pfc_soc_info sh7722_pinmux_info
;
271 extern const struct sh_pfc_soc_info sh7723_pinmux_info
;
272 extern const struct sh_pfc_soc_info sh7724_pinmux_info
;
273 extern const struct sh_pfc_soc_info sh7734_pinmux_info
;
274 extern const struct sh_pfc_soc_info sh7757_pinmux_info
;
275 extern const struct sh_pfc_soc_info sh7785_pinmux_info
;
276 extern const struct sh_pfc_soc_info sh7786_pinmux_info
;
277 extern const struct sh_pfc_soc_info shx3_pinmux_info
;
279 /* -----------------------------------------------------------------------------
280 * Helper macros to create pin and port lists
284 * sh_pfc_soc_info pinmux_data array macros
288 * Describe generic pinmux data
289 * - data_or_mark: *_DATA or *_MARK enum ID
290 * - ids...: List of enum IDs to associate with data_or_mark
292 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
295 * Describe a pinmux configuration without GPIO function that needs
296 * configuration in a Peripheral Function Select Register (IPSR)
297 * - ipsr: IPSR field (unused, for documentation purposes only)
298 * - fn: Function name, referring to a field in the IPSR
300 #define PINMUX_IPSR_NOGP(ipsr, fn) \
301 PINMUX_DATA(fn##_MARK, FN_##fn)
304 * Describe a pinmux configuration with GPIO function that needs configuration
305 * in both a Peripheral Function Select Register (IPSR) and in a
306 * GPIO/Peripheral Function Select Register (GPSR)
308 * - fn: Function name, also referring to the IPSR field
310 #define PINMUX_IPSR_GPSR(ipsr, fn) \
311 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
314 * Describe a pinmux configuration without GPIO function that needs
315 * configuration in a Peripheral Function Select Register (IPSR), and where the
316 * pinmux function has a representation in a Module Select Register (MOD_SEL).
317 * - ipsr: IPSR field (unused, for documentation purposes only)
318 * - fn: Function name, also referring to the IPSR field
319 * - msel: Module selector
321 #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
322 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
325 * Describe a pinmux configuration with GPIO function where the pinmux function
326 * has no representation in a Peripheral Function Select Register (IPSR), but
327 * instead solely depends on a group selection.
329 * - fn: Function name, also referring to the GPSR field
330 * - gsel: Group selector
332 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
333 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
336 * Describe a pinmux configuration with GPIO function that needs configuration
337 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
338 * Function Select Register (GPSR), and where the pinmux function has a
339 * representation in a Module Select Register (MOD_SEL).
341 * - fn: Function name, also referring to the IPSR field
342 * - msel: Module selector
344 #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
345 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
348 * Describe a pinmux configuration for a single-function pin with GPIO
350 * - fn: Function name
352 #define PINMUX_SINGLE(fn) \
353 PINMUX_DATA(fn##_MARK, FN_##fn)
356 * GP port style (32 ports banks)
359 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
360 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
361 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
363 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
364 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
365 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
366 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
367 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
368 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
370 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
371 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
372 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
373 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
374 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
375 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
376 #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
378 #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
379 PORT_GP_CFG_8(bank, fn, sfx, cfg), \
380 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
381 #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
383 #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
384 PORT_GP_CFG_9(bank, fn, sfx, cfg), \
385 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \
386 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
387 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
388 #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
390 #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
391 PORT_GP_CFG_12(bank, fn, sfx, cfg), \
392 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
393 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
394 #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
396 #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
397 PORT_GP_CFG_14(bank, fn, sfx, cfg), \
398 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
399 #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
401 #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
402 PORT_GP_CFG_15(bank, fn, sfx, cfg), \
403 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
404 #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
406 #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
407 PORT_GP_CFG_16(bank, fn, sfx, cfg), \
408 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
409 #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
411 #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
412 PORT_GP_CFG_17(bank, fn, sfx, cfg), \
413 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
414 #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
416 #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
417 PORT_GP_CFG_18(bank, fn, sfx, cfg), \
418 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
419 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
420 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), \
421 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
422 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
423 #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
425 #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
426 PORT_GP_CFG_23(bank, fn, sfx, cfg), \
427 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
428 #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
430 #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
431 PORT_GP_CFG_24(bank, fn, sfx, cfg), \
432 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
433 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
434 #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
436 #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
437 PORT_GP_CFG_26(bank, fn, sfx, cfg), \
438 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
439 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
440 #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
442 #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
443 PORT_GP_CFG_28(bank, fn, sfx, cfg), \
444 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
445 #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
447 #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
448 PORT_GP_CFG_29(bank, fn, sfx, cfg), \
449 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
450 #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
452 #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
453 PORT_GP_CFG_30(bank, fn, sfx, cfg), \
454 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
455 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
456 #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
458 #define PORT_GP_32_REV(bank, fn, sfx) \
459 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
460 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
461 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
462 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
463 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
464 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
465 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
466 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
467 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
468 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
469 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
470 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
471 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
472 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
473 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
474 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
476 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
477 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
478 #define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
480 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
481 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
483 .pin = (bank * 32) + _pin, \
484 .name = __stringify(_name), \
485 .enum_id = _name##_DATA, \
488 #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
490 /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
491 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
492 #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
495 * PORT style (linear pin space)
498 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
500 #define PORT_10(pn, fn, pfx, sfx) \
501 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
502 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
503 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
504 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
505 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
507 #define PORT_90(pn, fn, pfx, sfx) \
508 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
509 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
510 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
511 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
512 PORT_10(pn+90, fn, pfx##9, sfx)
514 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
515 #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
516 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
518 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
519 #define PINMUX_GPIO(_pin) \
522 .name = __stringify(GPIO_##_pin), \
523 .enum_id = _pin##_DATA, \
526 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
527 #define SH_PFC_PIN_CFG(_pin, cfgs) \
530 .name = __stringify(PORT##_pin), \
531 .enum_id = PORT##_pin##_DATA, \
535 /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
536 #define SH_PFC_PIN_NAMED(row, col, _name) \
538 .pin = PIN_NUMBER(row, col), \
539 .name = __stringify(PIN_##_name), \
540 .configs = SH_PFC_PIN_CFG_NO_GPIO, \
543 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
544 * PORT_name_OUT, PORT_name_IN marks
546 #define _PORT_DATA(pn, pfx, sfx) \
547 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
548 PORT##pfx##_OUT, PORT##pfx##_IN)
549 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
551 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
552 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
553 [gpio - (base)] = { \
554 .name = __stringify(gpio), \
555 .enum_id = data_or_mark, \
557 #define GPIO_FN(str) \
558 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
561 * PORTnCR helper macro for SH-Mobile/R-Mobile
563 #define PORTCR(nr, reg) \
565 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
566 /* PULMD[1:0], handled by .set_bias() */ \
569 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
570 /* SEC, not supported */ \
573 PORT##nr##_FN0, PORT##nr##_FN1, \
574 PORT##nr##_FN2, PORT##nr##_FN3, \
575 PORT##nr##_FN4, PORT##nr##_FN5, \
576 PORT##nr##_FN6, PORT##nr##_FN7 \
581 * GPIO number helper macro for R-Car
583 #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
585 #endif /* __SH_PFC_H */