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[mirror_ubuntu-bionic-kernel.git] / drivers / pinctrl / sirf / pinctrl-atlas7.c
1 /*
2 * pinctrl pads, groups, functions for CSR SiRFatlasVII
3 *
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
5 * company.
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10 #include <linux/init.h>
11 #include <linux/platform_device.h>
12 #include <linux/io.h>
13 #include <linux/bitops.h>
14 #include <linux/irq.h>
15 #include <linux/slab.h>
16 #include <linux/clk.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_gpio.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/pinctrl/pinconf-generic.h>
29 #include <linux/gpio.h>
30
31 /* Definition of Pad&Mux Properties */
32 #define N 0
33
34 /* The Bank contains input-disable regisgers */
35 #define BANK_DS 0
36
37 /* Clear Register offset */
38 #define CLR_REG(r) ((r) + 0x04)
39
40 /* Definition of multiple function select register */
41 #define FUNC_CLEAR_MASK 0x7
42 #define FUNC_GPIO 0
43 #define FUNC_ANALOGUE 0x8
44 #define ANA_CLEAR_MASK 0x1
45
46 /* The Atlas7's Pad Type List */
47 enum altas7_pad_type {
48 PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */
49 PAD_T_4WE_PU, /* ZIO_PAD3V_4WE_PD */
50 PAD_T_16ST, /* ZIO_PAD3V_SDCLK_PD */
51 PAD_T_M31_0204_PD, /* PRDW0204SDGZ_M311311_PD */
52 PAD_T_M31_0204_PU, /* PRDW0204SDGZ_M311311_PU */
53 PAD_T_M31_0610_PD, /* PRUW0610SDGZ_M311311_PD */
54 PAD_T_M31_0610_PU, /* PRUW0610SDGZ_M311311_PU */
55 PAD_T_AD, /* PRDWUWHW08SCDG_HZ */
56 };
57
58 /* Raw value of Driver-Strength Bits */
59 #define DS3 BIT(3)
60 #define DS2 BIT(2)
61 #define DS1 BIT(1)
62 #define DS0 BIT(0)
63 #define DSZ 0
64
65 /* Drive-Strength Intermediate Values */
66 #define DS_NULL -1
67 #define DS_1BIT_IM_VAL DS0
68 #define DS_1BIT_MASK 0x1
69 #define DS_2BIT_IM_VAL (DS1 | DS0)
70 #define DS_2BIT_MASK 0x3
71 #define DS_4BIT_IM_VAL (DS3 | DS2 | DS1 | DS0)
72 #define DS_4BIT_MASK 0xf
73
74 /* The Drive-Strength of 4WE Pad DS1 0 CO */
75 #define DS_4WE_3 (DS1 | DS0) /* 1 1 3 */
76 #define DS_4WE_2 (DS1) /* 1 0 2 */
77 #define DS_4WE_1 (DS0) /* 0 1 1 */
78 #define DS_4WE_0 (DSZ) /* 0 0 0 */
79
80 /* The Drive-Strength of 16st Pad DS3 2 1 0 CO */
81 #define DS_16ST_15 (DS3 | DS2 | DS1 | DS0) /* 1 1 1 1 15 */
82 #define DS_16ST_14 (DS3 | DS2 | DS0) /* 1 1 0 1 13 */
83 #define DS_16ST_13 (DS3 | DS2 | DS1) /* 1 1 1 0 14 */
84 #define DS_16ST_12 (DS2 | DS1 | DS0) /* 0 1 1 1 7 */
85 #define DS_16ST_11 (DS2 | DS0) /* 0 1 0 1 5 */
86 #define DS_16ST_10 (DS3 | DS1 | DS0) /* 1 0 1 1 11 */
87 #define DS_16ST_9 (DS3 | DS0) /* 1 0 0 1 9 */
88 #define DS_16ST_8 (DS1 | DS0) /* 0 0 1 1 3 */
89 #define DS_16ST_7 (DS2 | DS1) /* 0 1 1 0 6 */
90 #define DS_16ST_6 (DS3 | DS2) /* 1 1 0 0 12 */
91 #define DS_16ST_5 (DS2) /* 0 1 0 0 4 */
92 #define DS_16ST_4 (DS3 | DS1) /* 1 0 1 0 10 */
93 #define DS_16ST_3 (DS1) /* 0 0 1 0 2 */
94 #define DS_16ST_2 (DS0) /* 0 0 0 1 1 */
95 #define DS_16ST_1 (DSZ) /* 0 0 0 0 0 */
96 #define DS_16ST_0 (DS3) /* 1 0 0 0 8 */
97
98 /* The Drive-Strength of M31 Pad DS0 CO */
99 #define DS_M31_0 (DSZ) /* 0 0 */
100 #define DS_M31_1 (DS0) /* 1 1 */
101
102 /* Raw values of Pull Option Bits */
103 #define PUN BIT(1)
104 #define PD BIT(0)
105 #define PE BIT(0)
106 #define PZ 0
107
108 /* Definition of Pull Types */
109 #define PULL_UP 0
110 #define HIGH_HYSTERESIS 1
111 #define HIGH_Z 2
112 #define PULL_DOWN 3
113 #define PULL_DISABLE 4
114 #define PULL_ENABLE 5
115 #define PULL_UNKNOWN -1
116
117 /* Pull Options for 4WE Pad PUN PD CO */
118 #define P4WE_PULL_MASK 0x3
119 #define P4WE_PULL_DOWN (PUN | PD) /* 1 1 3 */
120 #define P4WE_HIGH_Z (PUN) /* 1 0 2 */
121 #define P4WE_HIGH_HYSTERESIS (PD) /* 0 1 1 */
122 #define P4WE_PULL_UP (PZ) /* 0 0 0 */
123
124 /* Pull Options for 16ST Pad PUN PD CO */
125 #define P16ST_PULL_MASK 0x3
126 #define P16ST_PULL_DOWN (PUN | PD) /* 1 1 3 */
127 #define P16ST_HIGH_Z (PUN) /* 1 0 2 */
128 #define P16ST_PULL_UP (PZ) /* 0 0 0 */
129
130 /* Pull Options for M31 Pad PE */
131 #define PM31_PULL_MASK 0x1
132 #define PM31_PULL_ENABLED (PE) /* 1 */
133 #define PM31_PULL_DISABLED (PZ) /* 0 */
134
135 /* Pull Options for A/D Pad PUN PD CO */
136 #define PANGD_PULL_MASK 0x3
137 #define PANGD_PULL_DOWN (PUN | PD) /* 1 1 3 */
138 #define PANGD_HIGH_Z (PUN) /* 1 0 2 */
139 #define PANGD_PULL_UP (PZ) /* 0 0 0 */
140
141 /* Definition of Input Disable */
142 #define DI_MASK 0x1
143 #define DI_DISABLE 0x1
144 #define DI_ENABLE 0x0
145
146 /* Definition of Input Disable Value */
147 #define DIV_MASK 0x1
148 #define DIV_DISABLE 0x1
149 #define DIV_ENABLE 0x0
150
151 /* Number of Function input disable registers */
152 #define NUM_OF_IN_DISABLE_REG 0x2
153
154 /* Offset of Function input disable registers */
155 #define IN_DISABLE_0_REG_SET 0x0A00
156 #define IN_DISABLE_0_REG_CLR 0x0A04
157 #define IN_DISABLE_1_REG_SET 0x0A08
158 #define IN_DISABLE_1_REG_CLR 0x0A0C
159 #define IN_DISABLE_VAL_0_REG_SET 0x0A80
160 #define IN_DISABLE_VAL_0_REG_CLR 0x0A84
161 #define IN_DISABLE_VAL_1_REG_SET 0x0A88
162 #define IN_DISABLE_VAL_1_REG_CLR 0x0A8C
163
164 /* Offset of the SDIO9SEL*/
165 #define SYS2PCI_SDIO9SEL 0x14
166
167 struct dt_params {
168 const char *property;
169 int value;
170 };
171
172 /**
173 * struct atlas7_pad_conf - Atlas7 Pad Configuration
174 * @id The ID of this Pad.
175 * @type: The type of this Pad.
176 * @mux_reg: The mux register offset.
177 * This register contains the mux.
178 * @pupd_reg: The pull-up/down register offset.
179 * @drvstr_reg: The drive-strength register offset.
180 * @ad_ctrl_reg: The Analogue/Digital Control register.
181 *
182 * @mux_bit: The start bit of mux register.
183 * @pupd_bit: The start bit of pull-up/down register.
184 * @drvstr_bit: The start bit of drive-strength register.
185 * @ad_ctrl_bit: The start bit of analogue/digital register.
186 */
187 struct atlas7_pad_config {
188 const u32 id;
189 u32 type;
190 u32 mux_reg;
191 u32 pupd_reg;
192 u32 drvstr_reg;
193 u32 ad_ctrl_reg;
194 /* bits in register */
195 u8 mux_bit;
196 u8 pupd_bit;
197 u8 drvstr_bit;
198 u8 ad_ctrl_bit;
199 };
200
201 #define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb) \
202 { \
203 .id = pad, \
204 .type = t, \
205 .mux_reg = mr, \
206 .pupd_reg = pr, \
207 .drvstr_reg = dsr, \
208 .ad_ctrl_reg = adr, \
209 .mux_bit = mb, \
210 .pupd_bit = pb, \
211 .drvstr_bit = dsb, \
212 .ad_ctrl_bit = adb, \
213 }
214
215 /**
216 * struct atlas7_pad_status - Atlas7 Pad status
217 */
218 struct atlas7_pad_status {
219 u8 func;
220 u8 pull;
221 u8 dstr;
222 u8 reserved;
223 };
224
225 /**
226 * struct atlas7_pad_mux - Atlas7 mux
227 * @bank: The bank of this pad's registers on.
228 * @pin : The ID of this Pad.
229 * @func: The mux func on this Pad.
230 * @dinput_reg: The Input-Disable register offset.
231 * @dinput_bit: The start bit of Input-Disable register.
232 * @dinput_val_reg: The Input-Disable-value register offset.
233 * This register is used to set the value of this pad
234 * if this pad was disabled.
235 * @dinput_val_bit: The start bit of Input-Disable Value register.
236 */
237 struct atlas7_pad_mux {
238 u32 bank;
239 u32 pin;
240 u32 func;
241 u32 dinput_reg;
242 u32 dinput_bit;
243 u32 dinput_val_reg;
244 u32 dinput_val_bit;
245 };
246
247 #define MUX(b, pad, f, dr, db, dvr, dvb) \
248 { \
249 .bank = b, \
250 .pin = pad, \
251 .func = f, \
252 .dinput_reg = dr, \
253 .dinput_bit = db, \
254 .dinput_val_reg = dvr, \
255 .dinput_val_bit = dvb, \
256 }
257
258 struct atlas7_grp_mux {
259 unsigned int group;
260 unsigned int pad_mux_count;
261 const struct atlas7_pad_mux *pad_mux_list;
262 };
263
264 /**
265 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
266 * @name: the name of this specific pin group
267 * @pins: an array of discrete physical pins used in this group, taken
268 * from the driver-local pin enumeration space
269 * @num_pins: the number of pins in this group array, i.e. the number of
270 * elements in .pins so we can iterate over that array
271 */
272 struct atlas7_pin_group {
273 const char *name;
274 const unsigned int *pins;
275 const unsigned num_pins;
276 };
277
278 #define GROUP(n, p) \
279 { \
280 .name = n, \
281 .pins = p, \
282 .num_pins = ARRAY_SIZE(p), \
283 }
284
285 struct atlas7_pmx_func {
286 const char *name;
287 const char * const *groups;
288 const unsigned num_groups;
289 const struct atlas7_grp_mux *grpmux;
290 };
291
292 #define FUNCTION(n, g, m) \
293 { \
294 .name = n, \
295 .groups = g, \
296 .num_groups = ARRAY_SIZE(g), \
297 .grpmux = m, \
298 }
299
300 struct atlas7_pinctrl_data {
301 struct pinctrl_pin_desc *pads;
302 int pads_cnt;
303 struct atlas7_pin_group *grps;
304 int grps_cnt;
305 struct atlas7_pmx_func *funcs;
306 int funcs_cnt;
307 struct atlas7_pad_config *confs;
308 int confs_cnt;
309 };
310
311 /* Platform info of atlas7 pinctrl */
312 #define ATLAS7_PINCTRL_REG_BANKS 2
313 #define ATLAS7_PINCTRL_BANK_0_PINS 18
314 #define ATLAS7_PINCTRL_BANK_1_PINS 141
315 #define ATLAS7_PINCTRL_TOTAL_PINS \
316 (ATLAS7_PINCTRL_BANK_0_PINS + ATLAS7_PINCTRL_BANK_1_PINS)
317
318 /**
319 * Atlas7 GPIO Chip
320 */
321
322 #define NGPIO_OF_BANK 32
323 #define GPIO_TO_BANK(gpio) ((gpio) / NGPIO_OF_BANK)
324
325 /* Registers of GPIO Controllers */
326 #define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b))
327 #define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i))
328 #define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C)
329
330 /* Definition bits of GPIO Control Registers */
331 #define ATLAS7_GPIO_CTL_INTR_LOW_MASK BIT(0)
332 #define ATLAS7_GPIO_CTL_INTR_HIGH_MASK BIT(1)
333 #define ATLAS7_GPIO_CTL_INTR_TYPE_MASK BIT(2)
334 #define ATLAS7_GPIO_CTL_INTR_EN_MASK BIT(3)
335 #define ATLAS7_GPIO_CTL_INTR_STATUS_MASK BIT(4)
336 #define ATLAS7_GPIO_CTL_OUT_EN_MASK BIT(5)
337 #define ATLAS7_GPIO_CTL_DATAOUT_MASK BIT(6)
338 #define ATLAS7_GPIO_CTL_DATAIN_MASK BIT(7)
339
340 struct atlas7_gpio_bank {
341 int id;
342 int irq;
343 void __iomem *base;
344 unsigned int gpio_offset;
345 unsigned int ngpio;
346 const unsigned int *gpio_pins;
347 u32 sleep_data[NGPIO_OF_BANK];
348 };
349
350 struct atlas7_gpio_chip {
351 const char *name;
352 void __iomem *reg;
353 struct clk *clk;
354 int nbank;
355 raw_spinlock_t lock;
356 struct gpio_chip chip;
357 struct atlas7_gpio_bank banks[0];
358 };
359
360 /**
361 * @dev: a pointer back to containing device
362 * @virtbase: the offset to the controller in virtual memory
363 */
364 struct atlas7_pmx {
365 struct device *dev;
366 struct pinctrl_dev *pctl;
367 struct pinctrl_desc pctl_desc;
368 struct atlas7_pinctrl_data *pctl_data;
369 void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS];
370 void __iomem *sys2pci_base;
371 u32 status_ds[NUM_OF_IN_DISABLE_REG];
372 u32 status_dsv[NUM_OF_IN_DISABLE_REG];
373 struct atlas7_pad_status sleep_data[ATLAS7_PINCTRL_TOTAL_PINS];
374 };
375
376 /*
377 * Pad list for the pinmux subsystem
378 * refer to A7DA IO Summary - CS-314158-DD-4E.xls
379 */
380
381 /*Pads in IOC RTC & TOP */
382 static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
383 /* RTC PADs */
384 PINCTRL_PIN(0, "rtc_gpio_0"),
385 PINCTRL_PIN(1, "rtc_gpio_1"),
386 PINCTRL_PIN(2, "rtc_gpio_2"),
387 PINCTRL_PIN(3, "rtc_gpio_3"),
388 PINCTRL_PIN(4, "low_bat_ind_b"),
389 PINCTRL_PIN(5, "on_key_b"),
390 PINCTRL_PIN(6, "ext_on"),
391 PINCTRL_PIN(7, "mem_on"),
392 PINCTRL_PIN(8, "core_on"),
393 PINCTRL_PIN(9, "io_on"),
394 PINCTRL_PIN(10, "can0_tx"),
395 PINCTRL_PIN(11, "can0_rx"),
396 PINCTRL_PIN(12, "spi0_clk"),
397 PINCTRL_PIN(13, "spi0_cs_b"),
398 PINCTRL_PIN(14, "spi0_io_0"),
399 PINCTRL_PIN(15, "spi0_io_1"),
400 PINCTRL_PIN(16, "spi0_io_2"),
401 PINCTRL_PIN(17, "spi0_io_3"),
402
403 /* TOP PADs */
404 PINCTRL_PIN(18, "spi1_en"),
405 PINCTRL_PIN(19, "spi1_clk"),
406 PINCTRL_PIN(20, "spi1_din"),
407 PINCTRL_PIN(21, "spi1_dout"),
408 PINCTRL_PIN(22, "trg_spi_clk"),
409 PINCTRL_PIN(23, "trg_spi_di"),
410 PINCTRL_PIN(24, "trg_spi_do"),
411 PINCTRL_PIN(25, "trg_spi_cs_b"),
412 PINCTRL_PIN(26, "trg_acq_d1"),
413 PINCTRL_PIN(27, "trg_irq_b"),
414 PINCTRL_PIN(28, "trg_acq_d0"),
415 PINCTRL_PIN(29, "trg_acq_clk"),
416 PINCTRL_PIN(30, "trg_shutdown_b_out"),
417 PINCTRL_PIN(31, "sdio2_clk"),
418 PINCTRL_PIN(32, "sdio2_cmd"),
419 PINCTRL_PIN(33, "sdio2_dat_0"),
420 PINCTRL_PIN(34, "sdio2_dat_1"),
421 PINCTRL_PIN(35, "sdio2_dat_2"),
422 PINCTRL_PIN(36, "sdio2_dat_3"),
423 PINCTRL_PIN(37, "df_ad_7"),
424 PINCTRL_PIN(38, "df_ad_6"),
425 PINCTRL_PIN(39, "df_ad_5"),
426 PINCTRL_PIN(40, "df_ad_4"),
427 PINCTRL_PIN(41, "df_ad_3"),
428 PINCTRL_PIN(42, "df_ad_2"),
429 PINCTRL_PIN(43, "df_ad_1"),
430 PINCTRL_PIN(44, "df_ad_0"),
431 PINCTRL_PIN(45, "df_dqs"),
432 PINCTRL_PIN(46, "df_cle"),
433 PINCTRL_PIN(47, "df_ale"),
434 PINCTRL_PIN(48, "df_we_b"),
435 PINCTRL_PIN(49, "df_re_b"),
436 PINCTRL_PIN(50, "df_ry_by"),
437 PINCTRL_PIN(51, "df_cs_b_1"),
438 PINCTRL_PIN(52, "df_cs_b_0"),
439 PINCTRL_PIN(53, "l_pclk"),
440 PINCTRL_PIN(54, "l_lck"),
441 PINCTRL_PIN(55, "l_fck"),
442 PINCTRL_PIN(56, "l_de"),
443 PINCTRL_PIN(57, "ldd_0"),
444 PINCTRL_PIN(58, "ldd_1"),
445 PINCTRL_PIN(59, "ldd_2"),
446 PINCTRL_PIN(60, "ldd_3"),
447 PINCTRL_PIN(61, "ldd_4"),
448 PINCTRL_PIN(62, "ldd_5"),
449 PINCTRL_PIN(63, "ldd_6"),
450 PINCTRL_PIN(64, "ldd_7"),
451 PINCTRL_PIN(65, "ldd_8"),
452 PINCTRL_PIN(66, "ldd_9"),
453 PINCTRL_PIN(67, "ldd_10"),
454 PINCTRL_PIN(68, "ldd_11"),
455 PINCTRL_PIN(69, "ldd_12"),
456 PINCTRL_PIN(70, "ldd_13"),
457 PINCTRL_PIN(71, "ldd_14"),
458 PINCTRL_PIN(72, "ldd_15"),
459 PINCTRL_PIN(73, "lcd_gpio_20"),
460 PINCTRL_PIN(74, "vip_0"),
461 PINCTRL_PIN(75, "vip_1"),
462 PINCTRL_PIN(76, "vip_2"),
463 PINCTRL_PIN(77, "vip_3"),
464 PINCTRL_PIN(78, "vip_4"),
465 PINCTRL_PIN(79, "vip_5"),
466 PINCTRL_PIN(80, "vip_6"),
467 PINCTRL_PIN(81, "vip_7"),
468 PINCTRL_PIN(82, "vip_pxclk"),
469 PINCTRL_PIN(83, "vip_hsync"),
470 PINCTRL_PIN(84, "vip_vsync"),
471 PINCTRL_PIN(85, "sdio3_clk"),
472 PINCTRL_PIN(86, "sdio3_cmd"),
473 PINCTRL_PIN(87, "sdio3_dat_0"),
474 PINCTRL_PIN(88, "sdio3_dat_1"),
475 PINCTRL_PIN(89, "sdio3_dat_2"),
476 PINCTRL_PIN(90, "sdio3_dat_3"),
477 PINCTRL_PIN(91, "sdio5_clk"),
478 PINCTRL_PIN(92, "sdio5_cmd"),
479 PINCTRL_PIN(93, "sdio5_dat_0"),
480 PINCTRL_PIN(94, "sdio5_dat_1"),
481 PINCTRL_PIN(95, "sdio5_dat_2"),
482 PINCTRL_PIN(96, "sdio5_dat_3"),
483 PINCTRL_PIN(97, "rgmii_txd_0"),
484 PINCTRL_PIN(98, "rgmii_txd_1"),
485 PINCTRL_PIN(99, "rgmii_txd_2"),
486 PINCTRL_PIN(100, "rgmii_txd_3"),
487 PINCTRL_PIN(101, "rgmii_txclk"),
488 PINCTRL_PIN(102, "rgmii_tx_ctl"),
489 PINCTRL_PIN(103, "rgmii_rxd_0"),
490 PINCTRL_PIN(104, "rgmii_rxd_1"),
491 PINCTRL_PIN(105, "rgmii_rxd_2"),
492 PINCTRL_PIN(106, "rgmii_rxd_3"),
493 PINCTRL_PIN(107, "rgmii_rx_clk"),
494 PINCTRL_PIN(108, "rgmii_rxc_ctl"),
495 PINCTRL_PIN(109, "rgmii_mdio"),
496 PINCTRL_PIN(110, "rgmii_mdc"),
497 PINCTRL_PIN(111, "rgmii_intr_n"),
498 PINCTRL_PIN(112, "i2s_mclk"),
499 PINCTRL_PIN(113, "i2s_bclk"),
500 PINCTRL_PIN(114, "i2s_ws"),
501 PINCTRL_PIN(115, "i2s_dout0"),
502 PINCTRL_PIN(116, "i2s_dout1"),
503 PINCTRL_PIN(117, "i2s_dout2"),
504 PINCTRL_PIN(118, "i2s_din"),
505 PINCTRL_PIN(119, "gpio_0"),
506 PINCTRL_PIN(120, "gpio_1"),
507 PINCTRL_PIN(121, "gpio_2"),
508 PINCTRL_PIN(122, "gpio_3"),
509 PINCTRL_PIN(123, "gpio_4"),
510 PINCTRL_PIN(124, "gpio_5"),
511 PINCTRL_PIN(125, "gpio_6"),
512 PINCTRL_PIN(126, "gpio_7"),
513 PINCTRL_PIN(127, "sda_0"),
514 PINCTRL_PIN(128, "scl_0"),
515 PINCTRL_PIN(129, "coex_pio_0"),
516 PINCTRL_PIN(130, "coex_pio_1"),
517 PINCTRL_PIN(131, "coex_pio_2"),
518 PINCTRL_PIN(132, "coex_pio_3"),
519 PINCTRL_PIN(133, "uart0_tx"),
520 PINCTRL_PIN(134, "uart0_rx"),
521 PINCTRL_PIN(135, "uart1_tx"),
522 PINCTRL_PIN(136, "uart1_rx"),
523 PINCTRL_PIN(137, "uart3_tx"),
524 PINCTRL_PIN(138, "uart3_rx"),
525 PINCTRL_PIN(139, "uart4_tx"),
526 PINCTRL_PIN(140, "uart4_rx"),
527 PINCTRL_PIN(141, "usp0_clk"),
528 PINCTRL_PIN(142, "usp0_tx"),
529 PINCTRL_PIN(143, "usp0_rx"),
530 PINCTRL_PIN(144, "usp0_fs"),
531 PINCTRL_PIN(145, "usp1_clk"),
532 PINCTRL_PIN(146, "usp1_tx"),
533 PINCTRL_PIN(147, "usp1_rx"),
534 PINCTRL_PIN(148, "usp1_fs"),
535 PINCTRL_PIN(149, "lvds_tx0d4p"),
536 PINCTRL_PIN(150, "lvds_tx0d4n"),
537 PINCTRL_PIN(151, "lvds_tx0d3p"),
538 PINCTRL_PIN(152, "lvds_tx0d3n"),
539 PINCTRL_PIN(153, "lvds_tx0d2p"),
540 PINCTRL_PIN(154, "lvds_tx0d2n"),
541 PINCTRL_PIN(155, "lvds_tx0d1p"),
542 PINCTRL_PIN(156, "lvds_tx0d1n"),
543 PINCTRL_PIN(157, "lvds_tx0d0p"),
544 PINCTRL_PIN(158, "lvds_tx0d0n"),
545 PINCTRL_PIN(159, "jtag_tdo"),
546 PINCTRL_PIN(160, "jtag_tms"),
547 PINCTRL_PIN(161, "jtag_tck"),
548 PINCTRL_PIN(162, "jtag_tdi"),
549 PINCTRL_PIN(163, "jtag_trstn"),
550 };
551
552 static struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
553 /* The Configuration of IOC_RTC Pads */
554 PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
555 PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
556 PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0),
557 PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0),
558 PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0),
559 PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0),
560 PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0),
561 PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0),
562 PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0),
563 PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0),
564 PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0),
565 PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0),
566 PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0),
567 PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0),
568 PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0),
569 PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0),
570 PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0),
571 PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0),
572 /* The Configuration of IOC_TOP Pads */
573 PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0),
574 PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0),
575 PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0),
576 PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0),
577 PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0),
578 PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0),
579 PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0),
580 PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0),
581 PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0),
582 PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0),
583 PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0),
584 PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0),
585 PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0),
586 PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0),
587 PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0),
588 PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0),
589 PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0),
590 PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0),
591 PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0),
592 PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0),
593 PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0),
594 PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0),
595 PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0),
596 PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0),
597 PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0),
598 PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0),
599 PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0),
600 PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0),
601 PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0),
602 PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0),
603 PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0),
604 PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0),
605 PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0),
606 PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0),
607 PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0),
608 PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0),
609 PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0),
610 PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0),
611 PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0),
612 PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0),
613 PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0),
614 PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0),
615 PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0),
616 PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0),
617 PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0),
618 PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0),
619 PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0),
620 PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0),
621 PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0),
622 PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0),
623 PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0),
624 PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0),
625 PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0),
626 PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0),
627 PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0),
628 PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0),
629 PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0),
630 PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0),
631 PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0),
632 PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0),
633 PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0),
634 PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0),
635 PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0),
636 PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0),
637 PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0),
638 PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0),
639 PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0),
640 PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0),
641 PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0),
642 PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0),
643 PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0),
644 PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0),
645 PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0),
646 PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0),
647 PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0),
648 PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0),
649 PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0),
650 PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0),
651 PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0),
652 PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0),
653 PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0),
654 PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0),
655 PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0),
656 PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0),
657 PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0),
658 PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0),
659 PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0),
660 PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0),
661 PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0),
662 PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0),
663 PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0),
664 PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0),
665 PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0),
666 PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0),
667 PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0),
668 PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0),
669 PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0),
670 PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0),
671 PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0),
672 PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0),
673 PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0),
674 PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0),
675 PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0),
676 PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0),
677 PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0),
678 PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0),
679 PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0),
680 PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0),
681 PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0),
682 PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0),
683 PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0),
684 PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0),
685 PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0),
686 PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0),
687 PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0),
688 PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0),
689 PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0),
690 PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0),
691 PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0),
692 PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0),
693 PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0),
694 PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0),
695 PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0),
696 PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0),
697 PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0),
698 PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0),
699 PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0),
700 PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0),
701 PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0),
702 PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0),
703 PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0),
704 PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0),
705 PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1),
706 PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2),
707 PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3),
708 PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4),
709 PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5),
710 PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6),
711 PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7),
712 PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8),
713 PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9),
714 PADCONF(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0),
715 PADCONF(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0),
716 PADCONF(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0),
717 PADCONF(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0),
718 PADCONF(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0),
719 };
720
721 /* pin list of each pin group */
722 static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124,
723 125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, };
724 static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80,
725 81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
726 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, };
727 static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36,
728 85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94,
729 95, 96, 112, 113, 114, 115, 116, 117, 118, };
730 static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102,
731 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21,
732 141, 142, 143, 144, 145, 146, 147, 148, };
733 static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154,
734 151, 152, 149, 150, };
735 static const unsigned int jtag_uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40,
736 39, 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135,
737 136, 137, 138, 139, 140, 159, 160, 161, 162, 163, };
738 static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13,
739 14, 15, 16, 17, 9, };
740 static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, };
741 static const unsigned int audio_digmic_pins0[] = { 51, };
742 static const unsigned int audio_digmic_pins1[] = { 122, };
743 static const unsigned int audio_digmic_pins2[] = { 161, };
744 static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41,
745 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118,
746 115, 49, 50, 142, 143, 80, };
747 static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113,
748 114, };
749 static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, };
750 static const unsigned int audio_i2s_extclk_pins[] = { 112, };
751 static const unsigned int audio_spdif_out_pins0[] = { 112, };
752 static const unsigned int audio_spdif_out_pins1[] = { 116, };
753 static const unsigned int audio_spdif_out_pins2[] = { 142, };
754 static const unsigned int audio_uart0_basic_pins[] = { 143, 142, 141, 144, };
755 static const unsigned int audio_uart0_urfs_pins0[] = { 117, };
756 static const unsigned int audio_uart0_urfs_pins1[] = { 139, };
757 static const unsigned int audio_uart0_urfs_pins2[] = { 163, };
758 static const unsigned int audio_uart0_urfs_pins3[] = { 162, };
759 static const unsigned int audio_uart1_basic_pins[] = { 147, 146, 145, 148, };
760 static const unsigned int audio_uart1_urfs_pins0[] = { 117, };
761 static const unsigned int audio_uart1_urfs_pins1[] = { 140, };
762 static const unsigned int audio_uart1_urfs_pins2[] = { 163, };
763 static const unsigned int audio_uart2_urfs_pins0[] = { 139, };
764 static const unsigned int audio_uart2_urfs_pins1[] = { 163, };
765 static const unsigned int audio_uart2_urfs_pins2[] = { 96, };
766 static const unsigned int audio_uart2_urxd_pins0[] = { 20, };
767 static const unsigned int audio_uart2_urxd_pins1[] = { 109, };
768 static const unsigned int audio_uart2_urxd_pins2[] = { 93, };
769 static const unsigned int audio_uart2_usclk_pins0[] = { 19, };
770 static const unsigned int audio_uart2_usclk_pins1[] = { 101, };
771 static const unsigned int audio_uart2_usclk_pins2[] = { 91, };
772 static const unsigned int audio_uart2_utfs_pins0[] = { 18, };
773 static const unsigned int audio_uart2_utfs_pins1[] = { 111, };
774 static const unsigned int audio_uart2_utfs_pins2[] = { 94, };
775 static const unsigned int audio_uart2_utxd_pins0[] = { 21, };
776 static const unsigned int audio_uart2_utxd_pins1[] = { 110, };
777 static const unsigned int audio_uart2_utxd_pins2[] = { 92, };
778 static const unsigned int c_can_trnsvr_en_pins0[] = { 2, };
779 static const unsigned int c_can_trnsvr_en_pins1[] = { 0, };
780 static const unsigned int c_can_trnsvr_intr_pins[] = { 1, };
781 static const unsigned int c_can_trnsvr_stb_n_pins[] = { 3, };
782 static const unsigned int c0_can_rxd_trnsv0_pins[] = { 11, };
783 static const unsigned int c0_can_rxd_trnsv1_pins[] = { 2, };
784 static const unsigned int c0_can_txd_trnsv0_pins[] = { 10, };
785 static const unsigned int c0_can_txd_trnsv1_pins[] = { 3, };
786 static const unsigned int c1_can_rxd_pins0[] = { 138, };
787 static const unsigned int c1_can_rxd_pins1[] = { 147, };
788 static const unsigned int c1_can_rxd_pins2[] = { 2, };
789 static const unsigned int c1_can_rxd_pins3[] = { 162, };
790 static const unsigned int c1_can_txd_pins0[] = { 137, };
791 static const unsigned int c1_can_txd_pins1[] = { 146, };
792 static const unsigned int c1_can_txd_pins2[] = { 3, };
793 static const unsigned int c1_can_txd_pins3[] = { 161, };
794 static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68,
795 69, 70, 71, };
796 static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, };
797 static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, };
798 static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, };
799 static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, };
800 static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47,
801 49, 50, 54, 55, 56, };
802 static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, };
803 static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, };
804 static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75,
805 76, 77, };
806 static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, };
807 static const unsigned int clkc_pins0[] = { 30, 47, };
808 static const unsigned int clkc_pins1[] = { 78, 54, };
809 static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, };
810 static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, };
811 static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, };
812 static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, };
813 static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, };
814 static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78,
815 79, 80, 81, 83, 84, 73, 55, 56, };
816 static const unsigned int cvbs_dbg_test_pins0[] = { 57, };
817 static const unsigned int cvbs_dbg_test_pins1[] = { 58, };
818 static const unsigned int cvbs_dbg_test_pins2[] = { 59, };
819 static const unsigned int cvbs_dbg_test_pins3[] = { 60, };
820 static const unsigned int cvbs_dbg_test_pins4[] = { 61, };
821 static const unsigned int cvbs_dbg_test_pins5[] = { 62, };
822 static const unsigned int cvbs_dbg_test_pins6[] = { 63, };
823 static const unsigned int cvbs_dbg_test_pins7[] = { 64, };
824 static const unsigned int cvbs_dbg_test_pins8[] = { 65, };
825 static const unsigned int cvbs_dbg_test_pins9[] = { 66, };
826 static const unsigned int cvbs_dbg_test_pins10[] = { 67, };
827 static const unsigned int cvbs_dbg_test_pins11[] = { 68, };
828 static const unsigned int cvbs_dbg_test_pins12[] = { 69, };
829 static const unsigned int cvbs_dbg_test_pins13[] = { 70, };
830 static const unsigned int cvbs_dbg_test_pins14[] = { 71, };
831 static const unsigned int cvbs_dbg_test_pins15[] = { 72, };
832 static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125,
833 120, };
834 static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61,
835 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, };
836 static const unsigned int gn_gnss_eclk_pins[] = { 113, };
837 static const unsigned int gn_gnss_irq1_pins0[] = { 112, };
838 static const unsigned int gn_gnss_irq2_pins0[] = { 118, };
839 static const unsigned int gn_gnss_tm_pins[] = { 115, };
840 static const unsigned int gn_gnss_tsync_pins[] = { 114, };
841 static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40,
842 39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, };
843 static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, };
844 static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, };
845 static const unsigned int gn_trg_shutdown_pins0[] = { 30, };
846 static const unsigned int gn_trg_shutdown_pins1[] = { 83, };
847 static const unsigned int gn_trg_shutdown_pins2[] = { 117, };
848 static const unsigned int gn_trg_shutdown_pins3[] = { 123, };
849 static const unsigned int i2c0_pins[] = { 128, 127, };
850 static const unsigned int i2c1_pins[] = { 126, 125, };
851 static const unsigned int i2s0_pins[] = { 91, 93, 94, 92, };
852 static const unsigned int i2s1_basic_pins[] = { 95, 96, };
853 static const unsigned int i2s1_rxd0_pins0[] = { 61, };
854 static const unsigned int i2s1_rxd0_pins1[] = { 131, };
855 static const unsigned int i2s1_rxd0_pins2[] = { 129, };
856 static const unsigned int i2s1_rxd0_pins3[] = { 117, };
857 static const unsigned int i2s1_rxd0_pins4[] = { 83, };
858 static const unsigned int i2s1_rxd1_pins0[] = { 72, };
859 static const unsigned int i2s1_rxd1_pins1[] = { 132, };
860 static const unsigned int i2s1_rxd1_pins2[] = { 130, };
861 static const unsigned int i2s1_rxd1_pins3[] = { 118, };
862 static const unsigned int i2s1_rxd1_pins4[] = { 84, };
863 static const unsigned int jtag_jt_dbg_nsrst_pins[] = { 125, };
864 static const unsigned int jtag_ntrst_pins0[] = { 4, };
865 static const unsigned int jtag_ntrst_pins1[] = { 163, };
866 static const unsigned int jtag_swdiotms_pins0[] = { 2, };
867 static const unsigned int jtag_swdiotms_pins1[] = { 160, };
868 static const unsigned int jtag_tck_pins0[] = { 0, };
869 static const unsigned int jtag_tck_pins1[] = { 161, };
870 static const unsigned int jtag_tdi_pins0[] = { 1, };
871 static const unsigned int jtag_tdi_pins1[] = { 162, };
872 static const unsigned int jtag_tdo_pins0[] = { 3, };
873 static const unsigned int jtag_tdo_pins1[] = { 159, };
874 static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, };
875 static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64,
876 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80,
877 81, 56, 53, };
878 static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63,
879 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, };
880 static const unsigned int ld_ldd_fck_pins[] = { 55, };
881 static const unsigned int ld_ldd_lck_pins[] = { 54, };
882 static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61,
883 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, };
884 static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154,
885 155, 156, 157, 158, };
886 static const unsigned int nd_df_basic_pins[] = { 44, 43, 42, 41, 40, 39, 38,
887 37, 47, 46, 52, 45, 49, 50, 48, };
888 static const unsigned int nd_df_wp_pins[] = { 124, };
889 static const unsigned int nd_df_cs_pins[] = { 51, };
890 static const unsigned int ps_pins[] = { 120, 119, 121, };
891 static const unsigned int ps_no_dir_pins[] = { 119, };
892 static const unsigned int pwc_core_on_pins[] = { 8, };
893 static const unsigned int pwc_ext_on_pins[] = { 6, };
894 static const unsigned int pwc_gpio3_clk_pins[] = { 3, };
895 static const unsigned int pwc_io_on_pins[] = { 9, };
896 static const unsigned int pwc_lowbatt_b_pins0[] = { 4, };
897 static const unsigned int pwc_mem_on_pins[] = { 7, };
898 static const unsigned int pwc_on_key_b_pins0[] = { 5, };
899 static const unsigned int pwc_wakeup_src0_pins[] = { 0, };
900 static const unsigned int pwc_wakeup_src1_pins[] = { 1, };
901 static const unsigned int pwc_wakeup_src2_pins[] = { 2, };
902 static const unsigned int pwc_wakeup_src3_pins[] = { 3, };
903 static const unsigned int pw_cko0_pins0[] = { 123, };
904 static const unsigned int pw_cko0_pins1[] = { 101, };
905 static const unsigned int pw_cko0_pins2[] = { 82, };
906 static const unsigned int pw_cko0_pins3[] = { 162, };
907 static const unsigned int pw_cko1_pins0[] = { 124, };
908 static const unsigned int pw_cko1_pins1[] = { 110, };
909 static const unsigned int pw_cko1_pins2[] = { 163, };
910 static const unsigned int pw_i2s01_clk_pins0[] = { 125, };
911 static const unsigned int pw_i2s01_clk_pins1[] = { 117, };
912 static const unsigned int pw_i2s01_clk_pins2[] = { 132, };
913 static const unsigned int pw_pwm0_pins0[] = { 119, };
914 static const unsigned int pw_pwm0_pins1[] = { 159, };
915 static const unsigned int pw_pwm1_pins0[] = { 120, };
916 static const unsigned int pw_pwm1_pins1[] = { 160, };
917 static const unsigned int pw_pwm1_pins2[] = { 131, };
918 static const unsigned int pw_pwm2_pins0[] = { 121, };
919 static const unsigned int pw_pwm2_pins1[] = { 98, };
920 static const unsigned int pw_pwm2_pins2[] = { 161, };
921 static const unsigned int pw_pwm3_pins0[] = { 122, };
922 static const unsigned int pw_pwm3_pins1[] = { 73, };
923 static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, };
924 static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, };
925 static const unsigned int pw_pwm_cpu_vol_pins2[] = { 161, };
926 static const unsigned int pw_backlight_pins0[] = { 122, };
927 static const unsigned int pw_backlight_pins1[] = { 73, };
928 static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107,
929 102, 97, 98, 99, 100, 101, };
930 static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, };
931 static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, };
932 static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, };
933 static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, };
934 static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38,
935 37, };
936 static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, };
937 static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38,
938 37, };
939 static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, };
940 static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, };
941 static const unsigned int sd2_basic_pins[] = { 31, 32, 33, 34, 35, 36, };
942 static const unsigned int sd2_cdb_pins0[] = { 124, };
943 static const unsigned int sd2_cdb_pins1[] = { 161, };
944 static const unsigned int sd2_wpb_pins0[] = { 123, };
945 static const unsigned int sd2_wpb_pins1[] = { 163, };
946 static const unsigned int sd3_9_pins[] = { 85, 86, 87, 88, 89, 90, };
947 static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, };
948 static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, };
949 static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, };
950 static const unsigned int sp0_ext_ldo_on_pins[] = { 4, };
951 static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, };
952 static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, };
953 static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61,
954 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, };
955 static const unsigned int uart0_pins[] = { 121, 120, 134, 133, };
956 static const unsigned int uart0_nopause_pins[] = { 134, 133, };
957 static const unsigned int uart1_pins[] = { 136, 135, };
958 static const unsigned int uart2_cts_pins0[] = { 132, };
959 static const unsigned int uart2_cts_pins1[] = { 162, };
960 static const unsigned int uart2_rts_pins0[] = { 131, };
961 static const unsigned int uart2_rts_pins1[] = { 161, };
962 static const unsigned int uart2_rxd_pins0[] = { 11, };
963 static const unsigned int uart2_rxd_pins1[] = { 160, };
964 static const unsigned int uart2_rxd_pins2[] = { 130, };
965 static const unsigned int uart2_txd_pins0[] = { 10, };
966 static const unsigned int uart2_txd_pins1[] = { 159, };
967 static const unsigned int uart2_txd_pins2[] = { 129, };
968 static const unsigned int uart3_cts_pins0[] = { 125, };
969 static const unsigned int uart3_cts_pins1[] = { 111, };
970 static const unsigned int uart3_cts_pins2[] = { 140, };
971 static const unsigned int uart3_rts_pins0[] = { 126, };
972 static const unsigned int uart3_rts_pins1[] = { 109, };
973 static const unsigned int uart3_rts_pins2[] = { 139, };
974 static const unsigned int uart3_rxd_pins0[] = { 138, };
975 static const unsigned int uart3_rxd_pins1[] = { 84, };
976 static const unsigned int uart3_rxd_pins2[] = { 162, };
977 static const unsigned int uart3_txd_pins0[] = { 137, };
978 static const unsigned int uart3_txd_pins1[] = { 83, };
979 static const unsigned int uart3_txd_pins2[] = { 161, };
980 static const unsigned int uart4_basic_pins[] = { 140, 139, };
981 static const unsigned int uart4_cts_pins0[] = { 122, };
982 static const unsigned int uart4_cts_pins1[] = { 100, };
983 static const unsigned int uart4_cts_pins2[] = { 117, };
984 static const unsigned int uart4_rts_pins0[] = { 123, };
985 static const unsigned int uart4_rts_pins1[] = { 99, };
986 static const unsigned int uart4_rts_pins2[] = { 116, };
987 static const unsigned int usb0_drvvbus_pins0[] = { 51, };
988 static const unsigned int usb0_drvvbus_pins1[] = { 162, };
989 static const unsigned int usb1_drvvbus_pins0[] = { 134, };
990 static const unsigned int usb1_drvvbus_pins1[] = { 163, };
991 static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63,
992 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86,
993 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, };
994 static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81,
995 82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, };
996 static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80,
997 81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98,
998 99, 100, };
999 static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79,
1000 80, 81, 82, 83, 84, };
1001 static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 103, 104,
1002 105, 106, 107, 102, 97, 98, };
1003
1004 /* definition of pin group table */
1005 static struct atlas7_pin_group altas7_pin_groups[] = {
1006 GROUP("gnss_gpio_grp", gnss_gpio_pins),
1007 GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
1008 GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
1009 GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins),
1010 GROUP("lvds_gpio_grp", lvds_gpio_pins),
1011 GROUP("jtag_uart_nand_gpio_grp", jtag_uart_nand_gpio_pins),
1012 GROUP("rtc_gpio_grp", rtc_gpio_pins),
1013 GROUP("audio_ac97_grp", audio_ac97_pins),
1014 GROUP("audio_digmic_grp0", audio_digmic_pins0),
1015 GROUP("audio_digmic_grp1", audio_digmic_pins1),
1016 GROUP("audio_digmic_grp2", audio_digmic_pins2),
1017 GROUP("audio_func_dbg_grp", audio_func_dbg_pins),
1018 GROUP("audio_i2s_grp", audio_i2s_pins),
1019 GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins),
1020 GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins),
1021 GROUP("audio_spdif_out_grp0", audio_spdif_out_pins0),
1022 GROUP("audio_spdif_out_grp1", audio_spdif_out_pins1),
1023 GROUP("audio_spdif_out_grp2", audio_spdif_out_pins2),
1024 GROUP("audio_uart0_basic_grp", audio_uart0_basic_pins),
1025 GROUP("audio_uart0_urfs_grp0", audio_uart0_urfs_pins0),
1026 GROUP("audio_uart0_urfs_grp1", audio_uart0_urfs_pins1),
1027 GROUP("audio_uart0_urfs_grp2", audio_uart0_urfs_pins2),
1028 GROUP("audio_uart0_urfs_grp3", audio_uart0_urfs_pins3),
1029 GROUP("audio_uart1_basic_grp", audio_uart1_basic_pins),
1030 GROUP("audio_uart1_urfs_grp0", audio_uart1_urfs_pins0),
1031 GROUP("audio_uart1_urfs_grp1", audio_uart1_urfs_pins1),
1032 GROUP("audio_uart1_urfs_grp2", audio_uart1_urfs_pins2),
1033 GROUP("audio_uart2_urfs_grp0", audio_uart2_urfs_pins0),
1034 GROUP("audio_uart2_urfs_grp1", audio_uart2_urfs_pins1),
1035 GROUP("audio_uart2_urfs_grp2", audio_uart2_urfs_pins2),
1036 GROUP("audio_uart2_urxd_grp0", audio_uart2_urxd_pins0),
1037 GROUP("audio_uart2_urxd_grp1", audio_uart2_urxd_pins1),
1038 GROUP("audio_uart2_urxd_grp2", audio_uart2_urxd_pins2),
1039 GROUP("audio_uart2_usclk_grp0", audio_uart2_usclk_pins0),
1040 GROUP("audio_uart2_usclk_grp1", audio_uart2_usclk_pins1),
1041 GROUP("audio_uart2_usclk_grp2", audio_uart2_usclk_pins2),
1042 GROUP("audio_uart2_utfs_grp0", audio_uart2_utfs_pins0),
1043 GROUP("audio_uart2_utfs_grp1", audio_uart2_utfs_pins1),
1044 GROUP("audio_uart2_utfs_grp2", audio_uart2_utfs_pins2),
1045 GROUP("audio_uart2_utxd_grp0", audio_uart2_utxd_pins0),
1046 GROUP("audio_uart2_utxd_grp1", audio_uart2_utxd_pins1),
1047 GROUP("audio_uart2_utxd_grp2", audio_uart2_utxd_pins2),
1048 GROUP("c_can_trnsvr_en_grp0", c_can_trnsvr_en_pins0),
1049 GROUP("c_can_trnsvr_en_grp1", c_can_trnsvr_en_pins1),
1050 GROUP("c_can_trnsvr_intr_grp", c_can_trnsvr_intr_pins),
1051 GROUP("c_can_trnsvr_stb_n_grp", c_can_trnsvr_stb_n_pins),
1052 GROUP("c0_can_rxd_trnsv0_grp", c0_can_rxd_trnsv0_pins),
1053 GROUP("c0_can_rxd_trnsv1_grp", c0_can_rxd_trnsv1_pins),
1054 GROUP("c0_can_txd_trnsv0_grp", c0_can_txd_trnsv0_pins),
1055 GROUP("c0_can_txd_trnsv1_grp", c0_can_txd_trnsv1_pins),
1056 GROUP("c1_can_rxd_grp0", c1_can_rxd_pins0),
1057 GROUP("c1_can_rxd_grp1", c1_can_rxd_pins1),
1058 GROUP("c1_can_rxd_grp2", c1_can_rxd_pins2),
1059 GROUP("c1_can_rxd_grp3", c1_can_rxd_pins3),
1060 GROUP("c1_can_txd_grp0", c1_can_txd_pins0),
1061 GROUP("c1_can_txd_grp1", c1_can_txd_pins1),
1062 GROUP("c1_can_txd_grp2", c1_can_txd_pins2),
1063 GROUP("c1_can_txd_grp3", c1_can_txd_pins3),
1064 GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins),
1065 GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins),
1066 GROUP("ca_coex_grp", ca_coex_pins),
1067 GROUP("ca_curator_lpc_grp", ca_curator_lpc_pins),
1068 GROUP("ca_pcm_debug_grp", ca_pcm_debug_pins),
1069 GROUP("ca_pio_grp", ca_pio_pins),
1070 GROUP("ca_sdio_debug_grp", ca_sdio_debug_pins),
1071 GROUP("ca_spi_grp", ca_spi_pins),
1072 GROUP("ca_trb_grp", ca_trb_pins),
1073 GROUP("ca_uart_debug_grp", ca_uart_debug_pins),
1074 GROUP("clkc_grp0", clkc_pins0),
1075 GROUP("clkc_grp1", clkc_pins1),
1076 GROUP("gn_gnss_i2c_grp", gn_gnss_i2c_pins),
1077 GROUP("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins),
1078 GROUP("gn_gnss_uart_grp", gn_gnss_uart_pins),
1079 GROUP("gn_trg_spi_grp0", gn_trg_spi_pins0),
1080 GROUP("gn_trg_spi_grp1", gn_trg_spi_pins1),
1081 GROUP("cvbs_dbg_grp", cvbs_dbg_pins),
1082 GROUP("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0),
1083 GROUP("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1),
1084 GROUP("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2),
1085 GROUP("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3),
1086 GROUP("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4),
1087 GROUP("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5),
1088 GROUP("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6),
1089 GROUP("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7),
1090 GROUP("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8),
1091 GROUP("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9),
1092 GROUP("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10),
1093 GROUP("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11),
1094 GROUP("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12),
1095 GROUP("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13),
1096 GROUP("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14),
1097 GROUP("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15),
1098 GROUP("gn_gnss_power_grp", gn_gnss_power_pins),
1099 GROUP("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins),
1100 GROUP("gn_gnss_eclk_grp", gn_gnss_eclk_pins),
1101 GROUP("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0),
1102 GROUP("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0),
1103 GROUP("gn_gnss_tm_grp", gn_gnss_tm_pins),
1104 GROUP("gn_gnss_tsync_grp", gn_gnss_tsync_pins),
1105 GROUP("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins),
1106 GROUP("gn_trg_grp0", gn_trg_pins0),
1107 GROUP("gn_trg_grp1", gn_trg_pins1),
1108 GROUP("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0),
1109 GROUP("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1),
1110 GROUP("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2),
1111 GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3),
1112 GROUP("i2c0_grp", i2c0_pins),
1113 GROUP("i2c1_grp", i2c1_pins),
1114 GROUP("i2s0_grp", i2s0_pins),
1115 GROUP("i2s1_basic_grp", i2s1_basic_pins),
1116 GROUP("i2s1_rxd0_grp0", i2s1_rxd0_pins0),
1117 GROUP("i2s1_rxd0_grp1", i2s1_rxd0_pins1),
1118 GROUP("i2s1_rxd0_grp2", i2s1_rxd0_pins2),
1119 GROUP("i2s1_rxd0_grp3", i2s1_rxd0_pins3),
1120 GROUP("i2s1_rxd0_grp4", i2s1_rxd0_pins4),
1121 GROUP("i2s1_rxd1_grp0", i2s1_rxd1_pins0),
1122 GROUP("i2s1_rxd1_grp1", i2s1_rxd1_pins1),
1123 GROUP("i2s1_rxd1_grp2", i2s1_rxd1_pins2),
1124 GROUP("i2s1_rxd1_grp3", i2s1_rxd1_pins3),
1125 GROUP("i2s1_rxd1_grp4", i2s1_rxd1_pins4),
1126 GROUP("jtag_jt_dbg_nsrst_grp", jtag_jt_dbg_nsrst_pins),
1127 GROUP("jtag_ntrst_grp0", jtag_ntrst_pins0),
1128 GROUP("jtag_ntrst_grp1", jtag_ntrst_pins1),
1129 GROUP("jtag_swdiotms_grp0", jtag_swdiotms_pins0),
1130 GROUP("jtag_swdiotms_grp1", jtag_swdiotms_pins1),
1131 GROUP("jtag_tck_grp0", jtag_tck_pins0),
1132 GROUP("jtag_tck_grp1", jtag_tck_pins1),
1133 GROUP("jtag_tdi_grp0", jtag_tdi_pins0),
1134 GROUP("jtag_tdi_grp1", jtag_tdi_pins1),
1135 GROUP("jtag_tdo_grp0", jtag_tdo_pins0),
1136 GROUP("jtag_tdo_grp1", jtag_tdo_pins1),
1137 GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0),
1138 GROUP("ld_ldd_grp", ld_ldd_pins),
1139 GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins),
1140 GROUP("ld_ldd_fck_grp", ld_ldd_fck_pins),
1141 GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins),
1142 GROUP("lr_lcdrom_grp", lr_lcdrom_pins),
1143 GROUP("lvds_analog_grp", lvds_analog_pins),
1144 GROUP("nd_df_basic_grp", nd_df_basic_pins),
1145 GROUP("nd_df_wp_grp", nd_df_wp_pins),
1146 GROUP("nd_df_cs_grp", nd_df_cs_pins),
1147 GROUP("ps_grp", ps_pins),
1148 GROUP("ps_no_dir_grp", ps_no_dir_pins),
1149 GROUP("pwc_core_on_grp", pwc_core_on_pins),
1150 GROUP("pwc_ext_on_grp", pwc_ext_on_pins),
1151 GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins),
1152 GROUP("pwc_io_on_grp", pwc_io_on_pins),
1153 GROUP("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0),
1154 GROUP("pwc_mem_on_grp", pwc_mem_on_pins),
1155 GROUP("pwc_on_key_b_grp0", pwc_on_key_b_pins0),
1156 GROUP("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins),
1157 GROUP("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins),
1158 GROUP("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins),
1159 GROUP("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins),
1160 GROUP("pw_cko0_grp0", pw_cko0_pins0),
1161 GROUP("pw_cko0_grp1", pw_cko0_pins1),
1162 GROUP("pw_cko0_grp2", pw_cko0_pins2),
1163 GROUP("pw_cko0_grp3", pw_cko0_pins3),
1164 GROUP("pw_cko1_grp0", pw_cko1_pins0),
1165 GROUP("pw_cko1_grp1", pw_cko1_pins1),
1166 GROUP("pw_cko1_grp2", pw_cko1_pins2),
1167 GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0),
1168 GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1),
1169 GROUP("pw_i2s01_clk_grp2", pw_i2s01_clk_pins2),
1170 GROUP("pw_pwm0_grp0", pw_pwm0_pins0),
1171 GROUP("pw_pwm0_grp1", pw_pwm0_pins1),
1172 GROUP("pw_pwm1_grp0", pw_pwm1_pins0),
1173 GROUP("pw_pwm1_grp1", pw_pwm1_pins1),
1174 GROUP("pw_pwm1_grp2", pw_pwm1_pins2),
1175 GROUP("pw_pwm2_grp0", pw_pwm2_pins0),
1176 GROUP("pw_pwm2_grp1", pw_pwm2_pins1),
1177 GROUP("pw_pwm2_grp2", pw_pwm2_pins2),
1178 GROUP("pw_pwm3_grp0", pw_pwm3_pins0),
1179 GROUP("pw_pwm3_grp1", pw_pwm3_pins1),
1180 GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0),
1181 GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1),
1182 GROUP("pw_pwm_cpu_vol_grp2", pw_pwm_cpu_vol_pins2),
1183 GROUP("pw_backlight_grp0", pw_backlight_pins0),
1184 GROUP("pw_backlight_grp1", pw_backlight_pins1),
1185 GROUP("rg_eth_mac_grp", rg_eth_mac_pins),
1186 GROUP("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins),
1187 GROUP("rg_rgmii_mac_grp", rg_rgmii_mac_pins),
1188 GROUP("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0),
1189 GROUP("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1),
1190 GROUP("sd0_grp", sd0_pins),
1191 GROUP("sd0_4bit_grp", sd0_4bit_pins),
1192 GROUP("sd1_grp", sd1_pins),
1193 GROUP("sd1_4bit_grp0", sd1_4bit_pins0),
1194 GROUP("sd1_4bit_grp1", sd1_4bit_pins1),
1195 GROUP("sd2_basic_grp", sd2_basic_pins),
1196 GROUP("sd2_cdb_grp0", sd2_cdb_pins0),
1197 GROUP("sd2_cdb_grp1", sd2_cdb_pins1),
1198 GROUP("sd2_wpb_grp0", sd2_wpb_pins0),
1199 GROUP("sd2_wpb_grp1", sd2_wpb_pins1),
1200 GROUP("sd3_9_grp", sd3_9_pins),
1201 GROUP("sd5_grp", sd5_pins),
1202 GROUP("sd6_grp0", sd6_pins0),
1203 GROUP("sd6_grp1", sd6_pins1),
1204 GROUP("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins),
1205 GROUP("sp0_qspi_grp", sp0_qspi_pins),
1206 GROUP("sp1_spi_grp", sp1_spi_pins),
1207 GROUP("tpiu_trace_grp", tpiu_trace_pins),
1208 GROUP("uart0_grp", uart0_pins),
1209 GROUP("uart0_nopause_grp", uart0_nopause_pins),
1210 GROUP("uart1_grp", uart1_pins),
1211 GROUP("uart2_cts_grp0", uart2_cts_pins0),
1212 GROUP("uart2_cts_grp1", uart2_cts_pins1),
1213 GROUP("uart2_rts_grp0", uart2_rts_pins0),
1214 GROUP("uart2_rts_grp1", uart2_rts_pins1),
1215 GROUP("uart2_rxd_grp0", uart2_rxd_pins0),
1216 GROUP("uart2_rxd_grp1", uart2_rxd_pins1),
1217 GROUP("uart2_rxd_grp2", uart2_rxd_pins2),
1218 GROUP("uart2_txd_grp0", uart2_txd_pins0),
1219 GROUP("uart2_txd_grp1", uart2_txd_pins1),
1220 GROUP("uart2_txd_grp2", uart2_txd_pins2),
1221 GROUP("uart3_cts_grp0", uart3_cts_pins0),
1222 GROUP("uart3_cts_grp1", uart3_cts_pins1),
1223 GROUP("uart3_cts_grp2", uart3_cts_pins2),
1224 GROUP("uart3_rts_grp0", uart3_rts_pins0),
1225 GROUP("uart3_rts_grp1", uart3_rts_pins1),
1226 GROUP("uart3_rts_grp2", uart3_rts_pins2),
1227 GROUP("uart3_rxd_grp0", uart3_rxd_pins0),
1228 GROUP("uart3_rxd_grp1", uart3_rxd_pins1),
1229 GROUP("uart3_rxd_grp2", uart3_rxd_pins2),
1230 GROUP("uart3_txd_grp0", uart3_txd_pins0),
1231 GROUP("uart3_txd_grp1", uart3_txd_pins1),
1232 GROUP("uart3_txd_grp2", uart3_txd_pins2),
1233 GROUP("uart4_basic_grp", uart4_basic_pins),
1234 GROUP("uart4_cts_grp0", uart4_cts_pins0),
1235 GROUP("uart4_cts_grp1", uart4_cts_pins1),
1236 GROUP("uart4_cts_grp2", uart4_cts_pins2),
1237 GROUP("uart4_rts_grp0", uart4_rts_pins0),
1238 GROUP("uart4_rts_grp1", uart4_rts_pins1),
1239 GROUP("uart4_rts_grp2", uart4_rts_pins2),
1240 GROUP("usb0_drvvbus_grp0", usb0_drvvbus_pins0),
1241 GROUP("usb0_drvvbus_grp1", usb0_drvvbus_pins1),
1242 GROUP("usb1_drvvbus_grp0", usb1_drvvbus_pins0),
1243 GROUP("usb1_drvvbus_grp1", usb1_drvvbus_pins1),
1244 GROUP("visbus_dout_grp", visbus_dout_pins),
1245 GROUP("vi_vip1_grp", vi_vip1_pins),
1246 GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins),
1247 GROUP("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins),
1248 GROUP("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins),
1249 };
1250
1251 /* How many groups that a function can use */
1252 static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", };
1253 static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", };
1254 static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", };
1255 static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", };
1256 static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", };
1257 static const char * const jtag_uart_nand_gpio_grp[] = {
1258 "jtag_uart_nand_gpio_grp", };
1259 static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", };
1260 static const char * const audio_ac97_grp[] = { "audio_ac97_grp", };
1261 static const char * const audio_digmic_grp0[] = { "audio_digmic_grp0", };
1262 static const char * const audio_digmic_grp1[] = { "audio_digmic_grp1", };
1263 static const char * const audio_digmic_grp2[] = { "audio_digmic_grp2", };
1264 static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", };
1265 static const char * const audio_i2s_grp[] = { "audio_i2s_grp", };
1266 static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", };
1267 static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", };
1268 static const char * const audio_spdif_out_grp0[] = { "audio_spdif_out_grp0", };
1269 static const char * const audio_spdif_out_grp1[] = { "audio_spdif_out_grp1", };
1270 static const char * const audio_spdif_out_grp2[] = { "audio_spdif_out_grp2", };
1271 static const char * const audio_uart0_basic_grp[] = {
1272 "audio_uart0_basic_grp", };
1273 static const char * const audio_uart0_urfs_grp0[] = {
1274 "audio_uart0_urfs_grp0", };
1275 static const char * const audio_uart0_urfs_grp1[] = {
1276 "audio_uart0_urfs_grp1", };
1277 static const char * const audio_uart0_urfs_grp2[] = {
1278 "audio_uart0_urfs_grp2", };
1279 static const char * const audio_uart0_urfs_grp3[] = {
1280 "audio_uart0_urfs_grp3", };
1281 static const char * const audio_uart1_basic_grp[] = {
1282 "audio_uart1_basic_grp", };
1283 static const char * const audio_uart1_urfs_grp0[] = {
1284 "audio_uart1_urfs_grp0", };
1285 static const char * const audio_uart1_urfs_grp1[] = {
1286 "audio_uart1_urfs_grp1", };
1287 static const char * const audio_uart1_urfs_grp2[] = {
1288 "audio_uart1_urfs_grp2", };
1289 static const char * const audio_uart2_urfs_grp0[] = {
1290 "audio_uart2_urfs_grp0", };
1291 static const char * const audio_uart2_urfs_grp1[] = {
1292 "audio_uart2_urfs_grp1", };
1293 static const char * const audio_uart2_urfs_grp2[] = {
1294 "audio_uart2_urfs_grp2", };
1295 static const char * const audio_uart2_urxd_grp0[] = {
1296 "audio_uart2_urxd_grp0", };
1297 static const char * const audio_uart2_urxd_grp1[] = {
1298 "audio_uart2_urxd_grp1", };
1299 static const char * const audio_uart2_urxd_grp2[] = {
1300 "audio_uart2_urxd_grp2", };
1301 static const char * const audio_uart2_usclk_grp0[] = {
1302 "audio_uart2_usclk_grp0", };
1303 static const char * const audio_uart2_usclk_grp1[] = {
1304 "audio_uart2_usclk_grp1", };
1305 static const char * const audio_uart2_usclk_grp2[] = {
1306 "audio_uart2_usclk_grp2", };
1307 static const char * const audio_uart2_utfs_grp0[] = {
1308 "audio_uart2_utfs_grp0", };
1309 static const char * const audio_uart2_utfs_grp1[] = {
1310 "audio_uart2_utfs_grp1", };
1311 static const char * const audio_uart2_utfs_grp2[] = {
1312 "audio_uart2_utfs_grp2", };
1313 static const char * const audio_uart2_utxd_grp0[] = {
1314 "audio_uart2_utxd_grp0", };
1315 static const char * const audio_uart2_utxd_grp1[] = {
1316 "audio_uart2_utxd_grp1", };
1317 static const char * const audio_uart2_utxd_grp2[] = {
1318 "audio_uart2_utxd_grp2", };
1319 static const char * const c_can_trnsvr_en_grp0[] = { "c_can_trnsvr_en_grp0", };
1320 static const char * const c_can_trnsvr_en_grp1[] = { "c_can_trnsvr_en_grp1", };
1321 static const char * const c_can_trnsvr_intr_grp[] = {
1322 "c_can_trnsvr_intr_grp", };
1323 static const char * const c_can_trnsvr_stb_n_grp[] = {
1324 "c_can_trnsvr_stb_n_grp", };
1325 static const char * const c0_can_rxd_trnsv0_grp[] = {
1326 "c0_can_rxd_trnsv0_grp", };
1327 static const char * const c0_can_rxd_trnsv1_grp[] = {
1328 "c0_can_rxd_trnsv1_grp", };
1329 static const char * const c0_can_txd_trnsv0_grp[] = {
1330 "c0_can_txd_trnsv0_grp", };
1331 static const char * const c0_can_txd_trnsv1_grp[] = {
1332 "c0_can_txd_trnsv1_grp", };
1333 static const char * const c1_can_rxd_grp0[] = { "c1_can_rxd_grp0", };
1334 static const char * const c1_can_rxd_grp1[] = { "c1_can_rxd_grp1", };
1335 static const char * const c1_can_rxd_grp2[] = { "c1_can_rxd_grp2", };
1336 static const char * const c1_can_rxd_grp3[] = { "c1_can_rxd_grp3", };
1337 static const char * const c1_can_txd_grp0[] = { "c1_can_txd_grp0", };
1338 static const char * const c1_can_txd_grp1[] = { "c1_can_txd_grp1", };
1339 static const char * const c1_can_txd_grp2[] = { "c1_can_txd_grp2", };
1340 static const char * const c1_can_txd_grp3[] = { "c1_can_txd_grp3", };
1341 static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", };
1342 static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", };
1343 static const char * const ca_coex_grp[] = { "ca_coex_grp", };
1344 static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", };
1345 static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", };
1346 static const char * const ca_pio_grp[] = { "ca_pio_grp", };
1347 static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", };
1348 static const char * const ca_spi_grp[] = { "ca_spi_grp", };
1349 static const char * const ca_trb_grp[] = { "ca_trb_grp", };
1350 static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", };
1351 static const char * const clkc_grp0[] = { "clkc_grp0", };
1352 static const char * const clkc_grp1[] = { "clkc_grp1", };
1353 static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", };
1354 static const char * const gn_gnss_uart_nopause_grp[] = {
1355 "gn_gnss_uart_nopause_grp", };
1356 static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", };
1357 static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", };
1358 static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", };
1359 static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", };
1360 static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", };
1361 static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", };
1362 static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", };
1363 static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", };
1364 static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", };
1365 static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", };
1366 static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", };
1367 static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", };
1368 static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", };
1369 static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", };
1370 static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", };
1371 static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", };
1372 static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", };
1373 static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", };
1374 static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", };
1375 static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", };
1376 static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", };
1377 static const char * const gn_gnss_sw_status_grp[] = {
1378 "gn_gnss_sw_status_grp", };
1379 static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", };
1380 static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", };
1381 static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", };
1382 static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", };
1383 static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", };
1384 static const char * const gn_io_gnsssys_sw_cfg_grp[] = {
1385 "gn_io_gnsssys_sw_cfg_grp", };
1386 static const char * const gn_trg_grp0[] = { "gn_trg_grp0", };
1387 static const char * const gn_trg_grp1[] = { "gn_trg_grp1", };
1388 static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", };
1389 static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", };
1390 static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", };
1391 static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", };
1392 static const char * const i2c0_grp[] = { "i2c0_grp", };
1393 static const char * const i2c1_grp[] = { "i2c1_grp", };
1394 static const char * const i2s0_grp[] = { "i2s0_grp", };
1395 static const char * const i2s1_basic_grp[] = { "i2s1_basic_grp", };
1396 static const char * const i2s1_rxd0_grp0[] = { "i2s1_rxd0_grp0", };
1397 static const char * const i2s1_rxd0_grp1[] = { "i2s1_rxd0_grp1", };
1398 static const char * const i2s1_rxd0_grp2[] = { "i2s1_rxd0_grp2", };
1399 static const char * const i2s1_rxd0_grp3[] = { "i2s1_rxd0_grp3", };
1400 static const char * const i2s1_rxd0_grp4[] = { "i2s1_rxd0_grp4", };
1401 static const char * const i2s1_rxd1_grp0[] = { "i2s1_rxd1_grp0", };
1402 static const char * const i2s1_rxd1_grp1[] = { "i2s1_rxd1_grp1", };
1403 static const char * const i2s1_rxd1_grp2[] = { "i2s1_rxd1_grp2", };
1404 static const char * const i2s1_rxd1_grp3[] = { "i2s1_rxd1_grp3", };
1405 static const char * const i2s1_rxd1_grp4[] = { "i2s1_rxd1_grp4", };
1406 static const char * const jtag_jt_dbg_nsrst_grp[] = {
1407 "jtag_jt_dbg_nsrst_grp", };
1408 static const char * const jtag_ntrst_grp0[] = { "jtag_ntrst_grp0", };
1409 static const char * const jtag_ntrst_grp1[] = { "jtag_ntrst_grp1", };
1410 static const char * const jtag_swdiotms_grp0[] = { "jtag_swdiotms_grp0", };
1411 static const char * const jtag_swdiotms_grp1[] = { "jtag_swdiotms_grp1", };
1412 static const char * const jtag_tck_grp0[] = { "jtag_tck_grp0", };
1413 static const char * const jtag_tck_grp1[] = { "jtag_tck_grp1", };
1414 static const char * const jtag_tdi_grp0[] = { "jtag_tdi_grp0", };
1415 static const char * const jtag_tdi_grp1[] = { "jtag_tdi_grp1", };
1416 static const char * const jtag_tdo_grp0[] = { "jtag_tdo_grp0", };
1417 static const char * const jtag_tdo_grp1[] = { "jtag_tdo_grp1", };
1418 static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", };
1419 static const char * const ld_ldd_grp[] = { "ld_ldd_grp", };
1420 static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", };
1421 static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", };
1422 static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", };
1423 static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", };
1424 static const char * const lvds_analog_grp[] = { "lvds_analog_grp", };
1425 static const char * const nd_df_basic_grp[] = { "nd_df_basic_grp", };
1426 static const char * const nd_df_wp_grp[] = { "nd_df_wp_grp", };
1427 static const char * const nd_df_cs_grp[] = { "nd_df_cs_grp", };
1428 static const char * const ps_grp[] = { "ps_grp", };
1429 static const char * const ps_no_dir_grp[] = { "ps_no_dir_grp", };
1430 static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", };
1431 static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", };
1432 static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", };
1433 static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", };
1434 static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", };
1435 static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", };
1436 static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", };
1437 static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", };
1438 static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", };
1439 static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", };
1440 static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", };
1441 static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", };
1442 static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", };
1443 static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", };
1444 static const char * const pw_cko0_grp3[] = { "pw_cko0_grp3", };
1445 static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", };
1446 static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", };
1447 static const char * const pw_cko1_grp2[] = { "pw_cko1_grp2", };
1448 static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", };
1449 static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", };
1450 static const char * const pw_i2s01_clk_grp2[] = { "pw_i2s01_clk_grp2", };
1451 static const char * const pw_pwm0_grp0[] = { "pw_pwm0_grp0", };
1452 static const char * const pw_pwm0_grp1[] = { "pw_pwm0_grp1", };
1453 static const char * const pw_pwm1_grp0[] = { "pw_pwm1_grp0", };
1454 static const char * const pw_pwm1_grp1[] = { "pw_pwm1_grp1", };
1455 static const char * const pw_pwm1_grp2[] = { "pw_pwm1_grp2", };
1456 static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", };
1457 static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", };
1458 static const char * const pw_pwm2_grp2[] = { "pw_pwm2_grp2", };
1459 static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", };
1460 static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", };
1461 static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", };
1462 static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", };
1463 static const char * const pw_pwm_cpu_vol_grp2[] = { "pw_pwm_cpu_vol_grp2", };
1464 static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", };
1465 static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", };
1466 static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", };
1467 static const char * const rg_gmac_phy_intr_n_grp[] = {
1468 "rg_gmac_phy_intr_n_grp", };
1469 static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", };
1470 static const char * const rg_rgmii_phy_ref_clk_grp0[] = {
1471 "rg_rgmii_phy_ref_clk_grp0", };
1472 static const char * const rg_rgmii_phy_ref_clk_grp1[] = {
1473 "rg_rgmii_phy_ref_clk_grp1", };
1474 static const char * const sd0_grp[] = { "sd0_grp", };
1475 static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", };
1476 static const char * const sd1_grp[] = { "sd1_grp", };
1477 static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", };
1478 static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", };
1479 static const char * const sd2_basic_grp[] = { "sd2_basic_grp", };
1480 static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", };
1481 static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", };
1482 static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", };
1483 static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", };
1484 static const char * const sd3_9_grp[] = { "sd3_9_grp", };
1485 static const char * const sd5_grp[] = { "sd5_grp", };
1486 static const char * const sd6_grp0[] = { "sd6_grp0", };
1487 static const char * const sd6_grp1[] = { "sd6_grp1", };
1488 static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", };
1489 static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", };
1490 static const char * const sp1_spi_grp[] = { "sp1_spi_grp", };
1491 static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", };
1492 static const char * const uart0_grp[] = { "uart0_grp", };
1493 static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", };
1494 static const char * const uart1_grp[] = { "uart1_grp", };
1495 static const char * const uart2_cts_grp0[] = { "uart2_cts_grp0", };
1496 static const char * const uart2_cts_grp1[] = { "uart2_cts_grp1", };
1497 static const char * const uart2_rts_grp0[] = { "uart2_rts_grp0", };
1498 static const char * const uart2_rts_grp1[] = { "uart2_rts_grp1", };
1499 static const char * const uart2_rxd_grp0[] = { "uart2_rxd_grp0", };
1500 static const char * const uart2_rxd_grp1[] = { "uart2_rxd_grp1", };
1501 static const char * const uart2_rxd_grp2[] = { "uart2_rxd_grp2", };
1502 static const char * const uart2_txd_grp0[] = { "uart2_txd_grp0", };
1503 static const char * const uart2_txd_grp1[] = { "uart2_txd_grp1", };
1504 static const char * const uart2_txd_grp2[] = { "uart2_txd_grp2", };
1505 static const char * const uart3_cts_grp0[] = { "uart3_cts_grp0", };
1506 static const char * const uart3_cts_grp1[] = { "uart3_cts_grp1", };
1507 static const char * const uart3_cts_grp2[] = { "uart3_cts_grp2", };
1508 static const char * const uart3_rts_grp0[] = { "uart3_rts_grp0", };
1509 static const char * const uart3_rts_grp1[] = { "uart3_rts_grp1", };
1510 static const char * const uart3_rts_grp2[] = { "uart3_rts_grp2", };
1511 static const char * const uart3_rxd_grp0[] = { "uart3_rxd_grp0", };
1512 static const char * const uart3_rxd_grp1[] = { "uart3_rxd_grp1", };
1513 static const char * const uart3_rxd_grp2[] = { "uart3_rxd_grp2", };
1514 static const char * const uart3_txd_grp0[] = { "uart3_txd_grp0", };
1515 static const char * const uart3_txd_grp1[] = { "uart3_txd_grp1", };
1516 static const char * const uart3_txd_grp2[] = { "uart3_txd_grp2", };
1517 static const char * const uart4_basic_grp[] = { "uart4_basic_grp", };
1518 static const char * const uart4_cts_grp0[] = { "uart4_cts_grp0", };
1519 static const char * const uart4_cts_grp1[] = { "uart4_cts_grp1", };
1520 static const char * const uart4_cts_grp2[] = { "uart4_cts_grp2", };
1521 static const char * const uart4_rts_grp0[] = { "uart4_rts_grp0", };
1522 static const char * const uart4_rts_grp1[] = { "uart4_rts_grp1", };
1523 static const char * const uart4_rts_grp2[] = { "uart4_rts_grp2", };
1524 static const char * const usb0_drvvbus_grp0[] = { "usb0_drvvbus_grp0", };
1525 static const char * const usb0_drvvbus_grp1[] = { "usb0_drvvbus_grp1", };
1526 static const char * const usb1_drvvbus_grp0[] = { "usb1_drvvbus_grp0", };
1527 static const char * const usb1_drvvbus_grp1[] = { "usb1_drvvbus_grp1", };
1528 static const char * const visbus_dout_grp[] = { "visbus_dout_grp", };
1529 static const char * const vi_vip1_grp[] = { "vi_vip1_grp", };
1530 static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", };
1531 static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", };
1532 static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", };
1533
1534 static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = {
1535 MUX(1, 119, 0, N, N, N, N),
1536 MUX(1, 120, 0, N, N, N, N),
1537 MUX(1, 121, 0, N, N, N, N),
1538 MUX(1, 122, 0, N, N, N, N),
1539 MUX(1, 123, 0, N, N, N, N),
1540 MUX(1, 124, 0, N, N, N, N),
1541 MUX(1, 125, 0, N, N, N, N),
1542 MUX(1, 126, 0, N, N, N, N),
1543 MUX(1, 127, 0, N, N, N, N),
1544 MUX(1, 128, 0, N, N, N, N),
1545 MUX(1, 22, 0, N, N, N, N),
1546 MUX(1, 23, 0, N, N, N, N),
1547 MUX(1, 24, 0, N, N, N, N),
1548 MUX(1, 25, 0, N, N, N, N),
1549 MUX(1, 26, 0, N, N, N, N),
1550 MUX(1, 27, 0, N, N, N, N),
1551 MUX(1, 28, 0, N, N, N, N),
1552 MUX(1, 29, 0, N, N, N, N),
1553 MUX(1, 30, 0, N, N, N, N),
1554 };
1555
1556 static struct atlas7_grp_mux gnss_gpio_grp_mux = {
1557 .pad_mux_count = ARRAY_SIZE(gnss_gpio_grp_pad_mux),
1558 .pad_mux_list = gnss_gpio_grp_pad_mux,
1559 };
1560
1561 static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = {
1562 MUX(1, 74, 0, N, N, N, N),
1563 MUX(1, 75, 0, N, N, N, N),
1564 MUX(1, 76, 0, N, N, N, N),
1565 MUX(1, 77, 0, N, N, N, N),
1566 MUX(1, 78, 0, N, N, N, N),
1567 MUX(1, 79, 0, N, N, N, N),
1568 MUX(1, 80, 0, N, N, N, N),
1569 MUX(1, 81, 0, N, N, N, N),
1570 MUX(1, 82, 0, N, N, N, N),
1571 MUX(1, 83, 0, N, N, N, N),
1572 MUX(1, 84, 0, N, N, N, N),
1573 MUX(1, 53, 0, N, N, N, N),
1574 MUX(1, 54, 0, N, N, N, N),
1575 MUX(1, 55, 0, N, N, N, N),
1576 MUX(1, 56, 0, N, N, N, N),
1577 MUX(1, 57, 0, N, N, N, N),
1578 MUX(1, 58, 0, N, N, N, N),
1579 MUX(1, 59, 0, N, N, N, N),
1580 MUX(1, 60, 0, N, N, N, N),
1581 MUX(1, 61, 0, N, N, N, N),
1582 MUX(1, 62, 0, N, N, N, N),
1583 MUX(1, 63, 0, N, N, N, N),
1584 MUX(1, 64, 0, N, N, N, N),
1585 MUX(1, 65, 0, N, N, N, N),
1586 MUX(1, 66, 0, N, N, N, N),
1587 MUX(1, 67, 0, N, N, N, N),
1588 MUX(1, 68, 0, N, N, N, N),
1589 MUX(1, 69, 0, N, N, N, N),
1590 MUX(1, 70, 0, N, N, N, N),
1591 MUX(1, 71, 0, N, N, N, N),
1592 MUX(1, 72, 0, N, N, N, N),
1593 MUX(1, 73, 0, N, N, N, N),
1594 };
1595
1596 static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = {
1597 .pad_mux_count = ARRAY_SIZE(lcd_vip_gpio_grp_pad_mux),
1598 .pad_mux_list = lcd_vip_gpio_grp_pad_mux,
1599 };
1600
1601 static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = {
1602 MUX(1, 31, 0, N, N, N, N),
1603 MUX(1, 32, 0, N, N, N, N),
1604 MUX(1, 33, 0, N, N, N, N),
1605 MUX(1, 34, 0, N, N, N, N),
1606 MUX(1, 35, 0, N, N, N, N),
1607 MUX(1, 36, 0, N, N, N, N),
1608 MUX(1, 85, 0, N, N, N, N),
1609 MUX(1, 86, 0, N, N, N, N),
1610 MUX(1, 87, 0, N, N, N, N),
1611 MUX(1, 88, 0, N, N, N, N),
1612 MUX(1, 89, 0, N, N, N, N),
1613 MUX(1, 90, 0, N, N, N, N),
1614 MUX(1, 129, 0, N, N, N, N),
1615 MUX(1, 130, 0, N, N, N, N),
1616 MUX(1, 131, 0, N, N, N, N),
1617 MUX(1, 132, 0, N, N, N, N),
1618 MUX(1, 91, 0, N, N, N, N),
1619 MUX(1, 92, 0, N, N, N, N),
1620 MUX(1, 93, 0, N, N, N, N),
1621 MUX(1, 94, 0, N, N, N, N),
1622 MUX(1, 95, 0, N, N, N, N),
1623 MUX(1, 96, 0, N, N, N, N),
1624 MUX(1, 112, 0, N, N, N, N),
1625 MUX(1, 113, 0, N, N, N, N),
1626 MUX(1, 114, 0, N, N, N, N),
1627 MUX(1, 115, 0, N, N, N, N),
1628 MUX(1, 116, 0, N, N, N, N),
1629 MUX(1, 117, 0, N, N, N, N),
1630 MUX(1, 118, 0, N, N, N, N),
1631 };
1632
1633 static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = {
1634 .pad_mux_count = ARRAY_SIZE(sdio_i2s_gpio_grp_pad_mux),
1635 .pad_mux_list = sdio_i2s_gpio_grp_pad_mux,
1636 };
1637
1638 static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = {
1639 MUX(1, 97, 0, N, N, N, N),
1640 MUX(1, 98, 0, N, N, N, N),
1641 MUX(1, 99, 0, N, N, N, N),
1642 MUX(1, 100, 0, N, N, N, N),
1643 MUX(1, 101, 0, N, N, N, N),
1644 MUX(1, 102, 0, N, N, N, N),
1645 MUX(1, 103, 0, N, N, N, N),
1646 MUX(1, 104, 0, N, N, N, N),
1647 MUX(1, 105, 0, N, N, N, N),
1648 MUX(1, 106, 0, N, N, N, N),
1649 MUX(1, 107, 0, N, N, N, N),
1650 MUX(1, 108, 0, N, N, N, N),
1651 MUX(1, 109, 0, N, N, N, N),
1652 MUX(1, 110, 0, N, N, N, N),
1653 MUX(1, 111, 0, N, N, N, N),
1654 MUX(1, 18, 0, N, N, N, N),
1655 MUX(1, 19, 0, N, N, N, N),
1656 MUX(1, 20, 0, N, N, N, N),
1657 MUX(1, 21, 0, N, N, N, N),
1658 MUX(1, 141, 0, N, N, N, N),
1659 MUX(1, 142, 0, N, N, N, N),
1660 MUX(1, 143, 0, N, N, N, N),
1661 MUX(1, 144, 0, N, N, N, N),
1662 MUX(1, 145, 0, N, N, N, N),
1663 MUX(1, 146, 0, N, N, N, N),
1664 MUX(1, 147, 0, N, N, N, N),
1665 MUX(1, 148, 0, N, N, N, N),
1666 };
1667
1668 static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = {
1669 .pad_mux_count = ARRAY_SIZE(sp_rgmii_gpio_grp_pad_mux),
1670 .pad_mux_list = sp_rgmii_gpio_grp_pad_mux,
1671 };
1672
1673 static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = {
1674 MUX(1, 157, 0, N, N, N, N),
1675 MUX(1, 158, 0, N, N, N, N),
1676 MUX(1, 155, 0, N, N, N, N),
1677 MUX(1, 156, 0, N, N, N, N),
1678 MUX(1, 153, 0, N, N, N, N),
1679 MUX(1, 154, 0, N, N, N, N),
1680 MUX(1, 151, 0, N, N, N, N),
1681 MUX(1, 152, 0, N, N, N, N),
1682 MUX(1, 149, 0, N, N, N, N),
1683 MUX(1, 150, 0, N, N, N, N),
1684 };
1685
1686 static struct atlas7_grp_mux lvds_gpio_grp_mux = {
1687 .pad_mux_count = ARRAY_SIZE(lvds_gpio_grp_pad_mux),
1688 .pad_mux_list = lvds_gpio_grp_pad_mux,
1689 };
1690
1691 static struct atlas7_pad_mux jtag_uart_nand_gpio_grp_pad_mux[] = {
1692 MUX(1, 44, 0, N, N, N, N),
1693 MUX(1, 43, 0, N, N, N, N),
1694 MUX(1, 42, 0, N, N, N, N),
1695 MUX(1, 41, 0, N, N, N, N),
1696 MUX(1, 40, 0, N, N, N, N),
1697 MUX(1, 39, 0, N, N, N, N),
1698 MUX(1, 38, 0, N, N, N, N),
1699 MUX(1, 37, 0, N, N, N, N),
1700 MUX(1, 46, 0, N, N, N, N),
1701 MUX(1, 47, 0, N, N, N, N),
1702 MUX(1, 48, 0, N, N, N, N),
1703 MUX(1, 49, 0, N, N, N, N),
1704 MUX(1, 50, 0, N, N, N, N),
1705 MUX(1, 52, 0, N, N, N, N),
1706 MUX(1, 51, 0, N, N, N, N),
1707 MUX(1, 45, 0, N, N, N, N),
1708 MUX(1, 133, 0, N, N, N, N),
1709 MUX(1, 134, 0, N, N, N, N),
1710 MUX(1, 135, 0, N, N, N, N),
1711 MUX(1, 136, 0, N, N, N, N),
1712 MUX(1, 137, 0, N, N, N, N),
1713 MUX(1, 138, 0, N, N, N, N),
1714 MUX(1, 139, 0, N, N, N, N),
1715 MUX(1, 140, 0, N, N, N, N),
1716 MUX(1, 159, 0, N, N, N, N),
1717 MUX(1, 160, 0, N, N, N, N),
1718 MUX(1, 161, 0, N, N, N, N),
1719 MUX(1, 162, 0, N, N, N, N),
1720 MUX(1, 163, 0, N, N, N, N),
1721 };
1722
1723 static struct atlas7_grp_mux jtag_uart_nand_gpio_grp_mux = {
1724 .pad_mux_count = ARRAY_SIZE(jtag_uart_nand_gpio_grp_pad_mux),
1725 .pad_mux_list = jtag_uart_nand_gpio_grp_pad_mux,
1726 };
1727
1728 static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = {
1729 MUX(0, 0, 0, N, N, N, N),
1730 MUX(0, 1, 0, N, N, N, N),
1731 MUX(0, 2, 0, N, N, N, N),
1732 MUX(0, 3, 0, N, N, N, N),
1733 MUX(0, 4, 0, N, N, N, N),
1734 MUX(0, 10, 0, N, N, N, N),
1735 MUX(0, 11, 0, N, N, N, N),
1736 MUX(0, 12, 0, N, N, N, N),
1737 MUX(0, 13, 0, N, N, N, N),
1738 MUX(0, 14, 0, N, N, N, N),
1739 MUX(0, 15, 0, N, N, N, N),
1740 MUX(0, 16, 0, N, N, N, N),
1741 MUX(0, 17, 0, N, N, N, N),
1742 MUX(0, 9, 0, N, N, N, N),
1743 };
1744
1745 static struct atlas7_grp_mux rtc_gpio_grp_mux = {
1746 .pad_mux_count = ARRAY_SIZE(rtc_gpio_grp_pad_mux),
1747 .pad_mux_list = rtc_gpio_grp_pad_mux,
1748 };
1749
1750 static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = {
1751 MUX(1, 113, 2, N, N, N, N),
1752 MUX(1, 118, 2, N, N, N, N),
1753 MUX(1, 115, 2, N, N, N, N),
1754 MUX(1, 114, 2, N, N, N, N),
1755 };
1756
1757 static struct atlas7_grp_mux audio_ac97_grp_mux = {
1758 .pad_mux_count = ARRAY_SIZE(audio_ac97_grp_pad_mux),
1759 .pad_mux_list = audio_ac97_grp_pad_mux,
1760 };
1761
1762 static struct atlas7_pad_mux audio_digmic_grp0_pad_mux[] = {
1763 MUX(1, 51, 3, 0xa10, 20, 0xa90, 20),
1764 };
1765
1766 static struct atlas7_grp_mux audio_digmic_grp0_mux = {
1767 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp0_pad_mux),
1768 .pad_mux_list = audio_digmic_grp0_pad_mux,
1769 };
1770
1771 static struct atlas7_pad_mux audio_digmic_grp1_pad_mux[] = {
1772 MUX(1, 122, 5, 0xa10, 20, 0xa90, 20),
1773 };
1774
1775 static struct atlas7_grp_mux audio_digmic_grp1_mux = {
1776 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp1_pad_mux),
1777 .pad_mux_list = audio_digmic_grp1_pad_mux,
1778 };
1779
1780 static struct atlas7_pad_mux audio_digmic_grp2_pad_mux[] = {
1781 MUX(1, 161, 7, 0xa10, 20, 0xa90, 20),
1782 };
1783
1784 static struct atlas7_grp_mux audio_digmic_grp2_mux = {
1785 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp2_pad_mux),
1786 .pad_mux_list = audio_digmic_grp2_pad_mux,
1787 };
1788
1789 static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = {
1790 MUX(1, 141, 4, N, N, N, N),
1791 MUX(1, 144, 4, N, N, N, N),
1792 MUX(1, 44, 6, N, N, N, N),
1793 MUX(1, 43, 6, N, N, N, N),
1794 MUX(1, 42, 6, N, N, N, N),
1795 MUX(1, 41, 6, N, N, N, N),
1796 MUX(1, 40, 6, N, N, N, N),
1797 MUX(1, 39, 6, N, N, N, N),
1798 MUX(1, 38, 6, N, N, N, N),
1799 MUX(1, 37, 6, N, N, N, N),
1800 MUX(1, 74, 6, N, N, N, N),
1801 MUX(1, 75, 6, N, N, N, N),
1802 MUX(1, 76, 6, N, N, N, N),
1803 MUX(1, 77, 6, N, N, N, N),
1804 MUX(1, 78, 6, N, N, N, N),
1805 MUX(1, 79, 6, N, N, N, N),
1806 MUX(1, 81, 6, N, N, N, N),
1807 MUX(1, 113, 6, N, N, N, N),
1808 MUX(1, 114, 6, N, N, N, N),
1809 MUX(1, 118, 6, N, N, N, N),
1810 MUX(1, 115, 6, N, N, N, N),
1811 MUX(1, 49, 6, N, N, N, N),
1812 MUX(1, 50, 6, N, N, N, N),
1813 MUX(1, 142, 4, N, N, N, N),
1814 MUX(1, 143, 4, N, N, N, N),
1815 MUX(1, 80, 6, N, N, N, N),
1816 };
1817
1818 static struct atlas7_grp_mux audio_func_dbg_grp_mux = {
1819 .pad_mux_count = ARRAY_SIZE(audio_func_dbg_grp_pad_mux),
1820 .pad_mux_list = audio_func_dbg_grp_pad_mux,
1821 };
1822
1823 static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = {
1824 MUX(1, 118, 1, N, N, N, N),
1825 MUX(1, 115, 1, N, N, N, N),
1826 MUX(1, 116, 1, N, N, N, N),
1827 MUX(1, 117, 1, N, N, N, N),
1828 MUX(1, 112, 1, N, N, N, N),
1829 MUX(1, 113, 1, N, N, N, N),
1830 MUX(1, 114, 1, N, N, N, N),
1831 };
1832
1833 static struct atlas7_grp_mux audio_i2s_grp_mux = {
1834 .pad_mux_count = ARRAY_SIZE(audio_i2s_grp_pad_mux),
1835 .pad_mux_list = audio_i2s_grp_pad_mux,
1836 };
1837
1838 static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = {
1839 MUX(1, 118, 1, N, N, N, N),
1840 MUX(1, 115, 1, N, N, N, N),
1841 MUX(1, 112, 1, N, N, N, N),
1842 MUX(1, 113, 1, N, N, N, N),
1843 MUX(1, 114, 1, N, N, N, N),
1844 };
1845
1846 static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = {
1847 .pad_mux_count = ARRAY_SIZE(audio_i2s_2ch_grp_pad_mux),
1848 .pad_mux_list = audio_i2s_2ch_grp_pad_mux,
1849 };
1850
1851 static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = {
1852 MUX(1, 112, 2, N, N, N, N),
1853 };
1854
1855 static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = {
1856 .pad_mux_count = ARRAY_SIZE(audio_i2s_extclk_grp_pad_mux),
1857 .pad_mux_list = audio_i2s_extclk_grp_pad_mux,
1858 };
1859
1860 static struct atlas7_pad_mux audio_spdif_out_grp0_pad_mux[] = {
1861 MUX(1, 112, 3, N, N, N, N),
1862 };
1863
1864 static struct atlas7_grp_mux audio_spdif_out_grp0_mux = {
1865 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp0_pad_mux),
1866 .pad_mux_list = audio_spdif_out_grp0_pad_mux,
1867 };
1868
1869 static struct atlas7_pad_mux audio_spdif_out_grp1_pad_mux[] = {
1870 MUX(1, 116, 3, N, N, N, N),
1871 };
1872
1873 static struct atlas7_grp_mux audio_spdif_out_grp1_mux = {
1874 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp1_pad_mux),
1875 .pad_mux_list = audio_spdif_out_grp1_pad_mux,
1876 };
1877
1878 static struct atlas7_pad_mux audio_spdif_out_grp2_pad_mux[] = {
1879 MUX(1, 142, 3, N, N, N, N),
1880 };
1881
1882 static struct atlas7_grp_mux audio_spdif_out_grp2_mux = {
1883 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp2_pad_mux),
1884 .pad_mux_list = audio_spdif_out_grp2_pad_mux,
1885 };
1886
1887 static struct atlas7_pad_mux audio_uart0_basic_grp_pad_mux[] = {
1888 MUX(1, 143, 1, N, N, N, N),
1889 MUX(1, 142, 1, N, N, N, N),
1890 MUX(1, 141, 1, N, N, N, N),
1891 MUX(1, 144, 1, N, N, N, N),
1892 };
1893
1894 static struct atlas7_grp_mux audio_uart0_basic_grp_mux = {
1895 .pad_mux_count = ARRAY_SIZE(audio_uart0_basic_grp_pad_mux),
1896 .pad_mux_list = audio_uart0_basic_grp_pad_mux,
1897 };
1898
1899 static struct atlas7_pad_mux audio_uart0_urfs_grp0_pad_mux[] = {
1900 MUX(1, 117, 5, 0xa10, 28, 0xa90, 28),
1901 };
1902
1903 static struct atlas7_grp_mux audio_uart0_urfs_grp0_mux = {
1904 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp0_pad_mux),
1905 .pad_mux_list = audio_uart0_urfs_grp0_pad_mux,
1906 };
1907
1908 static struct atlas7_pad_mux audio_uart0_urfs_grp1_pad_mux[] = {
1909 MUX(1, 139, 3, 0xa10, 28, 0xa90, 28),
1910 };
1911
1912 static struct atlas7_grp_mux audio_uart0_urfs_grp1_mux = {
1913 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp1_pad_mux),
1914 .pad_mux_list = audio_uart0_urfs_grp1_pad_mux,
1915 };
1916
1917 static struct atlas7_pad_mux audio_uart0_urfs_grp2_pad_mux[] = {
1918 MUX(1, 163, 3, 0xa10, 28, 0xa90, 28),
1919 };
1920
1921 static struct atlas7_grp_mux audio_uart0_urfs_grp2_mux = {
1922 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp2_pad_mux),
1923 .pad_mux_list = audio_uart0_urfs_grp2_pad_mux,
1924 };
1925
1926 static struct atlas7_pad_mux audio_uart0_urfs_grp3_pad_mux[] = {
1927 MUX(1, 162, 6, 0xa10, 28, 0xa90, 28),
1928 };
1929
1930 static struct atlas7_grp_mux audio_uart0_urfs_grp3_mux = {
1931 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp3_pad_mux),
1932 .pad_mux_list = audio_uart0_urfs_grp3_pad_mux,
1933 };
1934
1935 static struct atlas7_pad_mux audio_uart1_basic_grp_pad_mux[] = {
1936 MUX(1, 147, 1, 0xa10, 24, 0xa90, 24),
1937 MUX(1, 146, 1, 0xa10, 25, 0xa90, 25),
1938 MUX(1, 145, 1, 0xa10, 23, 0xa90, 23),
1939 MUX(1, 148, 1, 0xa10, 22, 0xa90, 22),
1940 };
1941
1942 static struct atlas7_grp_mux audio_uart1_basic_grp_mux = {
1943 .pad_mux_count = ARRAY_SIZE(audio_uart1_basic_grp_pad_mux),
1944 .pad_mux_list = audio_uart1_basic_grp_pad_mux,
1945 };
1946
1947 static struct atlas7_pad_mux audio_uart1_urfs_grp0_pad_mux[] = {
1948 MUX(1, 117, 6, 0xa10, 29, 0xa90, 29),
1949 };
1950
1951 static struct atlas7_grp_mux audio_uart1_urfs_grp0_mux = {
1952 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp0_pad_mux),
1953 .pad_mux_list = audio_uart1_urfs_grp0_pad_mux,
1954 };
1955
1956 static struct atlas7_pad_mux audio_uart1_urfs_grp1_pad_mux[] = {
1957 MUX(1, 140, 3, 0xa10, 29, 0xa90, 29),
1958 };
1959
1960 static struct atlas7_grp_mux audio_uart1_urfs_grp1_mux = {
1961 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp1_pad_mux),
1962 .pad_mux_list = audio_uart1_urfs_grp1_pad_mux,
1963 };
1964
1965 static struct atlas7_pad_mux audio_uart1_urfs_grp2_pad_mux[] = {
1966 MUX(1, 163, 4, 0xa10, 29, 0xa90, 29),
1967 };
1968
1969 static struct atlas7_grp_mux audio_uart1_urfs_grp2_mux = {
1970 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp2_pad_mux),
1971 .pad_mux_list = audio_uart1_urfs_grp2_pad_mux,
1972 };
1973
1974 static struct atlas7_pad_mux audio_uart2_urfs_grp0_pad_mux[] = {
1975 MUX(1, 139, 4, 0xa10, 30, 0xa90, 30),
1976 };
1977
1978 static struct atlas7_grp_mux audio_uart2_urfs_grp0_mux = {
1979 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp0_pad_mux),
1980 .pad_mux_list = audio_uart2_urfs_grp0_pad_mux,
1981 };
1982
1983 static struct atlas7_pad_mux audio_uart2_urfs_grp1_pad_mux[] = {
1984 MUX(1, 163, 6, 0xa10, 30, 0xa90, 30),
1985 };
1986
1987 static struct atlas7_grp_mux audio_uart2_urfs_grp1_mux = {
1988 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp1_pad_mux),
1989 .pad_mux_list = audio_uart2_urfs_grp1_pad_mux,
1990 };
1991
1992 static struct atlas7_pad_mux audio_uart2_urfs_grp2_pad_mux[] = {
1993 MUX(1, 96, 3, 0xa10, 30, 0xa90, 30),
1994 };
1995
1996 static struct atlas7_grp_mux audio_uart2_urfs_grp2_mux = {
1997 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp2_pad_mux),
1998 .pad_mux_list = audio_uart2_urfs_grp2_pad_mux,
1999 };
2000
2001 static struct atlas7_pad_mux audio_uart2_urxd_grp0_pad_mux[] = {
2002 MUX(1, 20, 2, 0xa00, 24, 0xa80, 24),
2003 };
2004
2005 static struct atlas7_grp_mux audio_uart2_urxd_grp0_mux = {
2006 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp0_pad_mux),
2007 .pad_mux_list = audio_uart2_urxd_grp0_pad_mux,
2008 };
2009
2010 static struct atlas7_pad_mux audio_uart2_urxd_grp1_pad_mux[] = {
2011 MUX(1, 109, 2, 0xa00, 24, 0xa80, 24),
2012 };
2013
2014 static struct atlas7_grp_mux audio_uart2_urxd_grp1_mux = {
2015 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp1_pad_mux),
2016 .pad_mux_list = audio_uart2_urxd_grp1_pad_mux,
2017 };
2018
2019 static struct atlas7_pad_mux audio_uart2_urxd_grp2_pad_mux[] = {
2020 MUX(1, 93, 3, 0xa00, 24, 0xa80, 24),
2021 };
2022
2023 static struct atlas7_grp_mux audio_uart2_urxd_grp2_mux = {
2024 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp2_pad_mux),
2025 .pad_mux_list = audio_uart2_urxd_grp2_pad_mux,
2026 };
2027
2028 static struct atlas7_pad_mux audio_uart2_usclk_grp0_pad_mux[] = {
2029 MUX(1, 19, 2, 0xa00, 23, 0xa80, 23),
2030 };
2031
2032 static struct atlas7_grp_mux audio_uart2_usclk_grp0_mux = {
2033 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp0_pad_mux),
2034 .pad_mux_list = audio_uart2_usclk_grp0_pad_mux,
2035 };
2036
2037 static struct atlas7_pad_mux audio_uart2_usclk_grp1_pad_mux[] = {
2038 MUX(1, 101, 2, 0xa00, 23, 0xa80, 23),
2039 };
2040
2041 static struct atlas7_grp_mux audio_uart2_usclk_grp1_mux = {
2042 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp1_pad_mux),
2043 .pad_mux_list = audio_uart2_usclk_grp1_pad_mux,
2044 };
2045
2046 static struct atlas7_pad_mux audio_uart2_usclk_grp2_pad_mux[] = {
2047 MUX(1, 91, 3, 0xa00, 23, 0xa80, 23),
2048 };
2049
2050 static struct atlas7_grp_mux audio_uart2_usclk_grp2_mux = {
2051 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp2_pad_mux),
2052 .pad_mux_list = audio_uart2_usclk_grp2_pad_mux,
2053 };
2054
2055 static struct atlas7_pad_mux audio_uart2_utfs_grp0_pad_mux[] = {
2056 MUX(1, 18, 2, 0xa00, 22, 0xa80, 22),
2057 };
2058
2059 static struct atlas7_grp_mux audio_uart2_utfs_grp0_mux = {
2060 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp0_pad_mux),
2061 .pad_mux_list = audio_uart2_utfs_grp0_pad_mux,
2062 };
2063
2064 static struct atlas7_pad_mux audio_uart2_utfs_grp1_pad_mux[] = {
2065 MUX(1, 111, 2, 0xa00, 22, 0xa80, 22),
2066 };
2067
2068 static struct atlas7_grp_mux audio_uart2_utfs_grp1_mux = {
2069 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp1_pad_mux),
2070 .pad_mux_list = audio_uart2_utfs_grp1_pad_mux,
2071 };
2072
2073 static struct atlas7_pad_mux audio_uart2_utfs_grp2_pad_mux[] = {
2074 MUX(1, 94, 3, 0xa00, 22, 0xa80, 22),
2075 };
2076
2077 static struct atlas7_grp_mux audio_uart2_utfs_grp2_mux = {
2078 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp2_pad_mux),
2079 .pad_mux_list = audio_uart2_utfs_grp2_pad_mux,
2080 };
2081
2082 static struct atlas7_pad_mux audio_uart2_utxd_grp0_pad_mux[] = {
2083 MUX(1, 21, 2, 0xa00, 25, 0xa80, 25),
2084 };
2085
2086 static struct atlas7_grp_mux audio_uart2_utxd_grp0_mux = {
2087 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp0_pad_mux),
2088 .pad_mux_list = audio_uart2_utxd_grp0_pad_mux,
2089 };
2090
2091 static struct atlas7_pad_mux audio_uart2_utxd_grp1_pad_mux[] = {
2092 MUX(1, 110, 2, 0xa00, 25, 0xa80, 25),
2093 };
2094
2095 static struct atlas7_grp_mux audio_uart2_utxd_grp1_mux = {
2096 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp1_pad_mux),
2097 .pad_mux_list = audio_uart2_utxd_grp1_pad_mux,
2098 };
2099
2100 static struct atlas7_pad_mux audio_uart2_utxd_grp2_pad_mux[] = {
2101 MUX(1, 92, 3, 0xa00, 25, 0xa80, 25),
2102 };
2103
2104 static struct atlas7_grp_mux audio_uart2_utxd_grp2_mux = {
2105 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp2_pad_mux),
2106 .pad_mux_list = audio_uart2_utxd_grp2_pad_mux,
2107 };
2108
2109 static struct atlas7_pad_mux c_can_trnsvr_en_grp0_pad_mux[] = {
2110 MUX(0, 2, 6, N, N, N, N),
2111 };
2112
2113 static struct atlas7_grp_mux c_can_trnsvr_en_grp0_mux = {
2114 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp0_pad_mux),
2115 .pad_mux_list = c_can_trnsvr_en_grp0_pad_mux,
2116 };
2117
2118 static struct atlas7_pad_mux c_can_trnsvr_en_grp1_pad_mux[] = {
2119 MUX(0, 0, 2, N, N, N, N),
2120 };
2121
2122 static struct atlas7_grp_mux c_can_trnsvr_en_grp1_mux = {
2123 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp1_pad_mux),
2124 .pad_mux_list = c_can_trnsvr_en_grp1_pad_mux,
2125 };
2126
2127 static struct atlas7_pad_mux c_can_trnsvr_intr_grp_pad_mux[] = {
2128 MUX(0, 1, 2, N, N, N, N),
2129 };
2130
2131 static struct atlas7_grp_mux c_can_trnsvr_intr_grp_mux = {
2132 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_intr_grp_pad_mux),
2133 .pad_mux_list = c_can_trnsvr_intr_grp_pad_mux,
2134 };
2135
2136 static struct atlas7_pad_mux c_can_trnsvr_stb_n_grp_pad_mux[] = {
2137 MUX(0, 3, 6, N, N, N, N),
2138 };
2139
2140 static struct atlas7_grp_mux c_can_trnsvr_stb_n_grp_mux = {
2141 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_stb_n_grp_pad_mux),
2142 .pad_mux_list = c_can_trnsvr_stb_n_grp_pad_mux,
2143 };
2144
2145 static struct atlas7_pad_mux c0_can_rxd_trnsv0_grp_pad_mux[] = {
2146 MUX(0, 11, 1, 0xa08, 9, 0xa88, 9),
2147 };
2148
2149 static struct atlas7_grp_mux c0_can_rxd_trnsv0_grp_mux = {
2150 .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv0_grp_pad_mux),
2151 .pad_mux_list = c0_can_rxd_trnsv0_grp_pad_mux,
2152 };
2153
2154 static struct atlas7_pad_mux c0_can_rxd_trnsv1_grp_pad_mux[] = {
2155 MUX(0, 2, 5, 0xa10, 9, 0xa90, 9),
2156 };
2157
2158 static struct atlas7_grp_mux c0_can_rxd_trnsv1_grp_mux = {
2159 .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv1_grp_pad_mux),
2160 .pad_mux_list = c0_can_rxd_trnsv1_grp_pad_mux,
2161 };
2162
2163 static struct atlas7_pad_mux c0_can_txd_trnsv0_grp_pad_mux[] = {
2164 MUX(0, 10, 1, N, N, N, N),
2165 };
2166
2167 static struct atlas7_grp_mux c0_can_txd_trnsv0_grp_mux = {
2168 .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv0_grp_pad_mux),
2169 .pad_mux_list = c0_can_txd_trnsv0_grp_pad_mux,
2170 };
2171
2172 static struct atlas7_pad_mux c0_can_txd_trnsv1_grp_pad_mux[] = {
2173 MUX(0, 3, 5, N, N, N, N),
2174 };
2175
2176 static struct atlas7_grp_mux c0_can_txd_trnsv1_grp_mux = {
2177 .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv1_grp_pad_mux),
2178 .pad_mux_list = c0_can_txd_trnsv1_grp_pad_mux,
2179 };
2180
2181 static struct atlas7_pad_mux c1_can_rxd_grp0_pad_mux[] = {
2182 MUX(1, 138, 2, 0xa00, 4, 0xa80, 4),
2183 };
2184
2185 static struct atlas7_grp_mux c1_can_rxd_grp0_mux = {
2186 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp0_pad_mux),
2187 .pad_mux_list = c1_can_rxd_grp0_pad_mux,
2188 };
2189
2190 static struct atlas7_pad_mux c1_can_rxd_grp1_pad_mux[] = {
2191 MUX(1, 147, 2, 0xa00, 4, 0xa80, 4),
2192 };
2193
2194 static struct atlas7_grp_mux c1_can_rxd_grp1_mux = {
2195 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp1_pad_mux),
2196 .pad_mux_list = c1_can_rxd_grp1_pad_mux,
2197 };
2198
2199 static struct atlas7_pad_mux c1_can_rxd_grp2_pad_mux[] = {
2200 MUX(0, 2, 2, 0xa00, 4, 0xa80, 4),
2201 };
2202
2203 static struct atlas7_grp_mux c1_can_rxd_grp2_mux = {
2204 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp2_pad_mux),
2205 .pad_mux_list = c1_can_rxd_grp2_pad_mux,
2206 };
2207
2208 static struct atlas7_pad_mux c1_can_rxd_grp3_pad_mux[] = {
2209 MUX(1, 162, 4, 0xa00, 4, 0xa80, 4),
2210 };
2211
2212 static struct atlas7_grp_mux c1_can_rxd_grp3_mux = {
2213 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp3_pad_mux),
2214 .pad_mux_list = c1_can_rxd_grp3_pad_mux,
2215 };
2216
2217 static struct atlas7_pad_mux c1_can_txd_grp0_pad_mux[] = {
2218 MUX(1, 137, 2, N, N, N, N),
2219 };
2220
2221 static struct atlas7_grp_mux c1_can_txd_grp0_mux = {
2222 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp0_pad_mux),
2223 .pad_mux_list = c1_can_txd_grp0_pad_mux,
2224 };
2225
2226 static struct atlas7_pad_mux c1_can_txd_grp1_pad_mux[] = {
2227 MUX(1, 146, 2, N, N, N, N),
2228 };
2229
2230 static struct atlas7_grp_mux c1_can_txd_grp1_mux = {
2231 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp1_pad_mux),
2232 .pad_mux_list = c1_can_txd_grp1_pad_mux,
2233 };
2234
2235 static struct atlas7_pad_mux c1_can_txd_grp2_pad_mux[] = {
2236 MUX(0, 3, 2, N, N, N, N),
2237 };
2238
2239 static struct atlas7_grp_mux c1_can_txd_grp2_mux = {
2240 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp2_pad_mux),
2241 .pad_mux_list = c1_can_txd_grp2_pad_mux,
2242 };
2243
2244 static struct atlas7_pad_mux c1_can_txd_grp3_pad_mux[] = {
2245 MUX(1, 161, 4, N, N, N, N),
2246 };
2247
2248 static struct atlas7_grp_mux c1_can_txd_grp3_mux = {
2249 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp3_pad_mux),
2250 .pad_mux_list = c1_can_txd_grp3_pad_mux,
2251 };
2252
2253 static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = {
2254 MUX(1, 62, 4, N, N, N, N),
2255 MUX(1, 63, 4, N, N, N, N),
2256 MUX(1, 64, 4, N, N, N, N),
2257 MUX(1, 65, 4, N, N, N, N),
2258 MUX(1, 66, 4, N, N, N, N),
2259 MUX(1, 67, 4, N, N, N, N),
2260 MUX(1, 68, 4, N, N, N, N),
2261 MUX(1, 69, 4, N, N, N, N),
2262 MUX(1, 70, 4, N, N, N, N),
2263 MUX(1, 71, 4, N, N, N, N),
2264 };
2265
2266 static struct atlas7_grp_mux ca_audio_lpc_grp_mux = {
2267 .pad_mux_count = ARRAY_SIZE(ca_audio_lpc_grp_pad_mux),
2268 .pad_mux_list = ca_audio_lpc_grp_pad_mux,
2269 };
2270
2271 static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = {
2272 MUX(1, 85, 5, N, N, N, N),
2273 MUX(1, 86, 5, N, N, N, N),
2274 MUX(1, 87, 5, N, N, N, N),
2275 MUX(1, 88, 5, N, N, N, N),
2276 MUX(1, 89, 5, N, N, N, N),
2277 MUX(1, 90, 5, N, N, N, N),
2278 };
2279
2280 static struct atlas7_grp_mux ca_bt_lpc_grp_mux = {
2281 .pad_mux_count = ARRAY_SIZE(ca_bt_lpc_grp_pad_mux),
2282 .pad_mux_list = ca_bt_lpc_grp_pad_mux,
2283 };
2284
2285 static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = {
2286 MUX(1, 129, 1, N, N, N, N),
2287 MUX(1, 130, 1, N, N, N, N),
2288 MUX(1, 131, 1, N, N, N, N),
2289 MUX(1, 132, 1, N, N, N, N),
2290 };
2291
2292 static struct atlas7_grp_mux ca_coex_grp_mux = {
2293 .pad_mux_count = ARRAY_SIZE(ca_coex_grp_pad_mux),
2294 .pad_mux_list = ca_coex_grp_pad_mux,
2295 };
2296
2297 static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = {
2298 MUX(1, 57, 4, N, N, N, N),
2299 MUX(1, 58, 4, N, N, N, N),
2300 MUX(1, 59, 4, N, N, N, N),
2301 MUX(1, 60, 4, N, N, N, N),
2302 };
2303
2304 static struct atlas7_grp_mux ca_curator_lpc_grp_mux = {
2305 .pad_mux_count = ARRAY_SIZE(ca_curator_lpc_grp_pad_mux),
2306 .pad_mux_list = ca_curator_lpc_grp_pad_mux,
2307 };
2308
2309 static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = {
2310 MUX(1, 91, 5, N, N, N, N),
2311 MUX(1, 93, 5, N, N, N, N),
2312 MUX(1, 94, 5, N, N, N, N),
2313 MUX(1, 92, 5, N, N, N, N),
2314 };
2315
2316 static struct atlas7_grp_mux ca_pcm_debug_grp_mux = {
2317 .pad_mux_count = ARRAY_SIZE(ca_pcm_debug_grp_pad_mux),
2318 .pad_mux_list = ca_pcm_debug_grp_pad_mux,
2319 };
2320
2321 static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = {
2322 MUX(1, 121, 2, N, N, N, N),
2323 MUX(1, 122, 2, N, N, N, N),
2324 MUX(1, 125, 6, N, N, N, N),
2325 MUX(1, 126, 6, N, N, N, N),
2326 MUX(1, 38, 5, N, N, N, N),
2327 MUX(1, 37, 5, N, N, N, N),
2328 MUX(1, 47, 5, N, N, N, N),
2329 MUX(1, 49, 5, N, N, N, N),
2330 MUX(1, 50, 5, N, N, N, N),
2331 MUX(1, 54, 4, N, N, N, N),
2332 MUX(1, 55, 4, N, N, N, N),
2333 MUX(1, 56, 4, N, N, N, N),
2334 };
2335
2336 static struct atlas7_grp_mux ca_pio_grp_mux = {
2337 .pad_mux_count = ARRAY_SIZE(ca_pio_grp_pad_mux),
2338 .pad_mux_list = ca_pio_grp_pad_mux,
2339 };
2340
2341 static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = {
2342 MUX(1, 40, 5, N, N, N, N),
2343 MUX(1, 39, 5, N, N, N, N),
2344 MUX(1, 44, 5, N, N, N, N),
2345 MUX(1, 43, 5, N, N, N, N),
2346 MUX(1, 42, 5, N, N, N, N),
2347 MUX(1, 41, 5, N, N, N, N),
2348 };
2349
2350 static struct atlas7_grp_mux ca_sdio_debug_grp_mux = {
2351 .pad_mux_count = ARRAY_SIZE(ca_sdio_debug_grp_pad_mux),
2352 .pad_mux_list = ca_sdio_debug_grp_pad_mux,
2353 };
2354
2355 static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = {
2356 MUX(1, 82, 5, N, N, N, N),
2357 MUX(1, 79, 5, 0xa08, 6, 0xa88, 6),
2358 MUX(1, 80, 5, N, N, N, N),
2359 MUX(1, 81, 5, N, N, N, N),
2360 };
2361
2362 static struct atlas7_grp_mux ca_spi_grp_mux = {
2363 .pad_mux_count = ARRAY_SIZE(ca_spi_grp_pad_mux),
2364 .pad_mux_list = ca_spi_grp_pad_mux,
2365 };
2366
2367 static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = {
2368 MUX(1, 91, 4, N, N, N, N),
2369 MUX(1, 93, 4, N, N, N, N),
2370 MUX(1, 94, 4, N, N, N, N),
2371 MUX(1, 95, 4, N, N, N, N),
2372 MUX(1, 96, 4, N, N, N, N),
2373 MUX(1, 78, 5, N, N, N, N),
2374 MUX(1, 74, 5, N, N, N, N),
2375 MUX(1, 75, 5, N, N, N, N),
2376 MUX(1, 76, 5, N, N, N, N),
2377 MUX(1, 77, 5, N, N, N, N),
2378 };
2379
2380 static struct atlas7_grp_mux ca_trb_grp_mux = {
2381 .pad_mux_count = ARRAY_SIZE(ca_trb_grp_pad_mux),
2382 .pad_mux_list = ca_trb_grp_pad_mux,
2383 };
2384
2385 static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = {
2386 MUX(1, 136, 3, N, N, N, N),
2387 MUX(1, 135, 3, N, N, N, N),
2388 MUX(1, 134, 3, N, N, N, N),
2389 MUX(1, 133, 3, N, N, N, N),
2390 };
2391
2392 static struct atlas7_grp_mux ca_uart_debug_grp_mux = {
2393 .pad_mux_count = ARRAY_SIZE(ca_uart_debug_grp_pad_mux),
2394 .pad_mux_list = ca_uart_debug_grp_pad_mux,
2395 };
2396
2397 static struct atlas7_pad_mux clkc_grp0_pad_mux[] = {
2398 MUX(1, 30, 2, 0xa08, 14, 0xa88, 14),
2399 MUX(1, 47, 6, N, N, N, N),
2400 };
2401
2402 static struct atlas7_grp_mux clkc_grp0_mux = {
2403 .pad_mux_count = ARRAY_SIZE(clkc_grp0_pad_mux),
2404 .pad_mux_list = clkc_grp0_pad_mux,
2405 };
2406
2407 static struct atlas7_pad_mux clkc_grp1_pad_mux[] = {
2408 MUX(1, 78, 3, 0xa08, 14, 0xa88, 14),
2409 MUX(1, 54, 5, N, N, N, N),
2410 };
2411
2412 static struct atlas7_grp_mux clkc_grp1_mux = {
2413 .pad_mux_count = ARRAY_SIZE(clkc_grp1_pad_mux),
2414 .pad_mux_list = clkc_grp1_pad_mux,
2415 };
2416
2417 static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = {
2418 MUX(1, 128, 2, N, N, N, N),
2419 MUX(1, 127, 2, N, N, N, N),
2420 };
2421
2422 static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = {
2423 .pad_mux_count = ARRAY_SIZE(gn_gnss_i2c_grp_pad_mux),
2424 .pad_mux_list = gn_gnss_i2c_grp_pad_mux,
2425 };
2426
2427 static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = {
2428 MUX(1, 134, 4, N, N, N, N),
2429 MUX(1, 133, 4, N, N, N, N),
2430 };
2431
2432 static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = {
2433 .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_nopause_grp_pad_mux),
2434 .pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux,
2435 };
2436
2437 static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = {
2438 MUX(1, 134, 4, N, N, N, N),
2439 MUX(1, 133, 4, N, N, N, N),
2440 MUX(1, 136, 4, N, N, N, N),
2441 MUX(1, 135, 4, N, N, N, N),
2442 };
2443
2444 static struct atlas7_grp_mux gn_gnss_uart_grp_mux = {
2445 .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_grp_pad_mux),
2446 .pad_mux_list = gn_gnss_uart_grp_pad_mux,
2447 };
2448
2449 static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = {
2450 MUX(1, 22, 1, N, N, N, N),
2451 MUX(1, 25, 1, N, N, N, N),
2452 MUX(1, 23, 1, 0xa00, 10, 0xa80, 10),
2453 MUX(1, 24, 1, N, N, N, N),
2454 };
2455
2456 static struct atlas7_grp_mux gn_trg_spi_grp0_mux = {
2457 .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp0_pad_mux),
2458 .pad_mux_list = gn_trg_spi_grp0_pad_mux,
2459 };
2460
2461 static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = {
2462 MUX(1, 82, 3, N, N, N, N),
2463 MUX(1, 79, 3, N, N, N, N),
2464 MUX(1, 80, 3, 0xa00, 10, 0xa80, 10),
2465 MUX(1, 81, 3, N, N, N, N),
2466 };
2467
2468 static struct atlas7_grp_mux gn_trg_spi_grp1_mux = {
2469 .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp1_pad_mux),
2470 .pad_mux_list = gn_trg_spi_grp1_pad_mux,
2471 };
2472
2473 static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = {
2474 MUX(1, 54, 3, N, N, N, N),
2475 MUX(1, 53, 3, N, N, N, N),
2476 MUX(1, 82, 7, N, N, N, N),
2477 MUX(1, 74, 7, N, N, N, N),
2478 MUX(1, 75, 7, N, N, N, N),
2479 MUX(1, 76, 7, N, N, N, N),
2480 MUX(1, 77, 7, N, N, N, N),
2481 MUX(1, 78, 7, N, N, N, N),
2482 MUX(1, 79, 7, N, N, N, N),
2483 MUX(1, 80, 7, N, N, N, N),
2484 MUX(1, 81, 7, N, N, N, N),
2485 MUX(1, 83, 7, N, N, N, N),
2486 MUX(1, 84, 7, N, N, N, N),
2487 MUX(1, 73, 3, N, N, N, N),
2488 MUX(1, 55, 3, N, N, N, N),
2489 MUX(1, 56, 3, N, N, N, N),
2490 };
2491
2492 static struct atlas7_grp_mux cvbs_dbg_grp_mux = {
2493 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_grp_pad_mux),
2494 .pad_mux_list = cvbs_dbg_grp_pad_mux,
2495 };
2496
2497 static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = {
2498 MUX(1, 57, 3, N, N, N, N),
2499 };
2500
2501 static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = {
2502 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp0_pad_mux),
2503 .pad_mux_list = cvbs_dbg_test_grp0_pad_mux,
2504 };
2505
2506 static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = {
2507 MUX(1, 58, 3, N, N, N, N),
2508 };
2509
2510 static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = {
2511 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp1_pad_mux),
2512 .pad_mux_list = cvbs_dbg_test_grp1_pad_mux,
2513 };
2514
2515 static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = {
2516 MUX(1, 59, 3, N, N, N, N),
2517 };
2518
2519 static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = {
2520 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp2_pad_mux),
2521 .pad_mux_list = cvbs_dbg_test_grp2_pad_mux,
2522 };
2523
2524 static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = {
2525 MUX(1, 60, 3, N, N, N, N),
2526 };
2527
2528 static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = {
2529 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp3_pad_mux),
2530 .pad_mux_list = cvbs_dbg_test_grp3_pad_mux,
2531 };
2532
2533 static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = {
2534 MUX(1, 61, 3, N, N, N, N),
2535 };
2536
2537 static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = {
2538 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp4_pad_mux),
2539 .pad_mux_list = cvbs_dbg_test_grp4_pad_mux,
2540 };
2541
2542 static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = {
2543 MUX(1, 62, 3, N, N, N, N),
2544 };
2545
2546 static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = {
2547 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp5_pad_mux),
2548 .pad_mux_list = cvbs_dbg_test_grp5_pad_mux,
2549 };
2550
2551 static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = {
2552 MUX(1, 63, 3, N, N, N, N),
2553 };
2554
2555 static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = {
2556 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp6_pad_mux),
2557 .pad_mux_list = cvbs_dbg_test_grp6_pad_mux,
2558 };
2559
2560 static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = {
2561 MUX(1, 64, 3, N, N, N, N),
2562 };
2563
2564 static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = {
2565 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp7_pad_mux),
2566 .pad_mux_list = cvbs_dbg_test_grp7_pad_mux,
2567 };
2568
2569 static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = {
2570 MUX(1, 65, 3, N, N, N, N),
2571 };
2572
2573 static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = {
2574 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp8_pad_mux),
2575 .pad_mux_list = cvbs_dbg_test_grp8_pad_mux,
2576 };
2577
2578 static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = {
2579 MUX(1, 66, 3, N, N, N, N),
2580 };
2581
2582 static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = {
2583 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp9_pad_mux),
2584 .pad_mux_list = cvbs_dbg_test_grp9_pad_mux,
2585 };
2586
2587 static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = {
2588 MUX(1, 67, 3, N, N, N, N),
2589 };
2590
2591 static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = {
2592 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp10_pad_mux),
2593 .pad_mux_list = cvbs_dbg_test_grp10_pad_mux,
2594 };
2595
2596 static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = {
2597 MUX(1, 68, 3, N, N, N, N),
2598 };
2599
2600 static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = {
2601 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp11_pad_mux),
2602 .pad_mux_list = cvbs_dbg_test_grp11_pad_mux,
2603 };
2604
2605 static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = {
2606 MUX(1, 69, 3, N, N, N, N),
2607 };
2608
2609 static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = {
2610 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp12_pad_mux),
2611 .pad_mux_list = cvbs_dbg_test_grp12_pad_mux,
2612 };
2613
2614 static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = {
2615 MUX(1, 70, 3, N, N, N, N),
2616 };
2617
2618 static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = {
2619 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp13_pad_mux),
2620 .pad_mux_list = cvbs_dbg_test_grp13_pad_mux,
2621 };
2622
2623 static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = {
2624 MUX(1, 71, 3, N, N, N, N),
2625 };
2626
2627 static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = {
2628 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp14_pad_mux),
2629 .pad_mux_list = cvbs_dbg_test_grp14_pad_mux,
2630 };
2631
2632 static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = {
2633 MUX(1, 72, 3, N, N, N, N),
2634 };
2635
2636 static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = {
2637 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp15_pad_mux),
2638 .pad_mux_list = cvbs_dbg_test_grp15_pad_mux,
2639 };
2640
2641 static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = {
2642 MUX(1, 123, 7, N, N, N, N),
2643 MUX(1, 124, 7, N, N, N, N),
2644 MUX(1, 121, 7, N, N, N, N),
2645 MUX(1, 122, 7, N, N, N, N),
2646 MUX(1, 125, 7, N, N, N, N),
2647 MUX(1, 120, 7, N, N, N, N),
2648 };
2649
2650 static struct atlas7_grp_mux gn_gnss_power_grp_mux = {
2651 .pad_mux_count = ARRAY_SIZE(gn_gnss_power_grp_pad_mux),
2652 .pad_mux_list = gn_gnss_power_grp_pad_mux,
2653 };
2654
2655 static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = {
2656 MUX(1, 57, 7, N, N, N, N),
2657 MUX(1, 58, 7, N, N, N, N),
2658 MUX(1, 59, 7, N, N, N, N),
2659 MUX(1, 60, 7, N, N, N, N),
2660 MUX(1, 61, 7, N, N, N, N),
2661 MUX(1, 62, 7, N, N, N, N),
2662 MUX(1, 63, 7, N, N, N, N),
2663 MUX(1, 64, 7, N, N, N, N),
2664 MUX(1, 65, 7, N, N, N, N),
2665 MUX(1, 66, 7, N, N, N, N),
2666 MUX(1, 67, 7, N, N, N, N),
2667 MUX(1, 68, 7, N, N, N, N),
2668 MUX(1, 69, 7, N, N, N, N),
2669 MUX(1, 70, 7, N, N, N, N),
2670 MUX(1, 71, 7, N, N, N, N),
2671 MUX(1, 72, 7, N, N, N, N),
2672 MUX(1, 53, 7, N, N, N, N),
2673 MUX(1, 55, 7, N, N, N, N),
2674 MUX(1, 56, 7, 0xa08, 12, 0xa88, 12),
2675 MUX(1, 54, 7, N, N, N, N),
2676 };
2677
2678 static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = {
2679 .pad_mux_count = ARRAY_SIZE(gn_gnss_sw_status_grp_pad_mux),
2680 .pad_mux_list = gn_gnss_sw_status_grp_pad_mux,
2681 };
2682
2683 static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = {
2684 MUX(1, 113, 4, N, N, N, N),
2685 };
2686
2687 static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = {
2688 .pad_mux_count = ARRAY_SIZE(gn_gnss_eclk_grp_pad_mux),
2689 .pad_mux_list = gn_gnss_eclk_grp_pad_mux,
2690 };
2691
2692 static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = {
2693 MUX(1, 112, 4, 0xa08, 10, 0xa88, 10),
2694 };
2695
2696 static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = {
2697 .pad_mux_count = ARRAY_SIZE(gn_gnss_irq1_grp0_pad_mux),
2698 .pad_mux_list = gn_gnss_irq1_grp0_pad_mux,
2699 };
2700
2701 static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = {
2702 MUX(1, 118, 4, 0xa08, 11, 0xa88, 11),
2703 };
2704
2705 static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = {
2706 .pad_mux_count = ARRAY_SIZE(gn_gnss_irq2_grp0_pad_mux),
2707 .pad_mux_list = gn_gnss_irq2_grp0_pad_mux,
2708 };
2709
2710 static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = {
2711 MUX(1, 115, 4, N, N, N, N),
2712 };
2713
2714 static struct atlas7_grp_mux gn_gnss_tm_grp_mux = {
2715 .pad_mux_count = ARRAY_SIZE(gn_gnss_tm_grp_pad_mux),
2716 .pad_mux_list = gn_gnss_tm_grp_pad_mux,
2717 };
2718
2719 static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = {
2720 MUX(1, 114, 4, N, N, N, N),
2721 };
2722
2723 static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = {
2724 .pad_mux_count = ARRAY_SIZE(gn_gnss_tsync_grp_pad_mux),
2725 .pad_mux_list = gn_gnss_tsync_grp_pad_mux,
2726 };
2727
2728 static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = {
2729 MUX(1, 44, 7, N, N, N, N),
2730 MUX(1, 43, 7, N, N, N, N),
2731 MUX(1, 42, 7, N, N, N, N),
2732 MUX(1, 41, 7, N, N, N, N),
2733 MUX(1, 40, 7, N, N, N, N),
2734 MUX(1, 39, 7, N, N, N, N),
2735 MUX(1, 38, 7, N, N, N, N),
2736 MUX(1, 37, 7, N, N, N, N),
2737 MUX(1, 49, 7, N, N, N, N),
2738 MUX(1, 50, 7, N, N, N, N),
2739 MUX(1, 91, 7, N, N, N, N),
2740 MUX(1, 92, 7, N, N, N, N),
2741 MUX(1, 93, 7, N, N, N, N),
2742 MUX(1, 94, 7, N, N, N, N),
2743 MUX(1, 95, 7, N, N, N, N),
2744 MUX(1, 96, 7, N, N, N, N),
2745 };
2746
2747 static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = {
2748 .pad_mux_count = ARRAY_SIZE(gn_io_gnsssys_sw_cfg_grp_pad_mux),
2749 .pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux,
2750 };
2751
2752 static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = {
2753 MUX(1, 29, 1, 0xa00, 6, 0xa80, 6),
2754 MUX(1, 28, 1, 0xa00, 7, 0xa80, 7),
2755 MUX(1, 26, 1, 0xa00, 8, 0xa80, 8),
2756 MUX(1, 27, 1, 0xa00, 9, 0xa80, 9),
2757 };
2758
2759 static struct atlas7_grp_mux gn_trg_grp0_mux = {
2760 .pad_mux_count = ARRAY_SIZE(gn_trg_grp0_pad_mux),
2761 .pad_mux_list = gn_trg_grp0_pad_mux,
2762 };
2763
2764 static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = {
2765 MUX(1, 77, 3, 0xa00, 6, 0xa80, 6),
2766 MUX(1, 76, 3, 0xa00, 7, 0xa80, 7),
2767 MUX(1, 74, 3, 0xa00, 8, 0xa80, 8),
2768 MUX(1, 75, 3, 0xa00, 9, 0xa80, 9),
2769 };
2770
2771 static struct atlas7_grp_mux gn_trg_grp1_mux = {
2772 .pad_mux_count = ARRAY_SIZE(gn_trg_grp1_pad_mux),
2773 .pad_mux_list = gn_trg_grp1_pad_mux,
2774 };
2775
2776 static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = {
2777 MUX(1, 30, 1, N, N, N, N),
2778 };
2779
2780 static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = {
2781 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp0_pad_mux),
2782 .pad_mux_list = gn_trg_shutdown_grp0_pad_mux,
2783 };
2784
2785 static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = {
2786 MUX(1, 83, 3, N, N, N, N),
2787 };
2788
2789 static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = {
2790 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp1_pad_mux),
2791 .pad_mux_list = gn_trg_shutdown_grp1_pad_mux,
2792 };
2793
2794 static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = {
2795 MUX(1, 117, 4, N, N, N, N),
2796 };
2797
2798 static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = {
2799 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp2_pad_mux),
2800 .pad_mux_list = gn_trg_shutdown_grp2_pad_mux,
2801 };
2802
2803 static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = {
2804 MUX(1, 123, 5, N, N, N, N),
2805 };
2806
2807 static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = {
2808 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp3_pad_mux),
2809 .pad_mux_list = gn_trg_shutdown_grp3_pad_mux,
2810 };
2811
2812 static struct atlas7_pad_mux i2c0_grp_pad_mux[] = {
2813 MUX(1, 128, 1, N, N, N, N),
2814 MUX(1, 127, 1, N, N, N, N),
2815 };
2816
2817 static struct atlas7_grp_mux i2c0_grp_mux = {
2818 .pad_mux_count = ARRAY_SIZE(i2c0_grp_pad_mux),
2819 .pad_mux_list = i2c0_grp_pad_mux,
2820 };
2821
2822 static struct atlas7_pad_mux i2c1_grp_pad_mux[] = {
2823 MUX(1, 126, 4, N, N, N, N),
2824 MUX(1, 125, 4, N, N, N, N),
2825 };
2826
2827 static struct atlas7_grp_mux i2c1_grp_mux = {
2828 .pad_mux_count = ARRAY_SIZE(i2c1_grp_pad_mux),
2829 .pad_mux_list = i2c1_grp_pad_mux,
2830 };
2831
2832 static struct atlas7_pad_mux i2s0_grp_pad_mux[] = {
2833 MUX(1, 91, 2, 0xa10, 12, 0xa90, 12),
2834 MUX(1, 93, 2, 0xa10, 13, 0xa90, 13),
2835 MUX(1, 94, 2, 0xa10, 14, 0xa90, 14),
2836 MUX(1, 92, 2, 0xa10, 15, 0xa90, 15),
2837 };
2838
2839 static struct atlas7_grp_mux i2s0_grp_mux = {
2840 .pad_mux_count = ARRAY_SIZE(i2s0_grp_pad_mux),
2841 .pad_mux_list = i2s0_grp_pad_mux,
2842 };
2843
2844 static struct atlas7_pad_mux i2s1_basic_grp_pad_mux[] = {
2845 MUX(1, 95, 2, 0xa10, 16, 0xa90, 16),
2846 MUX(1, 96, 2, 0xa10, 19, 0xa90, 19),
2847 };
2848
2849 static struct atlas7_grp_mux i2s1_basic_grp_mux = {
2850 .pad_mux_count = ARRAY_SIZE(i2s1_basic_grp_pad_mux),
2851 .pad_mux_list = i2s1_basic_grp_pad_mux,
2852 };
2853
2854 static struct atlas7_pad_mux i2s1_rxd0_grp0_pad_mux[] = {
2855 MUX(1, 61, 4, 0xa10, 17, 0xa90, 17),
2856 };
2857
2858 static struct atlas7_grp_mux i2s1_rxd0_grp0_mux = {
2859 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp0_pad_mux),
2860 .pad_mux_list = i2s1_rxd0_grp0_pad_mux,
2861 };
2862
2863 static struct atlas7_pad_mux i2s1_rxd0_grp1_pad_mux[] = {
2864 MUX(1, 131, 4, 0xa10, 17, 0xa90, 17),
2865 };
2866
2867 static struct atlas7_grp_mux i2s1_rxd0_grp1_mux = {
2868 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp1_pad_mux),
2869 .pad_mux_list = i2s1_rxd0_grp1_pad_mux,
2870 };
2871
2872 static struct atlas7_pad_mux i2s1_rxd0_grp2_pad_mux[] = {
2873 MUX(1, 129, 2, 0xa10, 17, 0xa90, 17),
2874 };
2875
2876 static struct atlas7_grp_mux i2s1_rxd0_grp2_mux = {
2877 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp2_pad_mux),
2878 .pad_mux_list = i2s1_rxd0_grp2_pad_mux,
2879 };
2880
2881 static struct atlas7_pad_mux i2s1_rxd0_grp3_pad_mux[] = {
2882 MUX(1, 117, 7, 0xa10, 17, 0xa90, 17),
2883 };
2884
2885 static struct atlas7_grp_mux i2s1_rxd0_grp3_mux = {
2886 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp3_pad_mux),
2887 .pad_mux_list = i2s1_rxd0_grp3_pad_mux,
2888 };
2889
2890 static struct atlas7_pad_mux i2s1_rxd0_grp4_pad_mux[] = {
2891 MUX(1, 83, 4, 0xa10, 17, 0xa90, 17),
2892 };
2893
2894 static struct atlas7_grp_mux i2s1_rxd0_grp4_mux = {
2895 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp4_pad_mux),
2896 .pad_mux_list = i2s1_rxd0_grp4_pad_mux,
2897 };
2898
2899 static struct atlas7_pad_mux i2s1_rxd1_grp0_pad_mux[] = {
2900 MUX(1, 72, 4, 0xa10, 18, 0xa90, 18),
2901 };
2902
2903 static struct atlas7_grp_mux i2s1_rxd1_grp0_mux = {
2904 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp0_pad_mux),
2905 .pad_mux_list = i2s1_rxd1_grp0_pad_mux,
2906 };
2907
2908 static struct atlas7_pad_mux i2s1_rxd1_grp1_pad_mux[] = {
2909 MUX(1, 132, 4, 0xa10, 18, 0xa90, 18),
2910 };
2911
2912 static struct atlas7_grp_mux i2s1_rxd1_grp1_mux = {
2913 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp1_pad_mux),
2914 .pad_mux_list = i2s1_rxd1_grp1_pad_mux,
2915 };
2916
2917 static struct atlas7_pad_mux i2s1_rxd1_grp2_pad_mux[] = {
2918 MUX(1, 130, 2, 0xa10, 18, 0xa90, 18),
2919 };
2920
2921 static struct atlas7_grp_mux i2s1_rxd1_grp2_mux = {
2922 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp2_pad_mux),
2923 .pad_mux_list = i2s1_rxd1_grp2_pad_mux,
2924 };
2925
2926 static struct atlas7_pad_mux i2s1_rxd1_grp3_pad_mux[] = {
2927 MUX(1, 118, 7, 0xa10, 18, 0xa90, 18),
2928 };
2929
2930 static struct atlas7_grp_mux i2s1_rxd1_grp3_mux = {
2931 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp3_pad_mux),
2932 .pad_mux_list = i2s1_rxd1_grp3_pad_mux,
2933 };
2934
2935 static struct atlas7_pad_mux i2s1_rxd1_grp4_pad_mux[] = {
2936 MUX(1, 84, 4, 0xa10, 18, 0xa90, 18),
2937 };
2938
2939 static struct atlas7_grp_mux i2s1_rxd1_grp4_mux = {
2940 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp4_pad_mux),
2941 .pad_mux_list = i2s1_rxd1_grp4_pad_mux,
2942 };
2943
2944 static struct atlas7_pad_mux jtag_jt_dbg_nsrst_grp_pad_mux[] = {
2945 MUX(1, 125, 5, 0xa08, 2, 0xa88, 2),
2946 };
2947
2948 static struct atlas7_grp_mux jtag_jt_dbg_nsrst_grp_mux = {
2949 .pad_mux_count = ARRAY_SIZE(jtag_jt_dbg_nsrst_grp_pad_mux),
2950 .pad_mux_list = jtag_jt_dbg_nsrst_grp_pad_mux,
2951 };
2952
2953 static struct atlas7_pad_mux jtag_ntrst_grp0_pad_mux[] = {
2954 MUX(0, 4, 3, 0xa08, 3, 0xa88, 3),
2955 };
2956
2957 static struct atlas7_grp_mux jtag_ntrst_grp0_mux = {
2958 .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp0_pad_mux),
2959 .pad_mux_list = jtag_ntrst_grp0_pad_mux,
2960 };
2961
2962 static struct atlas7_pad_mux jtag_ntrst_grp1_pad_mux[] = {
2963 MUX(1, 163, 1, 0xa08, 3, 0xa88, 3),
2964 };
2965
2966 static struct atlas7_grp_mux jtag_ntrst_grp1_mux = {
2967 .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp1_pad_mux),
2968 .pad_mux_list = jtag_ntrst_grp1_pad_mux,
2969 };
2970
2971 static struct atlas7_pad_mux jtag_swdiotms_grp0_pad_mux[] = {
2972 MUX(0, 2, 3, 0xa10, 10, 0xa90, 10),
2973 };
2974
2975 static struct atlas7_grp_mux jtag_swdiotms_grp0_mux = {
2976 .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp0_pad_mux),
2977 .pad_mux_list = jtag_swdiotms_grp0_pad_mux,
2978 };
2979
2980 static struct atlas7_pad_mux jtag_swdiotms_grp1_pad_mux[] = {
2981 MUX(1, 160, 1, 0xa10, 10, 0xa90, 10),
2982 };
2983
2984 static struct atlas7_grp_mux jtag_swdiotms_grp1_mux = {
2985 .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp1_pad_mux),
2986 .pad_mux_list = jtag_swdiotms_grp1_pad_mux,
2987 };
2988
2989 static struct atlas7_pad_mux jtag_tck_grp0_pad_mux[] = {
2990 MUX(0, 0, 3, 0xa10, 11, 0xa90, 11),
2991 };
2992
2993 static struct atlas7_grp_mux jtag_tck_grp0_mux = {
2994 .pad_mux_count = ARRAY_SIZE(jtag_tck_grp0_pad_mux),
2995 .pad_mux_list = jtag_tck_grp0_pad_mux,
2996 };
2997
2998 static struct atlas7_pad_mux jtag_tck_grp1_pad_mux[] = {
2999 MUX(1, 161, 1, 0xa10, 11, 0xa90, 11),
3000 };
3001
3002 static struct atlas7_grp_mux jtag_tck_grp1_mux = {
3003 .pad_mux_count = ARRAY_SIZE(jtag_tck_grp1_pad_mux),
3004 .pad_mux_list = jtag_tck_grp1_pad_mux,
3005 };
3006
3007 static struct atlas7_pad_mux jtag_tdi_grp0_pad_mux[] = {
3008 MUX(0, 1, 3, 0xa10, 31, 0xa90, 31),
3009 };
3010
3011 static struct atlas7_grp_mux jtag_tdi_grp0_mux = {
3012 .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp0_pad_mux),
3013 .pad_mux_list = jtag_tdi_grp0_pad_mux,
3014 };
3015
3016 static struct atlas7_pad_mux jtag_tdi_grp1_pad_mux[] = {
3017 MUX(1, 162, 1, 0xa10, 31, 0xa90, 31),
3018 };
3019
3020 static struct atlas7_grp_mux jtag_tdi_grp1_mux = {
3021 .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp1_pad_mux),
3022 .pad_mux_list = jtag_tdi_grp1_pad_mux,
3023 };
3024
3025 static struct atlas7_pad_mux jtag_tdo_grp0_pad_mux[] = {
3026 MUX(0, 3, 3, N, N, N, N),
3027 };
3028
3029 static struct atlas7_grp_mux jtag_tdo_grp0_mux = {
3030 .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp0_pad_mux),
3031 .pad_mux_list = jtag_tdo_grp0_pad_mux,
3032 };
3033
3034 static struct atlas7_pad_mux jtag_tdo_grp1_pad_mux[] = {
3035 MUX(1, 159, 1, N, N, N, N),
3036 };
3037
3038 static struct atlas7_grp_mux jtag_tdo_grp1_mux = {
3039 .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp1_pad_mux),
3040 .pad_mux_list = jtag_tdo_grp1_pad_mux,
3041 };
3042
3043 static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = {
3044 MUX(1, 141, 2, N, N, N, N),
3045 MUX(1, 144, 2, 0xa08, 8, 0xa88, 8),
3046 MUX(1, 143, 2, N, N, N, N),
3047 MUX(1, 142, 2, N, N, N, N),
3048 };
3049
3050 static struct atlas7_grp_mux ks_kas_spi_grp0_mux = {
3051 .pad_mux_count = ARRAY_SIZE(ks_kas_spi_grp0_pad_mux),
3052 .pad_mux_list = ks_kas_spi_grp0_pad_mux,
3053 };
3054
3055 static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = {
3056 MUX(1, 57, 1, N, N, N, N),
3057 MUX(1, 58, 1, N, N, N, N),
3058 MUX(1, 59, 1, N, N, N, N),
3059 MUX(1, 60, 1, N, N, N, N),
3060 MUX(1, 61, 1, N, N, N, N),
3061 MUX(1, 62, 1, N, N, N, N),
3062 MUX(1, 63, 1, N, N, N, N),
3063 MUX(1, 64, 1, N, N, N, N),
3064 MUX(1, 65, 1, N, N, N, N),
3065 MUX(1, 66, 1, N, N, N, N),
3066 MUX(1, 67, 1, N, N, N, N),
3067 MUX(1, 68, 1, N, N, N, N),
3068 MUX(1, 69, 1, N, N, N, N),
3069 MUX(1, 70, 1, N, N, N, N),
3070 MUX(1, 71, 1, N, N, N, N),
3071 MUX(1, 72, 1, N, N, N, N),
3072 MUX(1, 74, 2, N, N, N, N),
3073 MUX(1, 75, 2, N, N, N, N),
3074 MUX(1, 76, 2, N, N, N, N),
3075 MUX(1, 77, 2, N, N, N, N),
3076 MUX(1, 78, 2, N, N, N, N),
3077 MUX(1, 79, 2, N, N, N, N),
3078 MUX(1, 80, 2, N, N, N, N),
3079 MUX(1, 81, 2, N, N, N, N),
3080 MUX(1, 56, 1, N, N, N, N),
3081 MUX(1, 53, 1, N, N, N, N),
3082 };
3083
3084 static struct atlas7_grp_mux ld_ldd_grp_mux = {
3085 .pad_mux_count = ARRAY_SIZE(ld_ldd_grp_pad_mux),
3086 .pad_mux_list = ld_ldd_grp_pad_mux,
3087 };
3088
3089 static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = {
3090 MUX(1, 57, 1, N, N, N, N),
3091 MUX(1, 58, 1, N, N, N, N),
3092 MUX(1, 59, 1, N, N, N, N),
3093 MUX(1, 60, 1, N, N, N, N),
3094 MUX(1, 61, 1, N, N, N, N),
3095 MUX(1, 62, 1, N, N, N, N),
3096 MUX(1, 63, 1, N, N, N, N),
3097 MUX(1, 64, 1, N, N, N, N),
3098 MUX(1, 65, 1, N, N, N, N),
3099 MUX(1, 66, 1, N, N, N, N),
3100 MUX(1, 67, 1, N, N, N, N),
3101 MUX(1, 68, 1, N, N, N, N),
3102 MUX(1, 69, 1, N, N, N, N),
3103 MUX(1, 70, 1, N, N, N, N),
3104 MUX(1, 71, 1, N, N, N, N),
3105 MUX(1, 72, 1, N, N, N, N),
3106 MUX(1, 56, 1, N, N, N, N),
3107 MUX(1, 53, 1, N, N, N, N),
3108 };
3109
3110 static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = {
3111 .pad_mux_count = ARRAY_SIZE(ld_ldd_16bit_grp_pad_mux),
3112 .pad_mux_list = ld_ldd_16bit_grp_pad_mux,
3113 };
3114
3115 static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = {
3116 MUX(1, 55, 1, N, N, N, N),
3117 };
3118
3119 static struct atlas7_grp_mux ld_ldd_fck_grp_mux = {
3120 .pad_mux_count = ARRAY_SIZE(ld_ldd_fck_grp_pad_mux),
3121 .pad_mux_list = ld_ldd_fck_grp_pad_mux,
3122 };
3123
3124 static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = {
3125 MUX(1, 54, 1, N, N, N, N),
3126 };
3127
3128 static struct atlas7_grp_mux ld_ldd_lck_grp_mux = {
3129 .pad_mux_count = ARRAY_SIZE(ld_ldd_lck_grp_pad_mux),
3130 .pad_mux_list = ld_ldd_lck_grp_pad_mux,
3131 };
3132
3133 static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = {
3134 MUX(1, 73, 2, N, N, N, N),
3135 MUX(1, 54, 2, N, N, N, N),
3136 MUX(1, 57, 2, N, N, N, N),
3137 MUX(1, 58, 2, N, N, N, N),
3138 MUX(1, 59, 2, N, N, N, N),
3139 MUX(1, 60, 2, N, N, N, N),
3140 MUX(1, 61, 2, N, N, N, N),
3141 MUX(1, 62, 2, N, N, N, N),
3142 MUX(1, 63, 2, N, N, N, N),
3143 MUX(1, 64, 2, N, N, N, N),
3144 MUX(1, 65, 2, N, N, N, N),
3145 MUX(1, 66, 2, N, N, N, N),
3146 MUX(1, 67, 2, N, N, N, N),
3147 MUX(1, 68, 2, N, N, N, N),
3148 MUX(1, 69, 2, N, N, N, N),
3149 MUX(1, 70, 2, N, N, N, N),
3150 MUX(1, 71, 2, N, N, N, N),
3151 MUX(1, 72, 2, N, N, N, N),
3152 MUX(1, 56, 2, N, N, N, N),
3153 MUX(1, 53, 2, N, N, N, N),
3154 MUX(1, 55, 2, N, N, N, N),
3155 };
3156
3157 static struct atlas7_grp_mux lr_lcdrom_grp_mux = {
3158 .pad_mux_count = ARRAY_SIZE(lr_lcdrom_grp_pad_mux),
3159 .pad_mux_list = lr_lcdrom_grp_pad_mux,
3160 };
3161
3162 static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = {
3163 MUX(1, 149, 8, N, N, N, N),
3164 MUX(1, 150, 8, N, N, N, N),
3165 MUX(1, 151, 8, N, N, N, N),
3166 MUX(1, 152, 8, N, N, N, N),
3167 MUX(1, 153, 8, N, N, N, N),
3168 MUX(1, 154, 8, N, N, N, N),
3169 MUX(1, 155, 8, N, N, N, N),
3170 MUX(1, 156, 8, N, N, N, N),
3171 MUX(1, 157, 8, N, N, N, N),
3172 MUX(1, 158, 8, N, N, N, N),
3173 };
3174
3175 static struct atlas7_grp_mux lvds_analog_grp_mux = {
3176 .pad_mux_count = ARRAY_SIZE(lvds_analog_grp_pad_mux),
3177 .pad_mux_list = lvds_analog_grp_pad_mux,
3178 };
3179
3180 static struct atlas7_pad_mux nd_df_basic_grp_pad_mux[] = {
3181 MUX(1, 44, 1, N, N, N, N),
3182 MUX(1, 43, 1, N, N, N, N),
3183 MUX(1, 42, 1, N, N, N, N),
3184 MUX(1, 41, 1, N, N, N, N),
3185 MUX(1, 40, 1, N, N, N, N),
3186 MUX(1, 39, 1, N, N, N, N),
3187 MUX(1, 38, 1, N, N, N, N),
3188 MUX(1, 37, 1, N, N, N, N),
3189 MUX(1, 47, 1, N, N, N, N),
3190 MUX(1, 46, 1, N, N, N, N),
3191 MUX(1, 52, 1, N, N, N, N),
3192 MUX(1, 45, 1, N, N, N, N),
3193 MUX(1, 49, 1, N, N, N, N),
3194 MUX(1, 50, 1, N, N, N, N),
3195 MUX(1, 48, 1, N, N, N, N),
3196 };
3197
3198 static struct atlas7_grp_mux nd_df_basic_grp_mux = {
3199 .pad_mux_count = ARRAY_SIZE(nd_df_basic_grp_pad_mux),
3200 .pad_mux_list = nd_df_basic_grp_pad_mux,
3201 };
3202
3203 static struct atlas7_pad_mux nd_df_wp_grp_pad_mux[] = {
3204 MUX(1, 124, 4, N, N, N, N),
3205 };
3206
3207 static struct atlas7_grp_mux nd_df_wp_grp_mux = {
3208 .pad_mux_count = ARRAY_SIZE(nd_df_wp_grp_pad_mux),
3209 .pad_mux_list = nd_df_wp_grp_pad_mux,
3210 };
3211
3212 static struct atlas7_pad_mux nd_df_cs_grp_pad_mux[] = {
3213 MUX(1, 51, 1, N, N, N, N),
3214 };
3215
3216 static struct atlas7_grp_mux nd_df_cs_grp_mux = {
3217 .pad_mux_count = ARRAY_SIZE(nd_df_cs_grp_pad_mux),
3218 .pad_mux_list = nd_df_cs_grp_pad_mux,
3219 };
3220
3221 static struct atlas7_pad_mux ps_grp_pad_mux[] = {
3222 MUX(1, 120, 2, N, N, N, N),
3223 MUX(1, 119, 2, N, N, N, N),
3224 MUX(1, 121, 5, N, N, N, N),
3225 };
3226
3227 static struct atlas7_grp_mux ps_grp_mux = {
3228 .pad_mux_count = ARRAY_SIZE(ps_grp_pad_mux),
3229 .pad_mux_list = ps_grp_pad_mux,
3230 };
3231
3232 static struct atlas7_pad_mux ps_no_dir_grp_pad_mux[] = {
3233 MUX(1, 119, 2, N, N, N, N),
3234 };
3235
3236 static struct atlas7_grp_mux ps_no_dir_grp_mux = {
3237 .pad_mux_count = ARRAY_SIZE(ps_no_dir_grp_pad_mux),
3238 .pad_mux_list = ps_no_dir_grp_pad_mux,
3239 };
3240
3241 static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = {
3242 MUX(0, 8, 1, N, N, N, N),
3243 };
3244
3245 static struct atlas7_grp_mux pwc_core_on_grp_mux = {
3246 .pad_mux_count = ARRAY_SIZE(pwc_core_on_grp_pad_mux),
3247 .pad_mux_list = pwc_core_on_grp_pad_mux,
3248 };
3249
3250 static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = {
3251 MUX(0, 6, 1, N, N, N, N),
3252 };
3253
3254 static struct atlas7_grp_mux pwc_ext_on_grp_mux = {
3255 .pad_mux_count = ARRAY_SIZE(pwc_ext_on_grp_pad_mux),
3256 .pad_mux_list = pwc_ext_on_grp_pad_mux,
3257 };
3258
3259 static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = {
3260 MUX(0, 3, 4, N, N, N, N),
3261 };
3262
3263 static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = {
3264 .pad_mux_count = ARRAY_SIZE(pwc_gpio3_clk_grp_pad_mux),
3265 .pad_mux_list = pwc_gpio3_clk_grp_pad_mux,
3266 };
3267
3268 static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = {
3269 MUX(0, 9, 1, N, N, N, N),
3270 };
3271
3272 static struct atlas7_grp_mux pwc_io_on_grp_mux = {
3273 .pad_mux_count = ARRAY_SIZE(pwc_io_on_grp_pad_mux),
3274 .pad_mux_list = pwc_io_on_grp_pad_mux,
3275 };
3276
3277 static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = {
3278 MUX(0, 4, 1, 0xa08, 4, 0xa88, 4),
3279 };
3280
3281 static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = {
3282 .pad_mux_count = ARRAY_SIZE(pwc_lowbatt_b_grp0_pad_mux),
3283 .pad_mux_list = pwc_lowbatt_b_grp0_pad_mux,
3284 };
3285
3286 static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = {
3287 MUX(0, 7, 1, N, N, N, N),
3288 };
3289
3290 static struct atlas7_grp_mux pwc_mem_on_grp_mux = {
3291 .pad_mux_count = ARRAY_SIZE(pwc_mem_on_grp_pad_mux),
3292 .pad_mux_list = pwc_mem_on_grp_pad_mux,
3293 };
3294
3295 static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = {
3296 MUX(0, 5, 1, 0xa08, 5, 0xa88, 5),
3297 };
3298
3299 static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = {
3300 .pad_mux_count = ARRAY_SIZE(pwc_on_key_b_grp0_pad_mux),
3301 .pad_mux_list = pwc_on_key_b_grp0_pad_mux,
3302 };
3303
3304 static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = {
3305 MUX(0, 0, 1, N, N, N, N),
3306 };
3307
3308 static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = {
3309 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src0_grp_pad_mux),
3310 .pad_mux_list = pwc_wakeup_src0_grp_pad_mux,
3311 };
3312
3313 static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = {
3314 MUX(0, 1, 1, N, N, N, N),
3315 };
3316
3317 static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = {
3318 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src1_grp_pad_mux),
3319 .pad_mux_list = pwc_wakeup_src1_grp_pad_mux,
3320 };
3321
3322 static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = {
3323 MUX(0, 2, 1, N, N, N, N),
3324 };
3325
3326 static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = {
3327 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src2_grp_pad_mux),
3328 .pad_mux_list = pwc_wakeup_src2_grp_pad_mux,
3329 };
3330
3331 static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = {
3332 MUX(0, 3, 1, N, N, N, N),
3333 };
3334
3335 static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = {
3336 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src3_grp_pad_mux),
3337 .pad_mux_list = pwc_wakeup_src3_grp_pad_mux,
3338 };
3339
3340 static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = {
3341 MUX(1, 123, 3, N, N, N, N),
3342 };
3343
3344 static struct atlas7_grp_mux pw_cko0_grp0_mux = {
3345 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp0_pad_mux),
3346 .pad_mux_list = pw_cko0_grp0_pad_mux,
3347 };
3348
3349 static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = {
3350 MUX(1, 101, 4, N, N, N, N),
3351 };
3352
3353 static struct atlas7_grp_mux pw_cko0_grp1_mux = {
3354 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp1_pad_mux),
3355 .pad_mux_list = pw_cko0_grp1_pad_mux,
3356 };
3357
3358 static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = {
3359 MUX(1, 82, 2, N, N, N, N),
3360 };
3361
3362 static struct atlas7_grp_mux pw_cko0_grp2_mux = {
3363 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp2_pad_mux),
3364 .pad_mux_list = pw_cko0_grp2_pad_mux,
3365 };
3366
3367 static struct atlas7_pad_mux pw_cko0_grp3_pad_mux[] = {
3368 MUX(1, 162, 5, N, N, N, N),
3369 };
3370
3371 static struct atlas7_grp_mux pw_cko0_grp3_mux = {
3372 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp3_pad_mux),
3373 .pad_mux_list = pw_cko0_grp3_pad_mux,
3374 };
3375
3376 static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = {
3377 MUX(1, 124, 3, N, N, N, N),
3378 };
3379
3380 static struct atlas7_grp_mux pw_cko1_grp0_mux = {
3381 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp0_pad_mux),
3382 .pad_mux_list = pw_cko1_grp0_pad_mux,
3383 };
3384
3385 static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = {
3386 MUX(1, 110, 4, N, N, N, N),
3387 };
3388
3389 static struct atlas7_grp_mux pw_cko1_grp1_mux = {
3390 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp1_pad_mux),
3391 .pad_mux_list = pw_cko1_grp1_pad_mux,
3392 };
3393
3394 static struct atlas7_pad_mux pw_cko1_grp2_pad_mux[] = {
3395 MUX(1, 163, 5, N, N, N, N),
3396 };
3397
3398 static struct atlas7_grp_mux pw_cko1_grp2_mux = {
3399 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp2_pad_mux),
3400 .pad_mux_list = pw_cko1_grp2_pad_mux,
3401 };
3402
3403 static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = {
3404 MUX(1, 125, 3, N, N, N, N),
3405 };
3406
3407 static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = {
3408 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp0_pad_mux),
3409 .pad_mux_list = pw_i2s01_clk_grp0_pad_mux,
3410 };
3411
3412 static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = {
3413 MUX(1, 117, 3, N, N, N, N),
3414 };
3415
3416 static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = {
3417 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp1_pad_mux),
3418 .pad_mux_list = pw_i2s01_clk_grp1_pad_mux,
3419 };
3420
3421 static struct atlas7_pad_mux pw_i2s01_clk_grp2_pad_mux[] = {
3422 MUX(1, 132, 2, N, N, N, N),
3423 };
3424
3425 static struct atlas7_grp_mux pw_i2s01_clk_grp2_mux = {
3426 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp2_pad_mux),
3427 .pad_mux_list = pw_i2s01_clk_grp2_pad_mux,
3428 };
3429
3430 static struct atlas7_pad_mux pw_pwm0_grp0_pad_mux[] = {
3431 MUX(1, 119, 3, N, N, N, N),
3432 };
3433
3434 static struct atlas7_grp_mux pw_pwm0_grp0_mux = {
3435 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp0_pad_mux),
3436 .pad_mux_list = pw_pwm0_grp0_pad_mux,
3437 };
3438
3439 static struct atlas7_pad_mux pw_pwm0_grp1_pad_mux[] = {
3440 MUX(1, 159, 5, N, N, N, N),
3441 };
3442
3443 static struct atlas7_grp_mux pw_pwm0_grp1_mux = {
3444 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp1_pad_mux),
3445 .pad_mux_list = pw_pwm0_grp1_pad_mux,
3446 };
3447
3448 static struct atlas7_pad_mux pw_pwm1_grp0_pad_mux[] = {
3449 MUX(1, 120, 3, N, N, N, N),
3450 };
3451
3452 static struct atlas7_grp_mux pw_pwm1_grp0_mux = {
3453 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp0_pad_mux),
3454 .pad_mux_list = pw_pwm1_grp0_pad_mux,
3455 };
3456
3457 static struct atlas7_pad_mux pw_pwm1_grp1_pad_mux[] = {
3458 MUX(1, 160, 5, N, N, N, N),
3459 };
3460
3461 static struct atlas7_grp_mux pw_pwm1_grp1_mux = {
3462 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp1_pad_mux),
3463 .pad_mux_list = pw_pwm1_grp1_pad_mux,
3464 };
3465
3466 static struct atlas7_pad_mux pw_pwm1_grp2_pad_mux[] = {
3467 MUX(1, 131, 2, N, N, N, N),
3468 };
3469
3470 static struct atlas7_grp_mux pw_pwm1_grp2_mux = {
3471 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp2_pad_mux),
3472 .pad_mux_list = pw_pwm1_grp2_pad_mux,
3473 };
3474
3475 static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = {
3476 MUX(1, 121, 3, N, N, N, N),
3477 };
3478
3479 static struct atlas7_grp_mux pw_pwm2_grp0_mux = {
3480 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp0_pad_mux),
3481 .pad_mux_list = pw_pwm2_grp0_pad_mux,
3482 };
3483
3484 static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = {
3485 MUX(1, 98, 3, N, N, N, N),
3486 };
3487
3488 static struct atlas7_grp_mux pw_pwm2_grp1_mux = {
3489 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp1_pad_mux),
3490 .pad_mux_list = pw_pwm2_grp1_pad_mux,
3491 };
3492
3493 static struct atlas7_pad_mux pw_pwm2_grp2_pad_mux[] = {
3494 MUX(1, 161, 5, N, N, N, N),
3495 };
3496
3497 static struct atlas7_grp_mux pw_pwm2_grp2_mux = {
3498 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp2_pad_mux),
3499 .pad_mux_list = pw_pwm2_grp2_pad_mux,
3500 };
3501
3502 static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = {
3503 MUX(1, 122, 3, N, N, N, N),
3504 };
3505
3506 static struct atlas7_grp_mux pw_pwm3_grp0_mux = {
3507 .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp0_pad_mux),
3508 .pad_mux_list = pw_pwm3_grp0_pad_mux,
3509 };
3510
3511 static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = {
3512 MUX(1, 73, 4, N, N, N, N),
3513 };
3514
3515 static struct atlas7_grp_mux pw_pwm3_grp1_mux = {
3516 .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp1_pad_mux),
3517 .pad_mux_list = pw_pwm3_grp1_pad_mux,
3518 };
3519
3520 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = {
3521 MUX(1, 121, 3, N, N, N, N),
3522 };
3523
3524 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = {
3525 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp0_pad_mux),
3526 .pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux,
3527 };
3528
3529 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = {
3530 MUX(1, 98, 3, N, N, N, N),
3531 };
3532
3533 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = {
3534 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp1_pad_mux),
3535 .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux,
3536 };
3537
3538 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp2_pad_mux[] = {
3539 MUX(1, 161, 5, N, N, N, N),
3540 };
3541
3542 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp2_mux = {
3543 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp2_pad_mux),
3544 .pad_mux_list = pw_pwm_cpu_vol_grp2_pad_mux,
3545 };
3546
3547 static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = {
3548 MUX(1, 122, 3, N, N, N, N),
3549 };
3550
3551 static struct atlas7_grp_mux pw_backlight_grp0_mux = {
3552 .pad_mux_count = ARRAY_SIZE(pw_backlight_grp0_pad_mux),
3553 .pad_mux_list = pw_backlight_grp0_pad_mux,
3554 };
3555
3556 static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = {
3557 MUX(1, 73, 4, N, N, N, N),
3558 };
3559
3560 static struct atlas7_grp_mux pw_backlight_grp1_mux = {
3561 .pad_mux_count = ARRAY_SIZE(pw_backlight_grp1_pad_mux),
3562 .pad_mux_list = pw_backlight_grp1_pad_mux,
3563 };
3564
3565 static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = {
3566 MUX(1, 108, 1, N, N, N, N),
3567 MUX(1, 103, 1, N, N, N, N),
3568 MUX(1, 104, 1, N, N, N, N),
3569 MUX(1, 105, 1, N, N, N, N),
3570 MUX(1, 106, 1, N, N, N, N),
3571 MUX(1, 107, 1, N, N, N, N),
3572 MUX(1, 102, 1, N, N, N, N),
3573 MUX(1, 97, 1, N, N, N, N),
3574 MUX(1, 98, 1, N, N, N, N),
3575 MUX(1, 99, 1, N, N, N, N),
3576 MUX(1, 100, 1, N, N, N, N),
3577 MUX(1, 101, 1, N, N, N, N),
3578 };
3579
3580 static struct atlas7_grp_mux rg_eth_mac_grp_mux = {
3581 .pad_mux_count = ARRAY_SIZE(rg_eth_mac_grp_pad_mux),
3582 .pad_mux_list = rg_eth_mac_grp_pad_mux,
3583 };
3584
3585 static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = {
3586 MUX(1, 111, 1, 0xa08, 13, 0xa88, 13),
3587 };
3588
3589 static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = {
3590 .pad_mux_count = ARRAY_SIZE(rg_gmac_phy_intr_n_grp_pad_mux),
3591 .pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux,
3592 };
3593
3594 static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = {
3595 MUX(1, 109, 1, N, N, N, N),
3596 MUX(1, 110, 1, N, N, N, N),
3597 };
3598
3599 static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = {
3600 .pad_mux_count = ARRAY_SIZE(rg_rgmii_mac_grp_pad_mux),
3601 .pad_mux_list = rg_rgmii_mac_grp_pad_mux,
3602 };
3603
3604 static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = {
3605 MUX(1, 111, 5, N, N, N, N),
3606 };
3607
3608 static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = {
3609 .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp0_pad_mux),
3610 .pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux,
3611 };
3612
3613 static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = {
3614 MUX(1, 53, 4, N, N, N, N),
3615 };
3616
3617 static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = {
3618 .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp1_pad_mux),
3619 .pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux,
3620 };
3621
3622 static struct atlas7_pad_mux sd0_grp_pad_mux[] = {
3623 MUX(1, 46, 2, N, N, N, N),
3624 MUX(1, 47, 2, N, N, N, N),
3625 MUX(1, 44, 2, N, N, N, N),
3626 MUX(1, 43, 2, N, N, N, N),
3627 MUX(1, 42, 2, N, N, N, N),
3628 MUX(1, 41, 2, N, N, N, N),
3629 MUX(1, 40, 2, N, N, N, N),
3630 MUX(1, 39, 2, N, N, N, N),
3631 MUX(1, 38, 2, N, N, N, N),
3632 MUX(1, 37, 2, N, N, N, N),
3633 };
3634
3635 static struct atlas7_grp_mux sd0_grp_mux = {
3636 .pad_mux_count = ARRAY_SIZE(sd0_grp_pad_mux),
3637 .pad_mux_list = sd0_grp_pad_mux,
3638 };
3639
3640 static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = {
3641 MUX(1, 46, 2, N, N, N, N),
3642 MUX(1, 47, 2, N, N, N, N),
3643 MUX(1, 44, 2, N, N, N, N),
3644 MUX(1, 43, 2, N, N, N, N),
3645 MUX(1, 42, 2, N, N, N, N),
3646 MUX(1, 41, 2, N, N, N, N),
3647 };
3648
3649 static struct atlas7_grp_mux sd0_4bit_grp_mux = {
3650 .pad_mux_count = ARRAY_SIZE(sd0_4bit_grp_pad_mux),
3651 .pad_mux_list = sd0_4bit_grp_pad_mux,
3652 };
3653
3654 static struct atlas7_pad_mux sd1_grp_pad_mux[] = {
3655 MUX(1, 48, 3, N, N, N, N),
3656 MUX(1, 49, 3, N, N, N, N),
3657 MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
3658 MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
3659 MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
3660 MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
3661 MUX(1, 40, 3, N, N, N, N),
3662 MUX(1, 39, 3, N, N, N, N),
3663 MUX(1, 38, 3, N, N, N, N),
3664 MUX(1, 37, 3, N, N, N, N),
3665 };
3666
3667 static struct atlas7_grp_mux sd1_grp_mux = {
3668 .pad_mux_count = ARRAY_SIZE(sd1_grp_pad_mux),
3669 .pad_mux_list = sd1_grp_pad_mux,
3670 };
3671
3672 static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = {
3673 MUX(1, 48, 3, N, N, N, N),
3674 MUX(1, 49, 3, N, N, N, N),
3675 MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
3676 MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
3677 MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
3678 MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
3679 };
3680
3681 static struct atlas7_grp_mux sd1_4bit_grp0_mux = {
3682 .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp0_pad_mux),
3683 .pad_mux_list = sd1_4bit_grp0_pad_mux,
3684 };
3685
3686 static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = {
3687 MUX(1, 48, 3, N, N, N, N),
3688 MUX(1, 49, 3, N, N, N, N),
3689 MUX(1, 40, 4, 0xa00, 0, 0xa80, 0),
3690 MUX(1, 39, 4, 0xa00, 1, 0xa80, 1),
3691 MUX(1, 38, 4, 0xa00, 2, 0xa80, 2),
3692 MUX(1, 37, 4, 0xa00, 3, 0xa80, 3),
3693 };
3694
3695 static struct atlas7_grp_mux sd1_4bit_grp1_mux = {
3696 .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp1_pad_mux),
3697 .pad_mux_list = sd1_4bit_grp1_pad_mux,
3698 };
3699
3700 static struct atlas7_pad_mux sd2_basic_grp_pad_mux[] = {
3701 MUX(1, 31, 1, N, N, N, N),
3702 MUX(1, 32, 1, N, N, N, N),
3703 MUX(1, 33, 1, N, N, N, N),
3704 MUX(1, 34, 1, N, N, N, N),
3705 MUX(1, 35, 1, N, N, N, N),
3706 MUX(1, 36, 1, N, N, N, N),
3707 };
3708
3709 static struct atlas7_grp_mux sd2_basic_grp_mux = {
3710 .pad_mux_count = ARRAY_SIZE(sd2_basic_grp_pad_mux),
3711 .pad_mux_list = sd2_basic_grp_pad_mux,
3712 };
3713
3714 static struct atlas7_pad_mux sd2_cdb_grp0_pad_mux[] = {
3715 MUX(1, 124, 2, 0xa08, 7, 0xa88, 7),
3716 };
3717
3718 static struct atlas7_grp_mux sd2_cdb_grp0_mux = {
3719 .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp0_pad_mux),
3720 .pad_mux_list = sd2_cdb_grp0_pad_mux,
3721 };
3722
3723 static struct atlas7_pad_mux sd2_cdb_grp1_pad_mux[] = {
3724 MUX(1, 161, 6, 0xa08, 7, 0xa88, 7),
3725 };
3726
3727 static struct atlas7_grp_mux sd2_cdb_grp1_mux = {
3728 .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp1_pad_mux),
3729 .pad_mux_list = sd2_cdb_grp1_pad_mux,
3730 };
3731
3732 static struct atlas7_pad_mux sd2_wpb_grp0_pad_mux[] = {
3733 MUX(1, 123, 2, 0xa10, 6, 0xa90, 6),
3734 };
3735
3736 static struct atlas7_grp_mux sd2_wpb_grp0_mux = {
3737 .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp0_pad_mux),
3738 .pad_mux_list = sd2_wpb_grp0_pad_mux,
3739 };
3740
3741 static struct atlas7_pad_mux sd2_wpb_grp1_pad_mux[] = {
3742 MUX(1, 163, 7, 0xa10, 6, 0xa90, 6),
3743 };
3744
3745 static struct atlas7_grp_mux sd2_wpb_grp1_mux = {
3746 .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp1_pad_mux),
3747 .pad_mux_list = sd2_wpb_grp1_pad_mux,
3748 };
3749
3750 static struct atlas7_pad_mux sd3_9_grp_pad_mux[] = {
3751 MUX(1, 85, 1, N, N, N, N),
3752 MUX(1, 86, 1, N, N, N, N),
3753 MUX(1, 87, 1, N, N, N, N),
3754 MUX(1, 88, 1, N, N, N, N),
3755 MUX(1, 89, 1, N, N, N, N),
3756 MUX(1, 90, 1, N, N, N, N),
3757 };
3758
3759 static struct atlas7_grp_mux sd3_9_grp_mux = {
3760 .pad_mux_count = ARRAY_SIZE(sd3_9_grp_pad_mux),
3761 .pad_mux_list = sd3_9_grp_pad_mux,
3762 };
3763
3764 static struct atlas7_pad_mux sd5_grp_pad_mux[] = {
3765 MUX(1, 91, 1, N, N, N, N),
3766 MUX(1, 92, 1, N, N, N, N),
3767 MUX(1, 93, 1, N, N, N, N),
3768 MUX(1, 94, 1, N, N, N, N),
3769 MUX(1, 95, 1, N, N, N, N),
3770 MUX(1, 96, 1, N, N, N, N),
3771 };
3772
3773 static struct atlas7_grp_mux sd5_grp_mux = {
3774 .pad_mux_count = ARRAY_SIZE(sd5_grp_pad_mux),
3775 .pad_mux_list = sd5_grp_pad_mux,
3776 };
3777
3778 static struct atlas7_pad_mux sd6_grp0_pad_mux[] = {
3779 MUX(1, 79, 4, 0xa00, 27, 0xa80, 27),
3780 MUX(1, 78, 4, 0xa00, 26, 0xa80, 26),
3781 MUX(1, 74, 4, 0xa00, 28, 0xa80, 28),
3782 MUX(1, 75, 4, 0xa00, 29, 0xa80, 29),
3783 MUX(1, 76, 4, 0xa00, 30, 0xa80, 30),
3784 MUX(1, 77, 4, 0xa00, 31, 0xa80, 31),
3785 };
3786
3787 static struct atlas7_grp_mux sd6_grp0_mux = {
3788 .pad_mux_count = ARRAY_SIZE(sd6_grp0_pad_mux),
3789 .pad_mux_list = sd6_grp0_pad_mux,
3790 };
3791
3792 static struct atlas7_pad_mux sd6_grp1_pad_mux[] = {
3793 MUX(1, 101, 3, 0xa00, 27, 0xa80, 27),
3794 MUX(1, 99, 3, 0xa00, 26, 0xa80, 26),
3795 MUX(1, 100, 3, 0xa00, 28, 0xa80, 28),
3796 MUX(1, 110, 3, 0xa00, 29, 0xa80, 29),
3797 MUX(1, 109, 3, 0xa00, 30, 0xa80, 30),
3798 MUX(1, 111, 3, 0xa00, 31, 0xa80, 31),
3799 };
3800
3801 static struct atlas7_grp_mux sd6_grp1_mux = {
3802 .pad_mux_count = ARRAY_SIZE(sd6_grp1_pad_mux),
3803 .pad_mux_list = sd6_grp1_pad_mux,
3804 };
3805
3806 static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = {
3807 MUX(0, 4, 2, N, N, N, N),
3808 };
3809
3810 static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = {
3811 .pad_mux_count = ARRAY_SIZE(sp0_ext_ldo_on_grp_pad_mux),
3812 .pad_mux_list = sp0_ext_ldo_on_grp_pad_mux,
3813 };
3814
3815 static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = {
3816 MUX(0, 12, 1, N, N, N, N),
3817 MUX(0, 13, 1, N, N, N, N),
3818 MUX(0, 14, 1, N, N, N, N),
3819 MUX(0, 15, 1, N, N, N, N),
3820 MUX(0, 16, 1, N, N, N, N),
3821 MUX(0, 17, 1, N, N, N, N),
3822 };
3823
3824 static struct atlas7_grp_mux sp0_qspi_grp_mux = {
3825 .pad_mux_count = ARRAY_SIZE(sp0_qspi_grp_pad_mux),
3826 .pad_mux_list = sp0_qspi_grp_pad_mux,
3827 };
3828
3829 static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = {
3830 MUX(1, 19, 1, N, N, N, N),
3831 MUX(1, 20, 1, N, N, N, N),
3832 MUX(1, 21, 1, N, N, N, N),
3833 MUX(1, 18, 1, N, N, N, N),
3834 };
3835
3836 static struct atlas7_grp_mux sp1_spi_grp_mux = {
3837 .pad_mux_count = ARRAY_SIZE(sp1_spi_grp_pad_mux),
3838 .pad_mux_list = sp1_spi_grp_pad_mux,
3839 };
3840
3841 static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = {
3842 MUX(1, 53, 5, N, N, N, N),
3843 MUX(1, 56, 5, N, N, N, N),
3844 MUX(1, 57, 5, N, N, N, N),
3845 MUX(1, 58, 5, N, N, N, N),
3846 MUX(1, 59, 5, N, N, N, N),
3847 MUX(1, 60, 5, N, N, N, N),
3848 MUX(1, 61, 5, N, N, N, N),
3849 MUX(1, 62, 5, N, N, N, N),
3850 MUX(1, 63, 5, N, N, N, N),
3851 MUX(1, 64, 5, N, N, N, N),
3852 MUX(1, 65, 5, N, N, N, N),
3853 MUX(1, 66, 5, N, N, N, N),
3854 MUX(1, 67, 5, N, N, N, N),
3855 MUX(1, 68, 5, N, N, N, N),
3856 MUX(1, 69, 5, N, N, N, N),
3857 MUX(1, 70, 5, N, N, N, N),
3858 MUX(1, 71, 5, N, N, N, N),
3859 MUX(1, 72, 5, N, N, N, N),
3860 };
3861
3862 static struct atlas7_grp_mux tpiu_trace_grp_mux = {
3863 .pad_mux_count = ARRAY_SIZE(tpiu_trace_grp_pad_mux),
3864 .pad_mux_list = tpiu_trace_grp_pad_mux,
3865 };
3866
3867 static struct atlas7_pad_mux uart0_grp_pad_mux[] = {
3868 MUX(1, 121, 4, N, N, N, N),
3869 MUX(1, 120, 4, N, N, N, N),
3870 MUX(1, 134, 1, N, N, N, N),
3871 MUX(1, 133, 1, N, N, N, N),
3872 };
3873
3874 static struct atlas7_grp_mux uart0_grp_mux = {
3875 .pad_mux_count = ARRAY_SIZE(uart0_grp_pad_mux),
3876 .pad_mux_list = uart0_grp_pad_mux,
3877 };
3878
3879 static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = {
3880 MUX(1, 134, 1, N, N, N, N),
3881 MUX(1, 133, 1, N, N, N, N),
3882 };
3883
3884 static struct atlas7_grp_mux uart0_nopause_grp_mux = {
3885 .pad_mux_count = ARRAY_SIZE(uart0_nopause_grp_pad_mux),
3886 .pad_mux_list = uart0_nopause_grp_pad_mux,
3887 };
3888
3889 static struct atlas7_pad_mux uart1_grp_pad_mux[] = {
3890 MUX(1, 136, 1, N, N, N, N),
3891 MUX(1, 135, 1, N, N, N, N),
3892 };
3893
3894 static struct atlas7_grp_mux uart1_grp_mux = {
3895 .pad_mux_count = ARRAY_SIZE(uart1_grp_pad_mux),
3896 .pad_mux_list = uart1_grp_pad_mux,
3897 };
3898
3899 static struct atlas7_pad_mux uart2_cts_grp0_pad_mux[] = {
3900 MUX(1, 132, 3, 0xa10, 2, 0xa90, 2),
3901 };
3902
3903 static struct atlas7_grp_mux uart2_cts_grp0_mux = {
3904 .pad_mux_count = ARRAY_SIZE(uart2_cts_grp0_pad_mux),
3905 .pad_mux_list = uart2_cts_grp0_pad_mux,
3906 };
3907
3908 static struct atlas7_pad_mux uart2_cts_grp1_pad_mux[] = {
3909 MUX(1, 162, 2, 0xa10, 2, 0xa90, 2),
3910 };
3911
3912 static struct atlas7_grp_mux uart2_cts_grp1_mux = {
3913 .pad_mux_count = ARRAY_SIZE(uart2_cts_grp1_pad_mux),
3914 .pad_mux_list = uart2_cts_grp1_pad_mux,
3915 };
3916
3917 static struct atlas7_pad_mux uart2_rts_grp0_pad_mux[] = {
3918 MUX(1, 131, 3, N, N, N, N),
3919 };
3920
3921 static struct atlas7_grp_mux uart2_rts_grp0_mux = {
3922 .pad_mux_count = ARRAY_SIZE(uart2_rts_grp0_pad_mux),
3923 .pad_mux_list = uart2_rts_grp0_pad_mux,
3924 };
3925
3926 static struct atlas7_pad_mux uart2_rts_grp1_pad_mux[] = {
3927 MUX(1, 161, 2, N, N, N, N),
3928 };
3929
3930 static struct atlas7_grp_mux uart2_rts_grp1_mux = {
3931 .pad_mux_count = ARRAY_SIZE(uart2_rts_grp1_pad_mux),
3932 .pad_mux_list = uart2_rts_grp1_pad_mux,
3933 };
3934
3935 static struct atlas7_pad_mux uart2_rxd_grp0_pad_mux[] = {
3936 MUX(0, 11, 2, 0xa10, 5, 0xa90, 5),
3937 };
3938
3939 static struct atlas7_grp_mux uart2_rxd_grp0_mux = {
3940 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp0_pad_mux),
3941 .pad_mux_list = uart2_rxd_grp0_pad_mux,
3942 };
3943
3944 static struct atlas7_pad_mux uart2_rxd_grp1_pad_mux[] = {
3945 MUX(1, 160, 2, 0xa10, 5, 0xa90, 5),
3946 };
3947
3948 static struct atlas7_grp_mux uart2_rxd_grp1_mux = {
3949 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp1_pad_mux),
3950 .pad_mux_list = uart2_rxd_grp1_pad_mux,
3951 };
3952
3953 static struct atlas7_pad_mux uart2_rxd_grp2_pad_mux[] = {
3954 MUX(1, 130, 3, 0xa10, 5, 0xa90, 5),
3955 };
3956
3957 static struct atlas7_grp_mux uart2_rxd_grp2_mux = {
3958 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp2_pad_mux),
3959 .pad_mux_list = uart2_rxd_grp2_pad_mux,
3960 };
3961
3962 static struct atlas7_pad_mux uart2_txd_grp0_pad_mux[] = {
3963 MUX(0, 10, 2, N, N, N, N),
3964 };
3965
3966 static struct atlas7_grp_mux uart2_txd_grp0_mux = {
3967 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp0_pad_mux),
3968 .pad_mux_list = uart2_txd_grp0_pad_mux,
3969 };
3970
3971 static struct atlas7_pad_mux uart2_txd_grp1_pad_mux[] = {
3972 MUX(1, 159, 2, N, N, N, N),
3973 };
3974
3975 static struct atlas7_grp_mux uart2_txd_grp1_mux = {
3976 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp1_pad_mux),
3977 .pad_mux_list = uart2_txd_grp1_pad_mux,
3978 };
3979
3980 static struct atlas7_pad_mux uart2_txd_grp2_pad_mux[] = {
3981 MUX(1, 129, 3, N, N, N, N),
3982 };
3983
3984 static struct atlas7_grp_mux uart2_txd_grp2_mux = {
3985 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp2_pad_mux),
3986 .pad_mux_list = uart2_txd_grp2_pad_mux,
3987 };
3988
3989 static struct atlas7_pad_mux uart3_cts_grp0_pad_mux[] = {
3990 MUX(1, 125, 2, 0xa08, 0, 0xa88, 0),
3991 };
3992
3993 static struct atlas7_grp_mux uart3_cts_grp0_mux = {
3994 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp0_pad_mux),
3995 .pad_mux_list = uart3_cts_grp0_pad_mux,
3996 };
3997
3998 static struct atlas7_pad_mux uart3_cts_grp1_pad_mux[] = {
3999 MUX(1, 111, 4, 0xa08, 0, 0xa88, 0),
4000 };
4001
4002 static struct atlas7_grp_mux uart3_cts_grp1_mux = {
4003 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp1_pad_mux),
4004 .pad_mux_list = uart3_cts_grp1_pad_mux,
4005 };
4006
4007 static struct atlas7_pad_mux uart3_cts_grp2_pad_mux[] = {
4008 MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
4009 };
4010
4011 static struct atlas7_grp_mux uart3_cts_grp2_mux = {
4012 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp2_pad_mux),
4013 .pad_mux_list = uart3_cts_grp2_pad_mux,
4014 };
4015
4016 static struct atlas7_pad_mux uart3_rts_grp0_pad_mux[] = {
4017 MUX(1, 126, 2, N, N, N, N),
4018 };
4019
4020 static struct atlas7_grp_mux uart3_rts_grp0_mux = {
4021 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp0_pad_mux),
4022 .pad_mux_list = uart3_rts_grp0_pad_mux,
4023 };
4024
4025 static struct atlas7_pad_mux uart3_rts_grp1_pad_mux[] = {
4026 MUX(1, 109, 4, N, N, N, N),
4027 };
4028
4029 static struct atlas7_grp_mux uart3_rts_grp1_mux = {
4030 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp1_pad_mux),
4031 .pad_mux_list = uart3_rts_grp1_pad_mux,
4032 };
4033
4034 static struct atlas7_pad_mux uart3_rts_grp2_pad_mux[] = {
4035 MUX(1, 139, 2, N, N, N, N),
4036 };
4037
4038 static struct atlas7_grp_mux uart3_rts_grp2_mux = {
4039 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp2_pad_mux),
4040 .pad_mux_list = uart3_rts_grp2_pad_mux,
4041 };
4042
4043 static struct atlas7_pad_mux uart3_rxd_grp0_pad_mux[] = {
4044 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
4045 };
4046
4047 static struct atlas7_grp_mux uart3_rxd_grp0_mux = {
4048 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp0_pad_mux),
4049 .pad_mux_list = uart3_rxd_grp0_pad_mux,
4050 };
4051
4052 static struct atlas7_pad_mux uart3_rxd_grp1_pad_mux[] = {
4053 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
4054 };
4055
4056 static struct atlas7_grp_mux uart3_rxd_grp1_mux = {
4057 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp1_pad_mux),
4058 .pad_mux_list = uart3_rxd_grp1_pad_mux,
4059 };
4060
4061 static struct atlas7_pad_mux uart3_rxd_grp2_pad_mux[] = {
4062 MUX(1, 162, 3, 0xa00, 5, 0xa80, 5),
4063 };
4064
4065 static struct atlas7_grp_mux uart3_rxd_grp2_mux = {
4066 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp2_pad_mux),
4067 .pad_mux_list = uart3_rxd_grp2_pad_mux,
4068 };
4069
4070 static struct atlas7_pad_mux uart3_txd_grp0_pad_mux[] = {
4071 MUX(1, 137, 1, N, N, N, N),
4072 };
4073
4074 static struct atlas7_grp_mux uart3_txd_grp0_mux = {
4075 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp0_pad_mux),
4076 .pad_mux_list = uart3_txd_grp0_pad_mux,
4077 };
4078
4079 static struct atlas7_pad_mux uart3_txd_grp1_pad_mux[] = {
4080 MUX(1, 83, 2, N, N, N, N),
4081 };
4082
4083 static struct atlas7_grp_mux uart3_txd_grp1_mux = {
4084 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp1_pad_mux),
4085 .pad_mux_list = uart3_txd_grp1_pad_mux,
4086 };
4087
4088 static struct atlas7_pad_mux uart3_txd_grp2_pad_mux[] = {
4089 MUX(1, 161, 3, N, N, N, N),
4090 };
4091
4092 static struct atlas7_grp_mux uart3_txd_grp2_mux = {
4093 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp2_pad_mux),
4094 .pad_mux_list = uart3_txd_grp2_pad_mux,
4095 };
4096
4097 static struct atlas7_pad_mux uart4_basic_grp_pad_mux[] = {
4098 MUX(1, 140, 1, N, N, N, N),
4099 MUX(1, 139, 1, N, N, N, N),
4100 };
4101
4102 static struct atlas7_grp_mux uart4_basic_grp_mux = {
4103 .pad_mux_count = ARRAY_SIZE(uart4_basic_grp_pad_mux),
4104 .pad_mux_list = uart4_basic_grp_pad_mux,
4105 };
4106
4107 static struct atlas7_pad_mux uart4_cts_grp0_pad_mux[] = {
4108 MUX(1, 122, 4, 0xa08, 1, 0xa88, 1),
4109 };
4110
4111 static struct atlas7_grp_mux uart4_cts_grp0_mux = {
4112 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp0_pad_mux),
4113 .pad_mux_list = uart4_cts_grp0_pad_mux,
4114 };
4115
4116 static struct atlas7_pad_mux uart4_cts_grp1_pad_mux[] = {
4117 MUX(1, 100, 4, 0xa08, 1, 0xa88, 1),
4118 };
4119
4120 static struct atlas7_grp_mux uart4_cts_grp1_mux = {
4121 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp1_pad_mux),
4122 .pad_mux_list = uart4_cts_grp1_pad_mux,
4123 };
4124
4125 static struct atlas7_pad_mux uart4_cts_grp2_pad_mux[] = {
4126 MUX(1, 117, 2, 0xa08, 1, 0xa88, 1),
4127 };
4128
4129 static struct atlas7_grp_mux uart4_cts_grp2_mux = {
4130 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp2_pad_mux),
4131 .pad_mux_list = uart4_cts_grp2_pad_mux,
4132 };
4133
4134 static struct atlas7_pad_mux uart4_rts_grp0_pad_mux[] = {
4135 MUX(1, 123, 4, N, N, N, N),
4136 };
4137
4138 static struct atlas7_grp_mux uart4_rts_grp0_mux = {
4139 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp0_pad_mux),
4140 .pad_mux_list = uart4_rts_grp0_pad_mux,
4141 };
4142
4143 static struct atlas7_pad_mux uart4_rts_grp1_pad_mux[] = {
4144 MUX(1, 99, 4, N, N, N, N),
4145 };
4146
4147 static struct atlas7_grp_mux uart4_rts_grp1_mux = {
4148 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp1_pad_mux),
4149 .pad_mux_list = uart4_rts_grp1_pad_mux,
4150 };
4151
4152 static struct atlas7_pad_mux uart4_rts_grp2_pad_mux[] = {
4153 MUX(1, 116, 2, N, N, N, N),
4154 };
4155
4156 static struct atlas7_grp_mux uart4_rts_grp2_mux = {
4157 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp2_pad_mux),
4158 .pad_mux_list = uart4_rts_grp2_pad_mux,
4159 };
4160
4161 static struct atlas7_pad_mux usb0_drvvbus_grp0_pad_mux[] = {
4162 MUX(1, 51, 2, N, N, N, N),
4163 };
4164
4165 static struct atlas7_grp_mux usb0_drvvbus_grp0_mux = {
4166 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp0_pad_mux),
4167 .pad_mux_list = usb0_drvvbus_grp0_pad_mux,
4168 };
4169
4170 static struct atlas7_pad_mux usb0_drvvbus_grp1_pad_mux[] = {
4171 MUX(1, 162, 7, N, N, N, N),
4172 };
4173
4174 static struct atlas7_grp_mux usb0_drvvbus_grp1_mux = {
4175 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp1_pad_mux),
4176 .pad_mux_list = usb0_drvvbus_grp1_pad_mux,
4177 };
4178
4179 static struct atlas7_pad_mux usb1_drvvbus_grp0_pad_mux[] = {
4180 MUX(1, 134, 2, N, N, N, N),
4181 };
4182
4183 static struct atlas7_grp_mux usb1_drvvbus_grp0_mux = {
4184 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp0_pad_mux),
4185 .pad_mux_list = usb1_drvvbus_grp0_pad_mux,
4186 };
4187
4188 static struct atlas7_pad_mux usb1_drvvbus_grp1_pad_mux[] = {
4189 MUX(1, 163, 2, N, N, N, N),
4190 };
4191
4192 static struct atlas7_grp_mux usb1_drvvbus_grp1_mux = {
4193 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp1_pad_mux),
4194 .pad_mux_list = usb1_drvvbus_grp1_pad_mux,
4195 };
4196
4197 static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = {
4198 MUX(1, 57, 6, N, N, N, N),
4199 MUX(1, 58, 6, N, N, N, N),
4200 MUX(1, 59, 6, N, N, N, N),
4201 MUX(1, 60, 6, N, N, N, N),
4202 MUX(1, 61, 6, N, N, N, N),
4203 MUX(1, 62, 6, N, N, N, N),
4204 MUX(1, 63, 6, N, N, N, N),
4205 MUX(1, 64, 6, N, N, N, N),
4206 MUX(1, 65, 6, N, N, N, N),
4207 MUX(1, 66, 6, N, N, N, N),
4208 MUX(1, 67, 6, N, N, N, N),
4209 MUX(1, 68, 6, N, N, N, N),
4210 MUX(1, 69, 6, N, N, N, N),
4211 MUX(1, 70, 6, N, N, N, N),
4212 MUX(1, 71, 6, N, N, N, N),
4213 MUX(1, 72, 6, N, N, N, N),
4214 MUX(1, 53, 6, N, N, N, N),
4215 MUX(1, 54, 6, N, N, N, N),
4216 MUX(1, 55, 6, N, N, N, N),
4217 MUX(1, 56, 6, N, N, N, N),
4218 MUX(1, 85, 6, N, N, N, N),
4219 MUX(1, 86, 6, N, N, N, N),
4220 MUX(1, 87, 6, N, N, N, N),
4221 MUX(1, 88, 6, N, N, N, N),
4222 MUX(1, 89, 6, N, N, N, N),
4223 MUX(1, 90, 6, N, N, N, N),
4224 MUX(1, 91, 6, N, N, N, N),
4225 MUX(1, 92, 6, N, N, N, N),
4226 MUX(1, 93, 6, N, N, N, N),
4227 MUX(1, 94, 6, N, N, N, N),
4228 MUX(1, 95, 6, N, N, N, N),
4229 MUX(1, 96, 6, N, N, N, N),
4230 };
4231
4232 static struct atlas7_grp_mux visbus_dout_grp_mux = {
4233 .pad_mux_count = ARRAY_SIZE(visbus_dout_grp_pad_mux),
4234 .pad_mux_list = visbus_dout_grp_pad_mux,
4235 };
4236
4237 static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = {
4238 MUX(1, 74, 1, N, N, N, N),
4239 MUX(1, 75, 1, N, N, N, N),
4240 MUX(1, 76, 1, N, N, N, N),
4241 MUX(1, 77, 1, N, N, N, N),
4242 MUX(1, 78, 1, N, N, N, N),
4243 MUX(1, 79, 1, N, N, N, N),
4244 MUX(1, 80, 1, N, N, N, N),
4245 MUX(1, 81, 1, N, N, N, N),
4246 MUX(1, 82, 1, N, N, N, N),
4247 MUX(1, 83, 1, N, N, N, N),
4248 MUX(1, 84, 1, N, N, N, N),
4249 MUX(1, 103, 2, N, N, N, N),
4250 MUX(1, 104, 2, N, N, N, N),
4251 MUX(1, 105, 2, N, N, N, N),
4252 MUX(1, 106, 2, N, N, N, N),
4253 MUX(1, 107, 2, N, N, N, N),
4254 MUX(1, 102, 2, N, N, N, N),
4255 MUX(1, 97, 2, N, N, N, N),
4256 MUX(1, 98, 2, N, N, N, N),
4257 };
4258
4259 static struct atlas7_grp_mux vi_vip1_grp_mux = {
4260 .pad_mux_count = ARRAY_SIZE(vi_vip1_grp_pad_mux),
4261 .pad_mux_list = vi_vip1_grp_pad_mux,
4262 };
4263
4264 static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = {
4265 MUX(1, 74, 1, N, N, N, N),
4266 MUX(1, 75, 1, N, N, N, N),
4267 MUX(1, 76, 1, N, N, N, N),
4268 MUX(1, 77, 1, N, N, N, N),
4269 MUX(1, 78, 1, N, N, N, N),
4270 MUX(1, 79, 1, N, N, N, N),
4271 MUX(1, 80, 1, N, N, N, N),
4272 MUX(1, 81, 1, N, N, N, N),
4273 MUX(1, 82, 1, N, N, N, N),
4274 MUX(1, 83, 1, N, N, N, N),
4275 MUX(1, 84, 1, N, N, N, N),
4276 MUX(1, 108, 2, N, N, N, N),
4277 MUX(1, 103, 2, N, N, N, N),
4278 MUX(1, 104, 2, N, N, N, N),
4279 MUX(1, 105, 2, N, N, N, N),
4280 MUX(1, 106, 2, N, N, N, N),
4281 MUX(1, 107, 2, N, N, N, N),
4282 MUX(1, 102, 2, N, N, N, N),
4283 MUX(1, 97, 2, N, N, N, N),
4284 MUX(1, 98, 2, N, N, N, N),
4285 MUX(1, 99, 2, N, N, N, N),
4286 MUX(1, 100, 2, N, N, N, N),
4287 };
4288
4289 static struct atlas7_grp_mux vi_vip1_ext_grp_mux = {
4290 .pad_mux_count = ARRAY_SIZE(vi_vip1_ext_grp_pad_mux),
4291 .pad_mux_list = vi_vip1_ext_grp_pad_mux,
4292 };
4293
4294 static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = {
4295 MUX(1, 74, 1, N, N, N, N),
4296 MUX(1, 75, 1, N, N, N, N),
4297 MUX(1, 76, 1, N, N, N, N),
4298 MUX(1, 77, 1, N, N, N, N),
4299 MUX(1, 78, 1, N, N, N, N),
4300 MUX(1, 79, 1, N, N, N, N),
4301 MUX(1, 80, 1, N, N, N, N),
4302 MUX(1, 81, 1, N, N, N, N),
4303 MUX(1, 82, 1, N, N, N, N),
4304 MUX(1, 83, 1, N, N, N, N),
4305 MUX(1, 84, 1, N, N, N, N),
4306 };
4307
4308 static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = {
4309 .pad_mux_count = ARRAY_SIZE(vi_vip1_low8bit_grp_pad_mux),
4310 .pad_mux_list = vi_vip1_low8bit_grp_pad_mux,
4311 };
4312
4313 static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = {
4314 MUX(1, 82, 1, N, N, N, N),
4315 MUX(1, 83, 1, N, N, N, N),
4316 MUX(1, 84, 1, N, N, N, N),
4317 MUX(1, 103, 2, N, N, N, N),
4318 MUX(1, 104, 2, N, N, N, N),
4319 MUX(1, 105, 2, N, N, N, N),
4320 MUX(1, 106, 2, N, N, N, N),
4321 MUX(1, 107, 2, N, N, N, N),
4322 MUX(1, 102, 2, N, N, N, N),
4323 MUX(1, 97, 2, N, N, N, N),
4324 MUX(1, 98, 2, N, N, N, N),
4325 };
4326
4327 static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = {
4328 .pad_mux_count = ARRAY_SIZE(vi_vip1_high8bit_grp_pad_mux),
4329 .pad_mux_list = vi_vip1_high8bit_grp_pad_mux,
4330 };
4331
4332 static struct atlas7_pmx_func atlas7_pmx_functions[] = {
4333 FUNCTION("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux),
4334 FUNCTION("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux),
4335 FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux),
4336 FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux),
4337 FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux),
4338 FUNCTION("jtag_uart_nand_gpio",
4339 jtag_uart_nand_gpio_grp,
4340 &jtag_uart_nand_gpio_grp_mux),
4341 FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux),
4342 FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux),
4343 FUNCTION("audio_digmic_m0",
4344 audio_digmic_grp0,
4345 &audio_digmic_grp0_mux),
4346 FUNCTION("audio_digmic_m1",
4347 audio_digmic_grp1,
4348 &audio_digmic_grp1_mux),
4349 FUNCTION("audio_digmic_m2",
4350 audio_digmic_grp2,
4351 &audio_digmic_grp2_mux),
4352 FUNCTION("audio_func_dbg",
4353 audio_func_dbg_grp,
4354 &audio_func_dbg_grp_mux),
4355 FUNCTION("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux),
4356 FUNCTION("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux),
4357 FUNCTION("audio_i2s_extclk",
4358 audio_i2s_extclk_grp,
4359 &audio_i2s_extclk_grp_mux),
4360 FUNCTION("audio_spdif_out_m0",
4361 audio_spdif_out_grp0,
4362 &audio_spdif_out_grp0_mux),
4363 FUNCTION("audio_spdif_out_m1",
4364 audio_spdif_out_grp1,
4365 &audio_spdif_out_grp1_mux),
4366 FUNCTION("audio_spdif_out_m2",
4367 audio_spdif_out_grp2,
4368 &audio_spdif_out_grp2_mux),
4369 FUNCTION("audio_uart0_basic",
4370 audio_uart0_basic_grp,
4371 &audio_uart0_basic_grp_mux),
4372 FUNCTION("audio_uart0_urfs_m0",
4373 audio_uart0_urfs_grp0,
4374 &audio_uart0_urfs_grp0_mux),
4375 FUNCTION("audio_uart0_urfs_m1",
4376 audio_uart0_urfs_grp1,
4377 &audio_uart0_urfs_grp1_mux),
4378 FUNCTION("audio_uart0_urfs_m2",
4379 audio_uart0_urfs_grp2,
4380 &audio_uart0_urfs_grp2_mux),
4381 FUNCTION("audio_uart0_urfs_m3",
4382 audio_uart0_urfs_grp3,
4383 &audio_uart0_urfs_grp3_mux),
4384 FUNCTION("audio_uart1_basic",
4385 audio_uart1_basic_grp,
4386 &audio_uart1_basic_grp_mux),
4387 FUNCTION("audio_uart1_urfs_m0",
4388 audio_uart1_urfs_grp0,
4389 &audio_uart1_urfs_grp0_mux),
4390 FUNCTION("audio_uart1_urfs_m1",
4391 audio_uart1_urfs_grp1,
4392 &audio_uart1_urfs_grp1_mux),
4393 FUNCTION("audio_uart1_urfs_m2",
4394 audio_uart1_urfs_grp2,
4395 &audio_uart1_urfs_grp2_mux),
4396 FUNCTION("audio_uart2_urfs_m0",
4397 audio_uart2_urfs_grp0,
4398 &audio_uart2_urfs_grp0_mux),
4399 FUNCTION("audio_uart2_urfs_m1",
4400 audio_uart2_urfs_grp1,
4401 &audio_uart2_urfs_grp1_mux),
4402 FUNCTION("audio_uart2_urfs_m2",
4403 audio_uart2_urfs_grp2,
4404 &audio_uart2_urfs_grp2_mux),
4405 FUNCTION("audio_uart2_urxd_m0",
4406 audio_uart2_urxd_grp0,
4407 &audio_uart2_urxd_grp0_mux),
4408 FUNCTION("audio_uart2_urxd_m1",
4409 audio_uart2_urxd_grp1,
4410 &audio_uart2_urxd_grp1_mux),
4411 FUNCTION("audio_uart2_urxd_m2",
4412 audio_uart2_urxd_grp2,
4413 &audio_uart2_urxd_grp2_mux),
4414 FUNCTION("audio_uart2_usclk_m0",
4415 audio_uart2_usclk_grp0,
4416 &audio_uart2_usclk_grp0_mux),
4417 FUNCTION("audio_uart2_usclk_m1",
4418 audio_uart2_usclk_grp1,
4419 &audio_uart2_usclk_grp1_mux),
4420 FUNCTION("audio_uart2_usclk_m2",
4421 audio_uart2_usclk_grp2,
4422 &audio_uart2_usclk_grp2_mux),
4423 FUNCTION("audio_uart2_utfs_m0",
4424 audio_uart2_utfs_grp0,
4425 &audio_uart2_utfs_grp0_mux),
4426 FUNCTION("audio_uart2_utfs_m1",
4427 audio_uart2_utfs_grp1,
4428 &audio_uart2_utfs_grp1_mux),
4429 FUNCTION("audio_uart2_utfs_m2",
4430 audio_uart2_utfs_grp2,
4431 &audio_uart2_utfs_grp2_mux),
4432 FUNCTION("audio_uart2_utxd_m0",
4433 audio_uart2_utxd_grp0,
4434 &audio_uart2_utxd_grp0_mux),
4435 FUNCTION("audio_uart2_utxd_m1",
4436 audio_uart2_utxd_grp1,
4437 &audio_uart2_utxd_grp1_mux),
4438 FUNCTION("audio_uart2_utxd_m2",
4439 audio_uart2_utxd_grp2,
4440 &audio_uart2_utxd_grp2_mux),
4441 FUNCTION("c_can_trnsvr_en_m0",
4442 c_can_trnsvr_en_grp0,
4443 &c_can_trnsvr_en_grp0_mux),
4444 FUNCTION("c_can_trnsvr_en_m1",
4445 c_can_trnsvr_en_grp1,
4446 &c_can_trnsvr_en_grp1_mux),
4447 FUNCTION("c_can_trnsvr_intr",
4448 c_can_trnsvr_intr_grp,
4449 &c_can_trnsvr_intr_grp_mux),
4450 FUNCTION("c_can_trnsvr_stb_n",
4451 c_can_trnsvr_stb_n_grp,
4452 &c_can_trnsvr_stb_n_grp_mux),
4453 FUNCTION("c0_can_rxd_trnsv0",
4454 c0_can_rxd_trnsv0_grp,
4455 &c0_can_rxd_trnsv0_grp_mux),
4456 FUNCTION("c0_can_rxd_trnsv1",
4457 c0_can_rxd_trnsv1_grp,
4458 &c0_can_rxd_trnsv1_grp_mux),
4459 FUNCTION("c0_can_txd_trnsv0",
4460 c0_can_txd_trnsv0_grp,
4461 &c0_can_txd_trnsv0_grp_mux),
4462 FUNCTION("c0_can_txd_trnsv1",
4463 c0_can_txd_trnsv1_grp,
4464 &c0_can_txd_trnsv1_grp_mux),
4465 FUNCTION("c1_can_rxd_m0", c1_can_rxd_grp0, &c1_can_rxd_grp0_mux),
4466 FUNCTION("c1_can_rxd_m1", c1_can_rxd_grp1, &c1_can_rxd_grp1_mux),
4467 FUNCTION("c1_can_rxd_m2", c1_can_rxd_grp2, &c1_can_rxd_grp2_mux),
4468 FUNCTION("c1_can_rxd_m3", c1_can_rxd_grp3, &c1_can_rxd_grp3_mux),
4469 FUNCTION("c1_can_txd_m0", c1_can_txd_grp0, &c1_can_txd_grp0_mux),
4470 FUNCTION("c1_can_txd_m1", c1_can_txd_grp1, &c1_can_txd_grp1_mux),
4471 FUNCTION("c1_can_txd_m2", c1_can_txd_grp2, &c1_can_txd_grp2_mux),
4472 FUNCTION("c1_can_txd_m3", c1_can_txd_grp3, &c1_can_txd_grp3_mux),
4473 FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux),
4474 FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux),
4475 FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux),
4476 FUNCTION("ca_curator_lpc",
4477 ca_curator_lpc_grp,
4478 &ca_curator_lpc_grp_mux),
4479 FUNCTION("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux),
4480 FUNCTION("ca_pio", ca_pio_grp, &ca_pio_grp_mux),
4481 FUNCTION("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux),
4482 FUNCTION("ca_spi", ca_spi_grp, &ca_spi_grp_mux),
4483 FUNCTION("ca_trb", ca_trb_grp, &ca_trb_grp_mux),
4484 FUNCTION("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux),
4485 FUNCTION("clkc_m0", clkc_grp0, &clkc_grp0_mux),
4486 FUNCTION("clkc_m1", clkc_grp1, &clkc_grp1_mux),
4487 FUNCTION("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux),
4488 FUNCTION("gn_gnss_uart_nopause",
4489 gn_gnss_uart_nopause_grp,
4490 &gn_gnss_uart_nopause_grp_mux),
4491 FUNCTION("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux),
4492 FUNCTION("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux),
4493 FUNCTION("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux),
4494 FUNCTION("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux),
4495 FUNCTION("cvbs_dbg_test_m0",
4496 cvbs_dbg_test_grp0,
4497 &cvbs_dbg_test_grp0_mux),
4498 FUNCTION("cvbs_dbg_test_m1",
4499 cvbs_dbg_test_grp1,
4500 &cvbs_dbg_test_grp1_mux),
4501 FUNCTION("cvbs_dbg_test_m2",
4502 cvbs_dbg_test_grp2,
4503 &cvbs_dbg_test_grp2_mux),
4504 FUNCTION("cvbs_dbg_test_m3",
4505 cvbs_dbg_test_grp3,
4506 &cvbs_dbg_test_grp3_mux),
4507 FUNCTION("cvbs_dbg_test_m4",
4508 cvbs_dbg_test_grp4,
4509 &cvbs_dbg_test_grp4_mux),
4510 FUNCTION("cvbs_dbg_test_m5",
4511 cvbs_dbg_test_grp5,
4512 &cvbs_dbg_test_grp5_mux),
4513 FUNCTION("cvbs_dbg_test_m6",
4514 cvbs_dbg_test_grp6,
4515 &cvbs_dbg_test_grp6_mux),
4516 FUNCTION("cvbs_dbg_test_m7",
4517 cvbs_dbg_test_grp7,
4518 &cvbs_dbg_test_grp7_mux),
4519 FUNCTION("cvbs_dbg_test_m8",
4520 cvbs_dbg_test_grp8,
4521 &cvbs_dbg_test_grp8_mux),
4522 FUNCTION("cvbs_dbg_test_m9",
4523 cvbs_dbg_test_grp9,
4524 &cvbs_dbg_test_grp9_mux),
4525 FUNCTION("cvbs_dbg_test_m10",
4526 cvbs_dbg_test_grp10,
4527 &cvbs_dbg_test_grp10_mux),
4528 FUNCTION("cvbs_dbg_test_m11",
4529 cvbs_dbg_test_grp11,
4530 &cvbs_dbg_test_grp11_mux),
4531 FUNCTION("cvbs_dbg_test_m12",
4532 cvbs_dbg_test_grp12,
4533 &cvbs_dbg_test_grp12_mux),
4534 FUNCTION("cvbs_dbg_test_m13",
4535 cvbs_dbg_test_grp13,
4536 &cvbs_dbg_test_grp13_mux),
4537 FUNCTION("cvbs_dbg_test_m14",
4538 cvbs_dbg_test_grp14,
4539 &cvbs_dbg_test_grp14_mux),
4540 FUNCTION("cvbs_dbg_test_m15",
4541 cvbs_dbg_test_grp15,
4542 &cvbs_dbg_test_grp15_mux),
4543 FUNCTION("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux),
4544 FUNCTION("gn_gnss_sw_status",
4545 gn_gnss_sw_status_grp,
4546 &gn_gnss_sw_status_grp_mux),
4547 FUNCTION("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux),
4548 FUNCTION("gn_gnss_irq1_m0",
4549 gn_gnss_irq1_grp0,
4550 &gn_gnss_irq1_grp0_mux),
4551 FUNCTION("gn_gnss_irq2_m0",
4552 gn_gnss_irq2_grp0,
4553 &gn_gnss_irq2_grp0_mux),
4554 FUNCTION("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux),
4555 FUNCTION("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux),
4556 FUNCTION("gn_io_gnsssys_sw_cfg",
4557 gn_io_gnsssys_sw_cfg_grp,
4558 &gn_io_gnsssys_sw_cfg_grp_mux),
4559 FUNCTION("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux),
4560 FUNCTION("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux),
4561 FUNCTION("gn_trg_shutdown_m0",
4562 gn_trg_shutdown_grp0,
4563 &gn_trg_shutdown_grp0_mux),
4564 FUNCTION("gn_trg_shutdown_m1",
4565 gn_trg_shutdown_grp1,
4566 &gn_trg_shutdown_grp1_mux),
4567 FUNCTION("gn_trg_shutdown_m2",
4568 gn_trg_shutdown_grp2,
4569 &gn_trg_shutdown_grp2_mux),
4570 FUNCTION("gn_trg_shutdown_m3",
4571 gn_trg_shutdown_grp3,
4572 &gn_trg_shutdown_grp3_mux),
4573 FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux),
4574 FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux),
4575 FUNCTION("i2s0", i2s0_grp, &i2s0_grp_mux),
4576 FUNCTION("i2s1_basic", i2s1_basic_grp, &i2s1_basic_grp_mux),
4577 FUNCTION("i2s1_rxd0_m0", i2s1_rxd0_grp0, &i2s1_rxd0_grp0_mux),
4578 FUNCTION("i2s1_rxd0_m1", i2s1_rxd0_grp1, &i2s1_rxd0_grp1_mux),
4579 FUNCTION("i2s1_rxd0_m2", i2s1_rxd0_grp2, &i2s1_rxd0_grp2_mux),
4580 FUNCTION("i2s1_rxd0_m3", i2s1_rxd0_grp3, &i2s1_rxd0_grp3_mux),
4581 FUNCTION("i2s1_rxd0_m4", i2s1_rxd0_grp4, &i2s1_rxd0_grp4_mux),
4582 FUNCTION("i2s1_rxd1_m0", i2s1_rxd1_grp0, &i2s1_rxd1_grp0_mux),
4583 FUNCTION("i2s1_rxd1_m1", i2s1_rxd1_grp1, &i2s1_rxd1_grp1_mux),
4584 FUNCTION("i2s1_rxd1_m2", i2s1_rxd1_grp2, &i2s1_rxd1_grp2_mux),
4585 FUNCTION("i2s1_rxd1_m3", i2s1_rxd1_grp3, &i2s1_rxd1_grp3_mux),
4586 FUNCTION("i2s1_rxd1_m4", i2s1_rxd1_grp4, &i2s1_rxd1_grp4_mux),
4587 FUNCTION("jtag_jt_dbg_nsrst",
4588 jtag_jt_dbg_nsrst_grp,
4589 &jtag_jt_dbg_nsrst_grp_mux),
4590 FUNCTION("jtag_ntrst_m0", jtag_ntrst_grp0, &jtag_ntrst_grp0_mux),
4591 FUNCTION("jtag_ntrst_m1", jtag_ntrst_grp1, &jtag_ntrst_grp1_mux),
4592 FUNCTION("jtag_swdiotms_m0",
4593 jtag_swdiotms_grp0,
4594 &jtag_swdiotms_grp0_mux),
4595 FUNCTION("jtag_swdiotms_m1",
4596 jtag_swdiotms_grp1,
4597 &jtag_swdiotms_grp1_mux),
4598 FUNCTION("jtag_tck_m0", jtag_tck_grp0, &jtag_tck_grp0_mux),
4599 FUNCTION("jtag_tck_m1", jtag_tck_grp1, &jtag_tck_grp1_mux),
4600 FUNCTION("jtag_tdi_m0", jtag_tdi_grp0, &jtag_tdi_grp0_mux),
4601 FUNCTION("jtag_tdi_m1", jtag_tdi_grp1, &jtag_tdi_grp1_mux),
4602 FUNCTION("jtag_tdo_m0", jtag_tdo_grp0, &jtag_tdo_grp0_mux),
4603 FUNCTION("jtag_tdo_m1", jtag_tdo_grp1, &jtag_tdo_grp1_mux),
4604 FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux),
4605 FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux),
4606 FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux),
4607 FUNCTION("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux),
4608 FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux),
4609 FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux),
4610 FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux),
4611 FUNCTION("nd_df_basic", nd_df_basic_grp, &nd_df_basic_grp_mux),
4612 FUNCTION("nd_df_wp", nd_df_wp_grp, &nd_df_wp_grp_mux),
4613 FUNCTION("nd_df_cs", nd_df_cs_grp, &nd_df_cs_grp_mux),
4614 FUNCTION("ps", ps_grp, &ps_grp_mux),
4615 FUNCTION("ps_no_dir", ps_no_dir_grp, &ps_no_dir_grp_mux),
4616 FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux),
4617 FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux),
4618 FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux),
4619 FUNCTION("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux),
4620 FUNCTION("pwc_lowbatt_b_m0",
4621 pwc_lowbatt_b_grp0,
4622 &pwc_lowbatt_b_grp0_mux),
4623 FUNCTION("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux),
4624 FUNCTION("pwc_on_key_b_m0",
4625 pwc_on_key_b_grp0,
4626 &pwc_on_key_b_grp0_mux),
4627 FUNCTION("pwc_wakeup_src0",
4628 pwc_wakeup_src0_grp,
4629 &pwc_wakeup_src0_grp_mux),
4630 FUNCTION("pwc_wakeup_src1",
4631 pwc_wakeup_src1_grp,
4632 &pwc_wakeup_src1_grp_mux),
4633 FUNCTION("pwc_wakeup_src2",
4634 pwc_wakeup_src2_grp,
4635 &pwc_wakeup_src2_grp_mux),
4636 FUNCTION("pwc_wakeup_src3",
4637 pwc_wakeup_src3_grp,
4638 &pwc_wakeup_src3_grp_mux),
4639 FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux),
4640 FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux),
4641 FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux),
4642 FUNCTION("pw_cko0_m3", pw_cko0_grp3, &pw_cko0_grp3_mux),
4643 FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux),
4644 FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux),
4645 FUNCTION("pw_cko1_m2", pw_cko1_grp2, &pw_cko1_grp2_mux),
4646 FUNCTION("pw_i2s01_clk_m0",
4647 pw_i2s01_clk_grp0,
4648 &pw_i2s01_clk_grp0_mux),
4649 FUNCTION("pw_i2s01_clk_m1",
4650 pw_i2s01_clk_grp1,
4651 &pw_i2s01_clk_grp1_mux),
4652 FUNCTION("pw_i2s01_clk_m2",
4653 pw_i2s01_clk_grp2,
4654 &pw_i2s01_clk_grp2_mux),
4655 FUNCTION("pw_pwm0_m0", pw_pwm0_grp0, &pw_pwm0_grp0_mux),
4656 FUNCTION("pw_pwm0_m1", pw_pwm0_grp1, &pw_pwm0_grp1_mux),
4657 FUNCTION("pw_pwm1_m0", pw_pwm1_grp0, &pw_pwm1_grp0_mux),
4658 FUNCTION("pw_pwm1_m1", pw_pwm1_grp1, &pw_pwm1_grp1_mux),
4659 FUNCTION("pw_pwm1_m2", pw_pwm1_grp2, &pw_pwm1_grp2_mux),
4660 FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux),
4661 FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux),
4662 FUNCTION("pw_pwm2_m2", pw_pwm2_grp2, &pw_pwm2_grp2_mux),
4663 FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux),
4664 FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux),
4665 FUNCTION("pw_pwm_cpu_vol_m0",
4666 pw_pwm_cpu_vol_grp0,
4667 &pw_pwm_cpu_vol_grp0_mux),
4668 FUNCTION("pw_pwm_cpu_vol_m1",
4669 pw_pwm_cpu_vol_grp1,
4670 &pw_pwm_cpu_vol_grp1_mux),
4671 FUNCTION("pw_pwm_cpu_vol_m2",
4672 pw_pwm_cpu_vol_grp2,
4673 &pw_pwm_cpu_vol_grp2_mux),
4674 FUNCTION("pw_backlight_m0",
4675 pw_backlight_grp0,
4676 &pw_backlight_grp0_mux),
4677 FUNCTION("pw_backlight_m1",
4678 pw_backlight_grp1,
4679 &pw_backlight_grp1_mux),
4680 FUNCTION("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux),
4681 FUNCTION("rg_gmac_phy_intr_n",
4682 rg_gmac_phy_intr_n_grp,
4683 &rg_gmac_phy_intr_n_grp_mux),
4684 FUNCTION("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux),
4685 FUNCTION("rg_rgmii_phy_ref_clk_m0",
4686 rg_rgmii_phy_ref_clk_grp0,
4687 &rg_rgmii_phy_ref_clk_grp0_mux),
4688 FUNCTION("rg_rgmii_phy_ref_clk_m1",
4689 rg_rgmii_phy_ref_clk_grp1,
4690 &rg_rgmii_phy_ref_clk_grp1_mux),
4691 FUNCTION("sd0", sd0_grp, &sd0_grp_mux),
4692 FUNCTION("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux),
4693 FUNCTION("sd1", sd1_grp, &sd1_grp_mux),
4694 FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux),
4695 FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux),
4696 FUNCTION("sd2_basic", sd2_basic_grp, &sd2_basic_grp_mux),
4697 FUNCTION("sd2_cdb_m0", sd2_cdb_grp0, &sd2_cdb_grp0_mux),
4698 FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux),
4699 FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux),
4700 FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux),
4701 FUNCTION("sd3", sd3_9_grp, &sd3_9_grp_mux),
4702 FUNCTION("sd5", sd5_grp, &sd5_grp_mux),
4703 FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux),
4704 FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux),
4705 FUNCTION("sd9", sd3_9_grp, &sd3_9_grp_mux),
4706 FUNCTION("sp0_ext_ldo_on",
4707 sp0_ext_ldo_on_grp,
4708 &sp0_ext_ldo_on_grp_mux),
4709 FUNCTION("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux),
4710 FUNCTION("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux),
4711 FUNCTION("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux),
4712 FUNCTION("uart0", uart0_grp, &uart0_grp_mux),
4713 FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux),
4714 FUNCTION("uart1", uart1_grp, &uart1_grp_mux),
4715 FUNCTION("uart2_cts_m0", uart2_cts_grp0, &uart2_cts_grp0_mux),
4716 FUNCTION("uart2_cts_m1", uart2_cts_grp1, &uart2_cts_grp1_mux),
4717 FUNCTION("uart2_rts_m0", uart2_rts_grp0, &uart2_rts_grp0_mux),
4718 FUNCTION("uart2_rts_m1", uart2_rts_grp1, &uart2_rts_grp1_mux),
4719 FUNCTION("uart2_rxd_m0", uart2_rxd_grp0, &uart2_rxd_grp0_mux),
4720 FUNCTION("uart2_rxd_m1", uart2_rxd_grp1, &uart2_rxd_grp1_mux),
4721 FUNCTION("uart2_rxd_m2", uart2_rxd_grp2, &uart2_rxd_grp2_mux),
4722 FUNCTION("uart2_txd_m0", uart2_txd_grp0, &uart2_txd_grp0_mux),
4723 FUNCTION("uart2_txd_m1", uart2_txd_grp1, &uart2_txd_grp1_mux),
4724 FUNCTION("uart2_txd_m2", uart2_txd_grp2, &uart2_txd_grp2_mux),
4725 FUNCTION("uart3_cts_m0", uart3_cts_grp0, &uart3_cts_grp0_mux),
4726 FUNCTION("uart3_cts_m1", uart3_cts_grp1, &uart3_cts_grp1_mux),
4727 FUNCTION("uart3_cts_m2", uart3_cts_grp2, &uart3_cts_grp2_mux),
4728 FUNCTION("uart3_rts_m0", uart3_rts_grp0, &uart3_rts_grp0_mux),
4729 FUNCTION("uart3_rts_m1", uart3_rts_grp1, &uart3_rts_grp1_mux),
4730 FUNCTION("uart3_rts_m2", uart3_rts_grp2, &uart3_rts_grp2_mux),
4731 FUNCTION("uart3_rxd_m0", uart3_rxd_grp0, &uart3_rxd_grp0_mux),
4732 FUNCTION("uart3_rxd_m1", uart3_rxd_grp1, &uart3_rxd_grp1_mux),
4733 FUNCTION("uart3_rxd_m2", uart3_rxd_grp2, &uart3_rxd_grp2_mux),
4734 FUNCTION("uart3_txd_m0", uart3_txd_grp0, &uart3_txd_grp0_mux),
4735 FUNCTION("uart3_txd_m1", uart3_txd_grp1, &uart3_txd_grp1_mux),
4736 FUNCTION("uart3_txd_m2", uart3_txd_grp2, &uart3_txd_grp2_mux),
4737 FUNCTION("uart4_basic", uart4_basic_grp, &uart4_basic_grp_mux),
4738 FUNCTION("uart4_cts_m0", uart4_cts_grp0, &uart4_cts_grp0_mux),
4739 FUNCTION("uart4_cts_m1", uart4_cts_grp1, &uart4_cts_grp1_mux),
4740 FUNCTION("uart4_cts_m2", uart4_cts_grp2, &uart4_cts_grp2_mux),
4741 FUNCTION("uart4_rts_m0", uart4_rts_grp0, &uart4_rts_grp0_mux),
4742 FUNCTION("uart4_rts_m1", uart4_rts_grp1, &uart4_rts_grp1_mux),
4743 FUNCTION("uart4_rts_m2", uart4_rts_grp2, &uart4_rts_grp2_mux),
4744 FUNCTION("usb0_drvvbus_m0",
4745 usb0_drvvbus_grp0,
4746 &usb0_drvvbus_grp0_mux),
4747 FUNCTION("usb0_drvvbus_m1",
4748 usb0_drvvbus_grp1,
4749 &usb0_drvvbus_grp1_mux),
4750 FUNCTION("usb1_drvvbus_m0",
4751 usb1_drvvbus_grp0,
4752 &usb1_drvvbus_grp0_mux),
4753 FUNCTION("usb1_drvvbus_m1",
4754 usb1_drvvbus_grp1,
4755 &usb1_drvvbus_grp1_mux),
4756 FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux),
4757 FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux),
4758 FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux),
4759 FUNCTION("vi_vip1_low8bit",
4760 vi_vip1_low8bit_grp,
4761 &vi_vip1_low8bit_grp_mux),
4762 FUNCTION("vi_vip1_high8bit",
4763 vi_vip1_high8bit_grp,
4764 &vi_vip1_high8bit_grp_mux),
4765 };
4766
4767 static struct atlas7_pinctrl_data atlas7_ioc_data = {
4768 .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
4769 .pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
4770 .grps = (struct atlas7_pin_group *)altas7_pin_groups,
4771 .grps_cnt = ARRAY_SIZE(altas7_pin_groups),
4772 .funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions,
4773 .funcs_cnt = ARRAY_SIZE(atlas7_pmx_functions),
4774 .confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs,
4775 .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs),
4776 };
4777
4778 /* Simple map data structure */
4779 struct map_data {
4780 u8 idx;
4781 u8 data;
4782 };
4783
4784 /**
4785 * struct atlas7_pull_info - Atlas7 Pad pull info
4786 * @type:The type of this Pad.
4787 * @mask:The mas value of this pin's pull bits.
4788 * @v2s: The map of pull register value to pull status.
4789 * @s2v: The map of pull status to pull register value.
4790 */
4791 struct atlas7_pull_info {
4792 u8 pad_type;
4793 u8 mask;
4794 const struct map_data *v2s;
4795 const struct map_data *s2v;
4796 };
4797
4798 /* Pull Register value map to status */
4799 static const struct map_data p4we_pull_v2s[] = {
4800 { P4WE_PULL_UP, PULL_UP },
4801 { P4WE_HIGH_HYSTERESIS, HIGH_HYSTERESIS },
4802 { P4WE_HIGH_Z, HIGH_Z },
4803 { P4WE_PULL_DOWN, PULL_DOWN },
4804 };
4805
4806 static const struct map_data p16st_pull_v2s[] = {
4807 { P16ST_PULL_UP, PULL_UP },
4808 { PD, PULL_UNKNOWN },
4809 { P16ST_HIGH_Z, HIGH_Z },
4810 { P16ST_PULL_DOWN, PULL_DOWN },
4811 };
4812
4813 static const struct map_data pm31_pull_v2s[] = {
4814 { PM31_PULL_DISABLED, PULL_DOWN },
4815 { PM31_PULL_ENABLED, PULL_UP },
4816 };
4817
4818 static const struct map_data pangd_pull_v2s[] = {
4819 { PANGD_PULL_UP, PULL_UP },
4820 { PD, PULL_UNKNOWN },
4821 { PANGD_HIGH_Z, HIGH_Z },
4822 { PANGD_PULL_DOWN, PULL_DOWN },
4823 };
4824
4825 /* Pull status map to register value */
4826 static const struct map_data p4we_pull_s2v[] = {
4827 { PULL_UP, P4WE_PULL_UP },
4828 { HIGH_HYSTERESIS, P4WE_HIGH_HYSTERESIS },
4829 { HIGH_Z, P4WE_HIGH_Z },
4830 { PULL_DOWN, P4WE_PULL_DOWN },
4831 { PULL_DISABLE, -1 },
4832 { PULL_ENABLE, -1 },
4833 };
4834
4835 static const struct map_data p16st_pull_s2v[] = {
4836 { PULL_UP, P16ST_PULL_UP },
4837 { HIGH_HYSTERESIS, -1 },
4838 { HIGH_Z, P16ST_HIGH_Z },
4839 { PULL_DOWN, P16ST_PULL_DOWN },
4840 { PULL_DISABLE, -1 },
4841 { PULL_ENABLE, -1 },
4842 };
4843
4844 static const struct map_data pm31_pull_s2v[] = {
4845 { PULL_UP, PM31_PULL_ENABLED },
4846 { HIGH_HYSTERESIS, -1 },
4847 { HIGH_Z, -1 },
4848 { PULL_DOWN, PM31_PULL_DISABLED },
4849 { PULL_DISABLE, -1 },
4850 { PULL_ENABLE, -1 },
4851 };
4852
4853 static const struct map_data pangd_pull_s2v[] = {
4854 { PULL_UP, PANGD_PULL_UP },
4855 { HIGH_HYSTERESIS, -1 },
4856 { HIGH_Z, PANGD_HIGH_Z },
4857 { PULL_DOWN, PANGD_PULL_DOWN },
4858 { PULL_DISABLE, -1 },
4859 { PULL_ENABLE, -1 },
4860 };
4861
4862 static const struct atlas7_pull_info atlas7_pull_map[] = {
4863 { PAD_T_4WE_PD, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
4864 { PAD_T_4WE_PU, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
4865 { PAD_T_16ST, P16ST_PULL_MASK, p16st_pull_v2s, p16st_pull_s2v },
4866 { PAD_T_M31_0204_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4867 { PAD_T_M31_0204_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4868 { PAD_T_M31_0610_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4869 { PAD_T_M31_0610_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4870 { PAD_T_AD, PANGD_PULL_MASK, pangd_pull_v2s, pangd_pull_s2v },
4871 };
4872
4873 /**
4874 * struct atlas7_ds_ma_info - Atlas7 Pad DriveStrength & currents info
4875 * @ma: The Drive Strength in current value .
4876 * @ds_16st: The correspond raw value of 16st pad.
4877 * @ds_4we: The correspond raw value of 4we pad.
4878 * @ds_0204m31: The correspond raw value of 0204m31 pad.
4879 * @ds_0610m31: The correspond raw value of 0610m31 pad.
4880 */
4881 struct atlas7_ds_ma_info {
4882 u32 ma;
4883 u32 ds_16st;
4884 u32 ds_4we;
4885 u32 ds_0204m31;
4886 u32 ds_0610m31;
4887 };
4888
4889 static const struct atlas7_ds_ma_info atlas7_ma2ds_map[] = {
4890 { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL },
4891 { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL },
4892 { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0 },
4893 { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL },
4894 { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1 },
4895 { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL },
4896 { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL },
4897 { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL },
4898 { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL },
4899 { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL },
4900 { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL },
4901 { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL },
4902 { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL },
4903 { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL },
4904 { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL },
4905 { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL },
4906 };
4907
4908 /**
4909 * struct atlas7_ds_info - Atlas7 Pad DriveStrength info
4910 * @type: The type of this Pad.
4911 * @mask: The mask value of this pin's pull bits.
4912 * @imval: The immediate value of drives trength register.
4913 */
4914 struct atlas7_ds_info {
4915 u8 type;
4916 u8 mask;
4917 u8 imval;
4918 u8 reserved;
4919 };
4920
4921 static const struct atlas7_ds_info atlas7_ds_map[] = {
4922 { PAD_T_4WE_PD, DS_2BIT_MASK, DS_2BIT_IM_VAL },
4923 { PAD_T_4WE_PU, DS_2BIT_MASK, DS_2BIT_IM_VAL },
4924 { PAD_T_16ST, DS_4BIT_MASK, DS_4BIT_IM_VAL },
4925 { PAD_T_M31_0204_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4926 { PAD_T_M31_0204_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4927 { PAD_T_M31_0610_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4928 { PAD_T_M31_0610_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4929 { PAD_T_AD, DS_NULL, DS_NULL },
4930 };
4931
4932 static inline u32 atlas7_pin_to_bank(u32 pin)
4933 {
4934 return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0;
4935 }
4936
4937 static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
4938 {
4939 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4940
4941 return pmx->pctl_data->funcs_cnt;
4942 }
4943
4944 static const char *atlas7_pmx_get_func_name(struct pinctrl_dev *pctldev,
4945 u32 selector)
4946 {
4947 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4948
4949 return pmx->pctl_data->funcs[selector].name;
4950 }
4951
4952 static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev,
4953 u32 selector, const char * const **groups,
4954 u32 * const num_groups)
4955 {
4956 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4957
4958 *groups = pmx->pctl_data->funcs[selector].groups;
4959 *num_groups = pmx->pctl_data->funcs[selector].num_groups;
4960
4961 return 0;
4962 }
4963
4964 static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx,
4965 const struct atlas7_pad_mux *mux)
4966 {
4967 /* Set Input Disable to avoid input glitches
4968 *
4969 * All Input-Disable Control registers are located on IOCRTC.
4970 * So the regs bank is always 0.
4971 *
4972 */
4973 if (mux->dinput_reg && mux->dinput_val_reg) {
4974 writel(DI_MASK << mux->dinput_bit,
4975 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
4976 writel(DI_DISABLE << mux->dinput_bit,
4977 pmx->regs[BANK_DS] + mux->dinput_reg);
4978
4979
4980 writel(DIV_MASK << mux->dinput_val_bit,
4981 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
4982 writel(DIV_DISABLE << mux->dinput_val_bit,
4983 pmx->regs[BANK_DS] + mux->dinput_val_reg);
4984 }
4985 }
4986
4987 static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx,
4988 const struct atlas7_pad_mux *mux)
4989 {
4990 /* Clear Input Disable to avoid input glitches */
4991 if (mux->dinput_reg && mux->dinput_val_reg) {
4992 writel(DI_MASK << mux->dinput_bit,
4993 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
4994 writel(DI_ENABLE << mux->dinput_bit,
4995 pmx->regs[BANK_DS] + mux->dinput_reg);
4996
4997 writel(DIV_MASK << mux->dinput_val_bit,
4998 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
4999 writel(DIV_ENABLE << mux->dinput_val_bit,
5000 pmx->regs[BANK_DS] + mux->dinput_val_reg);
5001 }
5002 }
5003
5004 static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx,
5005 struct atlas7_pad_config *conf,
5006 u32 bank, u32 ad_sel)
5007 {
5008 unsigned long regv;
5009
5010 /* Write to clear register to clear A/D selector */
5011 writel(ANA_CLEAR_MASK << conf->ad_ctrl_bit,
5012 pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg));
5013
5014 /* Set target pad A/D selector */
5015 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5016 regv &= ~(ANA_CLEAR_MASK << conf->ad_ctrl_bit);
5017 writel(regv | (ad_sel << conf->ad_ctrl_bit),
5018 pmx->regs[bank] + conf->ad_ctrl_reg);
5019
5020 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5021 pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
5022 bank, conf->ad_ctrl_reg, regv);
5023 return 0;
5024 }
5025
5026 static int __atlas7_pmx_pin_analog_enable(struct atlas7_pmx *pmx,
5027 struct atlas7_pad_config *conf, u32 bank)
5028 {
5029 /* Only PAD_T_AD pins can change between Analogue&Digital */
5030 if (conf->type != PAD_T_AD)
5031 return -EINVAL;
5032
5033 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0);
5034 }
5035
5036 static int __atlas7_pmx_pin_digital_enable(struct atlas7_pmx *pmx,
5037 struct atlas7_pad_config *conf, u32 bank)
5038 {
5039 /* Other type pads are always digital */
5040 if (conf->type != PAD_T_AD)
5041 return 0;
5042
5043 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1);
5044 }
5045
5046 static int __atlas7_pmx_pin_enable(struct atlas7_pmx *pmx,
5047 u32 pin, u32 func)
5048 {
5049 struct atlas7_pad_config *conf;
5050 u32 bank;
5051 int ret;
5052 unsigned long regv;
5053
5054 pr_debug("PMX DUMP ### pin#%d func:%d #### START >>>\n",
5055 pin, func);
5056
5057 /* Get this Pad's descriptor from PINCTRL */
5058 conf = &pmx->pctl_data->confs[pin];
5059 bank = atlas7_pin_to_bank(pin);
5060
5061 /* Just enable the analog function of this pad */
5062 if (FUNC_ANALOGUE == func) {
5063 ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank);
5064 if (ret)
5065 dev_err(pmx->dev,
5066 "Convert pad#%d to analog failed, ret=%d\n",
5067 pin, ret);
5068 return ret;
5069 }
5070
5071 /* Set Pads from analog to digital */
5072 ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank);
5073 if (ret) {
5074 dev_err(pmx->dev,
5075 "Convert pad#%d to digital failed, ret=%d\n",
5076 pin, ret);
5077 return ret;
5078 }
5079
5080 /* Write to clear register to clear current function */
5081 writel(FUNC_CLEAR_MASK << conf->mux_bit,
5082 pmx->regs[bank] + CLR_REG(conf->mux_reg));
5083
5084 /* Set target pad mux function */
5085 regv = readl(pmx->regs[bank] + conf->mux_reg);
5086 regv &= ~(FUNC_CLEAR_MASK << conf->mux_bit);
5087 writel(regv | (func << conf->mux_bit),
5088 pmx->regs[bank] + conf->mux_reg);
5089
5090 regv = readl(pmx->regs[bank] + conf->mux_reg);
5091 pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
5092 bank, conf->mux_reg, regv);
5093
5094 return 0;
5095 }
5096
5097 static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev,
5098 u32 func_selector, u32 group_selector)
5099 {
5100 int idx, ret;
5101 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5102 struct atlas7_pmx_func *pmx_func;
5103 struct atlas7_pin_group *pin_grp;
5104 const struct atlas7_grp_mux *grp_mux;
5105 const struct atlas7_pad_mux *mux;
5106
5107 pmx_func = &pmx->pctl_data->funcs[func_selector];
5108 pin_grp = &pmx->pctl_data->grps[group_selector];
5109
5110 pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n",
5111 pmx_func->name, pin_grp->name);
5112
5113 /* the sd3 and sd9 pin select by SYS2PCI_SDIO9SEL register */
5114 if (pin_grp->pins == (unsigned int *)&sd3_9_pins) {
5115 if (!strcmp(pmx_func->name, "sd9"))
5116 writel(1, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
5117 else
5118 writel(0, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
5119 }
5120
5121 grp_mux = pmx_func->grpmux;
5122
5123 for (idx = 0; idx < grp_mux->pad_mux_count; idx++) {
5124 mux = &grp_mux->pad_mux_list[idx];
5125 __atlas7_pmx_pin_input_disable_set(pmx, mux);
5126 ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func);
5127 if (ret) {
5128 dev_err(pmx->dev,
5129 "FUNC:%s GRP:%s PIN#%d.%d failed, ret=%d\n",
5130 pmx_func->name, pin_grp->name,
5131 mux->pin, mux->func, ret);
5132 BUG_ON(1);
5133 }
5134 __atlas7_pmx_pin_input_disable_clr(pmx, mux);
5135 }
5136 pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### END <<<\n",
5137 pmx_func->name, pin_grp->name);
5138
5139 return 0;
5140 }
5141
5142 static u32 convert_current_to_drive_strength(u32 type, u32 ma)
5143 {
5144 int idx;
5145
5146 for (idx = 0; idx < ARRAY_SIZE(atlas7_ma2ds_map); idx++) {
5147 if (atlas7_ma2ds_map[idx].ma != ma)
5148 continue;
5149
5150 if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU)
5151 return atlas7_ma2ds_map[idx].ds_4we;
5152 else if (type == PAD_T_16ST)
5153 return atlas7_ma2ds_map[idx].ds_16st;
5154 else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU)
5155 return atlas7_ma2ds_map[idx].ds_0204m31;
5156 else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU)
5157 return atlas7_ma2ds_map[idx].ds_0610m31;
5158 }
5159
5160 return DS_NULL;
5161 }
5162
5163 static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev,
5164 u32 pin, u32 sel)
5165 {
5166 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5167 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5168 const struct atlas7_pull_info *pull_info;
5169 u32 bank;
5170 unsigned long regv;
5171 void __iomem *pull_sel_reg;
5172
5173 bank = atlas7_pin_to_bank(pin);
5174 pull_info = &atlas7_pull_map[conf->type];
5175 pull_sel_reg = pmx->regs[bank] + conf->pupd_reg;
5176
5177 /* Retrieve correspond register value from table by sel */
5178 regv = pull_info->s2v[sel].data & pull_info->mask;
5179
5180 /* Clear & Set new value to pull register */
5181 writel(pull_info->mask << conf->pupd_bit, CLR_REG(pull_sel_reg));
5182 writel(regv << conf->pupd_bit, pull_sel_reg);
5183
5184 pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n",
5185 pin, sel);
5186 return 0;
5187 }
5188
5189 static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
5190 u32 pin, u32 sel)
5191 {
5192 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5193 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5194 const struct atlas7_ds_info *ds_info;
5195 u32 bank;
5196 void __iomem *ds_sel_reg;
5197
5198 ds_info = &atlas7_ds_map[conf->type];
5199 if (sel & (~(ds_info->mask)))
5200 goto unsupport;
5201
5202 bank = atlas7_pin_to_bank(pin);
5203 ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg;
5204
5205 writel(ds_info->imval << conf->drvstr_bit, CLR_REG(ds_sel_reg));
5206 writel(sel << conf->drvstr_bit, ds_sel_reg);
5207
5208 return 0;
5209
5210 unsupport:
5211 pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n",
5212 pin, conf->type, sel);
5213 return -ENOTSUPP;
5214 }
5215
5216 static int altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
5217 u32 pin, u32 ma)
5218 {
5219 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5220 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5221 u32 type = conf->type;
5222 u32 sel;
5223 int ret;
5224
5225 sel = convert_current_to_drive_strength(conf->type, ma);
5226 if (DS_NULL == sel) {
5227 pr_err("Pad#%d type[%d] doesn't support ds current[%d]!\n",
5228 pin, type, ma);
5229 return -ENOTSUPP;
5230 }
5231
5232 ret = __altas7_pinctrl_set_drive_strength_sel(pctldev,
5233 pin, sel);
5234 pr_debug("PIN_CFG ### SET PIN#%d DS:%d MA:%d == %s ####\n",
5235 pin, sel, ma, ret?"FAILED":"OK");
5236 return ret;
5237 }
5238
5239 static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
5240 struct pinctrl_gpio_range *range, u32 pin)
5241 {
5242 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5243 u32 idx;
5244
5245 dev_dbg(pmx->dev,
5246 "atlas7_pmx_gpio_request_enable: pin=%d\n", pin);
5247 for (idx = 0; idx < range->npins; idx++) {
5248 if (pin == range->pins[idx])
5249 break;
5250 }
5251
5252 if (idx >= range->npins) {
5253 dev_err(pmx->dev,
5254 "The pin#%d could not be requested as GPIO!!\n",
5255 pin);
5256 return -EPERM;
5257 }
5258
5259 __atlas7_pmx_pin_enable(pmx, pin, FUNC_GPIO);
5260
5261 return 0;
5262 }
5263
5264 static const struct pinmux_ops atlas7_pinmux_ops = {
5265 .get_functions_count = atlas7_pmx_get_funcs_count,
5266 .get_function_name = atlas7_pmx_get_func_name,
5267 .get_function_groups = atlas7_pmx_get_func_groups,
5268 .set_mux = atlas7_pmx_set_mux,
5269 .gpio_request_enable = atlas7_pmx_gpio_request_enable,
5270 };
5271
5272 static int atlas7_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
5273 {
5274 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5275
5276 return pmx->pctl_data->grps_cnt;
5277 }
5278
5279 static const char *atlas7_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
5280 u32 group)
5281 {
5282 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5283
5284 return pmx->pctl_data->grps[group].name;
5285 }
5286
5287 static int atlas7_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
5288 u32 group, const u32 **pins, u32 *num_pins)
5289 {
5290 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5291
5292 *num_pins = pmx->pctl_data->grps[group].num_pins;
5293 *pins = pmx->pctl_data->grps[group].pins;
5294
5295 return 0;
5296 }
5297
5298 static int atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
5299 struct device_node *np_config,
5300 struct pinctrl_map **map,
5301 u32 *num_maps)
5302 {
5303 return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
5304 num_maps, PIN_MAP_TYPE_INVALID);
5305 }
5306
5307 static void atlas7_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
5308 struct pinctrl_map *map, u32 num_maps)
5309 {
5310 kfree(map);
5311 }
5312
5313 static const struct pinctrl_ops atlas7_pinctrl_ops = {
5314 .get_groups_count = atlas7_pinctrl_get_groups_count,
5315 .get_group_name = atlas7_pinctrl_get_group_name,
5316 .get_group_pins = atlas7_pinctrl_get_group_pins,
5317 .dt_node_to_map = atlas7_pinctrl_dt_node_to_map,
5318 .dt_free_map = atlas7_pinctrl_dt_free_map,
5319 };
5320
5321 static int atlas7_pin_config_set(struct pinctrl_dev *pctldev,
5322 unsigned pin, unsigned long *configs,
5323 unsigned num_configs)
5324 {
5325 u16 param;
5326 u32 arg;
5327 int idx, err;
5328
5329 for (idx = 0; idx < num_configs; idx++) {
5330 param = pinconf_to_config_param(configs[idx]);
5331 arg = pinconf_to_config_argument(configs[idx]);
5332
5333 pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d >>>>>\n",
5334 pin, atlas7_ioc_pads[pin].name, param, arg);
5335 switch (param) {
5336 case PIN_CONFIG_BIAS_PULL_UP:
5337 err = altas7_pinctrl_set_pull_sel(pctldev,
5338 pin, PULL_UP);
5339 if (err)
5340 return err;
5341 break;
5342
5343 case PIN_CONFIG_BIAS_PULL_DOWN:
5344 err = altas7_pinctrl_set_pull_sel(pctldev,
5345 pin, PULL_DOWN);
5346 if (err)
5347 return err;
5348 break;
5349
5350 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
5351 err = altas7_pinctrl_set_pull_sel(pctldev,
5352 pin, HIGH_HYSTERESIS);
5353 if (err)
5354 return err;
5355 break;
5356 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
5357 err = altas7_pinctrl_set_pull_sel(pctldev,
5358 pin, HIGH_Z);
5359 if (err)
5360 return err;
5361 break;
5362
5363 case PIN_CONFIG_DRIVE_STRENGTH:
5364 err = altas7_pinctrl_set_drive_strength_sel(pctldev,
5365 pin, arg);
5366 if (err)
5367 return err;
5368 break;
5369 default:
5370 return -ENOTSUPP;
5371 }
5372 pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d <<<<\n",
5373 pin, atlas7_ioc_pads[pin].name, param, arg);
5374 }
5375
5376 return 0;
5377 }
5378
5379 static int atlas7_pin_config_group_set(struct pinctrl_dev *pctldev,
5380 unsigned group, unsigned long *configs,
5381 unsigned num_configs)
5382 {
5383 const unsigned *pins;
5384 unsigned npins;
5385 int i, ret;
5386
5387 ret = atlas7_pinctrl_get_group_pins(pctldev, group, &pins, &npins);
5388 if (ret)
5389 return ret;
5390 for (i = 0; i < npins; i++) {
5391 if (atlas7_pin_config_set(pctldev, pins[i],
5392 configs, num_configs))
5393 return -ENOTSUPP;
5394 }
5395 return 0;
5396 }
5397
5398 static const struct pinconf_ops atlas7_pinconf_ops = {
5399 .pin_config_set = atlas7_pin_config_set,
5400 .pin_config_group_set = atlas7_pin_config_group_set,
5401 .is_generic = true,
5402 };
5403
5404 static int atlas7_pinmux_probe(struct platform_device *pdev)
5405 {
5406 int ret, idx;
5407 struct atlas7_pmx *pmx;
5408 struct device_node *np = pdev->dev.of_node;
5409 u32 banks = ATLAS7_PINCTRL_REG_BANKS;
5410 struct device_node *sys2pci_np;
5411 struct resource res;
5412
5413 /* Create state holders etc for this driver */
5414 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
5415 if (!pmx)
5416 return -ENOMEM;
5417
5418 /* The sd3 and sd9 shared all pins, and the function select by
5419 * SYS2PCI_SDIO9SEL register
5420 */
5421 sys2pci_np = of_find_node_by_name(NULL, "sys2pci");
5422 if (!sys2pci_np)
5423 return -EINVAL;
5424
5425 ret = of_address_to_resource(sys2pci_np, 0, &res);
5426 of_node_put(sys2pci_np);
5427 if (ret)
5428 return ret;
5429
5430 pmx->sys2pci_base = devm_ioremap_resource(&pdev->dev, &res);
5431 if (IS_ERR(pmx->sys2pci_base))
5432 return -ENOMEM;
5433
5434 pmx->dev = &pdev->dev;
5435
5436 pmx->pctl_data = &atlas7_ioc_data;
5437 pmx->pctl_desc.name = "pinctrl-atlas7";
5438 pmx->pctl_desc.pins = pmx->pctl_data->pads;
5439 pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt;
5440 pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops;
5441 pmx->pctl_desc.pmxops = &atlas7_pinmux_ops;
5442 pmx->pctl_desc.confops = &atlas7_pinconf_ops;
5443
5444 for (idx = 0; idx < banks; idx++) {
5445 pmx->regs[idx] = of_iomap(np, idx);
5446 if (!pmx->regs[idx]) {
5447 dev_err(&pdev->dev,
5448 "can't map ioc bank#%d registers\n", idx);
5449 ret = -ENOMEM;
5450 goto unmap_io;
5451 }
5452 }
5453
5454 /* Now register the pin controller and all pins it handles */
5455 pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx);
5456 if (IS_ERR(pmx->pctl)) {
5457 dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n");
5458 ret = PTR_ERR(pmx->pctl);
5459 goto unmap_io;
5460 }
5461
5462 platform_set_drvdata(pdev, pmx);
5463
5464 dev_info(&pdev->dev, "initialized atlas7 pinmux driver\n");
5465
5466 return 0;
5467
5468 unmap_io:
5469 for (idx = 0; idx < banks; idx++) {
5470 if (!pmx->regs[idx])
5471 break;
5472 iounmap(pmx->regs[idx]);
5473 }
5474
5475 return ret;
5476 }
5477
5478 #ifdef CONFIG_PM_SLEEP
5479 static int atlas7_pinmux_suspend_noirq(struct device *dev)
5480 {
5481 struct atlas7_pmx *pmx = dev_get_drvdata(dev);
5482 struct atlas7_pad_status *status;
5483 struct atlas7_pad_config *conf;
5484 const struct atlas7_ds_info *ds_info;
5485 const struct atlas7_pull_info *pull_info;
5486 int idx;
5487 u32 bank;
5488 unsigned long regv;
5489
5490 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
5491 /* Get this Pad's descriptor from PINCTRL */
5492 conf = &pmx->pctl_data->confs[idx];
5493 bank = atlas7_pin_to_bank(idx);
5494 status = &pmx->sleep_data[idx];
5495
5496 /* Save Function selector */
5497 regv = readl(pmx->regs[bank] + conf->mux_reg);
5498 status->func = (regv >> conf->mux_bit) & FUNC_CLEAR_MASK;
5499
5500 /* Check if Pad is in Analogue selector */
5501 if (conf->ad_ctrl_reg == -1)
5502 goto save_ds_sel;
5503
5504 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5505 if (!(regv & (conf->ad_ctrl_bit << ANA_CLEAR_MASK)))
5506 status->func = FUNC_ANALOGUE;
5507
5508 save_ds_sel:
5509 if (conf->drvstr_reg == -1)
5510 goto save_pull_sel;
5511
5512 /* Save Drive Strength selector */
5513 ds_info = &atlas7_ds_map[conf->type];
5514 regv = readl(pmx->regs[bank] + conf->drvstr_reg);
5515 status->dstr = (regv >> conf->drvstr_bit) & ds_info->mask;
5516
5517 save_pull_sel:
5518 /* Save Pull selector */
5519 pull_info = &atlas7_pull_map[conf->type];
5520 regv = readl(pmx->regs[bank] + conf->pupd_reg);
5521 regv = (regv >> conf->pupd_bit) & pull_info->mask;
5522 status->pull = pull_info->v2s[regv].data;
5523 }
5524
5525 /*
5526 * Save disable input selector, this selector is not for Pin,
5527 * but for Mux function.
5528 */
5529 for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
5530 pmx->status_ds[idx] = readl(pmx->regs[BANK_DS] +
5531 IN_DISABLE_0_REG_SET + 0x8 * idx);
5532 pmx->status_dsv[idx] = readl(pmx->regs[BANK_DS] +
5533 IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
5534 }
5535
5536 return 0;
5537 }
5538
5539 static int atlas7_pinmux_resume_noirq(struct device *dev)
5540 {
5541 struct atlas7_pmx *pmx = dev_get_drvdata(dev);
5542 struct atlas7_pad_status *status;
5543 struct atlas7_pad_config *conf;
5544 int idx;
5545 u32 bank;
5546
5547 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
5548 /* Get this Pad's descriptor from PINCTRL */
5549 conf = &pmx->pctl_data->confs[idx];
5550 bank = atlas7_pin_to_bank(idx);
5551 status = &pmx->sleep_data[idx];
5552
5553 /* Restore Function selector */
5554 __atlas7_pmx_pin_enable(pmx, idx, (u32)status->func & 0xff);
5555
5556 if (FUNC_ANALOGUE == status->func)
5557 goto restore_pull_sel;
5558
5559 /* Restore Drive Strength selector */
5560 __altas7_pinctrl_set_drive_strength_sel(pmx->pctl, idx,
5561 (u32)status->dstr & 0xff);
5562
5563 restore_pull_sel:
5564 /* Restore Pull selector */
5565 altas7_pinctrl_set_pull_sel(pmx->pctl, idx,
5566 (u32)status->pull & 0xff);
5567 }
5568
5569 /*
5570 * Restore disable input selector, this selector is not for Pin,
5571 * but for Mux function
5572 */
5573 for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
5574 writel(~0, pmx->regs[BANK_DS] +
5575 IN_DISABLE_0_REG_CLR + 0x8 * idx);
5576 writel(pmx->status_ds[idx], pmx->regs[BANK_DS] +
5577 IN_DISABLE_0_REG_SET + 0x8 * idx);
5578 writel(~0, pmx->regs[BANK_DS] +
5579 IN_DISABLE_VAL_0_REG_CLR + 0x8 * idx);
5580 writel(pmx->status_dsv[idx], pmx->regs[BANK_DS] +
5581 IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
5582 }
5583
5584 return 0;
5585 }
5586
5587 static const struct dev_pm_ops atlas7_pinmux_pm_ops = {
5588 .suspend_noirq = atlas7_pinmux_suspend_noirq,
5589 .resume_noirq = atlas7_pinmux_resume_noirq,
5590 .freeze_noirq = atlas7_pinmux_suspend_noirq,
5591 .restore_noirq = atlas7_pinmux_resume_noirq,
5592 };
5593 #endif
5594
5595 static const struct of_device_id atlas7_pinmux_ids[] = {
5596 { .compatible = "sirf,atlas7-ioc",},
5597 {},
5598 };
5599
5600 static struct platform_driver atlas7_pinmux_driver = {
5601 .driver = {
5602 .name = "atlas7-ioc",
5603 .of_match_table = atlas7_pinmux_ids,
5604 #ifdef CONFIG_PM_SLEEP
5605 .pm = &atlas7_pinmux_pm_ops,
5606 #endif
5607 },
5608 .probe = atlas7_pinmux_probe,
5609 };
5610
5611 static int __init atlas7_pinmux_init(void)
5612 {
5613 return platform_driver_register(&atlas7_pinmux_driver);
5614 }
5615 arch_initcall(atlas7_pinmux_init);
5616
5617
5618 /**
5619 * The Following is GPIO Code
5620 */
5621 static inline struct
5622 atlas7_gpio_bank *atlas7_gpio_to_bank(struct atlas7_gpio_chip *a7gc, u32 gpio)
5623 {
5624 return &a7gc->banks[GPIO_TO_BANK(gpio)];
5625 }
5626
5627 static int __atlas7_gpio_to_pin(struct atlas7_gpio_chip *a7gc, u32 gpio)
5628 {
5629 struct atlas7_gpio_bank *bank;
5630 u32 ofs;
5631
5632 bank = atlas7_gpio_to_bank(a7gc, gpio);
5633 ofs = gpio - bank->gpio_offset;
5634 if (ofs >= bank->ngpio)
5635 return -ENODEV;
5636
5637 return bank->gpio_pins[ofs];
5638 }
5639
5640 static void atlas7_gpio_irq_ack(struct irq_data *d)
5641 {
5642 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5643 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5644 struct atlas7_gpio_bank *bank;
5645 void __iomem *ctrl_reg;
5646 u32 val, pin_in_bank;
5647 unsigned long flags;
5648
5649 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5650 pin_in_bank = d->hwirq - bank->gpio_offset;
5651 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5652
5653 raw_spin_lock_irqsave(&a7gc->lock, flags);
5654
5655 val = readl(ctrl_reg);
5656 /* clear interrupt status */
5657 writel(val, ctrl_reg);
5658
5659 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5660 }
5661
5662 static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx)
5663 {
5664 struct atlas7_gpio_bank *bank;
5665 void __iomem *ctrl_reg;
5666 u32 val, pin_in_bank;
5667
5668 bank = atlas7_gpio_to_bank(a7gc, idx);
5669 pin_in_bank = idx - bank->gpio_offset;
5670 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5671
5672 val = readl(ctrl_reg);
5673 val &= ~(ATLAS7_GPIO_CTL_INTR_EN_MASK |
5674 ATLAS7_GPIO_CTL_INTR_STATUS_MASK);
5675 writel(val, ctrl_reg);
5676 }
5677
5678 static void atlas7_gpio_irq_mask(struct irq_data *d)
5679 {
5680 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5681 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5682 unsigned long flags;
5683
5684 raw_spin_lock_irqsave(&a7gc->lock, flags);
5685
5686 __atlas7_gpio_irq_mask(a7gc, d->hwirq);
5687
5688 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5689 }
5690
5691 static void atlas7_gpio_irq_unmask(struct irq_data *d)
5692 {
5693 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5694 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5695 struct atlas7_gpio_bank *bank;
5696 void __iomem *ctrl_reg;
5697 u32 val, pin_in_bank;
5698 unsigned long flags;
5699
5700 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5701 pin_in_bank = d->hwirq - bank->gpio_offset;
5702 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5703
5704 raw_spin_lock_irqsave(&a7gc->lock, flags);
5705
5706 val = readl(ctrl_reg);
5707 val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK;
5708 val |= ATLAS7_GPIO_CTL_INTR_EN_MASK;
5709 writel(val, ctrl_reg);
5710
5711 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5712 }
5713
5714 static int atlas7_gpio_irq_type(struct irq_data *d,
5715 unsigned int type)
5716 {
5717 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5718 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5719 struct atlas7_gpio_bank *bank;
5720 void __iomem *ctrl_reg;
5721 u32 val, pin_in_bank;
5722 unsigned long flags;
5723
5724 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5725 pin_in_bank = d->hwirq - bank->gpio_offset;
5726 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5727
5728 raw_spin_lock_irqsave(&a7gc->lock, flags);
5729
5730 val = readl(ctrl_reg);
5731 val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK |
5732 ATLAS7_GPIO_CTL_INTR_EN_MASK);
5733
5734 switch (type) {
5735 case IRQ_TYPE_NONE:
5736 break;
5737
5738 case IRQ_TYPE_EDGE_RISING:
5739 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5740 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5741 val &= ~ATLAS7_GPIO_CTL_INTR_LOW_MASK;
5742 break;
5743
5744 case IRQ_TYPE_EDGE_FALLING:
5745 val &= ~ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
5746 val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5747 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5748 break;
5749
5750 case IRQ_TYPE_EDGE_BOTH:
5751 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5752 ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5753 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5754 break;
5755
5756 case IRQ_TYPE_LEVEL_LOW:
5757 val &= ~(ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5758 ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
5759 val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK;
5760 break;
5761
5762 case IRQ_TYPE_LEVEL_HIGH:
5763 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
5764 val &= ~(ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5765 ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
5766 break;
5767 }
5768
5769 writel(val, ctrl_reg);
5770
5771 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5772
5773 return 0;
5774 }
5775
5776 static struct irq_chip atlas7_gpio_irq_chip = {
5777 .name = "atlas7-gpio-irq",
5778 .irq_ack = atlas7_gpio_irq_ack,
5779 .irq_mask = atlas7_gpio_irq_mask,
5780 .irq_unmask = atlas7_gpio_irq_unmask,
5781 .irq_set_type = atlas7_gpio_irq_type,
5782 };
5783
5784 static void atlas7_gpio_handle_irq(struct irq_desc *desc)
5785 {
5786 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
5787 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5788 struct atlas7_gpio_bank *bank = NULL;
5789 u32 status, ctrl;
5790 int pin_in_bank = 0, idx;
5791 struct irq_chip *chip = irq_desc_get_chip(desc);
5792 unsigned int irq = irq_desc_get_irq(desc);
5793
5794 for (idx = 0; idx < a7gc->nbank; idx++) {
5795 bank = &a7gc->banks[idx];
5796 if (bank->irq == irq)
5797 break;
5798 }
5799 BUG_ON(idx == a7gc->nbank);
5800
5801 chained_irq_enter(chip, desc);
5802
5803 status = readl(ATLAS7_GPIO_INT_STATUS(bank));
5804 if (!status) {
5805 pr_warn("%s: gpio [%s] status %#x no interrupt is flagged\n",
5806 __func__, gc->label, status);
5807 handle_bad_irq(desc);
5808 return;
5809 }
5810
5811 while (status) {
5812 ctrl = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
5813
5814 /*
5815 * Here we must check whether the corresponding GPIO's
5816 * interrupt has been enabled, otherwise just skip it
5817 */
5818 if ((status & 0x1) && (ctrl & ATLAS7_GPIO_CTL_INTR_EN_MASK)) {
5819 pr_debug("%s: chip[%s] gpio:%d happens\n",
5820 __func__, gc->label,
5821 bank->gpio_offset + pin_in_bank);
5822 generic_handle_irq(
5823 irq_find_mapping(gc->irqdomain,
5824 bank->gpio_offset + pin_in_bank));
5825 }
5826
5827 if (++pin_in_bank >= bank->ngpio)
5828 break;
5829
5830 status = status >> 1;
5831 }
5832
5833 chained_irq_exit(chip, desc);
5834 }
5835
5836 static void __atlas7_gpio_set_input(struct atlas7_gpio_chip *a7gc,
5837 unsigned int gpio)
5838 {
5839 struct atlas7_gpio_bank *bank;
5840 void __iomem *ctrl_reg;
5841 u32 val, pin_in_bank;
5842
5843 bank = atlas7_gpio_to_bank(a7gc, gpio);
5844 pin_in_bank = gpio - bank->gpio_offset;
5845 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5846
5847 val = readl(ctrl_reg);
5848 val &= ~ATLAS7_GPIO_CTL_OUT_EN_MASK;
5849 writel(val, ctrl_reg);
5850 }
5851
5852 static int atlas7_gpio_request(struct gpio_chip *chip,
5853 unsigned int gpio)
5854 {
5855 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5856 int ret;
5857 unsigned long flags;
5858
5859 ret = __atlas7_gpio_to_pin(a7gc, gpio);
5860 if (ret < 0)
5861 return ret;
5862
5863 if (pinctrl_request_gpio(chip->base + gpio))
5864 return -ENODEV;
5865
5866 raw_spin_lock_irqsave(&a7gc->lock, flags);
5867
5868 /*
5869 * default status:
5870 * set direction as input and mask irq
5871 */
5872 __atlas7_gpio_set_input(a7gc, gpio);
5873 __atlas7_gpio_irq_mask(a7gc, gpio);
5874
5875 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5876
5877 return 0;
5878 }
5879
5880 static void atlas7_gpio_free(struct gpio_chip *chip,
5881 unsigned int gpio)
5882 {
5883 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5884 unsigned long flags;
5885
5886 raw_spin_lock_irqsave(&a7gc->lock, flags);
5887
5888 __atlas7_gpio_irq_mask(a7gc, gpio);
5889 __atlas7_gpio_set_input(a7gc, gpio);
5890
5891 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5892
5893 pinctrl_free_gpio(chip->base + gpio);
5894 }
5895
5896 static int atlas7_gpio_direction_input(struct gpio_chip *chip,
5897 unsigned int gpio)
5898 {
5899 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5900 unsigned long flags;
5901
5902 raw_spin_lock_irqsave(&a7gc->lock, flags);
5903
5904 __atlas7_gpio_set_input(a7gc, gpio);
5905
5906 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5907
5908 return 0;
5909 }
5910
5911 static void __atlas7_gpio_set_output(struct atlas7_gpio_chip *a7gc,
5912 unsigned int gpio, int value)
5913 {
5914 struct atlas7_gpio_bank *bank;
5915 void __iomem *ctrl_reg;
5916 u32 out_ctrl, pin_in_bank;
5917
5918 bank = atlas7_gpio_to_bank(a7gc, gpio);
5919 pin_in_bank = gpio - bank->gpio_offset;
5920 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5921
5922 out_ctrl = readl(ctrl_reg);
5923 if (value)
5924 out_ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
5925 else
5926 out_ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
5927
5928 out_ctrl &= ~ATLAS7_GPIO_CTL_INTR_EN_MASK;
5929 out_ctrl |= ATLAS7_GPIO_CTL_OUT_EN_MASK;
5930 writel(out_ctrl, ctrl_reg);
5931 }
5932
5933 static int atlas7_gpio_direction_output(struct gpio_chip *chip,
5934 unsigned int gpio, int value)
5935 {
5936 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5937 unsigned long flags;
5938
5939 raw_spin_lock_irqsave(&a7gc->lock, flags);
5940
5941 __atlas7_gpio_set_output(a7gc, gpio, value);
5942
5943 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5944
5945 return 0;
5946 }
5947
5948 static int atlas7_gpio_get_value(struct gpio_chip *chip,
5949 unsigned int gpio)
5950 {
5951 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5952 struct atlas7_gpio_bank *bank;
5953 u32 val, pin_in_bank;
5954 unsigned long flags;
5955
5956 bank = atlas7_gpio_to_bank(a7gc, gpio);
5957 pin_in_bank = gpio - bank->gpio_offset;
5958
5959 raw_spin_lock_irqsave(&a7gc->lock, flags);
5960
5961 val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
5962
5963 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5964
5965 return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK);
5966 }
5967
5968 static void atlas7_gpio_set_value(struct gpio_chip *chip,
5969 unsigned int gpio, int value)
5970 {
5971 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5972 struct atlas7_gpio_bank *bank;
5973 void __iomem *ctrl_reg;
5974 u32 ctrl, pin_in_bank;
5975 unsigned long flags;
5976
5977 bank = atlas7_gpio_to_bank(a7gc, gpio);
5978 pin_in_bank = gpio - bank->gpio_offset;
5979 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5980
5981 raw_spin_lock_irqsave(&a7gc->lock, flags);
5982
5983 ctrl = readl(ctrl_reg);
5984 if (value)
5985 ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
5986 else
5987 ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
5988 writel(ctrl, ctrl_reg);
5989
5990 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5991 }
5992
5993 static const struct of_device_id atlas7_gpio_ids[] = {
5994 { .compatible = "sirf,atlas7-gpio", },
5995 {},
5996 };
5997
5998 static int atlas7_gpio_probe(struct platform_device *pdev)
5999 {
6000 struct device_node *np = pdev->dev.of_node;
6001 struct atlas7_gpio_chip *a7gc;
6002 struct gpio_chip *chip;
6003 u32 nbank;
6004 int ret, idx;
6005
6006 ret = of_property_read_u32(np, "gpio-banks", &nbank);
6007 if (ret) {
6008 dev_err(&pdev->dev,
6009 "Could not find GPIO bank info,ret=%d!\n",
6010 ret);
6011 return ret;
6012 }
6013
6014 /* retrieve gpio descriptor data */
6015 a7gc = devm_kzalloc(&pdev->dev, sizeof(*a7gc) +
6016 sizeof(struct atlas7_gpio_bank) * nbank, GFP_KERNEL);
6017 if (!a7gc)
6018 return -ENOMEM;
6019
6020 /* Get Gpio clk */
6021 a7gc->clk = of_clk_get(np, 0);
6022 if (!IS_ERR(a7gc->clk)) {
6023 ret = clk_prepare_enable(a7gc->clk);
6024 if (ret) {
6025 dev_err(&pdev->dev,
6026 "Could not enable clock!\n");
6027 return ret;
6028 }
6029 }
6030
6031 /* Get Gpio Registers */
6032 a7gc->reg = of_iomap(np, 0);
6033 if (!a7gc->reg) {
6034 dev_err(&pdev->dev, "Could not map GPIO Registers!\n");
6035 return -ENOMEM;
6036 }
6037
6038 a7gc->nbank = nbank;
6039 raw_spin_lock_init(&a7gc->lock);
6040
6041 /* Setup GPIO Chip */
6042 chip = &a7gc->chip;
6043 chip->request = atlas7_gpio_request;
6044 chip->free = atlas7_gpio_free;
6045 chip->direction_input = atlas7_gpio_direction_input;
6046 chip->get = atlas7_gpio_get_value;
6047 chip->direction_output = atlas7_gpio_direction_output;
6048 chip->set = atlas7_gpio_set_value;
6049 chip->base = -1;
6050 /* Each chip can support 32 pins at one bank */
6051 chip->ngpio = NGPIO_OF_BANK * nbank;
6052 chip->label = kstrdup(np->name, GFP_KERNEL);
6053 chip->of_node = np;
6054 chip->of_gpio_n_cells = 2;
6055 chip->parent = &pdev->dev;
6056
6057 /* Add gpio chip to system */
6058 ret = gpiochip_add_data(chip, a7gc);
6059 if (ret) {
6060 dev_err(&pdev->dev,
6061 "%s: error in probe function with status %d\n",
6062 np->name, ret);
6063 goto failed;
6064 }
6065
6066 /* Add gpio chip to irq subsystem */
6067 ret = gpiochip_irqchip_add(chip, &atlas7_gpio_irq_chip,
6068 0, handle_level_irq, IRQ_TYPE_NONE);
6069 if (ret) {
6070 dev_err(&pdev->dev,
6071 "could not connect irqchip to gpiochip\n");
6072 goto failed;
6073 }
6074
6075 for (idx = 0; idx < nbank; idx++) {
6076 struct atlas7_gpio_bank *bank;
6077
6078 bank = &a7gc->banks[idx];
6079 /* Set ctrl registers' base of this bank */
6080 bank->base = ATLAS7_GPIO_BASE(a7gc, idx);
6081 bank->gpio_offset = idx * NGPIO_OF_BANK;
6082
6083 /* Get interrupt number from DTS */
6084 ret = of_irq_get(np, idx);
6085 if (ret <= 0) {
6086 dev_err(&pdev->dev,
6087 "Unable to find IRQ number. ret=%d\n", ret);
6088 if (!ret)
6089 ret = -ENXIO;
6090 goto failed;
6091 }
6092 bank->irq = ret;
6093
6094 gpiochip_set_chained_irqchip(chip, &atlas7_gpio_irq_chip,
6095 bank->irq, atlas7_gpio_handle_irq);
6096 }
6097
6098 platform_set_drvdata(pdev, a7gc);
6099 dev_info(&pdev->dev, "add to system.\n");
6100 return 0;
6101 failed:
6102 return ret;
6103 }
6104
6105 #ifdef CONFIG_PM_SLEEP
6106 static int atlas7_gpio_suspend_noirq(struct device *dev)
6107 {
6108 struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
6109 struct atlas7_gpio_bank *bank;
6110 void __iomem *ctrl_reg;
6111 u32 idx, pin;
6112
6113 for (idx = 0; idx < a7gc->nbank; idx++) {
6114 bank = &a7gc->banks[idx];
6115 for (pin = 0; pin < bank->ngpio; pin++) {
6116 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
6117 bank->sleep_data[pin] = readl(ctrl_reg);
6118 }
6119 }
6120
6121 return 0;
6122 }
6123
6124 static int atlas7_gpio_resume_noirq(struct device *dev)
6125 {
6126 struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
6127 struct atlas7_gpio_bank *bank;
6128 void __iomem *ctrl_reg;
6129 u32 idx, pin;
6130
6131 for (idx = 0; idx < a7gc->nbank; idx++) {
6132 bank = &a7gc->banks[idx];
6133 for (pin = 0; pin < bank->ngpio; pin++) {
6134 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
6135 writel(bank->sleep_data[pin], ctrl_reg);
6136 }
6137 }
6138
6139 return 0;
6140 }
6141
6142 static const struct dev_pm_ops atlas7_gpio_pm_ops = {
6143 .suspend_noirq = atlas7_gpio_suspend_noirq,
6144 .resume_noirq = atlas7_gpio_resume_noirq,
6145 .freeze_noirq = atlas7_gpio_suspend_noirq,
6146 .restore_noirq = atlas7_gpio_resume_noirq,
6147 };
6148 #endif
6149
6150 static struct platform_driver atlas7_gpio_driver = {
6151 .driver = {
6152 .name = "atlas7-gpio",
6153 .of_match_table = atlas7_gpio_ids,
6154 #ifdef CONFIG_PM_SLEEP
6155 .pm = &atlas7_gpio_pm_ops,
6156 #endif
6157 },
6158 .probe = atlas7_gpio_probe,
6159 };
6160
6161 static int __init atlas7_gpio_init(void)
6162 {
6163 return platform_driver_register(&atlas7_gpio_driver);
6164 }
6165 subsys_initcall(atlas7_gpio_init);
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