drivers/pinctrl/spear/pinctrl-plgpio.c

   1 /*
   2  * SPEAr platform PLGPIO driver
   3  *
   4  * Copyright (C) 2012 ST Microelectronics
   5  * Viresh Kumar <viresh.kumar@linaro.org>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/err.h>
  14 #include <linux/gpio.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17 #include <linux/irqdomain.h>
  18 #include <linux/irqchip/chained_irq.h>
  19 #include <linux/module.h>
  20 #include <linux/pinctrl/consumer.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm.h>
  23 #include <linux/spinlock.h>
  24
  25 #define MAX_GPIO_PER_REG                32
  26 #define PIN_OFFSET(pin)                 (pin % MAX_GPIO_PER_REG)
  27 #define REG_OFFSET(base, reg, pin)      (base + reg + (pin / MAX_GPIO_PER_REG) \
  28                                                         * sizeof(int *))
  29
  30 /*
  31  * plgpio pins in all machines are not one to one mapped, bitwise with registers
  32  * bits. These set of macros define register masks for which below functions
  33  * (pin_to_offset and offset_to_pin) are required to be called.
  34  */
  35 #define PTO_ENB_REG             0x001
  36 #define PTO_WDATA_REG           0x002
  37 #define PTO_DIR_REG             0x004
  38 #define PTO_IE_REG              0x008
  39 #define PTO_RDATA_REG           0x010
  40 #define PTO_MIS_REG             0x020
  41
  42 struct plgpio_regs {
  43         u32 enb;                /* enable register */
  44         u32 wdata;              /* write data register */
  45         u32 dir;                /* direction set register */
  46         u32 rdata;              /* read data register */
  47         u32 ie;                 /* interrupt enable register */
  48         u32 mis;                /* mask interrupt status register */
  49         u32 eit;                /* edge interrupt type */
  50 };
  51
  52 /*
  53  * struct plgpio: plgpio driver specific structure
  54  *
  55  * lock: lock for guarding gpio registers
  56  * base: base address of plgpio block
  57  * irq_base: irq number of plgpio0
  58  * chip: gpio framework specific chip information structure
  59  * p2o: function ptr for pin to offset conversion. This is required only for
  60  *      machines where mapping b/w pin and offset is not 1-to-1.
  61  * o2p: function ptr for offset to pin conversion. This is required only for
  62  *      machines where mapping b/w pin and offset is not 1-to-1.
  63  * p2o_regs: mask of registers for which p2o and o2p are applicable
  64  * regs: register offsets
  65  * csave_regs: context save registers for standby/sleep/hibernate cases
  66  */
  67 struct plgpio {
  68         spinlock_t              lock;
  69         void __iomem            *base;
  70         struct clk              *clk;
  71         unsigned                irq_base;
  72         struct irq_domain       *irq_domain;
  73         struct gpio_chip        chip;
  74         int                     (*p2o)(int pin);        /* pin_to_offset */
  75         int                     (*o2p)(int offset);     /* offset_to_pin */
  76         u32                     p2o_regs;
  77         struct plgpio_regs      regs;
  78 #ifdef CONFIG_PM_SLEEP
  79         struct plgpio_regs      *csave_regs;
  80 #endif
  81 };
  82
  83 /* register manipulation inline functions */
  84 static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg)
  85 {
  86         u32 offset = PIN_OFFSET(pin);
  87         void __iomem *reg_off = REG_OFFSET(base, reg, pin);
  88         u32 val = readl_relaxed(reg_off);
  89
  90         return !!(val & (1 << offset));
  91 }
  92
  93 static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg)
  94 {
  95         u32 offset = PIN_OFFSET(pin);
  96         void __iomem *reg_off = REG_OFFSET(base, reg, pin);
  97         u32 val = readl_relaxed(reg_off);
  98
  99         writel_relaxed(val | (1 << offset), reg_off);
 100 }
 101
 102 static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg)
 103 {
 104         u32 offset = PIN_OFFSET(pin);
 105         void __iomem *reg_off = REG_OFFSET(base, reg, pin);
 106         u32 val = readl_relaxed(reg_off);
 107
 108         writel_relaxed(val & ~(1 << offset), reg_off);
 109 }
 110
 111 /* gpio framework specific routines */
 112 static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset)
 113 {
 114         struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
 115         unsigned long flags;
 116
 117         /* get correct offset for "offset" pin */
 118         if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) {
 119                 offset = plgpio->p2o(offset);
 120                 if (offset == -1)
 121                         return -EINVAL;
 122         }
 123
 124         spin_lock_irqsave(&plgpio->lock, flags);
 125         plgpio_reg_set(plgpio->base, offset, plgpio->regs.dir);
 126         spin_unlock_irqrestore(&plgpio->lock, flags);
 127
 128         return 0;
 129 }
 130
 131 static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset,
 132                 int value)
 133 {
 134         struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
 135         unsigned long flags;
 136         unsigned dir_offset = offset, wdata_offset = offset, tmp;
 137
 138         /* get correct offset for "offset" pin */
 139         if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) {
 140                 tmp = plgpio->p2o(offset);
 141                 if (tmp == -1)
 142                         return -EINVAL;
 143
 144                 if (plgpio->p2o_regs & PTO_DIR_REG)
 145                         dir_offset = tmp;
 146                 if (plgpio->p2o_regs & PTO_WDATA_REG)
 147                         wdata_offset = tmp;
 148         }
 149
 150         spin_lock_irqsave(&plgpio->lock, flags);
 151         if (value)
 152                 plgpio_reg_set(plgpio->base, wdata_offset,
 153                                 plgpio->regs.wdata);
 154         else
 155                 plgpio_reg_reset(plgpio->base, wdata_offset,
 156                                 plgpio->regs.wdata);
 157
 158         plgpio_reg_reset(plgpio->base, dir_offset, plgpio->regs.dir);
 159         spin_unlock_irqrestore(&plgpio->lock, flags);
 160
 161         return 0;
 162 }
 163
 164 static int plgpio_get_value(struct gpio_chip *chip, unsigned offset)
 165 {
 166         struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
 167
 168         if (offset >= chip->ngpio)
 169                 return -EINVAL;
 170
 171         /* get correct offset for "offset" pin */
 172         if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) {
 173                 offset = plgpio->p2o(offset);
 174                 if (offset == -1)
 175                         return -EINVAL;
 176         }
 177
 178         return is_plgpio_set(plgpio->base, offset, plgpio->regs.rdata);
 179 }
 180
 181 static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
 182 {
 183         struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
 184
 185         if (offset >= chip->ngpio)
 186                 return;
 187
 188         /* get correct offset for "offset" pin */
 189         if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) {
 190                 offset = plgpio->p2o(offset);
 191                 if (offset == -1)
 192                         return;
 193         }
 194
 195         if (value)
 196                 plgpio_reg_set(plgpio->base, offset, plgpio->regs.wdata);
 197         else
 198                 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.wdata);
 199 }
 200
 201 static int plgpio_request(struct gpio_chip *chip, unsigned offset)
 202 {
 203         struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
 204         int gpio = chip->base + offset;
 205         unsigned long flags;
 206         int ret = 0;
 207
 208         if (offset >= chip->ngpio)
 209                 return -EINVAL;
 210
 211         ret = pinctrl_request_gpio(gpio);
 212         if (ret)
 213                 return ret;
 214
 215         if (!IS_ERR(plgpio->clk)) {
 216                 ret = clk_enable(plgpio->clk);
 217                 if (ret)
 218                         goto err0;
 219         }
 220
 221         if (plgpio->regs.enb == -1)
 222                 return 0;
 223
 224         /*
 225          * put gpio in IN mode before enabling it. This make enabling gpio safe
 226          */
 227         ret = plgpio_direction_input(chip, offset);
 228         if (ret)
 229                 goto err1;
 230
 231         /* get correct offset for "offset" pin */
 232         if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
 233                 offset = plgpio->p2o(offset);
 234                 if (offset == -1) {
 235                         ret = -EINVAL;
 236                         goto err1;
 237                 }
 238         }
 239
 240         spin_lock_irqsave(&plgpio->lock, flags);
 241         plgpio_reg_set(plgpio->base, offset, plgpio->regs.enb);
 242         spin_unlock_irqrestore(&plgpio->lock, flags);
 243         return 0;
 244
 245 err1:
 246         if (!IS_ERR(plgpio->clk))
 247                 clk_disable(plgpio->clk);
 248 err0:
 249         pinctrl_free_gpio(gpio);
 250         return ret;
 251 }
 252
 253 static void plgpio_free(struct gpio_chip *chip, unsigned offset)
 254 {
 255         struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
 256         int gpio = chip->base + offset;
 257         unsigned long flags;
 258
 259         if (offset >= chip->ngpio)
 260                 return;
 261
 262         if (plgpio->regs.enb == -1)
 263                 goto disable_clk;
 264
 265         /* get correct offset for "offset" pin */
 266         if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
 267                 offset = plgpio->p2o(offset);
 268                 if (offset == -1)
 269                         return;
 270         }
 271
 272         spin_lock_irqsave(&plgpio->lock, flags);
 273         plgpio_reg_reset(plgpio->base, offset, plgpio->regs.enb);
 274         spin_unlock_irqrestore(&plgpio->lock, flags);
 275
 276 disable_clk:
 277         if (!IS_ERR(plgpio->clk))
 278                 clk_disable(plgpio->clk);
 279
 280         pinctrl_free_gpio(gpio);
 281 }
 282
 283 static int plgpio_to_irq(struct gpio_chip *chip, unsigned offset)
 284 {
 285         struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
 286
 287         if (IS_ERR_VALUE(plgpio->irq_base))
 288                 return -EINVAL;
 289
 290         return irq_find_mapping(plgpio->irq_domain, offset);
 291 }
 292
 293 /* PLGPIO IRQ */
 294 static void plgpio_irq_disable(struct irq_data *d)
 295 {
 296         struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
 297         int offset = d->irq - plgpio->irq_base;
 298         unsigned long flags;
 299
 300         /* get correct offset for "offset" pin */
 301         if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
 302                 offset = plgpio->p2o(offset);
 303                 if (offset == -1)
 304                         return;
 305         }
 306
 307         spin_lock_irqsave(&plgpio->lock, flags);
 308         plgpio_reg_set(plgpio->base, offset, plgpio->regs.ie);
 309         spin_unlock_irqrestore(&plgpio->lock, flags);
 310 }
 311
 312 static void plgpio_irq_enable(struct irq_data *d)
 313 {
 314         struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
 315         int offset = d->irq - plgpio->irq_base;
 316         unsigned long flags;
 317
 318         /* get correct offset for "offset" pin */
 319         if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
 320                 offset = plgpio->p2o(offset);
 321                 if (offset == -1)
 322                         return;
 323         }
 324
 325         spin_lock_irqsave(&plgpio->lock, flags);
 326         plgpio_reg_reset(plgpio->base, offset, plgpio->regs.ie);
 327         spin_unlock_irqrestore(&plgpio->lock, flags);
 328 }
 329
 330 static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
 331 {
 332         struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
 333         int offset = d->irq - plgpio->irq_base;
 334         void __iomem *reg_off;
 335         unsigned int supported_type = 0, val;
 336
 337         if (offset >= plgpio->chip.ngpio)
 338                 return -EINVAL;
 339
 340         if (plgpio->regs.eit == -1)
 341                 supported_type = IRQ_TYPE_LEVEL_HIGH;
 342         else
 343                 supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 344
 345         if (!(trigger & supported_type))
 346                 return -EINVAL;
 347
 348         if (plgpio->regs.eit == -1)
 349                 return 0;
 350
 351         reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset);
 352         val = readl_relaxed(reg_off);
 353
 354         offset = PIN_OFFSET(offset);
 355         if (trigger & IRQ_TYPE_EDGE_RISING)
 356                 writel_relaxed(val | (1 << offset), reg_off);
 357         else
 358                 writel_relaxed(val & ~(1 << offset), reg_off);
 359
 360         return 0;
 361 }
 362
 363 static struct irq_chip plgpio_irqchip = {
 364         .name           = "PLGPIO",
 365         .irq_enable     = plgpio_irq_enable,
 366         .irq_disable    = plgpio_irq_disable,
 367         .irq_set_type   = plgpio_irq_set_type,
 368 };
 369
 370 static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
 371 {
 372         struct plgpio *plgpio = irq_get_handler_data(irq);
 373         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 374         int regs_count, count, pin, offset, i = 0;
 375         unsigned long pending;
 376
 377         count = plgpio->chip.ngpio;
 378         regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG);
 379
 380         chained_irq_enter(irqchip, desc);
 381         /* check all plgpio MIS registers for a possible interrupt */
 382         for (; i < regs_count; i++) {
 383                 pending = readl_relaxed(plgpio->base + plgpio->regs.mis +
 384                                 i * sizeof(int *));
 385                 if (!pending)
 386                         continue;
 387
 388                 /* clear interrupts */
 389                 writel_relaxed(~pending, plgpio->base + plgpio->regs.mis +
 390                                 i * sizeof(int *));
 391                 /*
 392                  * clear extra bits in last register having gpios < MAX/REG
 393                  * ex: Suppose there are max 102 plgpios. then last register
 394                  * must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits
 395                  * so, we must not take other 28 bits into consideration for
 396                  * checking interrupt. so clear those bits.
 397                  */
 398                 count = count - i * MAX_GPIO_PER_REG;
 399                 if (count < MAX_GPIO_PER_REG)
 400                         pending &= (1 << count) - 1;
 401
 402                 for_each_set_bit(offset, &pending, MAX_GPIO_PER_REG) {
 403                         /* get correct pin for "offset" */
 404                         if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) {
 405                                 pin = plgpio->o2p(offset);
 406                                 if (pin == -1)
 407                                         continue;
 408                         } else
 409                                 pin = offset;
 410
 411                         /* get correct irq line number */
 412                         pin = i * MAX_GPIO_PER_REG + pin;
 413                         generic_handle_irq(plgpio_to_irq(&plgpio->chip, pin));
 414                 }
 415         }
 416         chained_irq_exit(irqchip, desc);
 417 }
 418
 419 /*
 420  * pin to offset and offset to pin converter functions
 421  *
 422  * In spear310 there is inconsistency among bit positions in plgpio regiseters,
 423  * for different plgpio pins. For example: for pin 27, bit offset is 23, pin
 424  * 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1
 425  */
 426 static int spear310_p2o(int pin)
 427 {
 428         int offset = pin;
 429
 430         if (pin <= 27)
 431                 offset += 4;
 432         else if (pin <= 33)
 433                 offset = -1;
 434         else if (pin <= 97)
 435                 offset -= 2;
 436         else if (pin <= 101)
 437                 offset = 101 - pin;
 438         else
 439                 offset = -1;
 440
 441         return offset;
 442 }
 443
 444 static int spear310_o2p(int offset)
 445 {
 446         if (offset <= 3)
 447                 return 101 - offset;
 448         else if (offset <= 31)
 449                 return offset - 4;
 450         else
 451                 return offset + 2;
 452 }
 453
 454 static int plgpio_probe_dt(struct platform_device *pdev, struct plgpio *plgpio)
 455 {
 456         struct device_node *np = pdev->dev.of_node;
 457         int ret = -EINVAL;
 458         u32 val;
 459
 460         if (of_machine_is_compatible("st,spear310")) {
 461                 plgpio->p2o = spear310_p2o;
 462                 plgpio->o2p = spear310_o2p;
 463                 plgpio->p2o_regs = PTO_WDATA_REG | PTO_DIR_REG | PTO_IE_REG |
 464                         PTO_RDATA_REG | PTO_MIS_REG;
 465         }
 466
 467         if (!of_property_read_u32(np, "st-plgpio,ngpio", &val)) {
 468                 plgpio->chip.ngpio = val;
 469         } else {
 470                 dev_err(&pdev->dev, "DT: Invalid ngpio field\n");
 471                 goto end;
 472         }
 473
 474         if (!of_property_read_u32(np, "st-plgpio,enb-reg", &val))
 475                 plgpio->regs.enb = val;
 476         else
 477                 plgpio->regs.enb = -1;
 478
 479         if (!of_property_read_u32(np, "st-plgpio,wdata-reg", &val)) {
 480                 plgpio->regs.wdata = val;
 481         } else {
 482                 dev_err(&pdev->dev, "DT: Invalid wdata reg\n");
 483                 goto end;
 484         }
 485
 486         if (!of_property_read_u32(np, "st-plgpio,dir-reg", &val)) {
 487                 plgpio->regs.dir = val;
 488         } else {
 489                 dev_err(&pdev->dev, "DT: Invalid dir reg\n");
 490                 goto end;
 491         }
 492
 493         if (!of_property_read_u32(np, "st-plgpio,ie-reg", &val)) {
 494                 plgpio->regs.ie = val;
 495         } else {
 496                 dev_err(&pdev->dev, "DT: Invalid ie reg\n");
 497                 goto end;
 498         }
 499
 500         if (!of_property_read_u32(np, "st-plgpio,rdata-reg", &val)) {
 501                 plgpio->regs.rdata = val;
 502         } else {
 503                 dev_err(&pdev->dev, "DT: Invalid rdata reg\n");
 504                 goto end;
 505         }
 506
 507         if (!of_property_read_u32(np, "st-plgpio,mis-reg", &val)) {
 508                 plgpio->regs.mis = val;
 509         } else {
 510                 dev_err(&pdev->dev, "DT: Invalid mis reg\n");
 511                 goto end;
 512         }
 513
 514         if (!of_property_read_u32(np, "st-plgpio,eit-reg", &val))
 515                 plgpio->regs.eit = val;
 516         else
 517                 plgpio->regs.eit = -1;
 518
 519         return 0;
 520
 521 end:
 522         return ret;
 523 }
 524 static int plgpio_probe(struct platform_device *pdev)
 525 {
 526         struct device_node *np = pdev->dev.of_node;
 527         struct plgpio *plgpio;
 528         struct resource *res;
 529         int ret, irq, i;
 530
 531         plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
 532         if (!plgpio) {
 533                 dev_err(&pdev->dev, "memory allocation fail\n");
 534                 return -ENOMEM;
 535         }
 536
 537         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 538         plgpio->base = devm_ioremap_resource(&pdev->dev, res);
 539         if (IS_ERR(plgpio->base))
 540                 return PTR_ERR(plgpio->base);
 541
 542         ret = plgpio_probe_dt(pdev, plgpio);
 543         if (ret) {
 544                 dev_err(&pdev->dev, "DT probe failed\n");
 545                 return ret;
 546         }
 547
 548         plgpio->clk = devm_clk_get(&pdev->dev, NULL);
 549         if (IS_ERR(plgpio->clk))
 550                 dev_warn(&pdev->dev, "clk_get() failed, work without it\n");
 551
 552 #ifdef CONFIG_PM_SLEEP
 553         plgpio->csave_regs = devm_kzalloc(&pdev->dev,
 554                         sizeof(*plgpio->csave_regs) *
 555                         DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG),
 556                         GFP_KERNEL);
 557         if (!plgpio->csave_regs) {
 558                 dev_err(&pdev->dev, "csave registers memory allocation fail\n");
 559                 return -ENOMEM;
 560         }
 561 #endif
 562
 563         platform_set_drvdata(pdev, plgpio);
 564         spin_lock_init(&plgpio->lock);
 565
 566         plgpio->irq_base = -1;
 567         plgpio->chip.base = -1;
 568         plgpio->chip.request = plgpio_request;
 569         plgpio->chip.free = plgpio_free;
 570         plgpio->chip.direction_input = plgpio_direction_input;
 571         plgpio->chip.direction_output = plgpio_direction_output;
 572         plgpio->chip.get = plgpio_get_value;
 573         plgpio->chip.set = plgpio_set_value;
 574         plgpio->chip.to_irq = plgpio_to_irq;
 575         plgpio->chip.label = dev_name(&pdev->dev);
 576         plgpio->chip.dev = &pdev->dev;
 577         plgpio->chip.owner = THIS_MODULE;
 578
 579         if (!IS_ERR(plgpio->clk)) {
 580                 ret = clk_prepare(plgpio->clk);
 581                 if (ret) {
 582                         dev_err(&pdev->dev, "clk prepare failed\n");
 583                         return ret;
 584                 }
 585         }
 586
 587         ret = gpiochip_add(&plgpio->chip);
 588         if (ret) {
 589                 dev_err(&pdev->dev, "unable to add gpio chip\n");
 590                 goto unprepare_clk;
 591         }
 592
 593         irq = platform_get_irq(pdev, 0);
 594         if (irq < 0) {
 595                 dev_info(&pdev->dev, "irqs not supported\n");
 596                 return 0;
 597         }
 598
 599         plgpio->irq_base = irq_alloc_descs(-1, 0, plgpio->chip.ngpio, 0);
 600         if (IS_ERR_VALUE(plgpio->irq_base)) {
 601                 /* we would not support irq for gpio */
 602                 dev_warn(&pdev->dev, "couldn't allocate irq base\n");
 603                 return 0;
 604         }
 605
 606         plgpio->irq_domain = irq_domain_add_legacy(np, plgpio->chip.ngpio,
 607                         plgpio->irq_base, 0, &irq_domain_simple_ops, NULL);
 608         if (WARN_ON(!plgpio->irq_domain)) {
 609                 dev_err(&pdev->dev, "irq domain init failed\n");
 610                 irq_free_descs(plgpio->irq_base, plgpio->chip.ngpio);
 611                 ret = -ENXIO;
 612                 goto remove_gpiochip;
 613         }
 614
 615         irq_set_chained_handler(irq, plgpio_irq_handler);
 616         for (i = 0; i < plgpio->chip.ngpio; i++) {
 617                 irq_set_chip_and_handler(i + plgpio->irq_base, &plgpio_irqchip,
 618                                 handle_simple_irq);
 619                 set_irq_flags(i + plgpio->irq_base, IRQF_VALID);
 620                 irq_set_chip_data(i + plgpio->irq_base, plgpio);
 621         }
 622
 623         irq_set_handler_data(irq, plgpio);
 624         dev_info(&pdev->dev, "PLGPIO registered with IRQs\n");
 625
 626         return 0;
 627
 628 remove_gpiochip:
 629         dev_info(&pdev->dev, "Remove gpiochip\n");
 630         if (gpiochip_remove(&plgpio->chip))
 631                 dev_err(&pdev->dev, "unable to remove gpiochip\n");
 632 unprepare_clk:
 633         if (!IS_ERR(plgpio->clk))
 634                 clk_unprepare(plgpio->clk);
 635
 636         return ret;
 637 }
 638
 639 #ifdef CONFIG_PM_SLEEP
 640 static int plgpio_suspend(struct device *dev)
 641 {
 642         struct plgpio *plgpio = dev_get_drvdata(dev);
 643         int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
 644         void __iomem *off;
 645
 646         for (i = 0; i < reg_count; i++) {
 647                 off = plgpio->base + i * sizeof(int *);
 648
 649                 if (plgpio->regs.enb != -1)
 650                         plgpio->csave_regs[i].enb =
 651                                 readl_relaxed(plgpio->regs.enb + off);
 652                 if (plgpio->regs.eit != -1)
 653                         plgpio->csave_regs[i].eit =
 654                                 readl_relaxed(plgpio->regs.eit + off);
 655                 plgpio->csave_regs[i].wdata = readl_relaxed(plgpio->regs.wdata +
 656                                 off);
 657                 plgpio->csave_regs[i].dir = readl_relaxed(plgpio->regs.dir +
 658                                 off);
 659                 plgpio->csave_regs[i].ie = readl_relaxed(plgpio->regs.ie + off);
 660         }
 661
 662         return 0;
 663 }
 664
 665 /*
 666  * This is used to correct the values in end registers. End registers contain
 667  * extra bits that might be used for other purpose in platform. So, we shouldn't
 668  * overwrite these bits. This macro, reads given register again, preserves other
 669  * bit values (non-plgpio bits), and retain captured value (plgpio bits).
 670  */
 671 #define plgpio_prepare_reg(__reg, _off, _mask, _tmp)            \
 672 {                                                               \
 673         _tmp = readl_relaxed(plgpio->regs.__reg + _off);                \
 674         _tmp &= ~_mask;                                         \
 675         plgpio->csave_regs[i].__reg =                           \
 676                 _tmp | (plgpio->csave_regs[i].__reg & _mask);   \
 677 }
 678
 679 static int plgpio_resume(struct device *dev)
 680 {
 681         struct plgpio *plgpio = dev_get_drvdata(dev);
 682         int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
 683         void __iomem *off;
 684         u32 mask, tmp;
 685
 686         for (i = 0; i < reg_count; i++) {
 687                 off = plgpio->base + i * sizeof(int *);
 688
 689                 if (i == reg_count - 1) {
 690                         mask = (1 << (plgpio->chip.ngpio - i *
 691                                                 MAX_GPIO_PER_REG)) - 1;
 692
 693                         if (plgpio->regs.enb != -1)
 694                                 plgpio_prepare_reg(enb, off, mask, tmp);
 695
 696                         if (plgpio->regs.eit != -1)
 697                                 plgpio_prepare_reg(eit, off, mask, tmp);
 698
 699                         plgpio_prepare_reg(wdata, off, mask, tmp);
 700                         plgpio_prepare_reg(dir, off, mask, tmp);
 701                         plgpio_prepare_reg(ie, off, mask, tmp);
 702                 }
 703
 704                 writel_relaxed(plgpio->csave_regs[i].wdata, plgpio->regs.wdata +
 705                                 off);
 706                 writel_relaxed(plgpio->csave_regs[i].dir, plgpio->regs.dir +
 707                                 off);
 708
 709                 if (plgpio->regs.eit != -1)
 710                         writel_relaxed(plgpio->csave_regs[i].eit,
 711                                         plgpio->regs.eit + off);
 712
 713                 writel_relaxed(plgpio->csave_regs[i].ie, plgpio->regs.ie + off);
 714
 715                 if (plgpio->regs.enb != -1)
 716                         writel_relaxed(plgpio->csave_regs[i].enb,
 717                                         plgpio->regs.enb + off);
 718         }
 719
 720         return 0;
 721 }
 722 #endif
 723
 724 static SIMPLE_DEV_PM_OPS(plgpio_dev_pm_ops, plgpio_suspend, plgpio_resume);
 725
 726 static const struct of_device_id plgpio_of_match[] = {
 727         { .compatible = "st,spear-plgpio" },
 728         {}
 729 };
 730 MODULE_DEVICE_TABLE(of, plgpio_of_match);
 731
 732 static struct platform_driver plgpio_driver = {
 733         .probe = plgpio_probe,
 734         .driver = {
 735                 .owner = THIS_MODULE,
 736                 .name = "spear-plgpio",
 737                 .pm = &plgpio_dev_pm_ops,
 738                 .of_match_table = plgpio_of_match,
 739         },
 740 };
 741
 742 static int __init plgpio_init(void)
 743 {
 744         return platform_driver_register(&plgpio_driver);
 745 }
 746 subsys_initcall(plgpio_init);
 747
 748 MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
 749 MODULE_DESCRIPTION("STMicroelectronics SPEAr PLGPIO driver");
 750 MODULE_LICENSE("GPL");