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Merge tag 'devicetree-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh...
[mirror_ubuntu-jammy-kernel.git] / drivers / pinctrl / stm32 / pinctrl-stm32.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 *
7 * Heavily based on Mediatek's pinctrl driver
8 */
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/hwspinlock.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/of_irq.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/platform_device.h>
27 #include <linux/regmap.h>
28 #include <linux/reset.h>
29 #include <linux/slab.h>
30
31 #include "../core.h"
32 #include "../pinconf.h"
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-stm32.h"
35
36 #define STM32_GPIO_MODER 0x00
37 #define STM32_GPIO_TYPER 0x04
38 #define STM32_GPIO_SPEEDR 0x08
39 #define STM32_GPIO_PUPDR 0x0c
40 #define STM32_GPIO_IDR 0x10
41 #define STM32_GPIO_ODR 0x14
42 #define STM32_GPIO_BSRR 0x18
43 #define STM32_GPIO_LCKR 0x1c
44 #define STM32_GPIO_AFRL 0x20
45 #define STM32_GPIO_AFRH 0x24
46
47 #define STM32_GPIO_PINS_PER_BANK 16
48 #define STM32_GPIO_IRQ_LINE 16
49
50 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
51
52 #define gpio_range_to_bank(chip) \
53 container_of(chip, struct stm32_gpio_bank, range)
54
55 #define HWSPINLOCK_TIMEOUT 5 /* msec */
56
57 static const char * const stm32_gpio_functions[] = {
58 "gpio", "af0", "af1",
59 "af2", "af3", "af4",
60 "af5", "af6", "af7",
61 "af8", "af9", "af10",
62 "af11", "af12", "af13",
63 "af14", "af15", "analog",
64 };
65
66 struct stm32_pinctrl_group {
67 const char *name;
68 unsigned long config;
69 unsigned pin;
70 };
71
72 struct stm32_gpio_bank {
73 void __iomem *base;
74 struct clk *clk;
75 spinlock_t lock;
76 struct gpio_chip gpio_chip;
77 struct pinctrl_gpio_range range;
78 struct fwnode_handle *fwnode;
79 struct irq_domain *domain;
80 u32 bank_nr;
81 u32 bank_ioport_nr;
82 };
83
84 struct stm32_pinctrl {
85 struct device *dev;
86 struct pinctrl_dev *pctl_dev;
87 struct pinctrl_desc pctl_desc;
88 struct stm32_pinctrl_group *groups;
89 unsigned ngroups;
90 const char **grp_names;
91 struct stm32_gpio_bank *banks;
92 unsigned nbanks;
93 const struct stm32_pinctrl_match_data *match_data;
94 struct irq_domain *domain;
95 struct regmap *regmap;
96 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
97 struct hwspinlock *hwlock;
98 struct stm32_desc_pin *pins;
99 u32 npins;
100 u32 pkg;
101 };
102
103 static inline int stm32_gpio_pin(int gpio)
104 {
105 return gpio % STM32_GPIO_PINS_PER_BANK;
106 }
107
108 static inline u32 stm32_gpio_get_mode(u32 function)
109 {
110 switch (function) {
111 case STM32_PIN_GPIO:
112 return 0;
113 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
114 return 2;
115 case STM32_PIN_ANALOG:
116 return 3;
117 }
118
119 return 0;
120 }
121
122 static inline u32 stm32_gpio_get_alt(u32 function)
123 {
124 switch (function) {
125 case STM32_PIN_GPIO:
126 return 0;
127 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
128 return function - 1;
129 case STM32_PIN_ANALOG:
130 return 0;
131 }
132
133 return 0;
134 }
135
136 /* GPIO functions */
137
138 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
139 unsigned offset, int value)
140 {
141 if (!value)
142 offset += STM32_GPIO_PINS_PER_BANK;
143
144 clk_enable(bank->clk);
145
146 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
147
148 clk_disable(bank->clk);
149 }
150
151 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
152 {
153 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
154 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
155 struct pinctrl_gpio_range *range;
156 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
157
158 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
159 if (!range) {
160 dev_err(pctl->dev, "pin %d not in range.\n", pin);
161 return -EINVAL;
162 }
163
164 return pinctrl_gpio_request(chip->base + offset);
165 }
166
167 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
168 {
169 pinctrl_gpio_free(chip->base + offset);
170 }
171
172 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
173 {
174 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
175 int ret;
176
177 clk_enable(bank->clk);
178
179 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
180
181 clk_disable(bank->clk);
182
183 return ret;
184 }
185
186 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
187 {
188 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
189
190 __stm32_gpio_set(bank, offset, value);
191 }
192
193 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
194 {
195 return pinctrl_gpio_direction_input(chip->base + offset);
196 }
197
198 static int stm32_gpio_direction_output(struct gpio_chip *chip,
199 unsigned offset, int value)
200 {
201 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
202
203 __stm32_gpio_set(bank, offset, value);
204 pinctrl_gpio_direction_output(chip->base + offset);
205
206 return 0;
207 }
208
209
210 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
211 {
212 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
213 struct irq_fwspec fwspec;
214
215 fwspec.fwnode = bank->fwnode;
216 fwspec.param_count = 2;
217 fwspec.param[0] = offset;
218 fwspec.param[1] = IRQ_TYPE_NONE;
219
220 return irq_create_fwspec_mapping(&fwspec);
221 }
222
223 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
224 {
225 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
226 int pin = stm32_gpio_pin(offset);
227 int ret;
228 u32 mode, alt;
229
230 stm32_pmx_get_mode(bank, pin, &mode, &alt);
231 if ((alt == 0) && (mode == 0))
232 ret = 1;
233 else if ((alt == 0) && (mode == 1))
234 ret = 0;
235 else
236 ret = -EINVAL;
237
238 return ret;
239 }
240
241 static const struct gpio_chip stm32_gpio_template = {
242 .request = stm32_gpio_request,
243 .free = stm32_gpio_free,
244 .get = stm32_gpio_get,
245 .set = stm32_gpio_set,
246 .direction_input = stm32_gpio_direction_input,
247 .direction_output = stm32_gpio_direction_output,
248 .to_irq = stm32_gpio_to_irq,
249 .get_direction = stm32_gpio_get_direction,
250 };
251
252 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
253 {
254 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
255 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
256 int ret;
257
258 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
259 if (ret)
260 return ret;
261
262 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
263 if (ret) {
264 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
265 irq_data->hwirq);
266 return ret;
267 }
268
269 return 0;
270 }
271
272 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
273 {
274 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
275
276 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
277 }
278
279 static struct irq_chip stm32_gpio_irq_chip = {
280 .name = "stm32gpio",
281 .irq_eoi = irq_chip_eoi_parent,
282 .irq_ack = irq_chip_ack_parent,
283 .irq_mask = irq_chip_mask_parent,
284 .irq_unmask = irq_chip_unmask_parent,
285 .irq_set_type = irq_chip_set_type_parent,
286 .irq_set_wake = irq_chip_set_wake_parent,
287 .irq_request_resources = stm32_gpio_irq_request_resources,
288 .irq_release_resources = stm32_gpio_irq_release_resources,
289 };
290
291 static int stm32_gpio_domain_translate(struct irq_domain *d,
292 struct irq_fwspec *fwspec,
293 unsigned long *hwirq,
294 unsigned int *type)
295 {
296 if ((fwspec->param_count != 2) ||
297 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
298 return -EINVAL;
299
300 *hwirq = fwspec->param[0];
301 *type = fwspec->param[1];
302 return 0;
303 }
304
305 static int stm32_gpio_domain_activate(struct irq_domain *d,
306 struct irq_data *irq_data, bool reserve)
307 {
308 struct stm32_gpio_bank *bank = d->host_data;
309 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
310
311 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
312 return 0;
313 }
314
315 static int stm32_gpio_domain_alloc(struct irq_domain *d,
316 unsigned int virq,
317 unsigned int nr_irqs, void *data)
318 {
319 struct stm32_gpio_bank *bank = d->host_data;
320 struct irq_fwspec *fwspec = data;
321 struct irq_fwspec parent_fwspec;
322 irq_hw_number_t hwirq;
323
324 hwirq = fwspec->param[0];
325 parent_fwspec.fwnode = d->parent->fwnode;
326 parent_fwspec.param_count = 2;
327 parent_fwspec.param[0] = fwspec->param[0];
328 parent_fwspec.param[1] = fwspec->param[1];
329
330 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
331 bank);
332
333 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
334 }
335
336 static const struct irq_domain_ops stm32_gpio_domain_ops = {
337 .translate = stm32_gpio_domain_translate,
338 .alloc = stm32_gpio_domain_alloc,
339 .free = irq_domain_free_irqs_common,
340 .activate = stm32_gpio_domain_activate,
341 };
342
343 /* Pinctrl functions */
344 static struct stm32_pinctrl_group *
345 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
346 {
347 int i;
348
349 for (i = 0; i < pctl->ngroups; i++) {
350 struct stm32_pinctrl_group *grp = pctl->groups + i;
351
352 if (grp->pin == pin)
353 return grp;
354 }
355
356 return NULL;
357 }
358
359 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
360 u32 pin_num, u32 fnum)
361 {
362 int i;
363
364 for (i = 0; i < pctl->npins; i++) {
365 const struct stm32_desc_pin *pin = pctl->pins + i;
366 const struct stm32_desc_function *func = pin->functions;
367
368 if (pin->pin.number != pin_num)
369 continue;
370
371 while (func && func->name) {
372 if (func->num == fnum)
373 return true;
374 func++;
375 }
376
377 break;
378 }
379
380 return false;
381 }
382
383 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
384 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
385 struct pinctrl_map **map, unsigned *reserved_maps,
386 unsigned *num_maps)
387 {
388 if (*num_maps == *reserved_maps)
389 return -ENOSPC;
390
391 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
392 (*map)[*num_maps].data.mux.group = grp->name;
393
394 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
395 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
396 fnum, pin);
397 return -EINVAL;
398 }
399
400 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
401 (*num_maps)++;
402
403 return 0;
404 }
405
406 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
407 struct device_node *node,
408 struct pinctrl_map **map,
409 unsigned *reserved_maps,
410 unsigned *num_maps)
411 {
412 struct stm32_pinctrl *pctl;
413 struct stm32_pinctrl_group *grp;
414 struct property *pins;
415 u32 pinfunc, pin, func;
416 unsigned long *configs;
417 unsigned int num_configs;
418 bool has_config = 0;
419 unsigned reserve = 0;
420 int num_pins, num_funcs, maps_per_pin, i, err = 0;
421
422 pctl = pinctrl_dev_get_drvdata(pctldev);
423
424 pins = of_find_property(node, "pinmux", NULL);
425 if (!pins) {
426 dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
427 node);
428 return -EINVAL;
429 }
430
431 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
432 &num_configs);
433 if (err)
434 return err;
435
436 if (num_configs)
437 has_config = 1;
438
439 num_pins = pins->length / sizeof(u32);
440 num_funcs = num_pins;
441 maps_per_pin = 0;
442 if (num_funcs)
443 maps_per_pin++;
444 if (has_config && num_pins >= 1)
445 maps_per_pin++;
446
447 if (!num_pins || !maps_per_pin) {
448 err = -EINVAL;
449 goto exit;
450 }
451
452 reserve = num_pins * maps_per_pin;
453
454 err = pinctrl_utils_reserve_map(pctldev, map,
455 reserved_maps, num_maps, reserve);
456 if (err)
457 goto exit;
458
459 for (i = 0; i < num_pins; i++) {
460 err = of_property_read_u32_index(node, "pinmux",
461 i, &pinfunc);
462 if (err)
463 goto exit;
464
465 pin = STM32_GET_PIN_NO(pinfunc);
466 func = STM32_GET_PIN_FUNC(pinfunc);
467
468 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
469 dev_err(pctl->dev, "invalid function.\n");
470 err = -EINVAL;
471 goto exit;
472 }
473
474 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
475 if (!grp) {
476 dev_err(pctl->dev, "unable to match pin %d to group\n",
477 pin);
478 err = -EINVAL;
479 goto exit;
480 }
481
482 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
483 reserved_maps, num_maps);
484 if (err)
485 goto exit;
486
487 if (has_config) {
488 err = pinctrl_utils_add_map_configs(pctldev, map,
489 reserved_maps, num_maps, grp->name,
490 configs, num_configs,
491 PIN_MAP_TYPE_CONFIGS_GROUP);
492 if (err)
493 goto exit;
494 }
495 }
496
497 exit:
498 kfree(configs);
499 return err;
500 }
501
502 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
503 struct device_node *np_config,
504 struct pinctrl_map **map, unsigned *num_maps)
505 {
506 struct device_node *np;
507 unsigned reserved_maps;
508 int ret;
509
510 *map = NULL;
511 *num_maps = 0;
512 reserved_maps = 0;
513
514 for_each_child_of_node(np_config, np) {
515 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
516 &reserved_maps, num_maps);
517 if (ret < 0) {
518 pinctrl_utils_free_map(pctldev, *map, *num_maps);
519 return ret;
520 }
521 }
522
523 return 0;
524 }
525
526 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
527 {
528 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
529
530 return pctl->ngroups;
531 }
532
533 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
534 unsigned group)
535 {
536 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
537
538 return pctl->groups[group].name;
539 }
540
541 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
542 unsigned group,
543 const unsigned **pins,
544 unsigned *num_pins)
545 {
546 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
547
548 *pins = (unsigned *)&pctl->groups[group].pin;
549 *num_pins = 1;
550
551 return 0;
552 }
553
554 static const struct pinctrl_ops stm32_pctrl_ops = {
555 .dt_node_to_map = stm32_pctrl_dt_node_to_map,
556 .dt_free_map = pinctrl_utils_free_map,
557 .get_groups_count = stm32_pctrl_get_groups_count,
558 .get_group_name = stm32_pctrl_get_group_name,
559 .get_group_pins = stm32_pctrl_get_group_pins,
560 };
561
562
563 /* Pinmux functions */
564
565 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
566 {
567 return ARRAY_SIZE(stm32_gpio_functions);
568 }
569
570 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
571 unsigned selector)
572 {
573 return stm32_gpio_functions[selector];
574 }
575
576 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
577 unsigned function,
578 const char * const **groups,
579 unsigned * const num_groups)
580 {
581 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
582
583 *groups = pctl->grp_names;
584 *num_groups = pctl->ngroups;
585
586 return 0;
587 }
588
589 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
590 int pin, u32 mode, u32 alt)
591 {
592 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
593 u32 val;
594 int alt_shift = (pin % 8) * 4;
595 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
596 unsigned long flags;
597 int err = 0;
598
599 clk_enable(bank->clk);
600 spin_lock_irqsave(&bank->lock, flags);
601
602 if (pctl->hwlock)
603 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
604
605 if (err) {
606 dev_err(pctl->dev, "Can't get hwspinlock\n");
607 goto unlock;
608 }
609
610 val = readl_relaxed(bank->base + alt_offset);
611 val &= ~GENMASK(alt_shift + 3, alt_shift);
612 val |= (alt << alt_shift);
613 writel_relaxed(val, bank->base + alt_offset);
614
615 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
616 val &= ~GENMASK(pin * 2 + 1, pin * 2);
617 val |= mode << (pin * 2);
618 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
619
620 if (pctl->hwlock)
621 hwspin_unlock(pctl->hwlock);
622
623 unlock:
624 spin_unlock_irqrestore(&bank->lock, flags);
625 clk_disable(bank->clk);
626
627 return err;
628 }
629
630 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
631 u32 *alt)
632 {
633 u32 val;
634 int alt_shift = (pin % 8) * 4;
635 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
636 unsigned long flags;
637
638 clk_enable(bank->clk);
639 spin_lock_irqsave(&bank->lock, flags);
640
641 val = readl_relaxed(bank->base + alt_offset);
642 val &= GENMASK(alt_shift + 3, alt_shift);
643 *alt = val >> alt_shift;
644
645 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
646 val &= GENMASK(pin * 2 + 1, pin * 2);
647 *mode = val >> (pin * 2);
648
649 spin_unlock_irqrestore(&bank->lock, flags);
650 clk_disable(bank->clk);
651 }
652
653 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
654 unsigned function,
655 unsigned group)
656 {
657 bool ret;
658 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
659 struct stm32_pinctrl_group *g = pctl->groups + group;
660 struct pinctrl_gpio_range *range;
661 struct stm32_gpio_bank *bank;
662 u32 mode, alt;
663 int pin;
664
665 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
666 if (!ret) {
667 dev_err(pctl->dev, "invalid function %d on group %d .\n",
668 function, group);
669 return -EINVAL;
670 }
671
672 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
673 if (!range) {
674 dev_err(pctl->dev, "No gpio range defined.\n");
675 return -EINVAL;
676 }
677
678 bank = gpiochip_get_data(range->gc);
679 pin = stm32_gpio_pin(g->pin);
680
681 mode = stm32_gpio_get_mode(function);
682 alt = stm32_gpio_get_alt(function);
683
684 return stm32_pmx_set_mode(bank, pin, mode, alt);
685 }
686
687 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
688 struct pinctrl_gpio_range *range, unsigned gpio,
689 bool input)
690 {
691 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
692 int pin = stm32_gpio_pin(gpio);
693
694 return stm32_pmx_set_mode(bank, pin, !input, 0);
695 }
696
697 static const struct pinmux_ops stm32_pmx_ops = {
698 .get_functions_count = stm32_pmx_get_funcs_cnt,
699 .get_function_name = stm32_pmx_get_func_name,
700 .get_function_groups = stm32_pmx_get_func_groups,
701 .set_mux = stm32_pmx_set_mux,
702 .gpio_set_direction = stm32_pmx_gpio_set_direction,
703 .strict = true,
704 };
705
706 /* Pinconf functions */
707
708 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
709 unsigned offset, u32 drive)
710 {
711 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
712 unsigned long flags;
713 u32 val;
714 int err = 0;
715
716 clk_enable(bank->clk);
717 spin_lock_irqsave(&bank->lock, flags);
718
719 if (pctl->hwlock)
720 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
721
722 if (err) {
723 dev_err(pctl->dev, "Can't get hwspinlock\n");
724 goto unlock;
725 }
726
727 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
728 val &= ~BIT(offset);
729 val |= drive << offset;
730 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
731
732 if (pctl->hwlock)
733 hwspin_unlock(pctl->hwlock);
734
735 unlock:
736 spin_unlock_irqrestore(&bank->lock, flags);
737 clk_disable(bank->clk);
738
739 return err;
740 }
741
742 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
743 unsigned int offset)
744 {
745 unsigned long flags;
746 u32 val;
747
748 clk_enable(bank->clk);
749 spin_lock_irqsave(&bank->lock, flags);
750
751 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
752 val &= BIT(offset);
753
754 spin_unlock_irqrestore(&bank->lock, flags);
755 clk_disable(bank->clk);
756
757 return (val >> offset);
758 }
759
760 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
761 unsigned offset, u32 speed)
762 {
763 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
764 unsigned long flags;
765 u32 val;
766 int err = 0;
767
768 clk_enable(bank->clk);
769 spin_lock_irqsave(&bank->lock, flags);
770
771 if (pctl->hwlock)
772 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
773
774 if (err) {
775 dev_err(pctl->dev, "Can't get hwspinlock\n");
776 goto unlock;
777 }
778
779 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
780 val &= ~GENMASK(offset * 2 + 1, offset * 2);
781 val |= speed << (offset * 2);
782 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
783
784 if (pctl->hwlock)
785 hwspin_unlock(pctl->hwlock);
786
787 unlock:
788 spin_unlock_irqrestore(&bank->lock, flags);
789 clk_disable(bank->clk);
790
791 return err;
792 }
793
794 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
795 unsigned int offset)
796 {
797 unsigned long flags;
798 u32 val;
799
800 clk_enable(bank->clk);
801 spin_lock_irqsave(&bank->lock, flags);
802
803 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
804 val &= GENMASK(offset * 2 + 1, offset * 2);
805
806 spin_unlock_irqrestore(&bank->lock, flags);
807 clk_disable(bank->clk);
808
809 return (val >> (offset * 2));
810 }
811
812 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
813 unsigned offset, u32 bias)
814 {
815 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
816 unsigned long flags;
817 u32 val;
818 int err = 0;
819
820 clk_enable(bank->clk);
821 spin_lock_irqsave(&bank->lock, flags);
822
823 if (pctl->hwlock)
824 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
825
826 if (err) {
827 dev_err(pctl->dev, "Can't get hwspinlock\n");
828 goto unlock;
829 }
830
831 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
832 val &= ~GENMASK(offset * 2 + 1, offset * 2);
833 val |= bias << (offset * 2);
834 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
835
836 if (pctl->hwlock)
837 hwspin_unlock(pctl->hwlock);
838
839 unlock:
840 spin_unlock_irqrestore(&bank->lock, flags);
841 clk_disable(bank->clk);
842
843 return err;
844 }
845
846 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
847 unsigned int offset)
848 {
849 unsigned long flags;
850 u32 val;
851
852 clk_enable(bank->clk);
853 spin_lock_irqsave(&bank->lock, flags);
854
855 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
856 val &= GENMASK(offset * 2 + 1, offset * 2);
857
858 spin_unlock_irqrestore(&bank->lock, flags);
859 clk_disable(bank->clk);
860
861 return (val >> (offset * 2));
862 }
863
864 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
865 unsigned int offset, bool dir)
866 {
867 unsigned long flags;
868 u32 val;
869
870 clk_enable(bank->clk);
871 spin_lock_irqsave(&bank->lock, flags);
872
873 if (dir)
874 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
875 BIT(offset));
876 else
877 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
878 BIT(offset));
879
880 spin_unlock_irqrestore(&bank->lock, flags);
881 clk_disable(bank->clk);
882
883 return val;
884 }
885
886 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
887 unsigned int pin, enum pin_config_param param,
888 enum pin_config_param arg)
889 {
890 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
891 struct pinctrl_gpio_range *range;
892 struct stm32_gpio_bank *bank;
893 int offset, ret = 0;
894
895 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
896 if (!range) {
897 dev_err(pctl->dev, "No gpio range defined.\n");
898 return -EINVAL;
899 }
900
901 bank = gpiochip_get_data(range->gc);
902 offset = stm32_gpio_pin(pin);
903
904 switch (param) {
905 case PIN_CONFIG_DRIVE_PUSH_PULL:
906 ret = stm32_pconf_set_driving(bank, offset, 0);
907 break;
908 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
909 ret = stm32_pconf_set_driving(bank, offset, 1);
910 break;
911 case PIN_CONFIG_SLEW_RATE:
912 ret = stm32_pconf_set_speed(bank, offset, arg);
913 break;
914 case PIN_CONFIG_BIAS_DISABLE:
915 ret = stm32_pconf_set_bias(bank, offset, 0);
916 break;
917 case PIN_CONFIG_BIAS_PULL_UP:
918 ret = stm32_pconf_set_bias(bank, offset, 1);
919 break;
920 case PIN_CONFIG_BIAS_PULL_DOWN:
921 ret = stm32_pconf_set_bias(bank, offset, 2);
922 break;
923 case PIN_CONFIG_OUTPUT:
924 __stm32_gpio_set(bank, offset, arg);
925 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
926 break;
927 default:
928 ret = -EINVAL;
929 }
930
931 return ret;
932 }
933
934 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
935 unsigned group,
936 unsigned long *config)
937 {
938 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
939
940 *config = pctl->groups[group].config;
941
942 return 0;
943 }
944
945 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
946 unsigned long *configs, unsigned num_configs)
947 {
948 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
949 struct stm32_pinctrl_group *g = &pctl->groups[group];
950 int i, ret;
951
952 for (i = 0; i < num_configs; i++) {
953 ret = stm32_pconf_parse_conf(pctldev, g->pin,
954 pinconf_to_config_param(configs[i]),
955 pinconf_to_config_argument(configs[i]));
956 if (ret < 0)
957 return ret;
958
959 g->config = configs[i];
960 }
961
962 return 0;
963 }
964
965 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
966 struct seq_file *s,
967 unsigned int pin)
968 {
969 struct pinctrl_gpio_range *range;
970 struct stm32_gpio_bank *bank;
971 int offset;
972 u32 mode, alt, drive, speed, bias;
973 static const char * const modes[] = {
974 "input", "output", "alternate", "analog" };
975 static const char * const speeds[] = {
976 "low", "medium", "high", "very high" };
977 static const char * const biasing[] = {
978 "floating", "pull up", "pull down", "" };
979 bool val;
980
981 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
982 if (!range)
983 return;
984
985 bank = gpiochip_get_data(range->gc);
986 offset = stm32_gpio_pin(pin);
987
988 stm32_pmx_get_mode(bank, offset, &mode, &alt);
989 bias = stm32_pconf_get_bias(bank, offset);
990
991 seq_printf(s, "%s ", modes[mode]);
992
993 switch (mode) {
994 /* input */
995 case 0:
996 val = stm32_pconf_get(bank, offset, true);
997 seq_printf(s, "- %s - %s",
998 val ? "high" : "low",
999 biasing[bias]);
1000 break;
1001
1002 /* output */
1003 case 1:
1004 drive = stm32_pconf_get_driving(bank, offset);
1005 speed = stm32_pconf_get_speed(bank, offset);
1006 val = stm32_pconf_get(bank, offset, false);
1007 seq_printf(s, "- %s - %s - %s - %s %s",
1008 val ? "high" : "low",
1009 drive ? "open drain" : "push pull",
1010 biasing[bias],
1011 speeds[speed], "speed");
1012 break;
1013
1014 /* alternate */
1015 case 2:
1016 drive = stm32_pconf_get_driving(bank, offset);
1017 speed = stm32_pconf_get_speed(bank, offset);
1018 seq_printf(s, "%d - %s - %s - %s %s", alt,
1019 drive ? "open drain" : "push pull",
1020 biasing[bias],
1021 speeds[speed], "speed");
1022 break;
1023
1024 /* analog */
1025 case 3:
1026 break;
1027 }
1028 }
1029
1030
1031 static const struct pinconf_ops stm32_pconf_ops = {
1032 .pin_config_group_get = stm32_pconf_group_get,
1033 .pin_config_group_set = stm32_pconf_group_set,
1034 .pin_config_dbg_show = stm32_pconf_dbg_show,
1035 };
1036
1037 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
1038 struct device_node *np)
1039 {
1040 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1041 int bank_ioport_nr;
1042 struct pinctrl_gpio_range *range = &bank->range;
1043 struct of_phandle_args args;
1044 struct device *dev = pctl->dev;
1045 struct resource res;
1046 struct reset_control *rstc;
1047 int npins = STM32_GPIO_PINS_PER_BANK;
1048 int bank_nr, err;
1049
1050 rstc = of_reset_control_get_exclusive(np, NULL);
1051 if (!IS_ERR(rstc))
1052 reset_control_deassert(rstc);
1053
1054 if (of_address_to_resource(np, 0, &res))
1055 return -ENODEV;
1056
1057 bank->base = devm_ioremap_resource(dev, &res);
1058 if (IS_ERR(bank->base))
1059 return PTR_ERR(bank->base);
1060
1061 bank->clk = of_clk_get_by_name(np, NULL);
1062 if (IS_ERR(bank->clk)) {
1063 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
1064 return PTR_ERR(bank->clk);
1065 }
1066
1067 err = clk_prepare(bank->clk);
1068 if (err) {
1069 dev_err(dev, "failed to prepare clk (%d)\n", err);
1070 return err;
1071 }
1072
1073 bank->gpio_chip = stm32_gpio_template;
1074
1075 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
1076
1077 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) {
1078 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1079 bank->gpio_chip.base = args.args[1];
1080 } else {
1081 bank_nr = pctl->nbanks;
1082 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1083 range->name = bank->gpio_chip.label;
1084 range->id = bank_nr;
1085 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1086 range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1087 range->npins = npins;
1088 range->gc = &bank->gpio_chip;
1089 pinctrl_add_gpio_range(pctl->pctl_dev,
1090 &pctl->banks[bank_nr].range);
1091 }
1092
1093 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
1094 bank_ioport_nr = bank_nr;
1095
1096 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1097
1098 bank->gpio_chip.ngpio = npins;
1099 bank->gpio_chip.of_node = np;
1100 bank->gpio_chip.parent = dev;
1101 bank->bank_nr = bank_nr;
1102 bank->bank_ioport_nr = bank_ioport_nr;
1103 spin_lock_init(&bank->lock);
1104
1105 /* create irq hierarchical domain */
1106 bank->fwnode = of_node_to_fwnode(np);
1107
1108 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
1109 STM32_GPIO_IRQ_LINE, bank->fwnode,
1110 &stm32_gpio_domain_ops, bank);
1111
1112 if (!bank->domain)
1113 return -ENODEV;
1114
1115 err = gpiochip_add_data(&bank->gpio_chip, bank);
1116 if (err) {
1117 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1118 return err;
1119 }
1120
1121 dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1122 return 0;
1123 }
1124
1125 static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
1126 {
1127 struct device_node *parent;
1128 struct irq_domain *domain;
1129
1130 if (!of_find_property(np, "interrupt-parent", NULL))
1131 return NULL;
1132
1133 parent = of_irq_find_parent(np);
1134 if (!parent)
1135 return ERR_PTR(-ENXIO);
1136
1137 domain = irq_find_host(parent);
1138 if (!domain)
1139 /* domain not registered yet */
1140 return ERR_PTR(-EPROBE_DEFER);
1141
1142 return domain;
1143 }
1144
1145 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1146 struct stm32_pinctrl *pctl)
1147 {
1148 struct device_node *np = pdev->dev.of_node;
1149 struct device *dev = &pdev->dev;
1150 struct regmap *rm;
1151 int offset, ret, i;
1152 int mask, mask_width;
1153
1154 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1155 if (IS_ERR(pctl->regmap))
1156 return PTR_ERR(pctl->regmap);
1157
1158 rm = pctl->regmap;
1159
1160 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1161 if (ret)
1162 return ret;
1163
1164 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1165 if (ret)
1166 mask = SYSCFG_IRQMUX_MASK;
1167
1168 mask_width = fls(mask);
1169
1170 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1171 struct reg_field mux;
1172
1173 mux.reg = offset + (i / 4) * 4;
1174 mux.lsb = (i % 4) * mask_width;
1175 mux.msb = mux.lsb + mask_width - 1;
1176
1177 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1178 i, mux.reg, mux.lsb, mux.msb);
1179
1180 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1181 if (IS_ERR(pctl->irqmux[i]))
1182 return PTR_ERR(pctl->irqmux[i]);
1183 }
1184
1185 return 0;
1186 }
1187
1188 static int stm32_pctrl_build_state(struct platform_device *pdev)
1189 {
1190 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1191 int i;
1192
1193 pctl->ngroups = pctl->npins;
1194
1195 /* Allocate groups */
1196 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1197 sizeof(*pctl->groups), GFP_KERNEL);
1198 if (!pctl->groups)
1199 return -ENOMEM;
1200
1201 /* We assume that one pin is one group, use pin name as group name. */
1202 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1203 sizeof(*pctl->grp_names), GFP_KERNEL);
1204 if (!pctl->grp_names)
1205 return -ENOMEM;
1206
1207 for (i = 0; i < pctl->npins; i++) {
1208 const struct stm32_desc_pin *pin = pctl->pins + i;
1209 struct stm32_pinctrl_group *group = pctl->groups + i;
1210
1211 group->name = pin->pin.name;
1212 group->pin = pin->pin.number;
1213 pctl->grp_names[i] = pin->pin.name;
1214 }
1215
1216 return 0;
1217 }
1218
1219 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1220 struct stm32_desc_pin *pins)
1221 {
1222 const struct stm32_desc_pin *p;
1223 int i, nb_pins_available = 0;
1224
1225 for (i = 0; i < pctl->match_data->npins; i++) {
1226 p = pctl->match_data->pins + i;
1227 if (pctl->pkg && !(pctl->pkg & p->pkg))
1228 continue;
1229 pins->pin = p->pin;
1230 pins->functions = p->functions;
1231 pins++;
1232 nb_pins_available++;
1233 }
1234
1235 pctl->npins = nb_pins_available;
1236
1237 return 0;
1238 }
1239
1240 static void stm32_pctl_get_package(struct device_node *np,
1241 struct stm32_pinctrl *pctl)
1242 {
1243 if (of_property_read_u32(np, "st,package", &pctl->pkg)) {
1244 pctl->pkg = 0;
1245 dev_warn(pctl->dev, "No package detected, use default one\n");
1246 } else {
1247 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1248 }
1249 }
1250
1251 int stm32_pctl_probe(struct platform_device *pdev)
1252 {
1253 struct device_node *np = pdev->dev.of_node;
1254 struct device_node *child;
1255 const struct of_device_id *match;
1256 struct device *dev = &pdev->dev;
1257 struct stm32_pinctrl *pctl;
1258 struct pinctrl_pin_desc *pins;
1259 int i, ret, hwlock_id, banks = 0;
1260
1261 if (!np)
1262 return -EINVAL;
1263
1264 match = of_match_device(dev->driver->of_match_table, dev);
1265 if (!match || !match->data)
1266 return -EINVAL;
1267
1268 if (!of_find_property(np, "pins-are-numbered", NULL)) {
1269 dev_err(dev, "only support pins-are-numbered format\n");
1270 return -EINVAL;
1271 }
1272
1273 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1274 if (!pctl)
1275 return -ENOMEM;
1276
1277 platform_set_drvdata(pdev, pctl);
1278
1279 /* check for IRQ controller (may require deferred probe) */
1280 pctl->domain = stm32_pctrl_get_irq_domain(np);
1281 if (IS_ERR(pctl->domain))
1282 return PTR_ERR(pctl->domain);
1283
1284 /* hwspinlock is optional */
1285 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1286 if (hwlock_id < 0) {
1287 if (hwlock_id == -EPROBE_DEFER)
1288 return hwlock_id;
1289 } else {
1290 pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1291 }
1292
1293 pctl->dev = dev;
1294 pctl->match_data = match->data;
1295
1296 /* get package information */
1297 stm32_pctl_get_package(np, pctl);
1298
1299 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1300 sizeof(*pctl->pins), GFP_KERNEL);
1301 if (!pctl->pins)
1302 return -ENOMEM;
1303
1304 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1305 if (ret)
1306 return ret;
1307
1308 ret = stm32_pctrl_build_state(pdev);
1309 if (ret) {
1310 dev_err(dev, "build state failed: %d\n", ret);
1311 return -EINVAL;
1312 }
1313
1314 if (pctl->domain) {
1315 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1316 if (ret)
1317 return ret;
1318 }
1319
1320 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1321 GFP_KERNEL);
1322 if (!pins)
1323 return -ENOMEM;
1324
1325 for (i = 0; i < pctl->npins; i++)
1326 pins[i] = pctl->pins[i].pin;
1327
1328 pctl->pctl_desc.name = dev_name(&pdev->dev);
1329 pctl->pctl_desc.owner = THIS_MODULE;
1330 pctl->pctl_desc.pins = pins;
1331 pctl->pctl_desc.npins = pctl->npins;
1332 pctl->pctl_desc.confops = &stm32_pconf_ops;
1333 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1334 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1335 pctl->dev = &pdev->dev;
1336
1337 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1338 pctl);
1339
1340 if (IS_ERR(pctl->pctl_dev)) {
1341 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1342 return PTR_ERR(pctl->pctl_dev);
1343 }
1344
1345 for_each_available_child_of_node(np, child)
1346 if (of_property_read_bool(child, "gpio-controller"))
1347 banks++;
1348
1349 if (!banks) {
1350 dev_err(dev, "at least one GPIO bank is required\n");
1351 return -EINVAL;
1352 }
1353 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1354 GFP_KERNEL);
1355 if (!pctl->banks)
1356 return -ENOMEM;
1357
1358 for_each_available_child_of_node(np, child) {
1359 if (of_property_read_bool(child, "gpio-controller")) {
1360 ret = stm32_gpiolib_register_bank(pctl, child);
1361 if (ret)
1362 return ret;
1363
1364 pctl->nbanks++;
1365 }
1366 }
1367
1368 dev_info(dev, "Pinctrl STM32 initialized\n");
1369
1370 return 0;
1371 }
Ubuntu Jammy Linux kernel mirror