2 * Copyright (C) Maxime Coquelin 2015
3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * License terms: GNU General Public License (GPL), version 2
6 * Heavily based on Mediatek's pinctrl driver
9 #include <linux/gpio/driver.h>
11 #include <linux/irq.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/pinctrl/machine.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/reset.h>
27 #include <linux/slab.h>
30 #include "../pinconf.h"
31 #include "../pinctrl-utils.h"
32 #include "pinctrl-stm32.h"
34 #define STM32_GPIO_MODER 0x00
35 #define STM32_GPIO_TYPER 0x04
36 #define STM32_GPIO_SPEEDR 0x08
37 #define STM32_GPIO_PUPDR 0x0c
38 #define STM32_GPIO_IDR 0x10
39 #define STM32_GPIO_ODR 0x14
40 #define STM32_GPIO_BSRR 0x18
41 #define STM32_GPIO_LCKR 0x1c
42 #define STM32_GPIO_AFRL 0x20
43 #define STM32_GPIO_AFRH 0x24
45 #define STM32_GPIO_PINS_PER_BANK 16
46 #define STM32_GPIO_IRQ_LINE 16
48 #define gpio_range_to_bank(chip) \
49 container_of(chip, struct stm32_gpio_bank, range)
51 static const char * const stm32_gpio_functions
[] = {
56 "af11", "af12", "af13",
57 "af14", "af15", "analog",
60 struct stm32_pinctrl_group
{
66 struct stm32_gpio_bank
{
70 struct gpio_chip gpio_chip
;
71 struct pinctrl_gpio_range range
;
72 struct fwnode_handle
*fwnode
;
73 struct irq_domain
*domain
;
77 struct stm32_pinctrl
{
79 struct pinctrl_dev
*pctl_dev
;
80 struct pinctrl_desc pctl_desc
;
81 struct stm32_pinctrl_group
*groups
;
83 const char **grp_names
;
84 struct stm32_gpio_bank
*banks
;
86 const struct stm32_pinctrl_match_data
*match_data
;
87 struct irq_domain
*domain
;
88 struct regmap
*regmap
;
89 struct regmap_field
*irqmux
[STM32_GPIO_PINS_PER_BANK
];
92 static inline int stm32_gpio_pin(int gpio
)
94 return gpio
% STM32_GPIO_PINS_PER_BANK
;
97 static inline u32
stm32_gpio_get_mode(u32 function
)
102 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
104 case STM32_PIN_ANALOG
:
111 static inline u32
stm32_gpio_get_alt(u32 function
)
116 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
118 case STM32_PIN_ANALOG
:
127 static inline void __stm32_gpio_set(struct stm32_gpio_bank
*bank
,
128 unsigned offset
, int value
)
131 offset
+= STM32_GPIO_PINS_PER_BANK
;
133 clk_enable(bank
->clk
);
135 writel_relaxed(BIT(offset
), bank
->base
+ STM32_GPIO_BSRR
);
137 clk_disable(bank
->clk
);
140 static int stm32_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
142 struct stm32_gpio_bank
*bank
= gpiochip_get_data(chip
);
143 struct stm32_pinctrl
*pctl
= dev_get_drvdata(bank
->gpio_chip
.parent
);
144 struct pinctrl_gpio_range
*range
;
145 int pin
= offset
+ (bank
->bank_nr
* STM32_GPIO_PINS_PER_BANK
);
147 range
= pinctrl_find_gpio_range_from_pin_nolock(pctl
->pctl_dev
, pin
);
149 dev_err(pctl
->dev
, "pin %d not in range.\n", pin
);
153 return pinctrl_gpio_request(chip
->base
+ offset
);
156 static void stm32_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
158 pinctrl_gpio_free(chip
->base
+ offset
);
161 static int stm32_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
163 struct stm32_gpio_bank
*bank
= gpiochip_get_data(chip
);
166 clk_enable(bank
->clk
);
168 ret
= !!(readl_relaxed(bank
->base
+ STM32_GPIO_IDR
) & BIT(offset
));
170 clk_disable(bank
->clk
);
175 static void stm32_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
177 struct stm32_gpio_bank
*bank
= gpiochip_get_data(chip
);
179 __stm32_gpio_set(bank
, offset
, value
);
182 static int stm32_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
184 return pinctrl_gpio_direction_input(chip
->base
+ offset
);
187 static int stm32_gpio_direction_output(struct gpio_chip
*chip
,
188 unsigned offset
, int value
)
190 struct stm32_gpio_bank
*bank
= gpiochip_get_data(chip
);
192 __stm32_gpio_set(bank
, offset
, value
);
193 pinctrl_gpio_direction_output(chip
->base
+ offset
);
199 static int stm32_gpio_to_irq(struct gpio_chip
*chip
, unsigned int offset
)
201 struct stm32_gpio_bank
*bank
= gpiochip_get_data(chip
);
202 struct irq_fwspec fwspec
;
204 fwspec
.fwnode
= bank
->fwnode
;
205 fwspec
.param_count
= 2;
206 fwspec
.param
[0] = offset
;
207 fwspec
.param
[1] = IRQ_TYPE_NONE
;
209 return irq_create_fwspec_mapping(&fwspec
);
212 static int stm32_gpio_get_direction(struct gpio_chip
*chip
, unsigned int offset
)
214 struct stm32_gpio_bank
*bank
= gpiochip_get_data(chip
);
215 int pin
= stm32_gpio_pin(offset
);
219 stm32_pmx_get_mode(bank
, pin
, &mode
, &alt
);
220 if ((alt
== 0) && (mode
== 0))
222 else if ((alt
== 0) && (mode
== 1))
230 static const struct gpio_chip stm32_gpio_template
= {
231 .request
= stm32_gpio_request
,
232 .free
= stm32_gpio_free
,
233 .get
= stm32_gpio_get
,
234 .set
= stm32_gpio_set
,
235 .direction_input
= stm32_gpio_direction_input
,
236 .direction_output
= stm32_gpio_direction_output
,
237 .to_irq
= stm32_gpio_to_irq
,
238 .get_direction
= stm32_gpio_get_direction
,
241 static int stm32_gpio_irq_request_resources(struct irq_data
*irq_data
)
243 struct stm32_gpio_bank
*bank
= irq_data
->domain
->host_data
;
244 struct stm32_pinctrl
*pctl
= dev_get_drvdata(bank
->gpio_chip
.parent
);
247 ret
= stm32_gpio_direction_input(&bank
->gpio_chip
, irq_data
->hwirq
);
251 ret
= gpiochip_lock_as_irq(&bank
->gpio_chip
, irq_data
->hwirq
);
253 dev_err(pctl
->dev
, "unable to lock HW IRQ %lu for IRQ\n",
261 static void stm32_gpio_irq_release_resources(struct irq_data
*irq_data
)
263 struct stm32_gpio_bank
*bank
= irq_data
->domain
->host_data
;
265 gpiochip_unlock_as_irq(&bank
->gpio_chip
, irq_data
->hwirq
);
268 static struct irq_chip stm32_gpio_irq_chip
= {
270 .irq_eoi
= irq_chip_eoi_parent
,
271 .irq_mask
= irq_chip_mask_parent
,
272 .irq_unmask
= irq_chip_unmask_parent
,
273 .irq_set_type
= irq_chip_set_type_parent
,
274 .irq_request_resources
= stm32_gpio_irq_request_resources
,
275 .irq_release_resources
= stm32_gpio_irq_release_resources
,
278 static int stm32_gpio_domain_translate(struct irq_domain
*d
,
279 struct irq_fwspec
*fwspec
,
280 unsigned long *hwirq
,
283 if ((fwspec
->param_count
!= 2) ||
284 (fwspec
->param
[0] >= STM32_GPIO_IRQ_LINE
))
287 *hwirq
= fwspec
->param
[0];
288 *type
= fwspec
->param
[1];
292 static int stm32_gpio_domain_activate(struct irq_domain
*d
,
293 struct irq_data
*irq_data
, bool early
)
295 struct stm32_gpio_bank
*bank
= d
->host_data
;
296 struct stm32_pinctrl
*pctl
= dev_get_drvdata(bank
->gpio_chip
.parent
);
298 regmap_field_write(pctl
->irqmux
[irq_data
->hwirq
], bank
->bank_nr
);
302 static int stm32_gpio_domain_alloc(struct irq_domain
*d
,
304 unsigned int nr_irqs
, void *data
)
306 struct stm32_gpio_bank
*bank
= d
->host_data
;
307 struct irq_fwspec
*fwspec
= data
;
308 struct irq_fwspec parent_fwspec
;
309 irq_hw_number_t hwirq
;
311 hwirq
= fwspec
->param
[0];
312 parent_fwspec
.fwnode
= d
->parent
->fwnode
;
313 parent_fwspec
.param_count
= 2;
314 parent_fwspec
.param
[0] = fwspec
->param
[0];
315 parent_fwspec
.param
[1] = fwspec
->param
[1];
317 irq_domain_set_hwirq_and_chip(d
, virq
, hwirq
, &stm32_gpio_irq_chip
,
320 return irq_domain_alloc_irqs_parent(d
, virq
, nr_irqs
, &parent_fwspec
);
323 static const struct irq_domain_ops stm32_gpio_domain_ops
= {
324 .translate
= stm32_gpio_domain_translate
,
325 .alloc
= stm32_gpio_domain_alloc
,
326 .free
= irq_domain_free_irqs_common
,
327 .activate
= stm32_gpio_domain_activate
,
330 /* Pinctrl functions */
331 static struct stm32_pinctrl_group
*
332 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl
*pctl
, u32 pin
)
336 for (i
= 0; i
< pctl
->ngroups
; i
++) {
337 struct stm32_pinctrl_group
*grp
= pctl
->groups
+ i
;
346 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl
*pctl
,
347 u32 pin_num
, u32 fnum
)
351 for (i
= 0; i
< pctl
->match_data
->npins
; i
++) {
352 const struct stm32_desc_pin
*pin
= pctl
->match_data
->pins
+ i
;
353 const struct stm32_desc_function
*func
= pin
->functions
;
355 if (pin
->pin
.number
!= pin_num
)
358 while (func
&& func
->name
) {
359 if (func
->num
== fnum
)
370 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl
*pctl
,
371 u32 pin
, u32 fnum
, struct stm32_pinctrl_group
*grp
,
372 struct pinctrl_map
**map
, unsigned *reserved_maps
,
375 if (*num_maps
== *reserved_maps
)
378 (*map
)[*num_maps
].type
= PIN_MAP_TYPE_MUX_GROUP
;
379 (*map
)[*num_maps
].data
.mux
.group
= grp
->name
;
381 if (!stm32_pctrl_is_function_valid(pctl
, pin
, fnum
)) {
382 dev_err(pctl
->dev
, "invalid function %d on pin %d .\n",
387 (*map
)[*num_maps
].data
.mux
.function
= stm32_gpio_functions
[fnum
];
393 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev
*pctldev
,
394 struct device_node
*node
,
395 struct pinctrl_map
**map
,
396 unsigned *reserved_maps
,
399 struct stm32_pinctrl
*pctl
;
400 struct stm32_pinctrl_group
*grp
;
401 struct property
*pins
;
402 u32 pinfunc
, pin
, func
;
403 unsigned long *configs
;
404 unsigned int num_configs
;
406 unsigned reserve
= 0;
407 int num_pins
, num_funcs
, maps_per_pin
, i
, err
;
409 pctl
= pinctrl_dev_get_drvdata(pctldev
);
411 pins
= of_find_property(node
, "pinmux", NULL
);
413 dev_err(pctl
->dev
, "missing pins property in node %s .\n",
418 err
= pinconf_generic_parse_dt_config(node
, pctldev
, &configs
,
426 num_pins
= pins
->length
/ sizeof(u32
);
427 num_funcs
= num_pins
;
431 if (has_config
&& num_pins
>= 1)
434 if (!num_pins
|| !maps_per_pin
)
437 reserve
= num_pins
* maps_per_pin
;
439 err
= pinctrl_utils_reserve_map(pctldev
, map
,
440 reserved_maps
, num_maps
, reserve
);
444 for (i
= 0; i
< num_pins
; i
++) {
445 err
= of_property_read_u32_index(node
, "pinmux",
450 pin
= STM32_GET_PIN_NO(pinfunc
);
451 func
= STM32_GET_PIN_FUNC(pinfunc
);
453 if (!stm32_pctrl_is_function_valid(pctl
, pin
, func
)) {
454 dev_err(pctl
->dev
, "invalid function.\n");
458 grp
= stm32_pctrl_find_group_by_pin(pctl
, pin
);
460 dev_err(pctl
->dev
, "unable to match pin %d to group\n",
465 err
= stm32_pctrl_dt_node_to_map_func(pctl
, pin
, func
, grp
, map
,
466 reserved_maps
, num_maps
);
471 err
= pinctrl_utils_add_map_configs(pctldev
, map
,
472 reserved_maps
, num_maps
, grp
->name
,
473 configs
, num_configs
,
474 PIN_MAP_TYPE_CONFIGS_GROUP
);
483 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev
*pctldev
,
484 struct device_node
*np_config
,
485 struct pinctrl_map
**map
, unsigned *num_maps
)
487 struct device_node
*np
;
488 unsigned reserved_maps
;
495 for_each_child_of_node(np_config
, np
) {
496 ret
= stm32_pctrl_dt_subnode_to_map(pctldev
, np
, map
,
497 &reserved_maps
, num_maps
);
499 pinctrl_utils_free_map(pctldev
, *map
, *num_maps
);
507 static int stm32_pctrl_get_groups_count(struct pinctrl_dev
*pctldev
)
509 struct stm32_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
511 return pctl
->ngroups
;
514 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev
*pctldev
,
517 struct stm32_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
519 return pctl
->groups
[group
].name
;
522 static int stm32_pctrl_get_group_pins(struct pinctrl_dev
*pctldev
,
524 const unsigned **pins
,
527 struct stm32_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
529 *pins
= (unsigned *)&pctl
->groups
[group
].pin
;
535 static const struct pinctrl_ops stm32_pctrl_ops
= {
536 .dt_node_to_map
= stm32_pctrl_dt_node_to_map
,
537 .dt_free_map
= pinctrl_utils_free_map
,
538 .get_groups_count
= stm32_pctrl_get_groups_count
,
539 .get_group_name
= stm32_pctrl_get_group_name
,
540 .get_group_pins
= stm32_pctrl_get_group_pins
,
544 /* Pinmux functions */
546 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev
*pctldev
)
548 return ARRAY_SIZE(stm32_gpio_functions
);
551 static const char *stm32_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
554 return stm32_gpio_functions
[selector
];
557 static int stm32_pmx_get_func_groups(struct pinctrl_dev
*pctldev
,
559 const char * const **groups
,
560 unsigned * const num_groups
)
562 struct stm32_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
564 *groups
= pctl
->grp_names
;
565 *num_groups
= pctl
->ngroups
;
570 static void stm32_pmx_set_mode(struct stm32_gpio_bank
*bank
,
571 int pin
, u32 mode
, u32 alt
)
574 int alt_shift
= (pin
% 8) * 4;
575 int alt_offset
= STM32_GPIO_AFRL
+ (pin
/ 8) * 4;
578 clk_enable(bank
->clk
);
579 spin_lock_irqsave(&bank
->lock
, flags
);
581 val
= readl_relaxed(bank
->base
+ alt_offset
);
582 val
&= ~GENMASK(alt_shift
+ 3, alt_shift
);
583 val
|= (alt
<< alt_shift
);
584 writel_relaxed(val
, bank
->base
+ alt_offset
);
586 val
= readl_relaxed(bank
->base
+ STM32_GPIO_MODER
);
587 val
&= ~GENMASK(pin
* 2 + 1, pin
* 2);
588 val
|= mode
<< (pin
* 2);
589 writel_relaxed(val
, bank
->base
+ STM32_GPIO_MODER
);
591 spin_unlock_irqrestore(&bank
->lock
, flags
);
592 clk_disable(bank
->clk
);
595 void stm32_pmx_get_mode(struct stm32_gpio_bank
*bank
, int pin
, u32
*mode
,
599 int alt_shift
= (pin
% 8) * 4;
600 int alt_offset
= STM32_GPIO_AFRL
+ (pin
/ 8) * 4;
603 clk_enable(bank
->clk
);
604 spin_lock_irqsave(&bank
->lock
, flags
);
606 val
= readl_relaxed(bank
->base
+ alt_offset
);
607 val
&= GENMASK(alt_shift
+ 3, alt_shift
);
608 *alt
= val
>> alt_shift
;
610 val
= readl_relaxed(bank
->base
+ STM32_GPIO_MODER
);
611 val
&= GENMASK(pin
* 2 + 1, pin
* 2);
612 *mode
= val
>> (pin
* 2);
614 spin_unlock_irqrestore(&bank
->lock
, flags
);
615 clk_disable(bank
->clk
);
618 static int stm32_pmx_set_mux(struct pinctrl_dev
*pctldev
,
623 struct stm32_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
624 struct stm32_pinctrl_group
*g
= pctl
->groups
+ group
;
625 struct pinctrl_gpio_range
*range
;
626 struct stm32_gpio_bank
*bank
;
630 ret
= stm32_pctrl_is_function_valid(pctl
, g
->pin
, function
);
632 dev_err(pctl
->dev
, "invalid function %d on group %d .\n",
637 range
= pinctrl_find_gpio_range_from_pin(pctldev
, g
->pin
);
638 bank
= gpiochip_get_data(range
->gc
);
639 pin
= stm32_gpio_pin(g
->pin
);
641 mode
= stm32_gpio_get_mode(function
);
642 alt
= stm32_gpio_get_alt(function
);
644 stm32_pmx_set_mode(bank
, pin
, mode
, alt
);
649 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev
,
650 struct pinctrl_gpio_range
*range
, unsigned gpio
,
653 struct stm32_gpio_bank
*bank
= gpiochip_get_data(range
->gc
);
654 int pin
= stm32_gpio_pin(gpio
);
656 stm32_pmx_set_mode(bank
, pin
, !input
, 0);
661 static const struct pinmux_ops stm32_pmx_ops
= {
662 .get_functions_count
= stm32_pmx_get_funcs_cnt
,
663 .get_function_name
= stm32_pmx_get_func_name
,
664 .get_function_groups
= stm32_pmx_get_func_groups
,
665 .set_mux
= stm32_pmx_set_mux
,
666 .gpio_set_direction
= stm32_pmx_gpio_set_direction
,
670 /* Pinconf functions */
672 static void stm32_pconf_set_driving(struct stm32_gpio_bank
*bank
,
673 unsigned offset
, u32 drive
)
678 clk_enable(bank
->clk
);
679 spin_lock_irqsave(&bank
->lock
, flags
);
681 val
= readl_relaxed(bank
->base
+ STM32_GPIO_TYPER
);
683 val
|= drive
<< offset
;
684 writel_relaxed(val
, bank
->base
+ STM32_GPIO_TYPER
);
686 spin_unlock_irqrestore(&bank
->lock
, flags
);
687 clk_disable(bank
->clk
);
690 static u32
stm32_pconf_get_driving(struct stm32_gpio_bank
*bank
,
696 clk_enable(bank
->clk
);
697 spin_lock_irqsave(&bank
->lock
, flags
);
699 val
= readl_relaxed(bank
->base
+ STM32_GPIO_TYPER
);
702 spin_unlock_irqrestore(&bank
->lock
, flags
);
703 clk_disable(bank
->clk
);
705 return (val
>> offset
);
708 static void stm32_pconf_set_speed(struct stm32_gpio_bank
*bank
,
709 unsigned offset
, u32 speed
)
714 clk_enable(bank
->clk
);
715 spin_lock_irqsave(&bank
->lock
, flags
);
717 val
= readl_relaxed(bank
->base
+ STM32_GPIO_SPEEDR
);
718 val
&= ~GENMASK(offset
* 2 + 1, offset
* 2);
719 val
|= speed
<< (offset
* 2);
720 writel_relaxed(val
, bank
->base
+ STM32_GPIO_SPEEDR
);
722 spin_unlock_irqrestore(&bank
->lock
, flags
);
723 clk_disable(bank
->clk
);
726 static u32
stm32_pconf_get_speed(struct stm32_gpio_bank
*bank
,
732 clk_enable(bank
->clk
);
733 spin_lock_irqsave(&bank
->lock
, flags
);
735 val
= readl_relaxed(bank
->base
+ STM32_GPIO_SPEEDR
);
736 val
&= GENMASK(offset
* 2 + 1, offset
* 2);
738 spin_unlock_irqrestore(&bank
->lock
, flags
);
739 clk_disable(bank
->clk
);
741 return (val
>> (offset
* 2));
744 static void stm32_pconf_set_bias(struct stm32_gpio_bank
*bank
,
745 unsigned offset
, u32 bias
)
750 clk_enable(bank
->clk
);
751 spin_lock_irqsave(&bank
->lock
, flags
);
753 val
= readl_relaxed(bank
->base
+ STM32_GPIO_PUPDR
);
754 val
&= ~GENMASK(offset
* 2 + 1, offset
* 2);
755 val
|= bias
<< (offset
* 2);
756 writel_relaxed(val
, bank
->base
+ STM32_GPIO_PUPDR
);
758 spin_unlock_irqrestore(&bank
->lock
, flags
);
759 clk_disable(bank
->clk
);
762 static u32
stm32_pconf_get_bias(struct stm32_gpio_bank
*bank
,
768 clk_enable(bank
->clk
);
769 spin_lock_irqsave(&bank
->lock
, flags
);
771 val
= readl_relaxed(bank
->base
+ STM32_GPIO_PUPDR
);
772 val
&= GENMASK(offset
* 2 + 1, offset
* 2);
774 spin_unlock_irqrestore(&bank
->lock
, flags
);
775 clk_disable(bank
->clk
);
777 return (val
>> (offset
* 2));
780 static bool stm32_pconf_get(struct stm32_gpio_bank
*bank
,
781 unsigned int offset
, bool dir
)
786 clk_enable(bank
->clk
);
787 spin_lock_irqsave(&bank
->lock
, flags
);
790 val
= !!(readl_relaxed(bank
->base
+ STM32_GPIO_IDR
) &
793 val
= !!(readl_relaxed(bank
->base
+ STM32_GPIO_ODR
) &
796 spin_unlock_irqrestore(&bank
->lock
, flags
);
797 clk_disable(bank
->clk
);
802 static int stm32_pconf_parse_conf(struct pinctrl_dev
*pctldev
,
803 unsigned int pin
, enum pin_config_param param
,
804 enum pin_config_param arg
)
806 struct pinctrl_gpio_range
*range
;
807 struct stm32_gpio_bank
*bank
;
810 range
= pinctrl_find_gpio_range_from_pin(pctldev
, pin
);
811 bank
= gpiochip_get_data(range
->gc
);
812 offset
= stm32_gpio_pin(pin
);
815 case PIN_CONFIG_DRIVE_PUSH_PULL
:
816 stm32_pconf_set_driving(bank
, offset
, 0);
818 case PIN_CONFIG_DRIVE_OPEN_DRAIN
:
819 stm32_pconf_set_driving(bank
, offset
, 1);
821 case PIN_CONFIG_SLEW_RATE
:
822 stm32_pconf_set_speed(bank
, offset
, arg
);
824 case PIN_CONFIG_BIAS_DISABLE
:
825 stm32_pconf_set_bias(bank
, offset
, 0);
827 case PIN_CONFIG_BIAS_PULL_UP
:
828 stm32_pconf_set_bias(bank
, offset
, 1);
830 case PIN_CONFIG_BIAS_PULL_DOWN
:
831 stm32_pconf_set_bias(bank
, offset
, 2);
833 case PIN_CONFIG_OUTPUT
:
834 __stm32_gpio_set(bank
, offset
, arg
);
835 ret
= stm32_pmx_gpio_set_direction(pctldev
, range
, pin
, false);
844 static int stm32_pconf_group_get(struct pinctrl_dev
*pctldev
,
846 unsigned long *config
)
848 struct stm32_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
850 *config
= pctl
->groups
[group
].config
;
855 static int stm32_pconf_group_set(struct pinctrl_dev
*pctldev
, unsigned group
,
856 unsigned long *configs
, unsigned num_configs
)
858 struct stm32_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
859 struct stm32_pinctrl_group
*g
= &pctl
->groups
[group
];
862 for (i
= 0; i
< num_configs
; i
++) {
863 ret
= stm32_pconf_parse_conf(pctldev
, g
->pin
,
864 pinconf_to_config_param(configs
[i
]),
865 pinconf_to_config_argument(configs
[i
]));
869 g
->config
= configs
[i
];
875 static void stm32_pconf_dbg_show(struct pinctrl_dev
*pctldev
,
879 struct pinctrl_gpio_range
*range
;
880 struct stm32_gpio_bank
*bank
;
882 u32 mode
, alt
, drive
, speed
, bias
;
883 static const char * const modes
[] = {
884 "input", "output", "alternate", "analog" };
885 static const char * const speeds
[] = {
886 "low", "medium", "high", "very high" };
887 static const char * const biasing
[] = {
888 "floating", "pull up", "pull down", "" };
891 range
= pinctrl_find_gpio_range_from_pin_nolock(pctldev
, pin
);
892 bank
= gpiochip_get_data(range
->gc
);
893 offset
= stm32_gpio_pin(pin
);
895 stm32_pmx_get_mode(bank
, offset
, &mode
, &alt
);
896 bias
= stm32_pconf_get_bias(bank
, offset
);
898 seq_printf(s
, "%s ", modes
[mode
]);
903 val
= stm32_pconf_get(bank
, offset
, true);
904 seq_printf(s
, "- %s - %s",
905 val
? "high" : "low",
911 drive
= stm32_pconf_get_driving(bank
, offset
);
912 speed
= stm32_pconf_get_speed(bank
, offset
);
913 val
= stm32_pconf_get(bank
, offset
, false);
914 seq_printf(s
, "- %s - %s - %s - %s %s",
915 val
? "high" : "low",
916 drive
? "open drain" : "push pull",
918 speeds
[speed
], "speed");
923 drive
= stm32_pconf_get_driving(bank
, offset
);
924 speed
= stm32_pconf_get_speed(bank
, offset
);
925 seq_printf(s
, "%d - %s - %s - %s %s", alt
,
926 drive
? "open drain" : "push pull",
928 speeds
[speed
], "speed");
938 static const struct pinconf_ops stm32_pconf_ops
= {
939 .pin_config_group_get
= stm32_pconf_group_get
,
940 .pin_config_group_set
= stm32_pconf_group_set
,
941 .pin_config_dbg_show
= stm32_pconf_dbg_show
,
944 static int stm32_gpiolib_register_bank(struct stm32_pinctrl
*pctl
,
945 struct device_node
*np
)
947 struct stm32_gpio_bank
*bank
= &pctl
->banks
[pctl
->nbanks
];
948 struct pinctrl_gpio_range
*range
= &bank
->range
;
949 struct of_phandle_args args
;
950 struct device
*dev
= pctl
->dev
;
952 struct reset_control
*rstc
;
953 int npins
= STM32_GPIO_PINS_PER_BANK
;
956 rstc
= of_reset_control_get_exclusive(np
, NULL
);
958 reset_control_deassert(rstc
);
960 if (of_address_to_resource(np
, 0, &res
))
963 bank
->base
= devm_ioremap_resource(dev
, &res
);
964 if (IS_ERR(bank
->base
))
965 return PTR_ERR(bank
->base
);
967 bank
->clk
= of_clk_get_by_name(np
, NULL
);
968 if (IS_ERR(bank
->clk
)) {
969 dev_err(dev
, "failed to get clk (%ld)\n", PTR_ERR(bank
->clk
));
970 return PTR_ERR(bank
->clk
);
973 err
= clk_prepare(bank
->clk
);
975 dev_err(dev
, "failed to prepare clk (%d)\n", err
);
979 bank
->gpio_chip
= stm32_gpio_template
;
981 of_property_read_string(np
, "st,bank-name", &bank
->gpio_chip
.label
);
983 if (!of_parse_phandle_with_fixed_args(np
, "gpio-ranges", 3, 0, &args
)) {
984 bank_nr
= args
.args
[1] / STM32_GPIO_PINS_PER_BANK
;
985 bank
->gpio_chip
.base
= args
.args
[1];
987 bank_nr
= pctl
->nbanks
;
988 bank
->gpio_chip
.base
= bank_nr
* STM32_GPIO_PINS_PER_BANK
;
989 range
->name
= bank
->gpio_chip
.label
;
991 range
->pin_base
= range
->id
* STM32_GPIO_PINS_PER_BANK
;
992 range
->base
= range
->id
* STM32_GPIO_PINS_PER_BANK
;
993 range
->npins
= npins
;
994 range
->gc
= &bank
->gpio_chip
;
995 pinctrl_add_gpio_range(pctl
->pctl_dev
,
996 &pctl
->banks
[bank_nr
].range
);
998 bank
->gpio_chip
.base
= bank_nr
* STM32_GPIO_PINS_PER_BANK
;
1000 bank
->gpio_chip
.ngpio
= npins
;
1001 bank
->gpio_chip
.of_node
= np
;
1002 bank
->gpio_chip
.parent
= dev
;
1003 bank
->bank_nr
= bank_nr
;
1004 spin_lock_init(&bank
->lock
);
1006 /* create irq hierarchical domain */
1007 bank
->fwnode
= of_node_to_fwnode(np
);
1009 bank
->domain
= irq_domain_create_hierarchy(pctl
->domain
, 0,
1010 STM32_GPIO_IRQ_LINE
, bank
->fwnode
,
1011 &stm32_gpio_domain_ops
, bank
);
1016 err
= gpiochip_add_data(&bank
->gpio_chip
, bank
);
1018 dev_err(dev
, "Failed to add gpiochip(%d)!\n", bank_nr
);
1022 dev_info(dev
, "%s bank added\n", bank
->gpio_chip
.label
);
1026 static int stm32_pctrl_dt_setup_irq(struct platform_device
*pdev
,
1027 struct stm32_pinctrl
*pctl
)
1029 struct device_node
*np
= pdev
->dev
.of_node
, *parent
;
1030 struct device
*dev
= &pdev
->dev
;
1034 parent
= of_irq_find_parent(np
);
1038 pctl
->domain
= irq_find_host(parent
);
1042 pctl
->regmap
= syscon_regmap_lookup_by_phandle(np
, "st,syscfg");
1043 if (IS_ERR(pctl
->regmap
))
1044 return PTR_ERR(pctl
->regmap
);
1048 ret
= of_property_read_u32_index(np
, "st,syscfg", 1, &offset
);
1052 for (i
= 0; i
< STM32_GPIO_PINS_PER_BANK
; i
++) {
1053 struct reg_field mux
;
1055 mux
.reg
= offset
+ (i
/ 4) * 4;
1056 mux
.lsb
= (i
% 4) * 4;
1057 mux
.msb
= mux
.lsb
+ 3;
1059 pctl
->irqmux
[i
] = devm_regmap_field_alloc(dev
, rm
, mux
);
1060 if (IS_ERR(pctl
->irqmux
[i
]))
1061 return PTR_ERR(pctl
->irqmux
[i
]);
1067 static int stm32_pctrl_build_state(struct platform_device
*pdev
)
1069 struct stm32_pinctrl
*pctl
= platform_get_drvdata(pdev
);
1072 pctl
->ngroups
= pctl
->match_data
->npins
;
1074 /* Allocate groups */
1075 pctl
->groups
= devm_kcalloc(&pdev
->dev
, pctl
->ngroups
,
1076 sizeof(*pctl
->groups
), GFP_KERNEL
);
1080 /* We assume that one pin is one group, use pin name as group name. */
1081 pctl
->grp_names
= devm_kcalloc(&pdev
->dev
, pctl
->ngroups
,
1082 sizeof(*pctl
->grp_names
), GFP_KERNEL
);
1083 if (!pctl
->grp_names
)
1086 for (i
= 0; i
< pctl
->match_data
->npins
; i
++) {
1087 const struct stm32_desc_pin
*pin
= pctl
->match_data
->pins
+ i
;
1088 struct stm32_pinctrl_group
*group
= pctl
->groups
+ i
;
1090 group
->name
= pin
->pin
.name
;
1091 group
->pin
= pin
->pin
.number
;
1093 pctl
->grp_names
[i
] = pin
->pin
.name
;
1099 int stm32_pctl_probe(struct platform_device
*pdev
)
1101 struct device_node
*np
= pdev
->dev
.of_node
;
1102 struct device_node
*child
;
1103 const struct of_device_id
*match
;
1104 struct device
*dev
= &pdev
->dev
;
1105 struct stm32_pinctrl
*pctl
;
1106 struct pinctrl_pin_desc
*pins
;
1107 int i
, ret
, banks
= 0;
1112 match
= of_match_device(dev
->driver
->of_match_table
, dev
);
1113 if (!match
|| !match
->data
)
1116 if (!of_find_property(np
, "pins-are-numbered", NULL
)) {
1117 dev_err(dev
, "only support pins-are-numbered format\n");
1121 pctl
= devm_kzalloc(dev
, sizeof(*pctl
), GFP_KERNEL
);
1125 platform_set_drvdata(pdev
, pctl
);
1128 pctl
->match_data
= match
->data
;
1129 ret
= stm32_pctrl_build_state(pdev
);
1131 dev_err(dev
, "build state failed: %d\n", ret
);
1135 if (of_find_property(np
, "interrupt-parent", NULL
)) {
1136 ret
= stm32_pctrl_dt_setup_irq(pdev
, pctl
);
1141 pins
= devm_kcalloc(&pdev
->dev
, pctl
->match_data
->npins
, sizeof(*pins
),
1146 for (i
= 0; i
< pctl
->match_data
->npins
; i
++)
1147 pins
[i
] = pctl
->match_data
->pins
[i
].pin
;
1149 pctl
->pctl_desc
.name
= dev_name(&pdev
->dev
);
1150 pctl
->pctl_desc
.owner
= THIS_MODULE
;
1151 pctl
->pctl_desc
.pins
= pins
;
1152 pctl
->pctl_desc
.npins
= pctl
->match_data
->npins
;
1153 pctl
->pctl_desc
.confops
= &stm32_pconf_ops
;
1154 pctl
->pctl_desc
.pctlops
= &stm32_pctrl_ops
;
1155 pctl
->pctl_desc
.pmxops
= &stm32_pmx_ops
;
1156 pctl
->dev
= &pdev
->dev
;
1158 pctl
->pctl_dev
= devm_pinctrl_register(&pdev
->dev
, &pctl
->pctl_desc
,
1161 if (IS_ERR(pctl
->pctl_dev
)) {
1162 dev_err(&pdev
->dev
, "Failed pinctrl registration\n");
1163 return PTR_ERR(pctl
->pctl_dev
);
1166 for_each_child_of_node(np
, child
)
1167 if (of_property_read_bool(child
, "gpio-controller"))
1171 dev_err(dev
, "at least one GPIO bank is required\n");
1174 pctl
->banks
= devm_kcalloc(dev
, banks
, sizeof(*pctl
->banks
),
1179 for_each_child_of_node(np
, child
) {
1180 if (of_property_read_bool(child
, "gpio-controller")) {
1181 ret
= stm32_gpiolib_register_bank(pctl
, child
);
1189 dev_info(dev
, "Pinctrl STM32 initialized\n");