2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/gpio.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
32 #include "../../gpio/gpiolib.h"
33 #include "pinctrl-sunxi.h"
35 static struct irq_chip sunxi_pinctrl_edge_irq_chip
;
36 static struct irq_chip sunxi_pinctrl_level_irq_chip
;
38 static struct sunxi_pinctrl_group
*
39 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl
*pctl
, const char *group
)
43 for (i
= 0; i
< pctl
->ngroups
; i
++) {
44 struct sunxi_pinctrl_group
*grp
= pctl
->groups
+ i
;
46 if (!strcmp(grp
->name
, group
))
53 static struct sunxi_pinctrl_function
*
54 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl
*pctl
,
57 struct sunxi_pinctrl_function
*func
= pctl
->functions
;
60 for (i
= 0; i
< pctl
->nfunctions
; i
++) {
64 if (!strcmp(func
[i
].name
, name
))
71 static struct sunxi_desc_function
*
72 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl
*pctl
,
74 const char *func_name
)
78 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
79 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
81 if (!strcmp(pin
->pin
.name
, pin_name
)) {
82 struct sunxi_desc_function
*func
= pin
->functions
;
85 if (!strcmp(func
->name
, func_name
))
96 static struct sunxi_desc_function
*
97 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl
*pctl
,
99 const char *func_name
)
103 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
104 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
106 if (pin
->pin
.number
== pin_num
) {
107 struct sunxi_desc_function
*func
= pin
->functions
;
110 if (!strcmp(func
->name
, func_name
))
121 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev
*pctldev
)
123 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
125 return pctl
->ngroups
;
128 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev
*pctldev
,
131 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
133 return pctl
->groups
[group
].name
;
136 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev
*pctldev
,
138 const unsigned **pins
,
141 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
143 *pins
= (unsigned *)&pctl
->groups
[group
].pin
;
149 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev
*pctldev
,
150 struct device_node
*node
,
151 struct pinctrl_map
**map
,
154 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
155 unsigned long *pinconfig
;
156 struct property
*prop
;
157 const char *function
;
159 int ret
, nmaps
, i
= 0;
165 ret
= of_property_read_string(node
, "allwinner,function", &function
);
168 "missing allwinner,function property in node %s\n",
173 nmaps
= of_property_count_strings(node
, "allwinner,pins") * 2;
176 "missing allwinner,pins property in node %s\n",
181 *map
= kmalloc(nmaps
* sizeof(struct pinctrl_map
), GFP_KERNEL
);
185 of_property_for_each_string(node
, "allwinner,pins", prop
, group
) {
186 struct sunxi_pinctrl_group
*grp
=
187 sunxi_pinctrl_find_group_by_name(pctl
, group
);
188 int j
= 0, configlen
= 0;
191 dev_err(pctl
->dev
, "unknown pin %s", group
);
195 if (!sunxi_pinctrl_desc_find_function_by_name(pctl
,
198 dev_err(pctl
->dev
, "unsupported function %s on pin %s",
203 (*map
)[i
].type
= PIN_MAP_TYPE_MUX_GROUP
;
204 (*map
)[i
].data
.mux
.group
= group
;
205 (*map
)[i
].data
.mux
.function
= function
;
209 (*map
)[i
].type
= PIN_MAP_TYPE_CONFIGS_GROUP
;
210 (*map
)[i
].data
.configs
.group_or_pin
= group
;
212 if (of_find_property(node
, "allwinner,drive", NULL
))
214 if (of_find_property(node
, "allwinner,pull", NULL
))
217 pinconfig
= kzalloc(configlen
* sizeof(*pinconfig
), GFP_KERNEL
);
223 if (!of_property_read_u32(node
, "allwinner,drive", &val
)) {
224 u16 strength
= (val
+ 1) * 10;
226 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH
,
230 if (!of_property_read_u32(node
, "allwinner,pull", &val
)) {
231 enum pin_config_param pull
= PIN_CONFIG_END
;
233 pull
= PIN_CONFIG_BIAS_PULL_UP
;
235 pull
= PIN_CONFIG_BIAS_PULL_DOWN
;
236 pinconfig
[j
++] = pinconf_to_config_packed(pull
, 0);
239 (*map
)[i
].data
.configs
.configs
= pinconfig
;
240 (*map
)[i
].data
.configs
.num_configs
= configlen
;
250 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev
*pctldev
,
251 struct pinctrl_map
*map
,
256 for (i
= 0; i
< num_maps
; i
++) {
257 if (map
[i
].type
== PIN_MAP_TYPE_CONFIGS_GROUP
)
258 kfree(map
[i
].data
.configs
.configs
);
264 static const struct pinctrl_ops sunxi_pctrl_ops
= {
265 .dt_node_to_map
= sunxi_pctrl_dt_node_to_map
,
266 .dt_free_map
= sunxi_pctrl_dt_free_map
,
267 .get_groups_count
= sunxi_pctrl_get_groups_count
,
268 .get_group_name
= sunxi_pctrl_get_group_name
,
269 .get_group_pins
= sunxi_pctrl_get_group_pins
,
272 static int sunxi_pconf_group_get(struct pinctrl_dev
*pctldev
,
274 unsigned long *config
)
276 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
278 *config
= pctl
->groups
[group
].config
;
283 static int sunxi_pconf_group_set(struct pinctrl_dev
*pctldev
,
285 unsigned long *configs
,
286 unsigned num_configs
)
288 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
289 struct sunxi_pinctrl_group
*g
= &pctl
->groups
[group
];
291 unsigned pin
= g
->pin
- pctl
->desc
->pin_base
;
297 spin_lock_irqsave(&pctl
->lock
, flags
);
299 for (i
= 0; i
< num_configs
; i
++) {
300 switch (pinconf_to_config_param(configs
[i
])) {
301 case PIN_CONFIG_DRIVE_STRENGTH
:
302 strength
= pinconf_to_config_argument(configs
[i
]);
304 spin_unlock_irqrestore(&pctl
->lock
, flags
);
308 * We convert from mA to what the register expects:
314 dlevel
= strength
/ 10 - 1;
315 val
= readl(pctl
->membase
+ sunxi_dlevel_reg(pin
));
316 mask
= DLEVEL_PINS_MASK
<< sunxi_dlevel_offset(pin
);
318 | dlevel
<< sunxi_dlevel_offset(pin
),
319 pctl
->membase
+ sunxi_dlevel_reg(pin
));
321 case PIN_CONFIG_BIAS_PULL_UP
:
322 val
= readl(pctl
->membase
+ sunxi_pull_reg(pin
));
323 mask
= PULL_PINS_MASK
<< sunxi_pull_offset(pin
);
324 writel((val
& ~mask
) | 1 << sunxi_pull_offset(pin
),
325 pctl
->membase
+ sunxi_pull_reg(pin
));
327 case PIN_CONFIG_BIAS_PULL_DOWN
:
328 val
= readl(pctl
->membase
+ sunxi_pull_reg(pin
));
329 mask
= PULL_PINS_MASK
<< sunxi_pull_offset(pin
);
330 writel((val
& ~mask
) | 2 << sunxi_pull_offset(pin
),
331 pctl
->membase
+ sunxi_pull_reg(pin
));
336 /* cache the config value */
337 g
->config
= configs
[i
];
338 } /* for each config */
340 spin_unlock_irqrestore(&pctl
->lock
, flags
);
345 static const struct pinconf_ops sunxi_pconf_ops
= {
346 .pin_config_group_get
= sunxi_pconf_group_get
,
347 .pin_config_group_set
= sunxi_pconf_group_set
,
350 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev
*pctldev
)
352 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
354 return pctl
->nfunctions
;
357 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
360 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
362 return pctl
->functions
[function
].name
;
365 static int sunxi_pmx_get_func_groups(struct pinctrl_dev
*pctldev
,
367 const char * const **groups
,
368 unsigned * const num_groups
)
370 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
372 *groups
= pctl
->functions
[function
].groups
;
373 *num_groups
= pctl
->functions
[function
].ngroups
;
378 static void sunxi_pmx_set(struct pinctrl_dev
*pctldev
,
382 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
386 spin_lock_irqsave(&pctl
->lock
, flags
);
388 pin
-= pctl
->desc
->pin_base
;
389 val
= readl(pctl
->membase
+ sunxi_mux_reg(pin
));
390 mask
= MUX_PINS_MASK
<< sunxi_mux_offset(pin
);
391 writel((val
& ~mask
) | config
<< sunxi_mux_offset(pin
),
392 pctl
->membase
+ sunxi_mux_reg(pin
));
394 spin_unlock_irqrestore(&pctl
->lock
, flags
);
397 static int sunxi_pmx_set_mux(struct pinctrl_dev
*pctldev
,
401 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
402 struct sunxi_pinctrl_group
*g
= pctl
->groups
+ group
;
403 struct sunxi_pinctrl_function
*func
= pctl
->functions
+ function
;
404 struct sunxi_desc_function
*desc
=
405 sunxi_pinctrl_desc_find_function_by_name(pctl
,
412 sunxi_pmx_set(pctldev
, g
->pin
, desc
->muxval
);
418 sunxi_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev
,
419 struct pinctrl_gpio_range
*range
,
423 struct sunxi_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
424 struct sunxi_desc_function
*desc
;
432 desc
= sunxi_pinctrl_desc_find_function_by_pin(pctl
, offset
, func
);
436 sunxi_pmx_set(pctldev
, offset
, desc
->muxval
);
441 static const struct pinmux_ops sunxi_pmx_ops
= {
442 .get_functions_count
= sunxi_pmx_get_funcs_cnt
,
443 .get_function_name
= sunxi_pmx_get_func_name
,
444 .get_function_groups
= sunxi_pmx_get_func_groups
,
445 .set_mux
= sunxi_pmx_set_mux
,
446 .gpio_set_direction
= sunxi_pmx_gpio_set_direction
,
449 static int sunxi_pinctrl_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
451 return pinctrl_request_gpio(chip
->base
+ offset
);
454 static void sunxi_pinctrl_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
456 pinctrl_free_gpio(chip
->base
+ offset
);
459 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip
*chip
,
462 return pinctrl_gpio_direction_input(chip
->base
+ offset
);
465 static int sunxi_pinctrl_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
467 struct sunxi_pinctrl
*pctl
= dev_get_drvdata(chip
->dev
);
468 u32 reg
= sunxi_data_reg(offset
);
469 u8 index
= sunxi_data_offset(offset
);
470 u32 set_mux
= pctl
->desc
->irq_read_needs_mux
&&
471 test_bit(FLAG_USED_AS_IRQ
, &chip
->desc
[offset
].flags
);
475 sunxi_pmx_set(pctl
->pctl_dev
, offset
, SUN4I_FUNC_INPUT
);
477 val
= (readl(pctl
->membase
+ reg
) >> index
) & DATA_PINS_MASK
;
480 sunxi_pmx_set(pctl
->pctl_dev
, offset
, SUN4I_FUNC_IRQ
);
485 static void sunxi_pinctrl_gpio_set(struct gpio_chip
*chip
,
486 unsigned offset
, int value
)
488 struct sunxi_pinctrl
*pctl
= dev_get_drvdata(chip
->dev
);
489 u32 reg
= sunxi_data_reg(offset
);
490 u8 index
= sunxi_data_offset(offset
);
494 spin_lock_irqsave(&pctl
->lock
, flags
);
496 regval
= readl(pctl
->membase
+ reg
);
499 regval
|= BIT(index
);
501 regval
&= ~(BIT(index
));
503 writel(regval
, pctl
->membase
+ reg
);
505 spin_unlock_irqrestore(&pctl
->lock
, flags
);
508 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip
*chip
,
509 unsigned offset
, int value
)
511 sunxi_pinctrl_gpio_set(chip
, offset
, value
);
512 return pinctrl_gpio_direction_output(chip
->base
+ offset
);
515 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip
*gc
,
516 const struct of_phandle_args
*gpiospec
,
521 base
= PINS_PER_BANK
* gpiospec
->args
[0];
522 pin
= base
+ gpiospec
->args
[1];
528 *flags
= gpiospec
->args
[2];
533 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
535 struct sunxi_pinctrl
*pctl
= dev_get_drvdata(chip
->dev
);
536 struct sunxi_desc_function
*desc
;
537 unsigned pinnum
= pctl
->desc
->pin_base
+ offset
;
540 if (offset
>= chip
->ngpio
)
543 desc
= sunxi_pinctrl_desc_find_function_by_pin(pctl
, pinnum
, "irq");
547 irqnum
= desc
->irqbank
* IRQ_PER_BANK
+ desc
->irqnum
;
549 dev_dbg(chip
->dev
, "%s: request IRQ for GPIO %d, return %d\n",
550 chip
->label
, offset
+ chip
->base
, irqnum
);
552 return irq_find_mapping(pctl
->domain
, irqnum
);
555 static int sunxi_pinctrl_irq_request_resources(struct irq_data
*d
)
557 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
558 struct sunxi_desc_function
*func
;
561 func
= sunxi_pinctrl_desc_find_function_by_pin(pctl
,
562 pctl
->irq_array
[d
->hwirq
], "irq");
566 ret
= gpiochip_lock_as_irq(pctl
->chip
,
567 pctl
->irq_array
[d
->hwirq
] - pctl
->desc
->pin_base
);
569 dev_err(pctl
->dev
, "unable to lock HW IRQ %lu for IRQ\n",
574 /* Change muxing to INT mode */
575 sunxi_pmx_set(pctl
->pctl_dev
, pctl
->irq_array
[d
->hwirq
], func
->muxval
);
580 static void sunxi_pinctrl_irq_release_resources(struct irq_data
*d
)
582 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
584 gpiochip_unlock_as_irq(pctl
->chip
,
585 pctl
->irq_array
[d
->hwirq
] - pctl
->desc
->pin_base
);
588 static int sunxi_pinctrl_irq_set_type(struct irq_data
*d
, unsigned int type
)
590 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
591 u32 reg
= sunxi_irq_cfg_reg(d
->hwirq
);
592 u8 index
= sunxi_irq_cfg_offset(d
->hwirq
);
598 case IRQ_TYPE_EDGE_RISING
:
599 mode
= IRQ_EDGE_RISING
;
601 case IRQ_TYPE_EDGE_FALLING
:
602 mode
= IRQ_EDGE_FALLING
;
604 case IRQ_TYPE_EDGE_BOTH
:
605 mode
= IRQ_EDGE_BOTH
;
607 case IRQ_TYPE_LEVEL_HIGH
:
608 mode
= IRQ_LEVEL_HIGH
;
610 case IRQ_TYPE_LEVEL_LOW
:
611 mode
= IRQ_LEVEL_LOW
;
617 spin_lock_irqsave(&pctl
->lock
, flags
);
619 if (type
& IRQ_TYPE_LEVEL_MASK
)
620 __irq_set_chip_handler_name_locked(d
->irq
,
621 &sunxi_pinctrl_level_irq_chip
,
622 handle_fasteoi_irq
, NULL
);
624 __irq_set_chip_handler_name_locked(d
->irq
,
625 &sunxi_pinctrl_edge_irq_chip
,
626 handle_edge_irq
, NULL
);
628 regval
= readl(pctl
->membase
+ reg
);
629 regval
&= ~(IRQ_CFG_IRQ_MASK
<< index
);
630 writel(regval
| (mode
<< index
), pctl
->membase
+ reg
);
632 spin_unlock_irqrestore(&pctl
->lock
, flags
);
637 static void sunxi_pinctrl_irq_ack(struct irq_data
*d
)
639 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
640 u32 status_reg
= sunxi_irq_status_reg(d
->hwirq
);
641 u8 status_idx
= sunxi_irq_status_offset(d
->hwirq
);
644 writel(1 << status_idx
, pctl
->membase
+ status_reg
);
647 static void sunxi_pinctrl_irq_mask(struct irq_data
*d
)
649 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
650 u32 reg
= sunxi_irq_ctrl_reg(d
->hwirq
);
651 u8 idx
= sunxi_irq_ctrl_offset(d
->hwirq
);
655 spin_lock_irqsave(&pctl
->lock
, flags
);
658 val
= readl(pctl
->membase
+ reg
);
659 writel(val
& ~(1 << idx
), pctl
->membase
+ reg
);
661 spin_unlock_irqrestore(&pctl
->lock
, flags
);
664 static void sunxi_pinctrl_irq_unmask(struct irq_data
*d
)
666 struct sunxi_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
667 u32 reg
= sunxi_irq_ctrl_reg(d
->hwirq
);
668 u8 idx
= sunxi_irq_ctrl_offset(d
->hwirq
);
672 spin_lock_irqsave(&pctl
->lock
, flags
);
675 val
= readl(pctl
->membase
+ reg
);
676 writel(val
| (1 << idx
), pctl
->membase
+ reg
);
678 spin_unlock_irqrestore(&pctl
->lock
, flags
);
681 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data
*d
)
683 sunxi_pinctrl_irq_ack(d
);
684 sunxi_pinctrl_irq_unmask(d
);
687 static struct irq_chip sunxi_pinctrl_edge_irq_chip
= {
688 .name
= "sunxi_pio_edge",
689 .irq_ack
= sunxi_pinctrl_irq_ack
,
690 .irq_mask
= sunxi_pinctrl_irq_mask
,
691 .irq_unmask
= sunxi_pinctrl_irq_unmask
,
692 .irq_request_resources
= sunxi_pinctrl_irq_request_resources
,
693 .irq_release_resources
= sunxi_pinctrl_irq_release_resources
,
694 .irq_set_type
= sunxi_pinctrl_irq_set_type
,
695 .flags
= IRQCHIP_SKIP_SET_WAKE
,
698 static struct irq_chip sunxi_pinctrl_level_irq_chip
= {
699 .name
= "sunxi_pio_level",
700 .irq_eoi
= sunxi_pinctrl_irq_ack
,
701 .irq_mask
= sunxi_pinctrl_irq_mask
,
702 .irq_unmask
= sunxi_pinctrl_irq_unmask
,
703 /* Define irq_enable / disable to avoid spurious irqs for drivers
704 * using these to suppress irqs while they clear the irq source */
705 .irq_enable
= sunxi_pinctrl_irq_ack_unmask
,
706 .irq_disable
= sunxi_pinctrl_irq_mask
,
707 .irq_request_resources
= sunxi_pinctrl_irq_request_resources
,
708 .irq_release_resources
= sunxi_pinctrl_irq_release_resources
,
709 .irq_set_type
= sunxi_pinctrl_irq_set_type
,
710 .flags
= IRQCHIP_SKIP_SET_WAKE
| IRQCHIP_EOI_THREADED
|
711 IRQCHIP_EOI_IF_HANDLED
,
714 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain
*d
,
715 struct device_node
*node
,
717 unsigned int intsize
,
718 unsigned long *out_hwirq
,
719 unsigned int *out_type
)
721 struct sunxi_desc_function
*desc
;
727 base
= PINS_PER_BANK
* intspec
[0];
728 pin
= base
+ intspec
[1];
730 desc
= sunxi_pinctrl_desc_find_function_by_pin(d
->host_data
,
735 *out_hwirq
= desc
->irqbank
* PINS_PER_BANK
+ desc
->irqnum
;
736 *out_type
= intspec
[2];
741 static struct irq_domain_ops sunxi_pinctrl_irq_domain_ops
= {
742 .xlate
= sunxi_pinctrl_irq_of_xlate
,
745 static void sunxi_pinctrl_irq_handler(unsigned __irq
, struct irq_desc
*desc
)
747 unsigned int irq
= irq_desc_get_irq(desc
);
748 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
749 struct sunxi_pinctrl
*pctl
= irq_desc_get_handler_data(desc
);
750 unsigned long bank
, reg
, val
;
752 for (bank
= 0; bank
< pctl
->desc
->irq_banks
; bank
++)
753 if (irq
== pctl
->irq
[bank
])
756 if (bank
== pctl
->desc
->irq_banks
)
759 reg
= sunxi_irq_status_reg_from_bank(bank
);
760 val
= readl(pctl
->membase
+ reg
);
765 chained_irq_enter(chip
, desc
);
766 for_each_set_bit(irqoffset
, &val
, IRQ_PER_BANK
) {
767 int pin_irq
= irq_find_mapping(pctl
->domain
,
768 bank
* IRQ_PER_BANK
+ irqoffset
);
769 generic_handle_irq(pin_irq
);
771 chained_irq_exit(chip
, desc
);
775 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl
*pctl
,
778 struct sunxi_pinctrl_function
*func
= pctl
->functions
;
781 /* function already there */
782 if (strcmp(func
->name
, name
) == 0) {
797 static int sunxi_pinctrl_build_state(struct platform_device
*pdev
)
799 struct sunxi_pinctrl
*pctl
= platform_get_drvdata(pdev
);
802 pctl
->ngroups
= pctl
->desc
->npins
;
804 /* Allocate groups */
805 pctl
->groups
= devm_kzalloc(&pdev
->dev
,
806 pctl
->ngroups
* sizeof(*pctl
->groups
),
811 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
812 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
813 struct sunxi_pinctrl_group
*group
= pctl
->groups
+ i
;
815 group
->name
= pin
->pin
.name
;
816 group
->pin
= pin
->pin
.number
;
820 * We suppose that we won't have any more functions than pins,
821 * we'll reallocate that later anyway
823 pctl
->functions
= devm_kzalloc(&pdev
->dev
,
824 pctl
->desc
->npins
* sizeof(*pctl
->functions
),
826 if (!pctl
->functions
)
829 /* Count functions and their associated groups */
830 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
831 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
832 struct sunxi_desc_function
*func
= pin
->functions
;
835 /* Create interrupt mapping while we're at it */
836 if (!strcmp(func
->name
, "irq")) {
837 int irqnum
= func
->irqnum
+ func
->irqbank
* IRQ_PER_BANK
;
838 pctl
->irq_array
[irqnum
] = pin
->pin
.number
;
841 sunxi_pinctrl_add_function(pctl
, func
->name
);
846 pctl
->functions
= krealloc(pctl
->functions
,
847 pctl
->nfunctions
* sizeof(*pctl
->functions
),
850 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
851 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
852 struct sunxi_desc_function
*func
= pin
->functions
;
855 struct sunxi_pinctrl_function
*func_item
;
856 const char **func_grp
;
858 func_item
= sunxi_pinctrl_find_function_by_name(pctl
,
863 if (!func_item
->groups
) {
865 devm_kzalloc(&pdev
->dev
,
866 func_item
->ngroups
* sizeof(*func_item
->groups
),
868 if (!func_item
->groups
)
872 func_grp
= func_item
->groups
;
876 *func_grp
= pin
->pin
.name
;
884 int sunxi_pinctrl_init(struct platform_device
*pdev
,
885 const struct sunxi_pinctrl_desc
*desc
)
887 struct device_node
*node
= pdev
->dev
.of_node
;
888 struct pinctrl_desc
*pctrl_desc
;
889 struct pinctrl_pin_desc
*pins
;
890 struct sunxi_pinctrl
*pctl
;
891 struct resource
*res
;
892 int i
, ret
, last_pin
;
895 pctl
= devm_kzalloc(&pdev
->dev
, sizeof(*pctl
), GFP_KERNEL
);
898 platform_set_drvdata(pdev
, pctl
);
900 spin_lock_init(&pctl
->lock
);
902 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
903 pctl
->membase
= devm_ioremap_resource(&pdev
->dev
, res
);
904 if (IS_ERR(pctl
->membase
))
905 return PTR_ERR(pctl
->membase
);
907 pctl
->dev
= &pdev
->dev
;
910 pctl
->irq_array
= devm_kcalloc(&pdev
->dev
,
911 IRQ_PER_BANK
* pctl
->desc
->irq_banks
,
912 sizeof(*pctl
->irq_array
),
914 if (!pctl
->irq_array
)
917 ret
= sunxi_pinctrl_build_state(pdev
);
919 dev_err(&pdev
->dev
, "dt probe failed: %d\n", ret
);
923 pins
= devm_kzalloc(&pdev
->dev
,
924 pctl
->desc
->npins
* sizeof(*pins
),
929 for (i
= 0; i
< pctl
->desc
->npins
; i
++)
930 pins
[i
] = pctl
->desc
->pins
[i
].pin
;
932 pctrl_desc
= devm_kzalloc(&pdev
->dev
,
938 pctrl_desc
->name
= dev_name(&pdev
->dev
);
939 pctrl_desc
->owner
= THIS_MODULE
;
940 pctrl_desc
->pins
= pins
;
941 pctrl_desc
->npins
= pctl
->desc
->npins
;
942 pctrl_desc
->confops
= &sunxi_pconf_ops
;
943 pctrl_desc
->pctlops
= &sunxi_pctrl_ops
;
944 pctrl_desc
->pmxops
= &sunxi_pmx_ops
;
946 pctl
->pctl_dev
= pinctrl_register(pctrl_desc
,
948 if (IS_ERR(pctl
->pctl_dev
)) {
949 dev_err(&pdev
->dev
, "couldn't register pinctrl driver\n");
950 return PTR_ERR(pctl
->pctl_dev
);
953 pctl
->chip
= devm_kzalloc(&pdev
->dev
, sizeof(*pctl
->chip
), GFP_KERNEL
);
959 last_pin
= pctl
->desc
->pins
[pctl
->desc
->npins
- 1].pin
.number
;
960 pctl
->chip
->owner
= THIS_MODULE
;
961 pctl
->chip
->request
= sunxi_pinctrl_gpio_request
,
962 pctl
->chip
->free
= sunxi_pinctrl_gpio_free
,
963 pctl
->chip
->direction_input
= sunxi_pinctrl_gpio_direction_input
,
964 pctl
->chip
->direction_output
= sunxi_pinctrl_gpio_direction_output
,
965 pctl
->chip
->get
= sunxi_pinctrl_gpio_get
,
966 pctl
->chip
->set
= sunxi_pinctrl_gpio_set
,
967 pctl
->chip
->of_xlate
= sunxi_pinctrl_gpio_of_xlate
,
968 pctl
->chip
->to_irq
= sunxi_pinctrl_gpio_to_irq
,
969 pctl
->chip
->of_gpio_n_cells
= 3,
970 pctl
->chip
->can_sleep
= false,
971 pctl
->chip
->ngpio
= round_up(last_pin
, PINS_PER_BANK
) -
972 pctl
->desc
->pin_base
;
973 pctl
->chip
->label
= dev_name(&pdev
->dev
);
974 pctl
->chip
->dev
= &pdev
->dev
;
975 pctl
->chip
->base
= pctl
->desc
->pin_base
;
977 ret
= gpiochip_add(pctl
->chip
);
981 for (i
= 0; i
< pctl
->desc
->npins
; i
++) {
982 const struct sunxi_desc_pin
*pin
= pctl
->desc
->pins
+ i
;
984 ret
= gpiochip_add_pin_range(pctl
->chip
, dev_name(&pdev
->dev
),
985 pin
->pin
.number
- pctl
->desc
->pin_base
,
991 clk
= devm_clk_get(&pdev
->dev
, NULL
);
997 ret
= clk_prepare_enable(clk
);
1001 pctl
->irq
= devm_kcalloc(&pdev
->dev
,
1002 pctl
->desc
->irq_banks
,
1010 for (i
= 0; i
< pctl
->desc
->irq_banks
; i
++) {
1011 pctl
->irq
[i
] = platform_get_irq(pdev
, i
);
1012 if (pctl
->irq
[i
] < 0) {
1018 pctl
->domain
= irq_domain_add_linear(node
,
1019 pctl
->desc
->irq_banks
* IRQ_PER_BANK
,
1020 &sunxi_pinctrl_irq_domain_ops
,
1022 if (!pctl
->domain
) {
1023 dev_err(&pdev
->dev
, "Couldn't register IRQ domain\n");
1028 for (i
= 0; i
< (pctl
->desc
->irq_banks
* IRQ_PER_BANK
); i
++) {
1029 int irqno
= irq_create_mapping(pctl
->domain
, i
);
1031 irq_set_chip_and_handler(irqno
, &sunxi_pinctrl_edge_irq_chip
,
1033 irq_set_chip_data(irqno
, pctl
);
1036 for (i
= 0; i
< pctl
->desc
->irq_banks
; i
++) {
1037 /* Mask and clear all IRQs before registering a handler */
1038 writel(0, pctl
->membase
+ sunxi_irq_ctrl_reg_from_bank(i
));
1040 pctl
->membase
+ sunxi_irq_status_reg_from_bank(i
));
1042 irq_set_chained_handler_and_data(pctl
->irq
[i
],
1043 sunxi_pinctrl_irq_handler
,
1047 dev_info(&pdev
->dev
, "initialized sunXi PIO driver\n");
1052 clk_disable_unprepare(clk
);
1054 gpiochip_remove(pctl
->chip
);
1056 pinctrl_unregister(pctl
->pctl_dev
);