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git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/pinctrl/sunxi/pinctrl-sunxi.h
2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #ifndef __PINCTRL_SUNXI_H
14 #define __PINCTRL_SUNXI_H
16 #include <linux/kernel.h>
17 #include <linux/spinlock.h>
32 #define SUNXI_PINCTRL_PIN(bank, pin) \
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
35 #define SUNXI_PIN_NAME_MAX_LEN 5
37 #define BANK_MEM_SIZE 0x24
38 #define MUX_REGS_OFFSET 0x0
39 #define DATA_REGS_OFFSET 0x10
40 #define DLEVEL_REGS_OFFSET 0x14
41 #define PULL_REGS_OFFSET 0x1c
43 #define PINS_PER_BANK 32
44 #define MUX_PINS_PER_REG 8
45 #define MUX_PINS_BITS 4
46 #define MUX_PINS_MASK 0x0f
47 #define DATA_PINS_PER_REG 32
48 #define DATA_PINS_BITS 1
49 #define DATA_PINS_MASK 0x01
50 #define DLEVEL_PINS_PER_REG 16
51 #define DLEVEL_PINS_BITS 2
52 #define DLEVEL_PINS_MASK 0x03
53 #define PULL_PINS_PER_REG 16
54 #define PULL_PINS_BITS 2
55 #define PULL_PINS_MASK 0x03
57 #define IRQ_PER_BANK 32
59 #define IRQ_CFG_REG 0x200
60 #define IRQ_CFG_IRQ_PER_REG 8
61 #define IRQ_CFG_IRQ_BITS 4
62 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
63 #define IRQ_CTRL_REG 0x210
64 #define IRQ_CTRL_IRQ_PER_REG 32
65 #define IRQ_CTRL_IRQ_BITS 1
66 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
67 #define IRQ_STATUS_REG 0x214
68 #define IRQ_STATUS_IRQ_PER_REG 32
69 #define IRQ_STATUS_IRQ_BITS 1
70 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
72 #define IRQ_MEM_SIZE 0x20
74 #define IRQ_EDGE_RISING 0x00
75 #define IRQ_EDGE_FALLING 0x01
76 #define IRQ_LEVEL_HIGH 0x02
77 #define IRQ_LEVEL_LOW 0x03
78 #define IRQ_EDGE_BOTH 0x04
80 #define SUN4I_FUNC_INPUT 0
81 #define SUN4I_FUNC_IRQ 6
83 struct sunxi_desc_function
{
90 struct sunxi_desc_pin
{
91 struct pinctrl_pin_desc pin
;
92 struct sunxi_desc_function
*functions
;
95 struct sunxi_pinctrl_desc
{
96 const struct sunxi_desc_pin
*pins
;
100 bool irq_read_needs_mux
;
103 struct sunxi_pinctrl_function
{
109 struct sunxi_pinctrl_group
{
111 unsigned long config
;
115 struct sunxi_pinctrl
{
116 void __iomem
*membase
;
117 struct gpio_chip
*chip
;
118 const struct sunxi_pinctrl_desc
*desc
;
120 struct irq_domain
*domain
;
121 struct sunxi_pinctrl_function
*functions
;
123 struct sunxi_pinctrl_group
*groups
;
128 struct pinctrl_dev
*pctl_dev
;
131 #define SUNXI_PIN(_pin, ...) \
134 .functions = (struct sunxi_desc_function[]){ \
135 __VA_ARGS__, { } }, \
138 #define SUNXI_FUNCTION(_val, _name) \
144 #define SUNXI_FUNCTION_IRQ(_val, _irq) \
151 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
160 * The sunXi PIO registers are organized as is:
161 * 0x00 - 0x0c Muxing values.
162 * 8 pins per register, each pin having a 4bits value
164 * 32 bits per register, each pin corresponding to one bit
165 * 0x14 - 0x18 Drive level
166 * 16 pins per register, each pin having a 2bits value
167 * 0x1c - 0x20 Pull-Up values
168 * 16 pins per register, each pin having a 2bits value
170 * This is for the first bank. Each bank will have the same layout,
171 * with an offset being a multiple of 0x24.
173 * The following functions calculate from the pin number the register
174 * and the bit offset that we should access.
176 static inline u32
sunxi_mux_reg(u16 pin
)
178 u8 bank
= pin
/ PINS_PER_BANK
;
179 u32 offset
= bank
* BANK_MEM_SIZE
;
180 offset
+= MUX_REGS_OFFSET
;
181 offset
+= pin
% PINS_PER_BANK
/ MUX_PINS_PER_REG
* 0x04;
182 return round_down(offset
, 4);
185 static inline u32
sunxi_mux_offset(u16 pin
)
187 u32 pin_num
= pin
% MUX_PINS_PER_REG
;
188 return pin_num
* MUX_PINS_BITS
;
191 static inline u32
sunxi_data_reg(u16 pin
)
193 u8 bank
= pin
/ PINS_PER_BANK
;
194 u32 offset
= bank
* BANK_MEM_SIZE
;
195 offset
+= DATA_REGS_OFFSET
;
196 offset
+= pin
% PINS_PER_BANK
/ DATA_PINS_PER_REG
* 0x04;
197 return round_down(offset
, 4);
200 static inline u32
sunxi_data_offset(u16 pin
)
202 u32 pin_num
= pin
% DATA_PINS_PER_REG
;
203 return pin_num
* DATA_PINS_BITS
;
206 static inline u32
sunxi_dlevel_reg(u16 pin
)
208 u8 bank
= pin
/ PINS_PER_BANK
;
209 u32 offset
= bank
* BANK_MEM_SIZE
;
210 offset
+= DLEVEL_REGS_OFFSET
;
211 offset
+= pin
% PINS_PER_BANK
/ DLEVEL_PINS_PER_REG
* 0x04;
212 return round_down(offset
, 4);
215 static inline u32
sunxi_dlevel_offset(u16 pin
)
217 u32 pin_num
= pin
% DLEVEL_PINS_PER_REG
;
218 return pin_num
* DLEVEL_PINS_BITS
;
221 static inline u32
sunxi_pull_reg(u16 pin
)
223 u8 bank
= pin
/ PINS_PER_BANK
;
224 u32 offset
= bank
* BANK_MEM_SIZE
;
225 offset
+= PULL_REGS_OFFSET
;
226 offset
+= pin
% PINS_PER_BANK
/ PULL_PINS_PER_REG
* 0x04;
227 return round_down(offset
, 4);
230 static inline u32
sunxi_pull_offset(u16 pin
)
232 u32 pin_num
= pin
% PULL_PINS_PER_REG
;
233 return pin_num
* PULL_PINS_BITS
;
236 static inline u32
sunxi_irq_cfg_reg(u16 irq
)
238 u8 bank
= irq
/ IRQ_PER_BANK
;
239 u8 reg
= (irq
% IRQ_PER_BANK
) / IRQ_CFG_IRQ_PER_REG
* 0x04;
241 return IRQ_CFG_REG
+ bank
* IRQ_MEM_SIZE
+ reg
;
244 static inline u32
sunxi_irq_cfg_offset(u16 irq
)
246 u32 irq_num
= irq
% IRQ_CFG_IRQ_PER_REG
;
247 return irq_num
* IRQ_CFG_IRQ_BITS
;
250 static inline u32
sunxi_irq_ctrl_reg_from_bank(u8 bank
)
252 return IRQ_CTRL_REG
+ bank
* IRQ_MEM_SIZE
;
255 static inline u32
sunxi_irq_ctrl_reg(u16 irq
)
257 u8 bank
= irq
/ IRQ_PER_BANK
;
259 return sunxi_irq_ctrl_reg_from_bank(bank
);
262 static inline u32
sunxi_irq_ctrl_offset(u16 irq
)
264 u32 irq_num
= irq
% IRQ_CTRL_IRQ_PER_REG
;
265 return irq_num
* IRQ_CTRL_IRQ_BITS
;
268 static inline u32
sunxi_irq_status_reg_from_bank(u8 bank
)
270 return IRQ_STATUS_REG
+ bank
* IRQ_MEM_SIZE
;
273 static inline u32
sunxi_irq_status_reg(u16 irq
)
275 u8 bank
= irq
/ IRQ_PER_BANK
;
277 return sunxi_irq_status_reg_from_bank(bank
);
280 static inline u32
sunxi_irq_status_offset(u16 irq
)
282 u32 irq_num
= irq
% IRQ_STATUS_IRQ_PER_REG
;
283 return irq_num
* IRQ_STATUS_IRQ_BITS
;
286 int sunxi_pinctrl_init(struct platform_device
*pdev
,
287 const struct sunxi_pinctrl_desc
*desc
);
289 #endif /* __PINCTRL_SUNXI_H */