drivers/platform/x86/intel_mid_powerbtn.c

   1 /*
   2  * Power button driver for Intel MID platforms.
   3  *
   4  * Copyright (C) 2010,2017 Intel Corp
   5  *
   6  * Author: Hong Liu <hong.liu@intel.com>
   7  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  16  * General Public License for more details.
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/input.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/mfd/intel_msic.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_wakeirq.h>
  26 #include <linux/slab.h>
  27
  28 #include <asm/cpu_device_id.h>
  29 #include <asm/intel-family.h>
  30 #include <asm/intel_scu_ipc.h>
  31
  32 #define DRIVER_NAME "msic_power_btn"
  33
  34 #define MSIC_PB_LEVEL   (1 << 3) /* 1 - release, 0 - press */
  35
  36 /*
  37  * MSIC document ti_datasheet defines the 1st bit reg 0x21 is used to mask
  38  * power button interrupt
  39  */
  40 #define MSIC_PWRBTNM    (1 << 0)
  41
  42 /* Intel Tangier */
  43 #define BCOVE_PB_LEVEL          (1 << 4)        /* 1 - release, 0 - press */
  44
  45 /* Basin Cove PMIC */
  46 #define BCOVE_PBIRQ             0x02
  47 #define BCOVE_IRQLVL1MSK        0x0c
  48 #define BCOVE_PBIRQMASK         0x0d
  49 #define BCOVE_PBSTATUS          0x27
  50
  51 struct mid_pb_ddata {
  52         struct device *dev;
  53         int irq;
  54         struct input_dev *input;
  55         unsigned short mirqlvl1_addr;
  56         unsigned short pbstat_addr;
  57         u8 pbstat_mask;
  58         int (*setup)(struct mid_pb_ddata *ddata);
  59 };
  60
  61 static int mid_pbstat(struct mid_pb_ddata *ddata, int *value)
  62 {
  63         struct input_dev *input = ddata->input;
  64         int ret;
  65         u8 pbstat;
  66
  67         ret = intel_scu_ipc_ioread8(ddata->pbstat_addr, &pbstat);
  68         if (ret)
  69                 return ret;
  70
  71         dev_dbg(input->dev.parent, "PB_INT status= %d\n", pbstat);
  72
  73         *value = !(pbstat & ddata->pbstat_mask);
  74         return 0;
  75 }
  76
  77 static int mid_irq_ack(struct mid_pb_ddata *ddata)
  78 {
  79         return intel_scu_ipc_update_register(ddata->mirqlvl1_addr, 0, MSIC_PWRBTNM);
  80 }
  81
  82 static int mrfld_setup(struct mid_pb_ddata *ddata)
  83 {
  84         /* Unmask the PBIRQ and MPBIRQ on Tangier */
  85         intel_scu_ipc_update_register(BCOVE_PBIRQ, 0, MSIC_PWRBTNM);
  86         intel_scu_ipc_update_register(BCOVE_PBIRQMASK, 0, MSIC_PWRBTNM);
  87
  88         return 0;
  89 }
  90
  91 static irqreturn_t mid_pb_isr(int irq, void *dev_id)
  92 {
  93         struct mid_pb_ddata *ddata = dev_id;
  94         struct input_dev *input = ddata->input;
  95         int value = 0;
  96         int ret;
  97
  98         ret = mid_pbstat(ddata, &value);
  99         if (ret < 0) {
 100                 dev_err(input->dev.parent,
 101                         "Read error %d while reading MSIC_PB_STATUS\n", ret);
 102         } else {
 103                 input_event(input, EV_KEY, KEY_POWER, value);
 104                 input_sync(input);
 105         }
 106
 107         mid_irq_ack(ddata);
 108         return IRQ_HANDLED;
 109 }
 110
 111 static struct mid_pb_ddata mfld_ddata = {
 112         .mirqlvl1_addr  = INTEL_MSIC_IRQLVL1MSK,
 113         .pbstat_addr    = INTEL_MSIC_PBSTATUS,
 114         .pbstat_mask    = MSIC_PB_LEVEL,
 115 };
 116
 117 static struct mid_pb_ddata mrfld_ddata = {
 118         .mirqlvl1_addr  = BCOVE_IRQLVL1MSK,
 119         .pbstat_addr    = BCOVE_PBSTATUS,
 120         .pbstat_mask    = BCOVE_PB_LEVEL,
 121         .setup  = mrfld_setup,
 122 };
 123
 124 #define ICPU(model, ddata)      \
 125         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (kernel_ulong_t)&ddata }
 126
 127 static const struct x86_cpu_id mid_pb_cpu_ids[] = {
 128         ICPU(INTEL_FAM6_ATOM_PENWELL,           mfld_ddata),
 129         ICPU(INTEL_FAM6_ATOM_MERRIFIELD,        mrfld_ddata),
 130         {}
 131 };
 132
 133 static int mid_pb_probe(struct platform_device *pdev)
 134 {
 135         const struct x86_cpu_id *id;
 136         struct mid_pb_ddata *ddata;
 137         struct input_dev *input;
 138         int irq = platform_get_irq(pdev, 0);
 139         int error;
 140
 141         id = x86_match_cpu(mid_pb_cpu_ids);
 142         if (!id)
 143                 return -ENODEV;
 144
 145         if (irq < 0)
 146                 return -EINVAL;
 147
 148         input = devm_input_allocate_device(&pdev->dev);
 149         if (!input)
 150                 return -ENOMEM;
 151
 152         input->name = pdev->name;
 153         input->phys = "power-button/input0";
 154         input->id.bustype = BUS_HOST;
 155         input->dev.parent = &pdev->dev;
 156
 157         input_set_capability(input, EV_KEY, KEY_POWER);
 158
 159         ddata = (struct mid_pb_ddata *)id->driver_data;
 160         if (!ddata)
 161                 return -ENODATA;
 162
 163         ddata->dev = &pdev->dev;
 164         ddata->irq = irq;
 165         ddata->input = input;
 166
 167         if (ddata->setup) {
 168                 error = ddata->setup(ddata);
 169                 if (error)
 170                         return error;
 171         }
 172
 173         error = devm_request_threaded_irq(&pdev->dev, irq, NULL, mid_pb_isr,
 174                                           IRQF_ONESHOT, DRIVER_NAME, ddata);
 175         if (error) {
 176                 dev_err(&pdev->dev,
 177                         "Unable to request irq %d for MID power button\n", irq);
 178                 return error;
 179         }
 180
 181         error = input_register_device(input);
 182         if (error) {
 183                 dev_err(&pdev->dev,
 184                         "Unable to register input dev, error %d\n", error);
 185                 return error;
 186         }
 187
 188         platform_set_drvdata(pdev, ddata);
 189
 190         /*
 191          * SCU firmware might send power button interrupts to IA core before
 192          * kernel boots and doesn't get EOI from IA core. The first bit of
 193          * MSIC reg 0x21 is kept masked, and SCU firmware doesn't send new
 194          * power interrupt to Android kernel. Unmask the bit when probing
 195          * power button in kernel.
 196          * There is a very narrow race between irq handler and power button
 197          * initialization. The race happens rarely. So we needn't worry
 198          * about it.
 199          */
 200         error = mid_irq_ack(ddata);
 201         if (error) {
 202                 dev_err(&pdev->dev,
 203                         "Unable to clear power button interrupt, error: %d\n",
 204                         error);
 205                 return error;
 206         }
 207
 208         device_init_wakeup(&pdev->dev, true);
 209         dev_pm_set_wake_irq(&pdev->dev, irq);
 210
 211         return 0;
 212 }
 213
 214 static int mid_pb_remove(struct platform_device *pdev)
 215 {
 216         dev_pm_clear_wake_irq(&pdev->dev);
 217         device_init_wakeup(&pdev->dev, false);
 218
 219         return 0;
 220 }
 221
 222 static struct platform_driver mid_pb_driver = {
 223         .driver = {
 224                 .name = DRIVER_NAME,
 225         },
 226         .probe  = mid_pb_probe,
 227         .remove = mid_pb_remove,
 228 };
 229
 230 module_platform_driver(mid_pb_driver);
 231
 232 MODULE_AUTHOR("Hong Liu <hong.liu@intel.com>");
 233 MODULE_DESCRIPTION("Intel MID Power Button Driver");
 234 MODULE_LICENSE("GPL v2");
 235 MODULE_ALIAS("platform:" DRIVER_NAME);