2 * Intel Core SoC Power Management Controller Driver
4 * Copyright (c) 2016, Intel Corporation.
7 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
8 * Vishwanath Somayaji <vishwanath.somayaji@intel.com>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 #include <linux/debugfs.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/uaccess.h>
29 #include <asm/cpu_device_id.h>
30 #include <asm/intel-family.h>
31 #include <asm/pmc_core.h>
33 #include "intel_pmc_core.h"
35 static struct pmc_dev pmc
;
37 static const struct pmc_bit_map spt_pll_map
[] = {
38 {"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0
},
39 {"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1
},
40 {"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2
},
41 {"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3
},
45 static const struct pmc_bit_map spt_mphy_map
[] = {
46 {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0
},
47 {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1
},
48 {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2
},
49 {"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3
},
50 {"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4
},
51 {"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5
},
52 {"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6
},
53 {"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7
},
54 {"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8
},
55 {"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9
},
56 {"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10
},
57 {"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11
},
58 {"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12
},
59 {"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13
},
60 {"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14
},
61 {"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15
},
65 static const struct pmc_bit_map spt_pfear_map
[] = {
66 {"PMC", SPT_PMC_BIT_PMC
},
67 {"OPI-DMI", SPT_PMC_BIT_OPI
},
68 {"SPI / eSPI", SPT_PMC_BIT_SPI
},
69 {"XHCI", SPT_PMC_BIT_XHCI
},
70 {"SPA", SPT_PMC_BIT_SPA
},
71 {"SPB", SPT_PMC_BIT_SPB
},
72 {"SPC", SPT_PMC_BIT_SPC
},
73 {"GBE", SPT_PMC_BIT_GBE
},
74 {"SATA", SPT_PMC_BIT_SATA
},
75 {"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0
},
76 {"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1
},
77 {"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2
},
78 {"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3
},
79 {"RSVD", SPT_PMC_BIT_RSVD_0B
},
80 {"LPSS", SPT_PMC_BIT_LPSS
},
81 {"LPC", SPT_PMC_BIT_LPC
},
82 {"SMB", SPT_PMC_BIT_SMB
},
83 {"ISH", SPT_PMC_BIT_ISH
},
84 {"P2SB", SPT_PMC_BIT_P2SB
},
85 {"DFX", SPT_PMC_BIT_DFX
},
86 {"SCC", SPT_PMC_BIT_SCC
},
87 {"RSVD", SPT_PMC_BIT_RSVD_0C
},
88 {"FUSE", SPT_PMC_BIT_FUSE
},
89 {"CAMERA", SPT_PMC_BIT_CAMREA
},
90 {"RSVD", SPT_PMC_BIT_RSVD_0D
},
91 {"USB3-OTG", SPT_PMC_BIT_USB3_OTG
},
92 {"EXI", SPT_PMC_BIT_EXI
},
93 {"CSE", SPT_PMC_BIT_CSE
},
94 {"CSME_KVM", SPT_PMC_BIT_CSME_KVM
},
95 {"CSME_PMT", SPT_PMC_BIT_CSME_PMT
},
96 {"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK
},
97 {"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO
},
98 {"CSME_USBR", SPT_PMC_BIT_CSME_USBR
},
99 {"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM
},
100 {"CSME_SMT", SPT_PMC_BIT_CSME_SMT
},
101 {"RSVD", SPT_PMC_BIT_RSVD_1A
},
102 {"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2
},
103 {"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1
},
104 {"CSME_RTC", SPT_PMC_BIT_CSME_RTC
},
105 {"CSME_PSF", SPT_PMC_BIT_CSME_PSF
},
109 static const struct pmc_reg_map spt_reg_map
= {
110 .pfear_sts
= spt_pfear_map
,
111 .mphy_sts
= spt_mphy_map
,
112 .pll_sts
= spt_pll_map
,
113 .slp_s0_offset
= SPT_PMC_SLP_S0_RES_COUNTER_OFFSET
,
114 .ltr_ignore_offset
= SPT_PMC_LTR_IGNORE_OFFSET
,
115 .regmap_length
= SPT_PMC_MMIO_REG_LEN
,
116 .ppfear0_offset
= SPT_PMC_XRAM_PPFEAR0A
,
117 .ppfear_buckets
= SPT_PPFEAR_NUM_ENTRIES
,
118 .pm_cfg_offset
= SPT_PMC_PM_CFG_OFFSET
,
119 .pm_read_disable_bit
= SPT_PMC_READ_DISABLE_BIT
,
122 static const struct pci_device_id pmc_pci_ids
[] = {
123 { PCI_VDEVICE(INTEL
, SPT_PMC_PCI_DEVICE_ID
),
124 (kernel_ulong_t
)&spt_reg_map
},
127 MODULE_DEVICE_TABLE(pci
, pmc_pci_ids
);
129 static inline u8
pmc_core_reg_read_byte(struct pmc_dev
*pmcdev
, int offset
)
131 return readb(pmcdev
->regbase
+ offset
);
134 static inline u32
pmc_core_reg_read(struct pmc_dev
*pmcdev
, int reg_offset
)
136 return readl(pmcdev
->regbase
+ reg_offset
);
139 static inline void pmc_core_reg_write(struct pmc_dev
*pmcdev
, int
142 writel(val
, pmcdev
->regbase
+ reg_offset
);
145 static inline u32
pmc_core_adjust_slp_s0_step(u32 value
)
147 return value
* SPT_PMC_SLP_S0_RES_COUNTER_STEP
;
150 static int pmc_core_dev_state_get(void *data
, u64
*val
)
152 struct pmc_dev
*pmcdev
= data
;
153 const struct pmc_reg_map
*map
= pmcdev
->map
;
156 value
= pmc_core_reg_read(pmcdev
, map
->slp_s0_offset
);
157 *val
= pmc_core_adjust_slp_s0_step(value
);
162 DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state
, pmc_core_dev_state_get
, NULL
, "%llu\n");
164 static int pmc_core_check_read_lock_bit(void)
166 struct pmc_dev
*pmcdev
= &pmc
;
169 value
= pmc_core_reg_read(pmcdev
, pmcdev
->map
->pm_cfg_offset
);
170 return value
& BIT(pmcdev
->map
->pm_read_disable_bit
);
173 #if IS_ENABLED(CONFIG_DEBUG_FS)
174 static void pmc_core_display_map(struct seq_file
*s
, int index
,
175 u8 pf_reg
, const struct pmc_bit_map
*pf_map
)
177 seq_printf(s
, "PCH IP: %-2d - %-32s\tState: %s\n",
178 index
, pf_map
[index
].name
,
179 pf_map
[index
].bit_mask
& pf_reg
? "Off" : "On");
182 static int pmc_core_ppfear_sts_show(struct seq_file
*s
, void *unused
)
184 struct pmc_dev
*pmcdev
= s
->private;
185 const struct pmc_bit_map
*map
= pmcdev
->map
->pfear_sts
;
186 u8 pf_regs
[PPFEAR_MAX_NUM_ENTRIES
];
189 iter
= pmcdev
->map
->ppfear0_offset
;
191 for (index
= 0; index
< pmcdev
->map
->ppfear_buckets
&&
192 index
< PPFEAR_MAX_NUM_ENTRIES
; index
++, iter
++)
193 pf_regs
[index
] = pmc_core_reg_read_byte(pmcdev
, iter
);
195 for (index
= 0; map
[index
].name
; index
++)
196 pmc_core_display_map(s
, index
, pf_regs
[index
/ 8], map
);
201 static int pmc_core_ppfear_sts_open(struct inode
*inode
, struct file
*file
)
203 return single_open(file
, pmc_core_ppfear_sts_show
, inode
->i_private
);
206 static const struct file_operations pmc_core_ppfear_ops
= {
207 .open
= pmc_core_ppfear_sts_open
,
210 .release
= single_release
,
213 /* This function should return link status, 0 means ready */
214 static int pmc_core_mtpmc_link_status(void)
216 struct pmc_dev
*pmcdev
= &pmc
;
219 value
= pmc_core_reg_read(pmcdev
, SPT_PMC_PM_STS_OFFSET
);
220 return value
& BIT(SPT_PMC_MSG_FULL_STS_BIT
);
223 static int pmc_core_send_msg(u32
*addr_xram
)
225 struct pmc_dev
*pmcdev
= &pmc
;
229 for (timeout
= NUM_RETRIES
; timeout
> 0; timeout
--) {
230 if (pmc_core_mtpmc_link_status() == 0)
235 if (timeout
<= 0 && pmc_core_mtpmc_link_status())
238 dest
= (*addr_xram
& MTPMC_MASK
) | (1U << 1);
239 pmc_core_reg_write(pmcdev
, SPT_PMC_MTPMC_OFFSET
, dest
);
243 static int pmc_core_mphy_pg_sts_show(struct seq_file
*s
, void *unused
)
245 struct pmc_dev
*pmcdev
= s
->private;
246 const struct pmc_bit_map
*map
= pmcdev
->map
->mphy_sts
;
247 u32 mphy_core_reg_low
, mphy_core_reg_high
;
248 u32 val_low
, val_high
;
251 if (pmcdev
->pmc_xram_read_bit
) {
252 seq_puts(s
, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
256 mphy_core_reg_low
= (SPT_PMC_MPHY_CORE_STS_0
<< 16);
257 mphy_core_reg_high
= (SPT_PMC_MPHY_CORE_STS_1
<< 16);
259 mutex_lock(&pmcdev
->lock
);
261 if (pmc_core_send_msg(&mphy_core_reg_low
) != 0) {
267 val_low
= pmc_core_reg_read(pmcdev
, SPT_PMC_MFPMC_OFFSET
);
269 if (pmc_core_send_msg(&mphy_core_reg_high
) != 0) {
275 val_high
= pmc_core_reg_read(pmcdev
, SPT_PMC_MFPMC_OFFSET
);
277 for (index
= 0; map
[index
].name
&& index
< 8; index
++) {
278 seq_printf(s
, "%-32s\tState: %s\n",
280 map
[index
].bit_mask
& val_low
? "Not power gated" :
284 for (index
= 8; map
[index
].name
; index
++) {
285 seq_printf(s
, "%-32s\tState: %s\n",
287 map
[index
].bit_mask
& val_high
? "Not power gated" :
292 mutex_unlock(&pmcdev
->lock
);
296 static int pmc_core_mphy_pg_sts_open(struct inode
*inode
, struct file
*file
)
298 return single_open(file
, pmc_core_mphy_pg_sts_show
, inode
->i_private
);
301 static const struct file_operations pmc_core_mphy_pg_ops
= {
302 .open
= pmc_core_mphy_pg_sts_open
,
305 .release
= single_release
,
308 static int pmc_core_pll_show(struct seq_file
*s
, void *unused
)
310 struct pmc_dev
*pmcdev
= s
->private;
311 const struct pmc_bit_map
*map
= pmcdev
->map
->pll_sts
;
312 u32 mphy_common_reg
, val
;
315 if (pmcdev
->pmc_xram_read_bit
) {
316 seq_puts(s
, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
320 mphy_common_reg
= (SPT_PMC_MPHY_COM_STS_0
<< 16);
321 mutex_lock(&pmcdev
->lock
);
323 if (pmc_core_send_msg(&mphy_common_reg
) != 0) {
328 /* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
330 val
= pmc_core_reg_read(pmcdev
, SPT_PMC_MFPMC_OFFSET
);
332 for (index
= 0; map
[index
].name
; index
++) {
333 seq_printf(s
, "%-32s\tState: %s\n",
335 map
[index
].bit_mask
& val
? "Active" : "Idle");
339 mutex_unlock(&pmcdev
->lock
);
343 static int pmc_core_pll_open(struct inode
*inode
, struct file
*file
)
345 return single_open(file
, pmc_core_pll_show
, inode
->i_private
);
348 static const struct file_operations pmc_core_pll_ops
= {
349 .open
= pmc_core_pll_open
,
352 .release
= single_release
,
355 static ssize_t
pmc_core_ltr_ignore_write(struct file
*file
, const char __user
356 *userbuf
, size_t count
, loff_t
*ppos
)
358 struct pmc_dev
*pmcdev
= &pmc
;
359 const struct pmc_reg_map
*map
= pmcdev
->map
;
360 u32 val
, buf_size
, fd
;
363 buf_size
= count
< 64 ? count
: 64;
364 mutex_lock(&pmcdev
->lock
);
366 if (kstrtou32_from_user(userbuf
, buf_size
, 10, &val
)) {
371 if (val
> NUM_IP_IGN_ALLOWED
) {
376 fd
= pmc_core_reg_read(pmcdev
, map
->ltr_ignore_offset
);
378 pmc_core_reg_write(pmcdev
, map
->ltr_ignore_offset
, fd
);
381 mutex_unlock(&pmcdev
->lock
);
382 return err
== 0 ? count
: err
;
385 static int pmc_core_ltr_ignore_show(struct seq_file
*s
, void *unused
)
390 static int pmc_core_ltr_ignore_open(struct inode
*inode
, struct file
*file
)
392 return single_open(file
, pmc_core_ltr_ignore_show
, inode
->i_private
);
395 static const struct file_operations pmc_core_ltr_ignore_ops
= {
396 .open
= pmc_core_ltr_ignore_open
,
398 .write
= pmc_core_ltr_ignore_write
,
400 .release
= single_release
,
403 static void pmc_core_dbgfs_unregister(struct pmc_dev
*pmcdev
)
405 debugfs_remove_recursive(pmcdev
->dbgfs_dir
);
408 static int pmc_core_dbgfs_register(struct pmc_dev
*pmcdev
)
410 struct dentry
*dir
, *file
;
412 dir
= debugfs_create_dir("pmc_core", NULL
);
416 pmcdev
->dbgfs_dir
= dir
;
417 file
= debugfs_create_file("slp_s0_residency_usec", S_IFREG
| S_IRUGO
,
418 dir
, pmcdev
, &pmc_core_dev_state
);
422 file
= debugfs_create_file("pch_ip_power_gating_status",
423 S_IFREG
| S_IRUGO
, dir
, pmcdev
,
424 &pmc_core_ppfear_ops
);
428 file
= debugfs_create_file("mphy_core_lanes_power_gating_status",
429 S_IFREG
| S_IRUGO
, dir
, pmcdev
,
430 &pmc_core_mphy_pg_ops
);
434 file
= debugfs_create_file("pll_status",
435 S_IFREG
| S_IRUGO
, dir
, pmcdev
,
440 file
= debugfs_create_file("ltr_ignore",
441 S_IFREG
| S_IRUGO
, dir
, pmcdev
,
442 &pmc_core_ltr_ignore_ops
);
449 pmc_core_dbgfs_unregister(pmcdev
);
453 static inline int pmc_core_dbgfs_register(struct pmc_dev
*pmcdev
)
458 static inline void pmc_core_dbgfs_unregister(struct pmc_dev
*pmcdev
)
461 #endif /* CONFIG_DEBUG_FS */
463 static const struct x86_cpu_id intel_pmc_core_ids
[] = {
464 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_SKYLAKE_MOBILE
, X86_FEATURE_MWAIT
,
465 (kernel_ulong_t
)NULL
},
466 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_SKYLAKE_DESKTOP
, X86_FEATURE_MWAIT
,
467 (kernel_ulong_t
)NULL
},
468 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_KABYLAKE_MOBILE
, X86_FEATURE_MWAIT
,
469 (kernel_ulong_t
)NULL
},
470 { X86_VENDOR_INTEL
, 6, INTEL_FAM6_KABYLAKE_DESKTOP
, X86_FEATURE_MWAIT
,
471 (kernel_ulong_t
)NULL
},
475 static int pmc_core_probe(struct pci_dev
*dev
, const struct pci_device_id
*id
)
477 struct device
*ptr_dev
= &dev
->dev
;
478 struct pmc_dev
*pmcdev
= &pmc
;
479 const struct x86_cpu_id
*cpu_id
;
480 const struct pmc_reg_map
*map
= (struct pmc_reg_map
*)id
->driver_data
;
483 cpu_id
= x86_match_cpu(intel_pmc_core_ids
);
485 dev_dbg(&dev
->dev
, "PMC Core: cpuid mismatch.\n");
489 err
= pcim_enable_device(dev
);
491 dev_dbg(&dev
->dev
, "PMC Core: failed to enable Power Management Controller.\n");
495 err
= pci_read_config_dword(dev
,
496 SPT_PMC_BASE_ADDR_OFFSET
,
499 dev_dbg(&dev
->dev
, "PMC Core: failed to read PCI config space.\n");
502 pmcdev
->base_addr
&= PMC_BASE_ADDR_MASK
;
503 dev_dbg(&dev
->dev
, "PMC Core: PWRMBASE is %#x\n", pmcdev
->base_addr
);
505 pmcdev
->regbase
= devm_ioremap_nocache(ptr_dev
,
507 SPT_PMC_MMIO_REG_LEN
);
508 if (!pmcdev
->regbase
) {
509 dev_dbg(&dev
->dev
, "PMC Core: ioremap failed.\n");
513 mutex_init(&pmcdev
->lock
);
515 pmcdev
->pmc_xram_read_bit
= pmc_core_check_read_lock_bit();
517 err
= pmc_core_dbgfs_register(pmcdev
);
519 dev_warn(&dev
->dev
, "PMC Core: debugfs register failed.\n");
524 static void pmc_core_remove(struct pci_dev
*dev
)
526 pmc_core_dbgfs_unregister(&pmc
);
527 mutex_destroy(&pmc
.lock
);
530 static struct pci_driver intel_pmc_core_driver
= {
531 .name
= "intel_pmc_core",
532 .id_table
= pmc_pci_ids
,
533 .probe
= pmc_core_probe
,
534 .remove
= pmc_core_remove
,
537 module_pci_driver(intel_pmc_core_driver
);
539 MODULE_LICENSE("GPL v2");
540 MODULE_DESCRIPTION("Intel PMC Core Driver");