drivers/platform/x86/intel_pmc_core.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Core SoC Power Management Controller Header File
   4  *
   5  * Copyright (c) 2016, Intel Corporation.
   6  * All Rights Reserved.
   7  *
   8  * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
   9  *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
  10  */
  11
  12 #ifndef PMC_CORE_H
  13 #define PMC_CORE_H
  14
  15 #include <linux/bits.h>
  16
  17 #define PMC_BASE_ADDR_DEFAULT                   0xFE000000
  18
  19 /* Sunrise Point Power Management Controller PCI Device ID */
  20 #define SPT_PMC_PCI_DEVICE_ID                   0x9d21
  21 #define SPT_PMC_BASE_ADDR_OFFSET                0x48
  22 #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET       0x13c
  23 #define SPT_PMC_PM_CFG_OFFSET                   0x18
  24 #define SPT_PMC_PM_STS_OFFSET                   0x1c
  25 #define SPT_PMC_MTPMC_OFFSET                    0x20
  26 #define SPT_PMC_MFPMC_OFFSET                    0x38
  27 #define SPT_PMC_LTR_IGNORE_OFFSET               0x30C
  28 #define SPT_PMC_MPHY_CORE_STS_0                 0x1143
  29 #define SPT_PMC_MPHY_CORE_STS_1                 0x1142
  30 #define SPT_PMC_MPHY_COM_STS_0                  0x1155
  31 #define SPT_PMC_MMIO_REG_LEN                    0x1000
  32 #define SPT_PMC_SLP_S0_RES_COUNTER_STEP         0x64
  33 #define PMC_BASE_ADDR_MASK                      ~(SPT_PMC_MMIO_REG_LEN - 1)
  34 #define MTPMC_MASK                              0xffff0000
  35 #define PPFEAR_MAX_NUM_ENTRIES                  5
  36 #define SPT_PPFEAR_NUM_ENTRIES                  5
  37 #define SPT_PMC_READ_DISABLE_BIT                0x16
  38 #define SPT_PMC_MSG_FULL_STS_BIT                0x18
  39 #define NUM_RETRIES                             100
  40 #define SPT_NUM_IP_IGN_ALLOWED                  17
  41
  42 #define SPT_PMC_LTR_CUR_PLT                     0x350
  43 #define SPT_PMC_LTR_CUR_ASLT                    0x354
  44 #define SPT_PMC_LTR_SPA                         0x360
  45 #define SPT_PMC_LTR_SPB                         0x364
  46 #define SPT_PMC_LTR_SATA                        0x368
  47 #define SPT_PMC_LTR_GBE                         0x36C
  48 #define SPT_PMC_LTR_XHCI                        0x370
  49 #define SPT_PMC_LTR_ME                          0x378
  50 #define SPT_PMC_LTR_EVA                         0x37C
  51 #define SPT_PMC_LTR_SPC                         0x380
  52 #define SPT_PMC_LTR_AZ                          0x384
  53 #define SPT_PMC_LTR_LPSS                        0x38C
  54 #define SPT_PMC_LTR_CAM                         0x390
  55 #define SPT_PMC_LTR_SPD                         0x394
  56 #define SPT_PMC_LTR_SPE                         0x398
  57 #define SPT_PMC_LTR_ESPI                        0x39C
  58 #define SPT_PMC_LTR_SCC                         0x3A0
  59 #define SPT_PMC_LTR_ISH                         0x3A4
  60
  61 /* Sunrise Point: PGD PFET Enable Ack Status Registers */
  62 enum ppfear_regs {
  63         SPT_PMC_XRAM_PPFEAR0A = 0x590,
  64         SPT_PMC_XRAM_PPFEAR0B,
  65         SPT_PMC_XRAM_PPFEAR0C,
  66         SPT_PMC_XRAM_PPFEAR0D,
  67         SPT_PMC_XRAM_PPFEAR1A,
  68 };
  69
  70 #define SPT_PMC_BIT_PMC                         BIT(0)
  71 #define SPT_PMC_BIT_OPI                         BIT(1)
  72 #define SPT_PMC_BIT_SPI                         BIT(2)
  73 #define SPT_PMC_BIT_XHCI                        BIT(3)
  74 #define SPT_PMC_BIT_SPA                         BIT(4)
  75 #define SPT_PMC_BIT_SPB                         BIT(5)
  76 #define SPT_PMC_BIT_SPC                         BIT(6)
  77 #define SPT_PMC_BIT_GBE                         BIT(7)
  78
  79 #define SPT_PMC_BIT_SATA                        BIT(0)
  80 #define SPT_PMC_BIT_HDA_PGD0                    BIT(1)
  81 #define SPT_PMC_BIT_HDA_PGD1                    BIT(2)
  82 #define SPT_PMC_BIT_HDA_PGD2                    BIT(3)
  83 #define SPT_PMC_BIT_HDA_PGD3                    BIT(4)
  84 #define SPT_PMC_BIT_RSVD_0B                     BIT(5)
  85 #define SPT_PMC_BIT_LPSS                        BIT(6)
  86 #define SPT_PMC_BIT_LPC                         BIT(7)
  87
  88 #define SPT_PMC_BIT_SMB                         BIT(0)
  89 #define SPT_PMC_BIT_ISH                         BIT(1)
  90 #define SPT_PMC_BIT_P2SB                        BIT(2)
  91 #define SPT_PMC_BIT_DFX                         BIT(3)
  92 #define SPT_PMC_BIT_SCC                         BIT(4)
  93 #define SPT_PMC_BIT_RSVD_0C                     BIT(5)
  94 #define SPT_PMC_BIT_FUSE                        BIT(6)
  95 #define SPT_PMC_BIT_CAMREA                      BIT(7)
  96
  97 #define SPT_PMC_BIT_RSVD_0D                     BIT(0)
  98 #define SPT_PMC_BIT_USB3_OTG                    BIT(1)
  99 #define SPT_PMC_BIT_EXI                         BIT(2)
 100 #define SPT_PMC_BIT_CSE                         BIT(3)
 101 #define SPT_PMC_BIT_CSME_KVM                    BIT(4)
 102 #define SPT_PMC_BIT_CSME_PMT                    BIT(5)
 103 #define SPT_PMC_BIT_CSME_CLINK                  BIT(6)
 104 #define SPT_PMC_BIT_CSME_PTIO                   BIT(7)
 105
 106 #define SPT_PMC_BIT_CSME_USBR                   BIT(0)
 107 #define SPT_PMC_BIT_CSME_SUSRAM                 BIT(1)
 108 #define SPT_PMC_BIT_CSME_SMT                    BIT(2)
 109 #define SPT_PMC_BIT_RSVD_1A                     BIT(3)
 110 #define SPT_PMC_BIT_CSME_SMS2                   BIT(4)
 111 #define SPT_PMC_BIT_CSME_SMS1                   BIT(5)
 112 #define SPT_PMC_BIT_CSME_RTC                    BIT(6)
 113 #define SPT_PMC_BIT_CSME_PSF                    BIT(7)
 114
 115 #define SPT_PMC_BIT_MPHY_LANE0                  BIT(0)
 116 #define SPT_PMC_BIT_MPHY_LANE1                  BIT(1)
 117 #define SPT_PMC_BIT_MPHY_LANE2                  BIT(2)
 118 #define SPT_PMC_BIT_MPHY_LANE3                  BIT(3)
 119 #define SPT_PMC_BIT_MPHY_LANE4                  BIT(4)
 120 #define SPT_PMC_BIT_MPHY_LANE5                  BIT(5)
 121 #define SPT_PMC_BIT_MPHY_LANE6                  BIT(6)
 122 #define SPT_PMC_BIT_MPHY_LANE7                  BIT(7)
 123
 124 #define SPT_PMC_BIT_MPHY_LANE8                  BIT(0)
 125 #define SPT_PMC_BIT_MPHY_LANE9                  BIT(1)
 126 #define SPT_PMC_BIT_MPHY_LANE10                 BIT(2)
 127 #define SPT_PMC_BIT_MPHY_LANE11                 BIT(3)
 128 #define SPT_PMC_BIT_MPHY_LANE12                 BIT(4)
 129 #define SPT_PMC_BIT_MPHY_LANE13                 BIT(5)
 130 #define SPT_PMC_BIT_MPHY_LANE14                 BIT(6)
 131 #define SPT_PMC_BIT_MPHY_LANE15                 BIT(7)
 132
 133 #define SPT_PMC_BIT_MPHY_CMN_LANE0              BIT(0)
 134 #define SPT_PMC_BIT_MPHY_CMN_LANE1              BIT(1)
 135 #define SPT_PMC_BIT_MPHY_CMN_LANE2              BIT(2)
 136 #define SPT_PMC_BIT_MPHY_CMN_LANE3              BIT(3)
 137
 138 /* Cannonlake Power Management Controller register offsets */
 139 #define CNP_PMC_SLPS0_DBG_OFFSET                0x10B4
 140 #define CNP_PMC_PM_CFG_OFFSET                   0x1818
 141 #define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET       0x193C
 142 #define CNP_PMC_LTR_IGNORE_OFFSET               0x1B0C
 143 /* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
 144 #define CNP_PMC_HOST_PPFEAR0A                   0x1D90
 145
 146 #define CNP_PMC_LATCH_SLPS0_EVENTS              BIT(31)
 147
 148 #define CNP_PMC_MMIO_REG_LEN                    0x2000
 149 #define CNP_PPFEAR_NUM_ENTRIES                  8
 150 #define CNP_PMC_READ_DISABLE_BIT                22
 151 #define CNP_NUM_IP_IGN_ALLOWED                  19
 152 #define CNP_PMC_LTR_CUR_PLT                     0x1B50
 153 #define CNP_PMC_LTR_CUR_ASLT                    0x1B54
 154 #define CNP_PMC_LTR_SPA                         0x1B60
 155 #define CNP_PMC_LTR_SPB                         0x1B64
 156 #define CNP_PMC_LTR_SATA                        0x1B68
 157 #define CNP_PMC_LTR_GBE                         0x1B6C
 158 #define CNP_PMC_LTR_XHCI                        0x1B70
 159 #define CNP_PMC_LTR_ME                          0x1B78
 160 #define CNP_PMC_LTR_EVA                         0x1B7C
 161 #define CNP_PMC_LTR_SPC                         0x1B80
 162 #define CNP_PMC_LTR_AZ                          0x1B84
 163 #define CNP_PMC_LTR_LPSS                        0x1B8C
 164 #define CNP_PMC_LTR_CAM                         0x1B90
 165 #define CNP_PMC_LTR_SPD                         0x1B94
 166 #define CNP_PMC_LTR_SPE                         0x1B98
 167 #define CNP_PMC_LTR_ESPI                        0x1B9C
 168 #define CNP_PMC_LTR_SCC                         0x1BA0
 169 #define CNP_PMC_LTR_ISH                         0x1BA4
 170 #define CNP_PMC_LTR_CNV                         0x1BF0
 171 #define CNP_PMC_LTR_EMMC                        0x1BF4
 172 #define CNP_PMC_LTR_UFSX2                       0x1BF8
 173
 174 #define LTR_DECODED_VAL                         GENMASK(9, 0)
 175 #define LTR_DECODED_SCALE                       GENMASK(12, 10)
 176 #define LTR_REQ_SNOOP                           BIT(15)
 177 #define LTR_REQ_NONSNOOP                        BIT(31)
 178
 179 struct pmc_bit_map {
 180         const char *name;
 181         u32 bit_mask;
 182 };
 183
 184 /**
 185  * struct pmc_reg_map - Structure used to define parameter unique to a
 186                         PCH family
 187  * @pfear_sts:          Maps name of IP block to PPFEAR* bit
 188  * @mphy_sts:           Maps name of MPHY lane to MPHY status lane status bit
 189  * @pll_sts:            Maps name of PLL to corresponding bit status
 190  * @slps0_dbg_maps:     Array of SLP_S0_DBG* registers containing debug info
 191  * @ltr_show_sts:       Maps PCH IP Names to their MMIO register offsets
 192  * @slp_s0_offset:      PWRMBASE offset to read SLP_S0 residency
 193  * @ltr_ignore_offset:  PWRMBASE offset to read/write LTR ignore bit
 194  * @regmap_length:      Length of memory to map from PWRMBASE address to access
 195  * @ppfear0_offset:     PWRMBASE offset to to read PPFEAR*
 196  * @ppfear_buckets:     Number of 8 bits blocks to read all IP blocks from
 197  *                      PPFEAR
 198  * @pm_cfg_offset:      PWRMBASE offset to PM_CFG register
 199  * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
 200  * @slps0_dbg_offset:   PWRMBASE offset to SLP_S0_DEBUG_REG*
 201  *
 202  * Each PCH has unique set of register offsets and bit indexes. This structure
 203  * captures them to have a common implementation.
 204  */
 205 struct pmc_reg_map {
 206         const struct pmc_bit_map *pfear_sts;
 207         const struct pmc_bit_map *mphy_sts;
 208         const struct pmc_bit_map *pll_sts;
 209         const struct pmc_bit_map **slps0_dbg_maps;
 210         const struct pmc_bit_map *ltr_show_sts;
 211         const u32 slp_s0_offset;
 212         const u32 ltr_ignore_offset;
 213         const int regmap_length;
 214         const u32 ppfear0_offset;
 215         const int ppfear_buckets;
 216         const u32 pm_cfg_offset;
 217         const int pm_read_disable_bit;
 218         const u32 slps0_dbg_offset;
 219         const u32 ltr_ignore_max;
 220 };
 221
 222 /**
 223  * struct pmc_dev - pmc device structure
 224  * @base_addr:          contains pmc base address
 225  * @regbase:            pointer to io-remapped memory location
 226  * @map:                pointer to pmc_reg_map struct that contains platform
 227  *                      specific attributes
 228  * @dbgfs_dir:          path to debugfs interface
 229  * @pmc_xram_read_bit:  flag to indicate whether PMC XRAM shadow registers
 230  *                      used to read MPHY PG and PLL status are available
 231  * @mutex_lock:         mutex to complete one transcation
 232  *
 233  * pmc_dev contains info about power management controller device.
 234  */
 235 struct pmc_dev {
 236         u32 base_addr;
 237         void __iomem *regbase;
 238         const struct pmc_reg_map *map;
 239 #if IS_ENABLED(CONFIG_DEBUG_FS)
 240         struct dentry *dbgfs_dir;
 241 #endif /* CONFIG_DEBUG_FS */
 242         int pmc_xram_read_bit;
 243         struct mutex lock; /* generic mutex lock for PMC Core */
 244 };
 245
 246 #endif /* PMC_CORE_H */