1 // SPDX-License-Identifier: GPL-2.0-only
3 * PTP 1588 clock using the EG20T PCH
5 * Copyright (C) 2010 OMICRON electronics GmbH
6 * Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
8 * This code was derived from the IXP46X driver.
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/ptp_clock_kernel.h>
21 #include <linux/ptp_pch.h>
22 #include <linux/slab.h>
24 #define STATION_ADDR_LEN 20
25 #define PCI_DEVICE_ID_PCH_1588 0x8819
28 #define DEFAULT_ADDEND 0xA0000000
29 #define TICKS_NS_SHIFT 5
36 PCH_INTERRUPTMODEINUSE
,
42 * struct pch_ts_regs - IEEE 1588 registers
81 #define PCH_TSC_RESET (1 << 0)
82 #define PCH_TSC_TTM_MASK (1 << 1)
83 #define PCH_TSC_ASMS_MASK (1 << 2)
84 #define PCH_TSC_AMMS_MASK (1 << 3)
85 #define PCH_TSC_PPSM_MASK (1 << 4)
86 #define PCH_TSE_TTIPEND (1 << 1)
87 #define PCH_TSE_SNS (1 << 2)
88 #define PCH_TSE_SNM (1 << 3)
89 #define PCH_TSE_PPS (1 << 4)
90 #define PCH_CC_MM (1 << 0)
91 #define PCH_CC_TA (1 << 1)
93 #define PCH_CC_MODE_SHIFT 16
94 #define PCH_CC_MODE_MASK 0x001F0000
95 #define PCH_CC_VERSION (1 << 31)
96 #define PCH_CE_TXS (1 << 0)
97 #define PCH_CE_RXS (1 << 1)
98 #define PCH_CE_OVR (1 << 0)
99 #define PCH_CE_VAL (1 << 1)
100 #define PCH_ECS_ETH (1 << 0)
102 #define PCH_ECS_CAN (1 << 1)
103 #define PCH_STATION_BYTES 6
105 #define PCH_IEEE1588_ETH (1 << 0)
106 #define PCH_IEEE1588_CAN (1 << 1)
109 * struct pch_dev - Driver private data
112 struct pch_ts_regs __iomem
*regs
;
113 struct ptp_clock
*ptp_clock
;
114 struct ptp_clock_info caps
;
121 struct pci_dev
*pdev
;
122 spinlock_t register_lock
;
126 * struct pch_params - 1588 module parameter
129 u8 station
[STATION_ADDR_LEN
];
132 /* structure to hold the module parameters */
133 static struct pch_params pch_param
= {
138 * Register access functions
140 static inline void pch_eth_enable_set(struct pch_dev
*chip
)
143 /* SET the eth_enable bit */
144 val
= ioread32(&chip
->regs
->ts_sel
) | (PCH_ECS_ETH
);
145 iowrite32(val
, (&chip
->regs
->ts_sel
));
148 static u64
pch_systime_read(struct pch_ts_regs __iomem
*regs
)
153 lo
= ioread32(®s
->systime_lo
);
154 hi
= ioread32(®s
->systime_hi
);
156 ns
= ((u64
) hi
) << 32;
158 ns
<<= TICKS_NS_SHIFT
;
163 static void pch_systime_write(struct pch_ts_regs __iomem
*regs
, u64 ns
)
167 ns
>>= TICKS_NS_SHIFT
;
169 lo
= ns
& 0xffffffff;
171 iowrite32(lo
, ®s
->systime_lo
);
172 iowrite32(hi
, ®s
->systime_hi
);
175 static inline void pch_block_reset(struct pch_dev
*chip
)
178 /* Reset Hardware Assist block */
179 val
= ioread32(&chip
->regs
->control
) | PCH_TSC_RESET
;
180 iowrite32(val
, (&chip
->regs
->control
));
181 val
= val
& ~PCH_TSC_RESET
;
182 iowrite32(val
, (&chip
->regs
->control
));
185 void pch_ch_control_write(struct pci_dev
*pdev
, u32 val
)
187 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
189 iowrite32(val
, (&chip
->regs
->ch_control
));
191 EXPORT_SYMBOL(pch_ch_control_write
);
193 u32
pch_ch_event_read(struct pci_dev
*pdev
)
195 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
198 val
= ioread32(&chip
->regs
->ch_event
);
202 EXPORT_SYMBOL(pch_ch_event_read
);
204 void pch_ch_event_write(struct pci_dev
*pdev
, u32 val
)
206 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
208 iowrite32(val
, (&chip
->regs
->ch_event
));
210 EXPORT_SYMBOL(pch_ch_event_write
);
212 u32
pch_src_uuid_lo_read(struct pci_dev
*pdev
)
214 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
217 val
= ioread32(&chip
->regs
->src_uuid_lo
);
221 EXPORT_SYMBOL(pch_src_uuid_lo_read
);
223 u32
pch_src_uuid_hi_read(struct pci_dev
*pdev
)
225 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
228 val
= ioread32(&chip
->regs
->src_uuid_hi
);
232 EXPORT_SYMBOL(pch_src_uuid_hi_read
);
234 u64
pch_rx_snap_read(struct pci_dev
*pdev
)
236 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
240 lo
= ioread32(&chip
->regs
->rx_snap_lo
);
241 hi
= ioread32(&chip
->regs
->rx_snap_hi
);
243 ns
= ((u64
) hi
) << 32;
245 ns
<<= TICKS_NS_SHIFT
;
249 EXPORT_SYMBOL(pch_rx_snap_read
);
251 u64
pch_tx_snap_read(struct pci_dev
*pdev
)
253 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
257 lo
= ioread32(&chip
->regs
->tx_snap_lo
);
258 hi
= ioread32(&chip
->regs
->tx_snap_hi
);
260 ns
= ((u64
) hi
) << 32;
262 ns
<<= TICKS_NS_SHIFT
;
266 EXPORT_SYMBOL(pch_tx_snap_read
);
268 /* This function enables all 64 bits in system time registers [high & low].
269 This is a work-around for non continuous value in the SystemTime Register*/
270 static void pch_set_system_time_count(struct pch_dev
*chip
)
272 iowrite32(0x01, &chip
->regs
->stl_max_set_en
);
273 iowrite32(0xFFFFFFFF, &chip
->regs
->stl_max_set
);
274 iowrite32(0x00, &chip
->regs
->stl_max_set_en
);
277 static void pch_reset(struct pch_dev
*chip
)
279 /* Reset Hardware Assist */
280 pch_block_reset(chip
);
282 /* enable all 32 bits in system time registers */
283 pch_set_system_time_count(chip
);
287 * pch_set_station_address() - This API sets the station address used by
288 * IEEE 1588 hardware when looking at PTP
289 * traffic on the ethernet interface
290 * @addr: dress which contain the column separated address to be used.
293 int pch_set_station_address(u8
*addr
, struct pci_dev
*pdev
)
296 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
298 /* Verify the parameter */
299 if ((chip
->regs
== NULL
) || addr
== (u8
*)NULL
) {
301 "invalid params returning PCH_INVALIDPARAM\n");
302 return PCH_INVALIDPARAM
;
304 /* For all station address bytes */
305 for (i
= 0; i
< PCH_STATION_BYTES
; i
++) {
309 tmp
= hex_to_bin(addr
[i
* 3]);
312 "invalid params returning PCH_INVALIDPARAM\n");
313 return PCH_INVALIDPARAM
;
316 tmp
= hex_to_bin(addr
[(i
* 3) + 1]);
319 "invalid params returning PCH_INVALIDPARAM\n");
320 return PCH_INVALIDPARAM
;
323 /* Expects ':' separated addresses */
324 if ((i
< 5) && (addr
[(i
* 3) + 2] != ':')) {
326 "invalid params returning PCH_INVALIDPARAM\n");
327 return PCH_INVALIDPARAM
;
330 /* Ideally we should set the address only after validating
332 dev_dbg(&pdev
->dev
, "invoking pch_station_set\n");
333 iowrite32(val
, &chip
->regs
->ts_st
[i
]);
337 EXPORT_SYMBOL(pch_set_station_address
);
340 * Interrupt service routine
342 static irqreturn_t
isr(int irq
, void *priv
)
344 struct pch_dev
*pch_dev
= priv
;
345 struct pch_ts_regs __iomem
*regs
= pch_dev
->regs
;
346 struct ptp_clock_event event
;
347 u32 ack
= 0, lo
, hi
, val
;
349 val
= ioread32(®s
->event
);
351 if (val
& PCH_TSE_SNS
) {
353 if (pch_dev
->exts0_enabled
) {
354 hi
= ioread32(®s
->asms_hi
);
355 lo
= ioread32(®s
->asms_lo
);
356 event
.type
= PTP_CLOCK_EXTTS
;
358 event
.timestamp
= ((u64
) hi
) << 32;
359 event
.timestamp
|= lo
;
360 event
.timestamp
<<= TICKS_NS_SHIFT
;
361 ptp_clock_event(pch_dev
->ptp_clock
, &event
);
365 if (val
& PCH_TSE_SNM
) {
367 if (pch_dev
->exts1_enabled
) {
368 hi
= ioread32(®s
->amms_hi
);
369 lo
= ioread32(®s
->amms_lo
);
370 event
.type
= PTP_CLOCK_EXTTS
;
372 event
.timestamp
= ((u64
) hi
) << 32;
373 event
.timestamp
|= lo
;
374 event
.timestamp
<<= TICKS_NS_SHIFT
;
375 ptp_clock_event(pch_dev
->ptp_clock
, &event
);
379 if (val
& PCH_TSE_TTIPEND
)
380 ack
|= PCH_TSE_TTIPEND
; /* this bit seems to be always set */
383 iowrite32(ack
, ®s
->event
);
390 * PTP clock operations
393 static int ptp_pch_adjfreq(struct ptp_clock_info
*ptp
, s32 ppb
)
398 struct pch_dev
*pch_dev
= container_of(ptp
, struct pch_dev
, caps
);
399 struct pch_ts_regs __iomem
*regs
= pch_dev
->regs
;
405 addend
= DEFAULT_ADDEND
;
408 diff
= div_u64(adj
, 1000000000ULL);
410 addend
= neg_adj
? addend
- diff
: addend
+ diff
;
412 iowrite32(addend
, ®s
->addend
);
417 static int ptp_pch_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
421 struct pch_dev
*pch_dev
= container_of(ptp
, struct pch_dev
, caps
);
422 struct pch_ts_regs __iomem
*regs
= pch_dev
->regs
;
424 spin_lock_irqsave(&pch_dev
->register_lock
, flags
);
425 now
= pch_systime_read(regs
);
427 pch_systime_write(regs
, now
);
428 spin_unlock_irqrestore(&pch_dev
->register_lock
, flags
);
433 static int ptp_pch_gettime(struct ptp_clock_info
*ptp
, struct timespec64
*ts
)
437 struct pch_dev
*pch_dev
= container_of(ptp
, struct pch_dev
, caps
);
438 struct pch_ts_regs __iomem
*regs
= pch_dev
->regs
;
440 spin_lock_irqsave(&pch_dev
->register_lock
, flags
);
441 ns
= pch_systime_read(regs
);
442 spin_unlock_irqrestore(&pch_dev
->register_lock
, flags
);
444 *ts
= ns_to_timespec64(ns
);
448 static int ptp_pch_settime(struct ptp_clock_info
*ptp
,
449 const struct timespec64
*ts
)
453 struct pch_dev
*pch_dev
= container_of(ptp
, struct pch_dev
, caps
);
454 struct pch_ts_regs __iomem
*regs
= pch_dev
->regs
;
456 ns
= timespec64_to_ns(ts
);
458 spin_lock_irqsave(&pch_dev
->register_lock
, flags
);
459 pch_systime_write(regs
, ns
);
460 spin_unlock_irqrestore(&pch_dev
->register_lock
, flags
);
465 static int ptp_pch_enable(struct ptp_clock_info
*ptp
,
466 struct ptp_clock_request
*rq
, int on
)
468 struct pch_dev
*pch_dev
= container_of(ptp
, struct pch_dev
, caps
);
471 case PTP_CLK_REQ_EXTTS
:
472 switch (rq
->extts
.index
) {
474 pch_dev
->exts0_enabled
= on
? 1 : 0;
477 pch_dev
->exts1_enabled
= on
? 1 : 0;
490 static const struct ptp_clock_info ptp_pch_caps
= {
491 .owner
= THIS_MODULE
,
494 .n_ext_ts
= N_EXT_TS
,
497 .adjfreq
= ptp_pch_adjfreq
,
498 .adjtime
= ptp_pch_adjtime
,
499 .gettime64
= ptp_pch_gettime
,
500 .settime64
= ptp_pch_settime
,
501 .enable
= ptp_pch_enable
,
504 #define pch_suspend NULL
505 #define pch_resume NULL
507 static void pch_remove(struct pci_dev
*pdev
)
509 struct pch_dev
*chip
= pci_get_drvdata(pdev
);
511 ptp_clock_unregister(chip
->ptp_clock
);
512 /* free the interrupt */
514 free_irq(pdev
->irq
, chip
);
516 /* unmap the virtual IO memory space */
517 if (chip
->regs
!= NULL
) {
521 /* release the reserved IO memory space */
522 if (chip
->mem_base
!= 0) {
523 release_mem_region(chip
->mem_base
, chip
->mem_size
);
526 pci_disable_device(pdev
);
528 dev_info(&pdev
->dev
, "complete\n");
532 pch_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
536 struct pch_dev
*chip
;
538 chip
= kzalloc(sizeof(struct pch_dev
), GFP_KERNEL
);
542 /* enable the 1588 pci device */
543 ret
= pci_enable_device(pdev
);
545 dev_err(&pdev
->dev
, "could not enable the pci device\n");
549 chip
->mem_base
= pci_resource_start(pdev
, IO_MEM_BAR
);
550 if (!chip
->mem_base
) {
551 dev_err(&pdev
->dev
, "could not locate IO memory address\n");
556 /* retrieve the available length of the IO memory space */
557 chip
->mem_size
= pci_resource_len(pdev
, IO_MEM_BAR
);
559 /* allocate the memory for the device registers */
560 if (!request_mem_region(chip
->mem_base
, chip
->mem_size
, "1588_regs")) {
562 "could not allocate register memory space\n");
564 goto err_req_mem_region
;
567 /* get the virtual address to the 1588 registers */
568 chip
->regs
= ioremap(chip
->mem_base
, chip
->mem_size
);
571 dev_err(&pdev
->dev
, "Could not get virtual address\n");
576 chip
->caps
= ptp_pch_caps
;
577 chip
->ptp_clock
= ptp_clock_register(&chip
->caps
, &pdev
->dev
);
578 if (IS_ERR(chip
->ptp_clock
)) {
579 ret
= PTR_ERR(chip
->ptp_clock
);
580 goto err_ptp_clock_reg
;
583 spin_lock_init(&chip
->register_lock
);
585 ret
= request_irq(pdev
->irq
, &isr
, IRQF_SHARED
, KBUILD_MODNAME
, chip
);
587 dev_err(&pdev
->dev
, "failed to get irq %d\n", pdev
->irq
);
591 /* indicate success */
592 chip
->irq
= pdev
->irq
;
594 pci_set_drvdata(pdev
, chip
);
596 spin_lock_irqsave(&chip
->register_lock
, flags
);
597 /* reset the ieee1588 h/w */
600 iowrite32(DEFAULT_ADDEND
, &chip
->regs
->addend
);
601 iowrite32(1, &chip
->regs
->trgt_lo
);
602 iowrite32(0, &chip
->regs
->trgt_hi
);
603 iowrite32(PCH_TSE_TTIPEND
, &chip
->regs
->event
);
605 pch_eth_enable_set(chip
);
607 if (strcmp(pch_param
.station
, "00:00:00:00:00:00") != 0) {
608 if (pch_set_station_address(pch_param
.station
, pdev
) != 0) {
610 "Invalid station address parameter\n"
611 "Module loaded but station address not set correctly\n"
615 spin_unlock_irqrestore(&chip
->register_lock
, flags
);
619 ptp_clock_unregister(chip
->ptp_clock
);
625 release_mem_region(chip
->mem_base
, chip
->mem_size
);
631 pci_disable_device(pdev
);
635 dev_err(&pdev
->dev
, "probe failed(ret=0x%x)\n", ret
);
640 static const struct pci_device_id pch_ieee1588_pcidev_id
[] = {
642 .vendor
= PCI_VENDOR_ID_INTEL
,
643 .device
= PCI_DEVICE_ID_PCH_1588
647 MODULE_DEVICE_TABLE(pci
, pch_ieee1588_pcidev_id
);
649 static SIMPLE_DEV_PM_OPS(pch_pm_ops
, pch_suspend
, pch_resume
);
651 static struct pci_driver pch_driver
= {
652 .name
= KBUILD_MODNAME
,
653 .id_table
= pch_ieee1588_pcidev_id
,
655 .remove
= pch_remove
,
656 .driver
.pm
= &pch_pm_ops
,
659 static void __exit
ptp_pch_exit(void)
661 pci_unregister_driver(&pch_driver
);
664 static s32 __init
ptp_pch_init(void)
668 /* register the driver with the pci core */
669 ret
= pci_register_driver(&pch_driver
);
674 module_init(ptp_pch_init
);
675 module_exit(ptp_pch_exit
);
677 module_param_string(station
,
678 pch_param
.station
, sizeof(pch_param
.station
), 0444);
679 MODULE_PARM_DESC(station
,
680 "IEEE 1588 station address to use - colon separated hex values");
682 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
683 MODULE_DESCRIPTION("PTP clock using the EG20T timer");
684 MODULE_LICENSE("GPL");