2 * Driver for Atmel Pulse Width Modulation Controller
4 * Copyright (C) 2013 Atmel Corporation
5 * Bo Shen <voice.shen@atmel.com>
7 * Licensed under GPLv2.
10 #include <linux/clk.h>
11 #include <linux/err.h>
13 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/pwm.h>
18 #include <linux/slab.h>
20 /* The following is global registers for PWM controller */
25 #define PWM_SR_ALL_CH_ON 0x0F
27 /* The following register is PWM channel related registers */
28 #define PWM_CH_REG_OFFSET 0x200
29 #define PWM_CH_REG_SIZE 0x20
32 /* Bit field in CMR */
33 #define PWM_CMR_CPOL (1 << 9)
34 #define PWM_CMR_UPD_CDTY (1 << 10)
35 #define PWM_CMR_CPRE_MSK 0xF
37 /* The following registers for PWM v1 */
38 #define PWMV1_CDTY 0x04
39 #define PWMV1_CPRD 0x08
40 #define PWMV1_CUPD 0x10
42 /* The following registers for PWM v2 */
43 #define PWMV2_CDTY 0x04
44 #define PWMV2_CDTYUPD 0x08
45 #define PWMV2_CPRD 0x0C
46 #define PWMV2_CPRDUPD 0x10
49 * Max value for duty and period
51 * Although the duty and period register is 32 bit,
52 * however only the LSB 16 bits are significant.
54 #define PWM_MAX_DTY 0xFFFF
55 #define PWM_MAX_PRD 0xFFFF
56 #define PRD_MAX_PRES 10
58 struct atmel_pwm_chip
{
63 void (*config
)(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
64 unsigned long dty
, unsigned long prd
);
67 static inline struct atmel_pwm_chip
*to_atmel_pwm_chip(struct pwm_chip
*chip
)
69 return container_of(chip
, struct atmel_pwm_chip
, chip
);
72 static inline u32
atmel_pwm_readl(struct atmel_pwm_chip
*chip
,
75 return readl_relaxed(chip
->base
+ offset
);
78 static inline void atmel_pwm_writel(struct atmel_pwm_chip
*chip
,
79 unsigned long offset
, unsigned long val
)
81 writel_relaxed(val
, chip
->base
+ offset
);
84 static inline u32
atmel_pwm_ch_readl(struct atmel_pwm_chip
*chip
,
85 unsigned int ch
, unsigned long offset
)
87 unsigned long base
= PWM_CH_REG_OFFSET
+ ch
* PWM_CH_REG_SIZE
;
89 return readl_relaxed(chip
->base
+ base
+ offset
);
92 static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip
*chip
,
93 unsigned int ch
, unsigned long offset
,
96 unsigned long base
= PWM_CH_REG_OFFSET
+ ch
* PWM_CH_REG_SIZE
;
98 writel_relaxed(val
, chip
->base
+ base
+ offset
);
101 static int atmel_pwm_config(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
102 int duty_ns
, int period_ns
)
104 struct atmel_pwm_chip
*atmel_pwm
= to_atmel_pwm_chip(chip
);
105 unsigned long clk_rate
, prd
, dty
;
106 unsigned long long div
;
107 unsigned int pres
= 0;
111 if (test_bit(PWMF_ENABLED
, &pwm
->flags
) && (period_ns
!= pwm
->period
)) {
112 dev_err(chip
->dev
, "cannot change PWM period while enabled\n");
116 clk_rate
= clk_get_rate(atmel_pwm
->clk
);
119 /* Calculate the period cycles */
120 while (div
> PWM_MAX_PRD
) {
121 div
= clk_rate
/ (1 << pres
);
122 div
= div
* period_ns
;
123 /* 1/Hz = 100000000 ns */
124 do_div(div
, 1000000000);
126 if (pres
++ > PRD_MAX_PRES
) {
127 dev_err(chip
->dev
, "pres exceeds the maximum value\n");
132 /* Calculate the duty cycles */
135 do_div(div
, period_ns
);
138 ret
= clk_enable(atmel_pwm
->clk
);
140 dev_err(chip
->dev
, "failed to enable PWM clock\n");
144 /* It is necessary to preserve CPOL, inside CMR */
145 val
= atmel_pwm_ch_readl(atmel_pwm
, pwm
->hwpwm
, PWM_CMR
);
146 val
= (val
& ~PWM_CMR_CPRE_MSK
) | (pres
& PWM_CMR_CPRE_MSK
);
147 atmel_pwm_ch_writel(atmel_pwm
, pwm
->hwpwm
, PWM_CMR
, val
);
148 atmel_pwm
->config(chip
, pwm
, dty
, prd
);
150 clk_disable(atmel_pwm
->clk
);
154 static void atmel_pwm_config_v1(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
155 unsigned long dty
, unsigned long prd
)
157 struct atmel_pwm_chip
*atmel_pwm
= to_atmel_pwm_chip(chip
);
160 if (test_bit(PWMF_ENABLED
, &pwm
->flags
)) {
162 * If the PWM channel is enabled, using the update register,
163 * it needs to set bit 10 of CMR to 0
165 atmel_pwm_ch_writel(atmel_pwm
, pwm
->hwpwm
, PWMV1_CUPD
, dty
);
167 val
= atmel_pwm_ch_readl(atmel_pwm
, pwm
->hwpwm
, PWM_CMR
);
168 val
&= ~PWM_CMR_UPD_CDTY
;
169 atmel_pwm_ch_writel(atmel_pwm
, pwm
->hwpwm
, PWM_CMR
, val
);
172 * If the PWM channel is disabled, write value to duty and
173 * period registers directly.
175 atmel_pwm_ch_writel(atmel_pwm
, pwm
->hwpwm
, PWMV1_CDTY
, dty
);
176 atmel_pwm_ch_writel(atmel_pwm
, pwm
->hwpwm
, PWMV1_CPRD
, prd
);
180 static void atmel_pwm_config_v2(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
181 unsigned long dty
, unsigned long prd
)
183 struct atmel_pwm_chip
*atmel_pwm
= to_atmel_pwm_chip(chip
);
185 if (test_bit(PWMF_ENABLED
, &pwm
->flags
)) {
187 * If the PWM channel is enabled, using the duty update register
188 * to update the value.
190 atmel_pwm_ch_writel(atmel_pwm
, pwm
->hwpwm
, PWMV2_CDTYUPD
, dty
);
193 * If the PWM channel is disabled, write value to duty and
194 * period registers directly.
196 atmel_pwm_ch_writel(atmel_pwm
, pwm
->hwpwm
, PWMV2_CDTY
, dty
);
197 atmel_pwm_ch_writel(atmel_pwm
, pwm
->hwpwm
, PWMV2_CPRD
, prd
);
201 static int atmel_pwm_set_polarity(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
202 enum pwm_polarity polarity
)
204 struct atmel_pwm_chip
*atmel_pwm
= to_atmel_pwm_chip(chip
);
208 val
= atmel_pwm_ch_readl(atmel_pwm
, pwm
->hwpwm
, PWM_CMR
);
210 if (polarity
== PWM_POLARITY_NORMAL
)
211 val
&= ~PWM_CMR_CPOL
;
215 ret
= clk_enable(atmel_pwm
->clk
);
217 dev_err(chip
->dev
, "failed to enable PWM clock\n");
221 atmel_pwm_ch_writel(atmel_pwm
, pwm
->hwpwm
, PWM_CMR
, val
);
223 clk_disable(atmel_pwm
->clk
);
228 static int atmel_pwm_enable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
230 struct atmel_pwm_chip
*atmel_pwm
= to_atmel_pwm_chip(chip
);
233 ret
= clk_enable(atmel_pwm
->clk
);
235 dev_err(chip
->dev
, "failed to enable PWM clock\n");
239 atmel_pwm_writel(atmel_pwm
, PWM_ENA
, 1 << pwm
->hwpwm
);
244 static void atmel_pwm_disable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
246 struct atmel_pwm_chip
*atmel_pwm
= to_atmel_pwm_chip(chip
);
248 atmel_pwm_writel(atmel_pwm
, PWM_DIS
, 1 << pwm
->hwpwm
);
250 clk_disable(atmel_pwm
->clk
);
253 static const struct pwm_ops atmel_pwm_ops
= {
254 .config
= atmel_pwm_config
,
255 .set_polarity
= atmel_pwm_set_polarity
,
256 .enable
= atmel_pwm_enable
,
257 .disable
= atmel_pwm_disable
,
258 .owner
= THIS_MODULE
,
261 struct atmel_pwm_data
{
262 void (*config
)(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
263 unsigned long dty
, unsigned long prd
);
266 static const struct atmel_pwm_data atmel_pwm_data_v1
= {
267 .config
= atmel_pwm_config_v1
,
270 static const struct atmel_pwm_data atmel_pwm_data_v2
= {
271 .config
= atmel_pwm_config_v2
,
274 static const struct platform_device_id atmel_pwm_devtypes
[] = {
276 .name
= "at91sam9rl-pwm",
277 .driver_data
= (kernel_ulong_t
)&atmel_pwm_data_v1
,
279 .name
= "sama5d3-pwm",
280 .driver_data
= (kernel_ulong_t
)&atmel_pwm_data_v2
,
285 MODULE_DEVICE_TABLE(platform
, atmel_pwm_devtypes
);
287 static const struct of_device_id atmel_pwm_dt_ids
[] = {
289 .compatible
= "atmel,at91sam9rl-pwm",
290 .data
= &atmel_pwm_data_v1
,
292 .compatible
= "atmel,sama5d3-pwm",
293 .data
= &atmel_pwm_data_v2
,
298 MODULE_DEVICE_TABLE(of
, atmel_pwm_dt_ids
);
300 static inline const struct atmel_pwm_data
*
301 atmel_pwm_get_driver_data(struct platform_device
*pdev
)
303 if (pdev
->dev
.of_node
) {
304 const struct of_device_id
*match
;
306 match
= of_match_device(atmel_pwm_dt_ids
, &pdev
->dev
);
312 const struct platform_device_id
*id
;
314 id
= platform_get_device_id(pdev
);
316 return (struct atmel_pwm_data
*)id
->driver_data
;
320 static int atmel_pwm_probe(struct platform_device
*pdev
)
322 const struct atmel_pwm_data
*data
;
323 struct atmel_pwm_chip
*atmel_pwm
;
324 struct resource
*res
;
327 data
= atmel_pwm_get_driver_data(pdev
);
331 atmel_pwm
= devm_kzalloc(&pdev
->dev
, sizeof(*atmel_pwm
), GFP_KERNEL
);
335 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
336 atmel_pwm
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
337 if (IS_ERR(atmel_pwm
->base
))
338 return PTR_ERR(atmel_pwm
->base
);
340 atmel_pwm
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
341 if (IS_ERR(atmel_pwm
->clk
))
342 return PTR_ERR(atmel_pwm
->clk
);
344 ret
= clk_prepare(atmel_pwm
->clk
);
346 dev_err(&pdev
->dev
, "failed to prepare PWM clock\n");
350 atmel_pwm
->chip
.dev
= &pdev
->dev
;
351 atmel_pwm
->chip
.ops
= &atmel_pwm_ops
;
353 if (pdev
->dev
.of_node
) {
354 atmel_pwm
->chip
.of_xlate
= of_pwm_xlate_with_flags
;
355 atmel_pwm
->chip
.of_pwm_n_cells
= 3;
358 atmel_pwm
->chip
.base
= -1;
359 atmel_pwm
->chip
.npwm
= 4;
360 atmel_pwm
->config
= data
->config
;
362 ret
= pwmchip_add(&atmel_pwm
->chip
);
364 dev_err(&pdev
->dev
, "failed to add PWM chip %d\n", ret
);
368 platform_set_drvdata(pdev
, atmel_pwm
);
373 clk_unprepare(atmel_pwm
->clk
);
377 static int atmel_pwm_remove(struct platform_device
*pdev
)
379 struct atmel_pwm_chip
*atmel_pwm
= platform_get_drvdata(pdev
);
381 clk_unprepare(atmel_pwm
->clk
);
383 return pwmchip_remove(&atmel_pwm
->chip
);
386 static struct platform_driver atmel_pwm_driver
= {
389 .of_match_table
= of_match_ptr(atmel_pwm_dt_ids
),
391 .id_table
= atmel_pwm_devtypes
,
392 .probe
= atmel_pwm_probe
,
393 .remove
= atmel_pwm_remove
,
395 module_platform_driver(atmel_pwm_driver
);
397 MODULE_ALIAS("platform:atmel-pwm");
398 MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
399 MODULE_DESCRIPTION("Atmel PWM driver");
400 MODULE_LICENSE("GPL v2");