1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be>
9 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/pwm.h>
14 #define PWM_CONTROL 0x000
15 #define PWM_CONTROL_SHIFT(x) ((x) * 8)
16 #define PWM_CONTROL_MASK 0xff
17 #define PWM_MODE 0x80 /* set timer in PWM mode */
18 #define PWM_ENABLE (1 << 0)
19 #define PWM_POLARITY (1 << 4)
21 #define PERIOD(x) (((x) * 0x10) + 0x10)
22 #define DUTY(x) (((x) * 0x10) + 0x14)
24 #define PERIOD_MIN 0x2
33 static inline struct bcm2835_pwm
*to_bcm2835_pwm(struct pwm_chip
*chip
)
35 return container_of(chip
, struct bcm2835_pwm
, chip
);
38 static int bcm2835_pwm_request(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
40 struct bcm2835_pwm
*pc
= to_bcm2835_pwm(chip
);
43 value
= readl(pc
->base
+ PWM_CONTROL
);
44 value
&= ~(PWM_CONTROL_MASK
<< PWM_CONTROL_SHIFT(pwm
->hwpwm
));
45 value
|= (PWM_MODE
<< PWM_CONTROL_SHIFT(pwm
->hwpwm
));
46 writel(value
, pc
->base
+ PWM_CONTROL
);
51 static void bcm2835_pwm_free(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
53 struct bcm2835_pwm
*pc
= to_bcm2835_pwm(chip
);
56 value
= readl(pc
->base
+ PWM_CONTROL
);
57 value
&= ~(PWM_CONTROL_MASK
<< PWM_CONTROL_SHIFT(pwm
->hwpwm
));
58 writel(value
, pc
->base
+ PWM_CONTROL
);
61 static int bcm2835_pwm_apply(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
62 const struct pwm_state
*state
)
65 struct bcm2835_pwm
*pc
= to_bcm2835_pwm(chip
);
66 unsigned long rate
= clk_get_rate(pc
->clk
);
67 unsigned long long period_cycles
;
73 dev_err(pc
->dev
, "failed to get clock rate\n");
78 * period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC
79 * must be <= U32_MAX. As U32_MAX * NSEC_PER_SEC < U64_MAX the
80 * multiplication period * rate doesn't overflow.
81 * To calculate the maximal possible period that guarantees the
84 * round(period * rate / NSEC_PER_SEC) <= U32_MAX
85 * <=> period * rate / NSEC_PER_SEC < U32_MAX + 0.5
86 * <=> period * rate < (U32_MAX + 0.5) * NSEC_PER_SEC
87 * <=> period < ((U32_MAX + 0.5) * NSEC_PER_SEC) / rate
88 * <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate
89 * <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1
91 max_period
= DIV_ROUND_UP_ULL((u64
)U32_MAX
* NSEC_PER_SEC
+ NSEC_PER_SEC
/ 2, rate
) - 1;
93 if (state
->period
> max_period
)
97 period_cycles
= DIV_ROUND_CLOSEST_ULL(state
->period
* rate
, NSEC_PER_SEC
);
99 /* don't accept a period that is too small */
100 if (period_cycles
< PERIOD_MIN
)
103 writel(period_cycles
, pc
->base
+ PERIOD(pwm
->hwpwm
));
106 val
= DIV_ROUND_CLOSEST_ULL(state
->duty_cycle
* rate
, NSEC_PER_SEC
);
107 writel(val
, pc
->base
+ DUTY(pwm
->hwpwm
));
110 val
= readl(pc
->base
+ PWM_CONTROL
);
112 if (state
->polarity
== PWM_POLARITY_NORMAL
)
113 val
&= ~(PWM_POLARITY
<< PWM_CONTROL_SHIFT(pwm
->hwpwm
));
115 val
|= PWM_POLARITY
<< PWM_CONTROL_SHIFT(pwm
->hwpwm
);
119 val
|= PWM_ENABLE
<< PWM_CONTROL_SHIFT(pwm
->hwpwm
);
121 val
&= ~(PWM_ENABLE
<< PWM_CONTROL_SHIFT(pwm
->hwpwm
));
123 writel(val
, pc
->base
+ PWM_CONTROL
);
128 static const struct pwm_ops bcm2835_pwm_ops
= {
129 .request
= bcm2835_pwm_request
,
130 .free
= bcm2835_pwm_free
,
131 .apply
= bcm2835_pwm_apply
,
132 .owner
= THIS_MODULE
,
135 static int bcm2835_pwm_probe(struct platform_device
*pdev
)
137 struct bcm2835_pwm
*pc
;
140 pc
= devm_kzalloc(&pdev
->dev
, sizeof(*pc
), GFP_KERNEL
);
144 pc
->dev
= &pdev
->dev
;
146 pc
->base
= devm_platform_ioremap_resource(pdev
, 0);
147 if (IS_ERR(pc
->base
))
148 return PTR_ERR(pc
->base
);
150 pc
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
152 return dev_err_probe(&pdev
->dev
, PTR_ERR(pc
->clk
),
153 "clock not found\n");
155 ret
= clk_prepare_enable(pc
->clk
);
159 pc
->chip
.dev
= &pdev
->dev
;
160 pc
->chip
.ops
= &bcm2835_pwm_ops
;
163 platform_set_drvdata(pdev
, pc
);
165 ret
= pwmchip_add(&pc
->chip
);
172 clk_disable_unprepare(pc
->clk
);
176 static int bcm2835_pwm_remove(struct platform_device
*pdev
)
178 struct bcm2835_pwm
*pc
= platform_get_drvdata(pdev
);
180 pwmchip_remove(&pc
->chip
);
182 clk_disable_unprepare(pc
->clk
);
187 static const struct of_device_id bcm2835_pwm_of_match
[] = {
188 { .compatible
= "brcm,bcm2835-pwm", },
191 MODULE_DEVICE_TABLE(of
, bcm2835_pwm_of_match
);
193 static struct platform_driver bcm2835_pwm_driver
= {
195 .name
= "bcm2835-pwm",
196 .of_match_table
= bcm2835_pwm_of_match
,
198 .probe
= bcm2835_pwm_probe
,
199 .remove
= bcm2835_pwm_remove
,
201 module_platform_driver(bcm2835_pwm_driver
);
203 MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>");
204 MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
205 MODULE_LICENSE("GPL v2");