2 * PWM Controller Driver for HiSilicon BVT SoCs
4 * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/bitops.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/pwm.h>
28 #include <linux/reset.h>
30 #define PWM_CFG0_ADDR(x) (((x) * 0x20) + 0x0)
31 #define PWM_CFG1_ADDR(x) (((x) * 0x20) + 0x4)
32 #define PWM_CFG2_ADDR(x) (((x) * 0x20) + 0x8)
33 #define PWM_CTRL_ADDR(x) (((x) * 0x20) + 0xC)
35 #define PWM_ENABLE_SHIFT 0
36 #define PWM_ENABLE_MASK BIT(0)
38 #define PWM_POLARITY_SHIFT 1
39 #define PWM_POLARITY_MASK BIT(1)
41 #define PWM_KEEP_SHIFT 2
42 #define PWM_KEEP_MASK BIT(2)
44 #define PWM_PERIOD_MASK GENMASK(31, 0)
45 #define PWM_DUTY_MASK GENMASK(31, 0)
47 struct hibvt_pwm_chip
{
51 struct reset_control
*rstc
;
52 const struct hibvt_pwm_soc
*soc
;
55 struct hibvt_pwm_soc
{
57 bool quirk_force_enable
;
60 static const struct hibvt_pwm_soc hi3516cv300_soc_info
= {
64 static const struct hibvt_pwm_soc hi3519v100_soc_info
= {
68 static const struct hibvt_pwm_soc hi3559v100_shub_soc_info
= {
70 .quirk_force_enable
= true,
73 static const struct hibvt_pwm_soc hi3559v100_soc_info
= {
75 .quirk_force_enable
= true,
78 static inline struct hibvt_pwm_chip
*to_hibvt_pwm_chip(struct pwm_chip
*chip
)
80 return container_of(chip
, struct hibvt_pwm_chip
, chip
);
83 static void hibvt_pwm_set_bits(void __iomem
*base
, u32 offset
,
86 void __iomem
*address
= base
+ offset
;
89 value
= readl(address
);
91 value
|= (data
& mask
);
92 writel(value
, address
);
95 static void hibvt_pwm_enable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
97 struct hibvt_pwm_chip
*hi_pwm_chip
= to_hibvt_pwm_chip(chip
);
99 hibvt_pwm_set_bits(hi_pwm_chip
->base
, PWM_CTRL_ADDR(pwm
->hwpwm
),
100 PWM_ENABLE_MASK
, 0x1);
103 static void hibvt_pwm_disable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
105 struct hibvt_pwm_chip
*hi_pwm_chip
= to_hibvt_pwm_chip(chip
);
107 hibvt_pwm_set_bits(hi_pwm_chip
->base
, PWM_CTRL_ADDR(pwm
->hwpwm
),
108 PWM_ENABLE_MASK
, 0x0);
111 static void hibvt_pwm_config(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
112 int duty_cycle_ns
, int period_ns
)
114 struct hibvt_pwm_chip
*hi_pwm_chip
= to_hibvt_pwm_chip(chip
);
115 u32 freq
, period
, duty
;
117 freq
= div_u64(clk_get_rate(hi_pwm_chip
->clk
), 1000000);
119 period
= div_u64(freq
* period_ns
, 1000);
120 duty
= div_u64(period
* duty_cycle_ns
, period_ns
);
122 hibvt_pwm_set_bits(hi_pwm_chip
->base
, PWM_CFG0_ADDR(pwm
->hwpwm
),
123 PWM_PERIOD_MASK
, period
);
125 hibvt_pwm_set_bits(hi_pwm_chip
->base
, PWM_CFG1_ADDR(pwm
->hwpwm
),
126 PWM_DUTY_MASK
, duty
);
129 static void hibvt_pwm_set_polarity(struct pwm_chip
*chip
,
130 struct pwm_device
*pwm
,
131 enum pwm_polarity polarity
)
133 struct hibvt_pwm_chip
*hi_pwm_chip
= to_hibvt_pwm_chip(chip
);
135 if (polarity
== PWM_POLARITY_INVERSED
)
136 hibvt_pwm_set_bits(hi_pwm_chip
->base
, PWM_CTRL_ADDR(pwm
->hwpwm
),
137 PWM_POLARITY_MASK
, (0x1 << PWM_POLARITY_SHIFT
));
139 hibvt_pwm_set_bits(hi_pwm_chip
->base
, PWM_CTRL_ADDR(pwm
->hwpwm
),
140 PWM_POLARITY_MASK
, (0x0 << PWM_POLARITY_SHIFT
));
143 static void hibvt_pwm_get_state(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
144 struct pwm_state
*state
)
146 struct hibvt_pwm_chip
*hi_pwm_chip
= to_hibvt_pwm_chip(chip
);
150 freq
= div_u64(clk_get_rate(hi_pwm_chip
->clk
), 1000000);
151 base
= hi_pwm_chip
->base
;
153 value
= readl(base
+ PWM_CFG0_ADDR(pwm
->hwpwm
));
154 state
->period
= div_u64(value
* 1000, freq
);
156 value
= readl(base
+ PWM_CFG1_ADDR(pwm
->hwpwm
));
157 state
->duty_cycle
= div_u64(value
* 1000, freq
);
159 value
= readl(base
+ PWM_CTRL_ADDR(pwm
->hwpwm
));
160 state
->enabled
= (PWM_ENABLE_MASK
& value
);
163 static int hibvt_pwm_apply(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
164 struct pwm_state
*state
)
166 struct hibvt_pwm_chip
*hi_pwm_chip
= to_hibvt_pwm_chip(chip
);
168 if (state
->polarity
!= pwm
->state
.polarity
)
169 hibvt_pwm_set_polarity(chip
, pwm
, state
->polarity
);
171 if (state
->period
!= pwm
->state
.period
||
172 state
->duty_cycle
!= pwm
->state
.duty_cycle
) {
173 hibvt_pwm_config(chip
, pwm
, state
->duty_cycle
, state
->period
);
176 * Some implementations require the PWM to be enabled twice
177 * each time the duty cycle is refreshed.
179 if (hi_pwm_chip
->soc
->quirk_force_enable
&& state
->enabled
)
180 hibvt_pwm_enable(chip
, pwm
);
183 if (state
->enabled
!= pwm
->state
.enabled
) {
185 hibvt_pwm_enable(chip
, pwm
);
187 hibvt_pwm_disable(chip
, pwm
);
193 static const struct pwm_ops hibvt_pwm_ops
= {
194 .get_state
= hibvt_pwm_get_state
,
195 .apply
= hibvt_pwm_apply
,
197 .owner
= THIS_MODULE
,
200 static int hibvt_pwm_probe(struct platform_device
*pdev
)
202 const struct hibvt_pwm_soc
*soc
=
203 of_device_get_match_data(&pdev
->dev
);
204 struct hibvt_pwm_chip
*pwm_chip
;
205 struct resource
*res
;
209 pwm_chip
= devm_kzalloc(&pdev
->dev
, sizeof(*pwm_chip
), GFP_KERNEL
);
210 if (pwm_chip
== NULL
)
213 pwm_chip
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
214 if (IS_ERR(pwm_chip
->clk
)) {
215 dev_err(&pdev
->dev
, "getting clock failed with %ld\n",
216 PTR_ERR(pwm_chip
->clk
));
217 return PTR_ERR(pwm_chip
->clk
);
220 pwm_chip
->chip
.ops
= &hibvt_pwm_ops
;
221 pwm_chip
->chip
.dev
= &pdev
->dev
;
222 pwm_chip
->chip
.base
= -1;
223 pwm_chip
->chip
.npwm
= soc
->num_pwms
;
224 pwm_chip
->chip
.of_xlate
= of_pwm_xlate_with_flags
;
225 pwm_chip
->chip
.of_pwm_n_cells
= 3;
228 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
229 pwm_chip
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
230 if (IS_ERR(pwm_chip
->base
))
231 return PTR_ERR(pwm_chip
->base
);
233 ret
= clk_prepare_enable(pwm_chip
->clk
);
237 pwm_chip
->rstc
= devm_reset_control_get_exclusive(&pdev
->dev
, NULL
);
238 if (IS_ERR(pwm_chip
->rstc
)) {
239 clk_disable_unprepare(pwm_chip
->clk
);
240 return PTR_ERR(pwm_chip
->rstc
);
243 reset_control_assert(pwm_chip
->rstc
);
245 reset_control_deassert(pwm_chip
->rstc
);
247 ret
= pwmchip_add(&pwm_chip
->chip
);
249 clk_disable_unprepare(pwm_chip
->clk
);
253 for (i
= 0; i
< pwm_chip
->chip
.npwm
; i
++) {
254 hibvt_pwm_set_bits(pwm_chip
->base
, PWM_CTRL_ADDR(i
),
255 PWM_KEEP_MASK
, (0x1 << PWM_KEEP_SHIFT
));
258 platform_set_drvdata(pdev
, pwm_chip
);
263 static int hibvt_pwm_remove(struct platform_device
*pdev
)
265 struct hibvt_pwm_chip
*pwm_chip
;
267 pwm_chip
= platform_get_drvdata(pdev
);
269 reset_control_assert(pwm_chip
->rstc
);
271 reset_control_deassert(pwm_chip
->rstc
);
273 clk_disable_unprepare(pwm_chip
->clk
);
275 return pwmchip_remove(&pwm_chip
->chip
);
278 static const struct of_device_id hibvt_pwm_of_match
[] = {
279 { .compatible
= "hisilicon,hi3516cv300-pwm",
280 .data
= &hi3516cv300_soc_info
},
281 { .compatible
= "hisilicon,hi3519v100-pwm",
282 .data
= &hi3519v100_soc_info
},
283 { .compatible
= "hisilicon,hi3559v100-shub-pwm",
284 .data
= &hi3559v100_shub_soc_info
},
285 { .compatible
= "hisilicon,hi3559v100-pwm",
286 .data
= &hi3559v100_soc_info
},
289 MODULE_DEVICE_TABLE(of
, hibvt_pwm_of_match
);
291 static struct platform_driver hibvt_pwm_driver
= {
294 .of_match_table
= hibvt_pwm_of_match
,
296 .probe
= hibvt_pwm_probe
,
297 .remove
= hibvt_pwm_remove
,
299 module_platform_driver(hibvt_pwm_driver
);
301 MODULE_AUTHOR("Jian Yuan");
302 MODULE_DESCRIPTION("HiSilicon BVT SoCs PWM driver");
303 MODULE_LICENSE("GPL");