drivers/pwm/pwm-lpss.c

   1 /*
   2  * Intel Low Power Subsystem PWM controller driver
   3  *
   4  * Copyright (C) 2014, Intel Corporation
   5  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  * Author: Chew Kean Ho <kean.ho.chew@intel.com>
   7  * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
   8  * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
   9  * Author: Alan Cox <alan@linux.intel.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/io.h>
  18 #include <linux/iopoll.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/time.h>
  23
  24 #include "pwm-lpss.h"
  25
  26 #define PWM                             0x00000000
  27 #define PWM_ENABLE                      BIT(31)
  28 #define PWM_SW_UPDATE                   BIT(30)
  29 #define PWM_BASE_UNIT_SHIFT             8
  30 #define PWM_ON_TIME_DIV_MASK            0x000000ff
  31
  32 /* Size of each PWM register space if multiple */
  33 #define PWM_SIZE                        0x400
  34
  35 #define MAX_PWMS                        4
  36
  37 struct pwm_lpss_chip {
  38         struct pwm_chip chip;
  39         void __iomem *regs;
  40         const struct pwm_lpss_boardinfo *info;
  41         u32 saved_ctrl[MAX_PWMS];
  42 };
  43
  44 static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
  45 {
  46         return container_of(chip, struct pwm_lpss_chip, chip);
  47 }
  48
  49 static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
  50 {
  51         struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
  52
  53         return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
  54 }
  55
  56 static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
  57 {
  58         struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
  59
  60         writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
  61 }
  62
  63 static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
  64 {
  65         struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
  66         const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
  67         const unsigned int ms = 500 * USEC_PER_MSEC;
  68         u32 val;
  69         int err;
  70
  71         /*
  72          * PWM Configuration register has SW_UPDATE bit that is set when a new
  73          * configuration is written to the register. The bit is automatically
  74          * cleared at the start of the next output cycle by the IP block.
  75          *
  76          * If one writes a new configuration to the register while it still has
  77          * the bit enabled, PWM may freeze. That is, while one can still write
  78          * to the register, it won't have an effect. Thus, we try to sleep long
  79          * enough that the bit gets cleared and make sure the bit is not
  80          * enabled while we update the configuration.
  81          */
  82         err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
  83         if (err)
  84                 dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
  85
  86         return err;
  87 }
  88
  89 static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
  90 {
  91         return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
  92 }
  93
  94 static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
  95                              int duty_ns, int period_ns)
  96 {
  97         unsigned long long on_time_div;
  98         unsigned long c = lpwm->info->clk_rate, base_unit_range;
  99         unsigned long long base_unit, freq = NSEC_PER_SEC;
 100         u32 orig_ctrl, ctrl;
 101
 102         do_div(freq, period_ns);
 103
 104         /*
 105          * The equation is:
 106          * base_unit = round(base_unit_range * freq / c)
 107          */
 108         base_unit_range = BIT(lpwm->info->base_unit_bits) - 1;
 109         freq *= base_unit_range;
 110
 111         base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
 112
 113         on_time_div = 255ULL * duty_ns;
 114         do_div(on_time_div, period_ns);
 115         on_time_div = 255ULL - on_time_div;
 116
 117         orig_ctrl = ctrl = pwm_lpss_read(pwm);
 118         ctrl &= ~PWM_ON_TIME_DIV_MASK;
 119         ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT);
 120         base_unit &= base_unit_range;
 121         ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
 122         ctrl |= on_time_div;
 123
 124         if (orig_ctrl != ctrl) {
 125                 pwm_lpss_write(pwm, ctrl);
 126                 pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
 127         }
 128 }
 129
 130 static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
 131 {
 132         if (cond)
 133                 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
 134 }
 135
 136 static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 137                           struct pwm_state *state)
 138 {
 139         struct pwm_lpss_chip *lpwm = to_lpwm(chip);
 140         int ret;
 141
 142         if (state->enabled) {
 143                 if (!pwm_is_enabled(pwm)) {
 144                         pm_runtime_get_sync(chip->dev);
 145                         ret = pwm_lpss_is_updating(pwm);
 146                         if (ret) {
 147                                 pm_runtime_put(chip->dev);
 148                                 return ret;
 149                         }
 150                         pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
 151                         pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
 152                         ret = pwm_lpss_wait_for_update(pwm);
 153                         if (ret) {
 154                                 pm_runtime_put(chip->dev);
 155                                 return ret;
 156                         }
 157                         pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
 158                 } else {
 159                         ret = pwm_lpss_is_updating(pwm);
 160                         if (ret)
 161                                 return ret;
 162                         pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
 163                         return pwm_lpss_wait_for_update(pwm);
 164                 }
 165         } else if (pwm_is_enabled(pwm)) {
 166                 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
 167                 pm_runtime_put(chip->dev);
 168         }
 169
 170         return 0;
 171 }
 172
 173 static const struct pwm_ops pwm_lpss_ops = {
 174         .apply = pwm_lpss_apply,
 175         .owner = THIS_MODULE,
 176 };
 177
 178 struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
 179                                      const struct pwm_lpss_boardinfo *info)
 180 {
 181         struct pwm_lpss_chip *lpwm;
 182         unsigned long c;
 183         int ret;
 184
 185         if (WARN_ON(info->npwm > MAX_PWMS))
 186                 return ERR_PTR(-ENODEV);
 187
 188         lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
 189         if (!lpwm)
 190                 return ERR_PTR(-ENOMEM);
 191
 192         lpwm->regs = devm_ioremap_resource(dev, r);
 193         if (IS_ERR(lpwm->regs))
 194                 return ERR_CAST(lpwm->regs);
 195
 196         lpwm->info = info;
 197
 198         c = lpwm->info->clk_rate;
 199         if (!c)
 200                 return ERR_PTR(-EINVAL);
 201
 202         lpwm->chip.dev = dev;
 203         lpwm->chip.ops = &pwm_lpss_ops;
 204         lpwm->chip.base = -1;
 205         lpwm->chip.npwm = info->npwm;
 206
 207         ret = pwmchip_add(&lpwm->chip);
 208         if (ret) {
 209                 dev_err(dev, "failed to add PWM chip: %d\n", ret);
 210                 return ERR_PTR(ret);
 211         }
 212
 213         return lpwm;
 214 }
 215 EXPORT_SYMBOL_GPL(pwm_lpss_probe);
 216
 217 int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
 218 {
 219         int i;
 220
 221         for (i = 0; i < lpwm->info->npwm; i++) {
 222                 if (pwm_is_enabled(&lpwm->chip.pwms[i]))
 223                         pm_runtime_put(lpwm->chip.dev);
 224         }
 225         return pwmchip_remove(&lpwm->chip);
 226 }
 227 EXPORT_SYMBOL_GPL(pwm_lpss_remove);
 228
 229 int pwm_lpss_suspend(struct device *dev)
 230 {
 231         struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
 232         int i;
 233
 234         for (i = 0; i < lpwm->info->npwm; i++)
 235                 lpwm->saved_ctrl[i] = readl(lpwm->regs + i * PWM_SIZE + PWM);
 236
 237         return 0;
 238 }
 239 EXPORT_SYMBOL_GPL(pwm_lpss_suspend);
 240
 241 int pwm_lpss_resume(struct device *dev)
 242 {
 243         struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
 244         int i;
 245
 246         for (i = 0; i < lpwm->info->npwm; i++)
 247                 writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM);
 248
 249         return 0;
 250 }
 251 EXPORT_SYMBOL_GPL(pwm_lpss_resume);
 252
 253 MODULE_DESCRIPTION("PWM driver for Intel LPSS");
 254 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
 255 MODULE_LICENSE("GPL v2");