2 * Mediatek Pulse Width Modulator driver
4 * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/err.h>
14 #include <linux/ioport.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/clk.h>
19 #include <linux/platform_device.h>
20 #include <linux/pwm.h>
21 #include <linux/slab.h>
22 #include <linux/types.h>
24 /* PWM registers and bits definitions */
29 #define PWMWAVENUM 0x28
30 #define PWMDWIDTH 0x2c
33 #define PWM_CLK_DIV_MAX 7
46 static const char * const mtk_pwm_clk_name
[] = {
47 "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5"
51 * struct mtk_pwm_chip - struct representing PWM chip
52 * @chip: linux PWM chip representation
53 * @regs: base address of PWM chip
54 * @clks: list of clocks
59 struct clk
*clks
[MTK_CLK_MAX
];
62 static inline struct mtk_pwm_chip
*to_mtk_pwm_chip(struct pwm_chip
*chip
)
64 return container_of(chip
, struct mtk_pwm_chip
, chip
);
67 static int mtk_pwm_clk_enable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
69 struct mtk_pwm_chip
*pc
= to_mtk_pwm_chip(chip
);
72 ret
= clk_prepare_enable(pc
->clks
[MTK_CLK_TOP
]);
76 ret
= clk_prepare_enable(pc
->clks
[MTK_CLK_MAIN
]);
80 ret
= clk_prepare_enable(pc
->clks
[MTK_CLK_PWM1
+ pwm
->hwpwm
]);
82 goto disable_clk_main
;
87 clk_disable_unprepare(pc
->clks
[MTK_CLK_MAIN
]);
89 clk_disable_unprepare(pc
->clks
[MTK_CLK_TOP
]);
94 static void mtk_pwm_clk_disable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
96 struct mtk_pwm_chip
*pc
= to_mtk_pwm_chip(chip
);
98 clk_disable_unprepare(pc
->clks
[MTK_CLK_PWM1
+ pwm
->hwpwm
]);
99 clk_disable_unprepare(pc
->clks
[MTK_CLK_MAIN
]);
100 clk_disable_unprepare(pc
->clks
[MTK_CLK_TOP
]);
103 static inline u32
mtk_pwm_readl(struct mtk_pwm_chip
*chip
, unsigned int num
,
106 return readl(chip
->regs
+ 0x10 + (num
* 0x40) + offset
);
109 static inline void mtk_pwm_writel(struct mtk_pwm_chip
*chip
,
110 unsigned int num
, unsigned int offset
,
113 writel(value
, chip
->regs
+ 0x10 + (num
* 0x40) + offset
);
116 static int mtk_pwm_config(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
117 int duty_ns
, int period_ns
)
119 struct mtk_pwm_chip
*pc
= to_mtk_pwm_chip(chip
);
120 struct clk
*clk
= pc
->clks
[MTK_CLK_PWM1
+ pwm
->hwpwm
];
121 u32 resolution
, clkdiv
= 0;
124 ret
= mtk_pwm_clk_enable(chip
, pwm
);
128 resolution
= NSEC_PER_SEC
/ clk_get_rate(clk
);
130 while (period_ns
/ resolution
> 8191) {
135 if (clkdiv
> PWM_CLK_DIV_MAX
) {
136 mtk_pwm_clk_disable(chip
, pwm
);
137 dev_err(chip
->dev
, "period %d not supported\n", period_ns
);
141 mtk_pwm_writel(pc
, pwm
->hwpwm
, PWMCON
, BIT(15) | clkdiv
);
142 mtk_pwm_writel(pc
, pwm
->hwpwm
, PWMDWIDTH
, period_ns
/ resolution
);
143 mtk_pwm_writel(pc
, pwm
->hwpwm
, PWMTHRES
, duty_ns
/ resolution
);
145 mtk_pwm_clk_disable(chip
, pwm
);
150 static int mtk_pwm_enable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
152 struct mtk_pwm_chip
*pc
= to_mtk_pwm_chip(chip
);
156 ret
= mtk_pwm_clk_enable(chip
, pwm
);
160 value
= readl(pc
->regs
);
161 value
|= BIT(pwm
->hwpwm
);
162 writel(value
, pc
->regs
);
167 static void mtk_pwm_disable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
169 struct mtk_pwm_chip
*pc
= to_mtk_pwm_chip(chip
);
172 value
= readl(pc
->regs
);
173 value
&= ~BIT(pwm
->hwpwm
);
174 writel(value
, pc
->regs
);
176 mtk_pwm_clk_disable(chip
, pwm
);
179 static const struct pwm_ops mtk_pwm_ops
= {
180 .config
= mtk_pwm_config
,
181 .enable
= mtk_pwm_enable
,
182 .disable
= mtk_pwm_disable
,
183 .owner
= THIS_MODULE
,
186 static int mtk_pwm_probe(struct platform_device
*pdev
)
188 struct mtk_pwm_chip
*pc
;
189 struct resource
*res
;
193 pc
= devm_kzalloc(&pdev
->dev
, sizeof(*pc
), GFP_KERNEL
);
197 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
198 pc
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
199 if (IS_ERR(pc
->regs
))
200 return PTR_ERR(pc
->regs
);
202 for (i
= 0; i
< MTK_CLK_MAX
; i
++) {
203 pc
->clks
[i
] = devm_clk_get(&pdev
->dev
, mtk_pwm_clk_name
[i
]);
204 if (IS_ERR(pc
->clks
[i
]))
205 return PTR_ERR(pc
->clks
[i
]);
208 platform_set_drvdata(pdev
, pc
);
210 pc
->chip
.dev
= &pdev
->dev
;
211 pc
->chip
.ops
= &mtk_pwm_ops
;
215 ret
= pwmchip_add(&pc
->chip
);
217 dev_err(&pdev
->dev
, "pwmchip_add() failed: %d\n", ret
);
224 static int mtk_pwm_remove(struct platform_device
*pdev
)
226 struct mtk_pwm_chip
*pc
= platform_get_drvdata(pdev
);
228 return pwmchip_remove(&pc
->chip
);
231 static const struct of_device_id mtk_pwm_of_match
[] = {
232 { .compatible
= "mediatek,mt7623-pwm" },
235 MODULE_DEVICE_TABLE(of
, mtk_pwm_of_match
);
237 static struct platform_driver mtk_pwm_driver
= {
240 .of_match_table
= mtk_pwm_of_match
,
242 .probe
= mtk_pwm_probe
,
243 .remove
= mtk_pwm_remove
,
245 module_platform_driver(mtk_pwm_driver
);
247 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
248 MODULE_ALIAS("platform:mtk-pwm");
249 MODULE_LICENSE("GPL");