drivers/pwm/pwm-omap-dmtimer.c

   1 /*
   2  * Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com>
   3  * Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com>
   4  * Copyright (c) 2012 NeilBrown <neilb@suse.de>
   5  * Heavily based on earlier code which is:
   6  * Copyright (c) 2010 Grant Erickson <marathon96@gmail.com>
   7  *
   8  * Also based on pwm-samsung.c
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * version 2 as published by the Free Software Foundation.
  13  *
  14  * Description:
  15  *   This file is the core OMAP support for the generic, Linux
  16  *   PWM driver / controller, using the OMAP's dual-mode timers.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/err.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/mutex.h>
  24 #include <linux/of.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/platform_data/pwm_omap_dmtimer.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/pwm.h>
  30 #include <linux/slab.h>
  31 #include <linux/time.h>
  32
  33 #define DM_TIMER_LOAD_MIN 0xfffffffe
  34 #define DM_TIMER_MAX      0xffffffff
  35
  36 struct pwm_omap_dmtimer_chip {
  37         struct pwm_chip chip;
  38         struct mutex mutex;
  39         pwm_omap_dmtimer *dm_timer;
  40         struct pwm_omap_dmtimer_pdata *pdata;
  41         struct platform_device *dm_timer_pdev;
  42 };
  43
  44 static inline struct pwm_omap_dmtimer_chip *
  45 to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
  46 {
  47         return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
  48 }
  49
  50 static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
  51 {
  52         return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
  53 }
  54
  55 static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
  56 {
  57         /*
  58          * According to OMAP 4 TRM section 22.2.4.10 the counter should be
  59          * started at 0xFFFFFFFE when overflow and match is used to ensure
  60          * that the PWM line is toggled on the first event.
  61          *
  62          * Note that omap_dm_timer_enable/disable is for register access and
  63          * not the timer counter itself.
  64          */
  65         omap->pdata->enable(omap->dm_timer);
  66         omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
  67         omap->pdata->disable(omap->dm_timer);
  68
  69         omap->pdata->start(omap->dm_timer);
  70 }
  71
  72 static int pwm_omap_dmtimer_enable(struct pwm_chip *chip,
  73                                    struct pwm_device *pwm)
  74 {
  75         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
  76
  77         mutex_lock(&omap->mutex);
  78         pwm_omap_dmtimer_start(omap);
  79         mutex_unlock(&omap->mutex);
  80
  81         return 0;
  82 }
  83
  84 static void pwm_omap_dmtimer_disable(struct pwm_chip *chip,
  85                                      struct pwm_device *pwm)
  86 {
  87         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
  88
  89         mutex_lock(&omap->mutex);
  90         omap->pdata->stop(omap->dm_timer);
  91         mutex_unlock(&omap->mutex);
  92 }
  93
  94 static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
  95                                    struct pwm_device *pwm,
  96                                    int duty_ns, int period_ns)
  97 {
  98         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
  99         u32 period_cycles, duty_cycles;
 100         u32 load_value, match_value;
 101         struct clk *fclk;
 102         unsigned long clk_rate;
 103         bool timer_active;
 104
 105         dev_dbg(chip->dev, "requested duty cycle: %d ns, period: %d ns\n",
 106                 duty_ns, period_ns);
 107
 108         mutex_lock(&omap->mutex);
 109         if (duty_ns == pwm_get_duty_cycle(pwm) &&
 110             period_ns == pwm_get_period(pwm)) {
 111                 /* No change - don't cause any transients. */
 112                 mutex_unlock(&omap->mutex);
 113                 return 0;
 114         }
 115
 116         fclk = omap->pdata->get_fclk(omap->dm_timer);
 117         if (!fclk) {
 118                 dev_err(chip->dev, "invalid pmtimer fclk\n");
 119                 goto err_einval;
 120         }
 121
 122         clk_rate = clk_get_rate(fclk);
 123         if (!clk_rate) {
 124                 dev_err(chip->dev, "invalid pmtimer fclk rate\n");
 125                 goto err_einval;
 126         }
 127
 128         dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
 129
 130         /*
 131          * Calculate the appropriate load and match values based on the
 132          * specified period and duty cycle. The load value determines the
 133          * period time and the match value determines the duty time.
 134          *
 135          * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
 136          * Similarly, the active time lasts (match_value-load_value+1) cycles.
 137          * The non-active time is the remainder: (DM_TIMER_MAX-match_value)
 138          * clock cycles.
 139          *
 140          * NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
 141          *
 142          * References:
 143          *   OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
 144          *   AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
 145          */
 146         period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
 147         duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
 148
 149         if (period_cycles < 2) {
 150                 dev_info(chip->dev,
 151                          "period %d ns too short for clock rate %lu Hz\n",
 152                          period_ns, clk_rate);
 153                 goto err_einval;
 154         }
 155
 156         if (duty_cycles < 1) {
 157                 dev_dbg(chip->dev,
 158                         "duty cycle %d ns is too short for clock rate %lu Hz\n",
 159                         duty_ns, clk_rate);
 160                 dev_dbg(chip->dev, "using minimum of 1 clock cycle\n");
 161                 duty_cycles = 1;
 162         } else if (duty_cycles >= period_cycles) {
 163                 dev_dbg(chip->dev,
 164                         "duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
 165                         duty_ns, period_ns, clk_rate);
 166                 dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n");
 167                 duty_cycles = period_cycles - 1;
 168         }
 169
 170         dev_dbg(chip->dev, "effective duty cycle: %lld ns, period: %lld ns\n",
 171                 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles,
 172                                       clk_rate),
 173                 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles,
 174                                       clk_rate));
 175
 176         load_value = (DM_TIMER_MAX - period_cycles) + 1;
 177         match_value = load_value + duty_cycles - 1;
 178
 179         /*
 180          * We MUST stop the associated dual-mode timer before attempting to
 181          * write its registers, but calls to omap_dm_timer_start/stop must
 182          * be balanced so check if timer is active before calling timer_stop.
 183          */
 184         timer_active = pm_runtime_active(&omap->dm_timer_pdev->dev);
 185         if (timer_active)
 186                 omap->pdata->stop(omap->dm_timer);
 187
 188         omap->pdata->set_load(omap->dm_timer, true, load_value);
 189         omap->pdata->set_match(omap->dm_timer, true, match_value);
 190
 191         dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
 192                 load_value, load_value, match_value, match_value);
 193
 194         omap->pdata->set_pwm(omap->dm_timer,
 195                               pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED,
 196                               true,
 197                               PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
 198
 199         /* If config was called while timer was running it must be reenabled. */
 200         if (timer_active)
 201                 pwm_omap_dmtimer_start(omap);
 202
 203         mutex_unlock(&omap->mutex);
 204
 205         return 0;
 206
 207 err_einval:
 208         mutex_unlock(&omap->mutex);
 209
 210         return -EINVAL;
 211 }
 212
 213 static int pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
 214                                          struct pwm_device *pwm,
 215                                          enum pwm_polarity polarity)
 216 {
 217         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
 218
 219         /*
 220          * PWM core will not call set_polarity while PWM is enabled so it's
 221          * safe to reconfigure the timer here without stopping it first.
 222          */
 223         mutex_lock(&omap->mutex);
 224         omap->pdata->set_pwm(omap->dm_timer,
 225                               polarity == PWM_POLARITY_INVERSED,
 226                               true,
 227                               PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
 228         mutex_unlock(&omap->mutex);
 229
 230         return 0;
 231 }
 232
 233 static const struct pwm_ops pwm_omap_dmtimer_ops = {
 234         .enable = pwm_omap_dmtimer_enable,
 235         .disable = pwm_omap_dmtimer_disable,
 236         .config = pwm_omap_dmtimer_config,
 237         .set_polarity = pwm_omap_dmtimer_set_polarity,
 238         .owner = THIS_MODULE,
 239 };
 240
 241 static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
 242 {
 243         struct device_node *np = pdev->dev.of_node;
 244         struct device_node *timer;
 245         struct pwm_omap_dmtimer_chip *omap;
 246         struct pwm_omap_dmtimer_pdata *pdata;
 247         pwm_omap_dmtimer *dm_timer;
 248         u32 v;
 249         int status;
 250
 251         pdata = dev_get_platdata(&pdev->dev);
 252         if (!pdata) {
 253                 dev_err(&pdev->dev, "Missing dmtimer platform data\n");
 254                 return -EINVAL;
 255         }
 256
 257         if (!pdata->request_by_node ||
 258             !pdata->free ||
 259             !pdata->enable ||
 260             !pdata->disable ||
 261             !pdata->get_fclk ||
 262             !pdata->start ||
 263             !pdata->stop ||
 264             !pdata->set_load ||
 265             !pdata->set_match ||
 266             !pdata->set_pwm ||
 267             !pdata->set_prescaler ||
 268             !pdata->write_counter) {
 269                 dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
 270                 return -EINVAL;
 271         }
 272
 273         timer = of_parse_phandle(np, "ti,timers", 0);
 274         if (!timer)
 275                 return -ENODEV;
 276
 277         if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
 278                 dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
 279                 return -ENODEV;
 280         }
 281
 282         dm_timer = pdata->request_by_node(timer);
 283         if (!dm_timer)
 284                 return -EPROBE_DEFER;
 285
 286         omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
 287         if (!omap) {
 288                 pdata->free(dm_timer);
 289                 return -ENOMEM;
 290         }
 291
 292         omap->pdata = pdata;
 293         omap->dm_timer = dm_timer;
 294
 295         omap->dm_timer_pdev = of_find_device_by_node(timer);
 296         if (!omap->dm_timer_pdev) {
 297                 dev_err(&pdev->dev, "Unable to find timer pdev\n");
 298                 omap->pdata->free(dm_timer);
 299                 return -EINVAL;
 300         }
 301
 302         /*
 303          * Ensure that the timer is stopped before we allow PWM core to call
 304          * pwm_enable.
 305          */
 306         if (pm_runtime_active(&omap->dm_timer_pdev->dev))
 307                 omap->pdata->stop(omap->dm_timer);
 308
 309         if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
 310                 omap->pdata->set_prescaler(omap->dm_timer, v);
 311
 312         /* setup dmtimer clock source */
 313         if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
 314                 omap->pdata->set_source(omap->dm_timer, v);
 315
 316         omap->chip.dev = &pdev->dev;
 317         omap->chip.ops = &pwm_omap_dmtimer_ops;
 318         omap->chip.base = -1;
 319         omap->chip.npwm = 1;
 320         omap->chip.of_xlate = of_pwm_xlate_with_flags;
 321         omap->chip.of_pwm_n_cells = 3;
 322
 323         mutex_init(&omap->mutex);
 324
 325         status = pwmchip_add(&omap->chip);
 326         if (status < 0) {
 327                 dev_err(&pdev->dev, "failed to register PWM\n");
 328                 omap->pdata->free(omap->dm_timer);
 329                 return status;
 330         }
 331
 332         platform_set_drvdata(pdev, omap);
 333
 334         return 0;
 335 }
 336
 337 static int pwm_omap_dmtimer_remove(struct platform_device *pdev)
 338 {
 339         struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);
 340
 341         if (pm_runtime_active(&omap->dm_timer_pdev->dev))
 342                 omap->pdata->stop(omap->dm_timer);
 343
 344         omap->pdata->free(omap->dm_timer);
 345
 346         mutex_destroy(&omap->mutex);
 347
 348         return pwmchip_remove(&omap->chip);
 349 }
 350
 351 static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
 352         {.compatible = "ti,omap-dmtimer-pwm"},
 353         {}
 354 };
 355 MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
 356
 357 static struct platform_driver pwm_omap_dmtimer_driver = {
 358         .driver = {
 359                 .name = "omap-dmtimer-pwm",
 360                 .of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match),
 361         },
 362         .probe = pwm_omap_dmtimer_probe,
 363         .remove = pwm_omap_dmtimer_remove,
 364 };
 365 module_platform_driver(pwm_omap_dmtimer_driver);
 366
 367 MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>");
 368 MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
 369 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
 370 MODULE_LICENSE("GPL v2");
 371 MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");