1 // SPDX-License-Identifier: GPL-2.0-only
3 * PWM driver for Rockchip SoCs
5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6 * Copyright (C) 2014 ROCKCHIP, Inc.
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/pwm.h>
16 #include <linux/time.h>
18 #define PWM_CTRL_TIMER_EN (1 << 0)
19 #define PWM_CTRL_OUTPUT_EN (1 << 3)
21 #define PWM_ENABLE (1 << 0)
22 #define PWM_CONTINUOUS (1 << 1)
23 #define PWM_DUTY_POSITIVE (1 << 3)
24 #define PWM_DUTY_NEGATIVE (0 << 3)
25 #define PWM_INACTIVE_NEGATIVE (0 << 4)
26 #define PWM_INACTIVE_POSITIVE (1 << 4)
27 #define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
28 #define PWM_OUTPUT_LEFT (0 << 5)
29 #define PWM_LOCK_EN (1 << 6)
30 #define PWM_LP_DISABLE (0 << 8)
32 struct rockchip_pwm_chip
{
36 const struct rockchip_pwm_data
*data
;
40 struct rockchip_pwm_regs
{
47 struct rockchip_pwm_data
{
48 struct rockchip_pwm_regs regs
;
49 unsigned int prescaler
;
50 bool supports_polarity
;
55 static inline struct rockchip_pwm_chip
*to_rockchip_pwm_chip(struct pwm_chip
*c
)
57 return container_of(c
, struct rockchip_pwm_chip
, chip
);
60 static void rockchip_pwm_get_state(struct pwm_chip
*chip
,
61 struct pwm_device
*pwm
,
62 struct pwm_state
*state
)
64 struct rockchip_pwm_chip
*pc
= to_rockchip_pwm_chip(chip
);
65 u32 enable_conf
= pc
->data
->enable_conf
;
66 unsigned long clk_rate
;
71 ret
= clk_enable(pc
->pclk
);
75 clk_rate
= clk_get_rate(pc
->clk
);
77 tmp
= readl_relaxed(pc
->base
+ pc
->data
->regs
.period
);
78 tmp
*= pc
->data
->prescaler
* NSEC_PER_SEC
;
79 state
->period
= DIV_ROUND_CLOSEST_ULL(tmp
, clk_rate
);
81 tmp
= readl_relaxed(pc
->base
+ pc
->data
->regs
.duty
);
82 tmp
*= pc
->data
->prescaler
* NSEC_PER_SEC
;
83 state
->duty_cycle
= DIV_ROUND_CLOSEST_ULL(tmp
, clk_rate
);
85 val
= readl_relaxed(pc
->base
+ pc
->data
->regs
.ctrl
);
86 state
->enabled
= (val
& enable_conf
) == enable_conf
;
88 if (pc
->data
->supports_polarity
&& !(val
& PWM_DUTY_POSITIVE
))
89 state
->polarity
= PWM_POLARITY_INVERSED
;
91 state
->polarity
= PWM_POLARITY_NORMAL
;
93 clk_disable(pc
->pclk
);
96 static void rockchip_pwm_config(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
97 const struct pwm_state
*state
)
99 struct rockchip_pwm_chip
*pc
= to_rockchip_pwm_chip(chip
);
100 unsigned long period
, duty
;
104 clk_rate
= clk_get_rate(pc
->clk
);
107 * Since period and duty cycle registers have a width of 32
108 * bits, every possible input period can be obtained using the
109 * default prescaler value for all practical clock rate values.
111 div
= clk_rate
* state
->period
;
112 period
= DIV_ROUND_CLOSEST_ULL(div
,
113 pc
->data
->prescaler
* NSEC_PER_SEC
);
115 div
= clk_rate
* state
->duty_cycle
;
116 duty
= DIV_ROUND_CLOSEST_ULL(div
, pc
->data
->prescaler
* NSEC_PER_SEC
);
119 * Lock the period and duty of previous configuration, then
120 * change the duty and period, that would not be effective.
122 ctrl
= readl_relaxed(pc
->base
+ pc
->data
->regs
.ctrl
);
123 if (pc
->data
->supports_lock
) {
125 writel_relaxed(ctrl
, pc
->base
+ pc
->data
->regs
.ctrl
);
128 writel(period
, pc
->base
+ pc
->data
->regs
.period
);
129 writel(duty
, pc
->base
+ pc
->data
->regs
.duty
);
131 if (pc
->data
->supports_polarity
) {
132 ctrl
&= ~PWM_POLARITY_MASK
;
133 if (state
->polarity
== PWM_POLARITY_INVERSED
)
134 ctrl
|= PWM_DUTY_NEGATIVE
| PWM_INACTIVE_POSITIVE
;
136 ctrl
|= PWM_DUTY_POSITIVE
| PWM_INACTIVE_NEGATIVE
;
140 * Unlock and set polarity at the same time,
141 * the configuration of duty, period and polarity
142 * would be effective together at next period.
144 if (pc
->data
->supports_lock
)
145 ctrl
&= ~PWM_LOCK_EN
;
147 writel(ctrl
, pc
->base
+ pc
->data
->regs
.ctrl
);
150 static int rockchip_pwm_enable(struct pwm_chip
*chip
,
151 struct pwm_device
*pwm
,
154 struct rockchip_pwm_chip
*pc
= to_rockchip_pwm_chip(chip
);
155 u32 enable_conf
= pc
->data
->enable_conf
;
160 ret
= clk_enable(pc
->clk
);
165 val
= readl_relaxed(pc
->base
+ pc
->data
->regs
.ctrl
);
172 writel_relaxed(val
, pc
->base
+ pc
->data
->regs
.ctrl
);
175 clk_disable(pc
->clk
);
180 static int rockchip_pwm_apply(struct pwm_chip
*chip
, struct pwm_device
*pwm
,
181 const struct pwm_state
*state
)
183 struct rockchip_pwm_chip
*pc
= to_rockchip_pwm_chip(chip
);
184 struct pwm_state curstate
;
188 ret
= clk_enable(pc
->pclk
);
192 pwm_get_state(pwm
, &curstate
);
193 enabled
= curstate
.enabled
;
195 if (state
->polarity
!= curstate
.polarity
&& enabled
&&
196 !pc
->data
->supports_lock
) {
197 ret
= rockchip_pwm_enable(chip
, pwm
, false);
203 rockchip_pwm_config(chip
, pwm
, state
);
204 if (state
->enabled
!= enabled
) {
205 ret
= rockchip_pwm_enable(chip
, pwm
, state
->enabled
);
211 clk_disable(pc
->pclk
);
216 static const struct pwm_ops rockchip_pwm_ops
= {
217 .get_state
= rockchip_pwm_get_state
,
218 .apply
= rockchip_pwm_apply
,
219 .owner
= THIS_MODULE
,
222 static const struct rockchip_pwm_data pwm_data_v1
= {
230 .supports_polarity
= false,
231 .supports_lock
= false,
232 .enable_conf
= PWM_CTRL_OUTPUT_EN
| PWM_CTRL_TIMER_EN
,
235 static const struct rockchip_pwm_data pwm_data_v2
= {
243 .supports_polarity
= true,
244 .supports_lock
= false,
245 .enable_conf
= PWM_OUTPUT_LEFT
| PWM_LP_DISABLE
| PWM_ENABLE
|
249 static const struct rockchip_pwm_data pwm_data_vop
= {
257 .supports_polarity
= true,
258 .supports_lock
= false,
259 .enable_conf
= PWM_OUTPUT_LEFT
| PWM_LP_DISABLE
| PWM_ENABLE
|
263 static const struct rockchip_pwm_data pwm_data_v3
= {
271 .supports_polarity
= true,
272 .supports_lock
= true,
273 .enable_conf
= PWM_OUTPUT_LEFT
| PWM_LP_DISABLE
| PWM_ENABLE
|
277 static const struct of_device_id rockchip_pwm_dt_ids
[] = {
278 { .compatible
= "rockchip,rk2928-pwm", .data
= &pwm_data_v1
},
279 { .compatible
= "rockchip,rk3288-pwm", .data
= &pwm_data_v2
},
280 { .compatible
= "rockchip,vop-pwm", .data
= &pwm_data_vop
},
281 { .compatible
= "rockchip,rk3328-pwm", .data
= &pwm_data_v3
},
284 MODULE_DEVICE_TABLE(of
, rockchip_pwm_dt_ids
);
286 static int rockchip_pwm_probe(struct platform_device
*pdev
)
288 const struct of_device_id
*id
;
289 struct rockchip_pwm_chip
*pc
;
293 id
= of_match_device(rockchip_pwm_dt_ids
, &pdev
->dev
);
297 pc
= devm_kzalloc(&pdev
->dev
, sizeof(*pc
), GFP_KERNEL
);
301 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
302 pc
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
303 if (IS_ERR(pc
->base
))
304 return PTR_ERR(pc
->base
);
306 pc
->clk
= devm_clk_get(&pdev
->dev
, "pwm");
307 if (IS_ERR(pc
->clk
)) {
308 pc
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
309 if (IS_ERR(pc
->clk
)) {
310 ret
= PTR_ERR(pc
->clk
);
311 if (ret
!= -EPROBE_DEFER
)
312 dev_err(&pdev
->dev
, "Can't get bus clk: %d\n",
318 count
= of_count_phandle_with_args(pdev
->dev
.of_node
,
319 "clocks", "#clock-cells");
321 pc
->pclk
= devm_clk_get(&pdev
->dev
, "pclk");
325 if (IS_ERR(pc
->pclk
)) {
326 ret
= PTR_ERR(pc
->pclk
);
327 if (ret
!= -EPROBE_DEFER
)
328 dev_err(&pdev
->dev
, "Can't get APB clk: %d\n", ret
);
332 ret
= clk_prepare_enable(pc
->clk
);
334 dev_err(&pdev
->dev
, "Can't prepare enable bus clk: %d\n", ret
);
338 ret
= clk_prepare(pc
->pclk
);
340 dev_err(&pdev
->dev
, "Can't prepare APB clk: %d\n", ret
);
344 platform_set_drvdata(pdev
, pc
);
347 pc
->chip
.dev
= &pdev
->dev
;
348 pc
->chip
.ops
= &rockchip_pwm_ops
;
352 if (pc
->data
->supports_polarity
) {
353 pc
->chip
.of_xlate
= of_pwm_xlate_with_flags
;
354 pc
->chip
.of_pwm_n_cells
= 3;
357 ret
= pwmchip_add(&pc
->chip
);
359 clk_unprepare(pc
->clk
);
360 dev_err(&pdev
->dev
, "pwmchip_add() failed: %d\n", ret
);
364 /* Keep the PWM clk enabled if the PWM appears to be up and running. */
365 if (!pwm_is_enabled(pc
->chip
.pwms
))
366 clk_disable(pc
->clk
);
371 clk_unprepare(pc
->pclk
);
373 clk_disable_unprepare(pc
->clk
);
378 static int rockchip_pwm_remove(struct platform_device
*pdev
)
380 struct rockchip_pwm_chip
*pc
= platform_get_drvdata(pdev
);
383 * Disable the PWM clk before unpreparing it if the PWM device is still
384 * running. This should only happen when the last PWM user left it
385 * enabled, or when nobody requested a PWM that was previously enabled
388 * FIXME: Maybe the core should disable all PWM devices in
389 * pwmchip_remove(). In this case we'd only have to call
390 * clk_unprepare() after pwmchip_remove().
393 if (pwm_is_enabled(pc
->chip
.pwms
))
394 clk_disable(pc
->clk
);
396 clk_unprepare(pc
->pclk
);
397 clk_unprepare(pc
->clk
);
399 return pwmchip_remove(&pc
->chip
);
402 static struct platform_driver rockchip_pwm_driver
= {
404 .name
= "rockchip-pwm",
405 .of_match_table
= rockchip_pwm_dt_ids
,
407 .probe
= rockchip_pwm_probe
,
408 .remove
= rockchip_pwm_remove
,
410 module_platform_driver(rockchip_pwm_driver
);
412 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
413 MODULE_DESCRIPTION("Rockchip SoC PWM driver");
414 MODULE_LICENSE("GPL v2");