drivers/remoteproc/qcom_wcnss.c

   1 /*
   2  * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
   3  *
   4  * Copyright (C) 2016 Linaro Ltd
   5  * Copyright (C) 2014 Sony Mobile Communications AB
   6  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/firmware.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/io.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/qcom_scm.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/remoteproc.h>
  31 #include <linux/soc/qcom/mdt_loader.h>
  32 #include <linux/soc/qcom/smem.h>
  33 #include <linux/soc/qcom/smem_state.h>
  34 #include <linux/rpmsg/qcom_smd.h>
  35
  36 #include "qcom_common.h"
  37 #include "remoteproc_internal.h"
  38 #include "qcom_wcnss.h"
  39
  40 #define WCNSS_CRASH_REASON_SMEM         422
  41 #define WCNSS_FIRMWARE_NAME             "wcnss.mdt"
  42 #define WCNSS_PAS_ID                    6
  43
  44 #define WCNSS_SPARE_NVBIN_DLND          BIT(25)
  45
  46 #define WCNSS_PMU_IRIS_XO_CFG           BIT(3)
  47 #define WCNSS_PMU_IRIS_XO_EN            BIT(4)
  48 #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP    BIT(5)
  49 #define WCNSS_PMU_IRIS_XO_CFG_STS       BIT(6) /* 1: in progress, 0: done */
  50
  51 #define WCNSS_PMU_IRIS_RESET            BIT(7)
  52 #define WCNSS_PMU_IRIS_RESET_STS        BIT(8) /* 1: in progress, 0: done */
  53 #define WCNSS_PMU_IRIS_XO_READ          BIT(9)
  54 #define WCNSS_PMU_IRIS_XO_READ_STS      BIT(10)
  55
  56 #define WCNSS_PMU_XO_MODE_MASK          GENMASK(2, 1)
  57 #define WCNSS_PMU_XO_MODE_19p2          0
  58 #define WCNSS_PMU_XO_MODE_48            3
  59
  60 struct wcnss_data {
  61         size_t pmu_offset;
  62         size_t spare_offset;
  63
  64         const struct wcnss_vreg_info *vregs;
  65         size_t num_vregs;
  66 };
  67
  68 struct qcom_wcnss {
  69         struct device *dev;
  70         struct rproc *rproc;
  71
  72         void __iomem *pmu_cfg;
  73         void __iomem *spare_out;
  74
  75         bool use_48mhz_xo;
  76
  77         int wdog_irq;
  78         int fatal_irq;
  79         int ready_irq;
  80         int handover_irq;
  81         int stop_ack_irq;
  82
  83         struct qcom_smem_state *state;
  84         unsigned stop_bit;
  85
  86         struct mutex iris_lock;
  87         struct qcom_iris *iris;
  88
  89         struct regulator_bulk_data *vregs;
  90         size_t num_vregs;
  91
  92         struct completion start_done;
  93         struct completion stop_done;
  94
  95         phys_addr_t mem_phys;
  96         phys_addr_t mem_reloc;
  97         void *mem_region;
  98         size_t mem_size;
  99
 100         struct qcom_rproc_subdev smd_subdev;
 101 };
 102
 103 static const struct wcnss_data riva_data = {
 104         .pmu_offset = 0x28,
 105         .spare_offset = 0xb4,
 106
 107         .vregs = (struct wcnss_vreg_info[]) {
 108                 { "vddmx",  1050000, 1150000, 0 },
 109                 { "vddcx",  1050000, 1150000, 0 },
 110                 { "vddpx",  1800000, 1800000, 0 },
 111         },
 112         .num_vregs = 3,
 113 };
 114
 115 static const struct wcnss_data pronto_v1_data = {
 116         .pmu_offset = 0x1004,
 117         .spare_offset = 0x1088,
 118
 119         .vregs = (struct wcnss_vreg_info[]) {
 120                 { "vddmx", 950000, 1150000, 0 },
 121                 { "vddcx", .super_turbo = true},
 122                 { "vddpx", 1800000, 1800000, 0 },
 123         },
 124         .num_vregs = 3,
 125 };
 126
 127 static const struct wcnss_data pronto_v2_data = {
 128         .pmu_offset = 0x1004,
 129         .spare_offset = 0x1088,
 130
 131         .vregs = (struct wcnss_vreg_info[]) {
 132                 { "vddmx", 1287500, 1287500, 0 },
 133                 { "vddcx", .super_turbo = true },
 134                 { "vddpx", 1800000, 1800000, 0 },
 135         },
 136         .num_vregs = 3,
 137 };
 138
 139 void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
 140                             struct qcom_iris *iris,
 141                             bool use_48mhz_xo)
 142 {
 143         mutex_lock(&wcnss->iris_lock);
 144
 145         wcnss->iris = iris;
 146         wcnss->use_48mhz_xo = use_48mhz_xo;
 147
 148         mutex_unlock(&wcnss->iris_lock);
 149 }
 150
 151 static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
 152 {
 153         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 154
 155         return qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
 156                              wcnss->mem_region, wcnss->mem_phys,
 157                              wcnss->mem_size, &wcnss->mem_reloc);
 158 }
 159
 160 static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
 161 {
 162         u32 val;
 163
 164         /* Indicate NV download capability */
 165         val = readl(wcnss->spare_out);
 166         val |= WCNSS_SPARE_NVBIN_DLND;
 167         writel(val, wcnss->spare_out);
 168 }
 169
 170 static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
 171 {
 172         u32 val;
 173
 174         /* Clear PMU cfg register */
 175         writel(0, wcnss->pmu_cfg);
 176
 177         val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN;
 178         writel(val, wcnss->pmu_cfg);
 179
 180         /* Clear XO_MODE */
 181         val &= ~WCNSS_PMU_XO_MODE_MASK;
 182         if (wcnss->use_48mhz_xo)
 183                 val |= WCNSS_PMU_XO_MODE_48 << 1;
 184         else
 185                 val |= WCNSS_PMU_XO_MODE_19p2 << 1;
 186         writel(val, wcnss->pmu_cfg);
 187
 188         /* Reset IRIS */
 189         val |= WCNSS_PMU_IRIS_RESET;
 190         writel(val, wcnss->pmu_cfg);
 191
 192         /* Wait for PMU.iris_reg_reset_sts */
 193         while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
 194                 cpu_relax();
 195
 196         /* Clear IRIS reset */
 197         val &= ~WCNSS_PMU_IRIS_RESET;
 198         writel(val, wcnss->pmu_cfg);
 199
 200         /* Start IRIS XO configuration */
 201         val |= WCNSS_PMU_IRIS_XO_CFG;
 202         writel(val, wcnss->pmu_cfg);
 203
 204         /* Wait for XO configuration to finish */
 205         while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
 206                 cpu_relax();
 207
 208         /* Stop IRIS XO configuration */
 209         val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
 210         val &= ~WCNSS_PMU_IRIS_XO_CFG;
 211         writel(val, wcnss->pmu_cfg);
 212
 213         /* Add some delay for XO to settle */
 214         msleep(20);
 215 }
 216
 217 static int wcnss_start(struct rproc *rproc)
 218 {
 219         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 220         int ret;
 221
 222         mutex_lock(&wcnss->iris_lock);
 223         if (!wcnss->iris) {
 224                 dev_err(wcnss->dev, "no iris registered\n");
 225                 ret = -EINVAL;
 226                 goto release_iris_lock;
 227         }
 228
 229         ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
 230         if (ret)
 231                 goto release_iris_lock;
 232
 233         ret = qcom_iris_enable(wcnss->iris);
 234         if (ret)
 235                 goto disable_regulators;
 236
 237         wcnss_indicate_nv_download(wcnss);
 238         wcnss_configure_iris(wcnss);
 239
 240         ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
 241         if (ret) {
 242                 dev_err(wcnss->dev,
 243                         "failed to authenticate image and release reset\n");
 244                 goto disable_iris;
 245         }
 246
 247         ret = wait_for_completion_timeout(&wcnss->start_done,
 248                                           msecs_to_jiffies(5000));
 249         if (wcnss->ready_irq > 0 && ret == 0) {
 250                 /* We have a ready_irq, but it didn't fire in time. */
 251                 dev_err(wcnss->dev, "start timed out\n");
 252                 qcom_scm_pas_shutdown(WCNSS_PAS_ID);
 253                 ret = -ETIMEDOUT;
 254                 goto disable_iris;
 255         }
 256
 257         ret = 0;
 258
 259 disable_iris:
 260         qcom_iris_disable(wcnss->iris);
 261 disable_regulators:
 262         regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
 263 release_iris_lock:
 264         mutex_unlock(&wcnss->iris_lock);
 265
 266         return ret;
 267 }
 268
 269 static int wcnss_stop(struct rproc *rproc)
 270 {
 271         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 272         int ret;
 273
 274         if (wcnss->state) {
 275                 qcom_smem_state_update_bits(wcnss->state,
 276                                             BIT(wcnss->stop_bit),
 277                                             BIT(wcnss->stop_bit));
 278
 279                 ret = wait_for_completion_timeout(&wcnss->stop_done,
 280                                                   msecs_to_jiffies(5000));
 281                 if (ret == 0)
 282                         dev_err(wcnss->dev, "timed out on wait\n");
 283
 284                 qcom_smem_state_update_bits(wcnss->state,
 285                                             BIT(wcnss->stop_bit),
 286                                             0);
 287         }
 288
 289         ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
 290         if (ret)
 291                 dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);
 292
 293         return ret;
 294 }
 295
 296 static void *wcnss_da_to_va(struct rproc *rproc, u64 da, int len)
 297 {
 298         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 299         int offset;
 300
 301         offset = da - wcnss->mem_reloc;
 302         if (offset < 0 || offset + len > wcnss->mem_size)
 303                 return NULL;
 304
 305         return wcnss->mem_region + offset;
 306 }
 307
 308 static const struct rproc_ops wcnss_ops = {
 309         .start = wcnss_start,
 310         .stop = wcnss_stop,
 311         .da_to_va = wcnss_da_to_va,
 312         .parse_fw = qcom_register_dump_segments,
 313         .load = wcnss_load,
 314 };
 315
 316 static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
 317 {
 318         struct qcom_wcnss *wcnss = dev;
 319
 320         rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);
 321
 322         return IRQ_HANDLED;
 323 }
 324
 325 static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
 326 {
 327         struct qcom_wcnss *wcnss = dev;
 328         size_t len;
 329         char *msg;
 330
 331         msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
 332         if (!IS_ERR(msg) && len > 0 && msg[0])
 333                 dev_err(wcnss->dev, "fatal error received: %s\n", msg);
 334
 335         rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);
 336
 337         return IRQ_HANDLED;
 338 }
 339
 340 static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
 341 {
 342         struct qcom_wcnss *wcnss = dev;
 343
 344         complete(&wcnss->start_done);
 345
 346         return IRQ_HANDLED;
 347 }
 348
 349 static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
 350 {
 351         /*
 352          * XXX: At this point we're supposed to release the resources that we
 353          * have been holding on behalf of the WCNSS. Unfortunately this
 354          * interrupt comes way before the other side seems to be done.
 355          *
 356          * So we're currently relying on the ready interrupt firing later then
 357          * this and we just disable the resources at the end of wcnss_start().
 358          */
 359
 360         return IRQ_HANDLED;
 361 }
 362
 363 static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
 364 {
 365         struct qcom_wcnss *wcnss = dev;
 366
 367         complete(&wcnss->stop_done);
 368
 369         return IRQ_HANDLED;
 370 }
 371
 372 static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
 373                                  const struct wcnss_vreg_info *info,
 374                                  int num_vregs)
 375 {
 376         struct regulator_bulk_data *bulk;
 377         int ret;
 378         int i;
 379
 380         bulk = devm_kcalloc(wcnss->dev,
 381                             num_vregs, sizeof(struct regulator_bulk_data),
 382                             GFP_KERNEL);
 383         if (!bulk)
 384                 return -ENOMEM;
 385
 386         for (i = 0; i < num_vregs; i++)
 387                 bulk[i].supply = info[i].name;
 388
 389         ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
 390         if (ret)
 391                 return ret;
 392
 393         for (i = 0; i < num_vregs; i++) {
 394                 if (info[i].max_voltage)
 395                         regulator_set_voltage(bulk[i].consumer,
 396                                               info[i].min_voltage,
 397                                               info[i].max_voltage);
 398
 399                 if (info[i].load_uA)
 400                         regulator_set_load(bulk[i].consumer, info[i].load_uA);
 401         }
 402
 403         wcnss->vregs = bulk;
 404         wcnss->num_vregs = num_vregs;
 405
 406         return 0;
 407 }
 408
 409 static int wcnss_request_irq(struct qcom_wcnss *wcnss,
 410                              struct platform_device *pdev,
 411                              const char *name,
 412                              bool optional,
 413                              irq_handler_t thread_fn)
 414 {
 415         int ret;
 416
 417         ret = platform_get_irq_byname(pdev, name);
 418         if (ret < 0 && optional) {
 419                 dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
 420                 return 0;
 421         } else if (ret < 0) {
 422                 dev_err(&pdev->dev, "no %s IRQ defined\n", name);
 423                 return ret;
 424         }
 425
 426         ret = devm_request_threaded_irq(&pdev->dev, ret,
 427                                         NULL, thread_fn,
 428                                         IRQF_TRIGGER_RISING | IRQF_ONESHOT,
 429                                         "wcnss", wcnss);
 430         if (ret)
 431                 dev_err(&pdev->dev, "request %s IRQ failed\n", name);
 432
 433         return ret;
 434 }
 435
 436 static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
 437 {
 438         struct device_node *node;
 439         struct resource r;
 440         int ret;
 441
 442         node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
 443         if (!node) {
 444                 dev_err(wcnss->dev, "no memory-region specified\n");
 445                 return -EINVAL;
 446         }
 447
 448         ret = of_address_to_resource(node, 0, &r);
 449         if (ret)
 450                 return ret;
 451
 452         wcnss->mem_phys = wcnss->mem_reloc = r.start;
 453         wcnss->mem_size = resource_size(&r);
 454         wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
 455         if (!wcnss->mem_region) {
 456                 dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
 457                         &r.start, wcnss->mem_size);
 458                 return -EBUSY;
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int wcnss_probe(struct platform_device *pdev)
 465 {
 466         const struct wcnss_data *data;
 467         struct qcom_wcnss *wcnss;
 468         struct resource *res;
 469         struct rproc *rproc;
 470         void __iomem *mmio;
 471         int ret;
 472
 473         data = of_device_get_match_data(&pdev->dev);
 474
 475         if (!qcom_scm_is_available())
 476                 return -EPROBE_DEFER;
 477
 478         if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
 479                 dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
 480                 return -ENXIO;
 481         }
 482
 483         rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
 484                             WCNSS_FIRMWARE_NAME, sizeof(*wcnss));
 485         if (!rproc) {
 486                 dev_err(&pdev->dev, "unable to allocate remoteproc\n");
 487                 return -ENOMEM;
 488         }
 489
 490         wcnss = (struct qcom_wcnss *)rproc->priv;
 491         wcnss->dev = &pdev->dev;
 492         wcnss->rproc = rproc;
 493         platform_set_drvdata(pdev, wcnss);
 494
 495         init_completion(&wcnss->start_done);
 496         init_completion(&wcnss->stop_done);
 497
 498         mutex_init(&wcnss->iris_lock);
 499
 500         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
 501         mmio = devm_ioremap_resource(&pdev->dev, res);
 502         if (IS_ERR(mmio)) {
 503                 ret = PTR_ERR(mmio);
 504                 goto free_rproc;
 505         };
 506
 507         ret = wcnss_alloc_memory_region(wcnss);
 508         if (ret)
 509                 goto free_rproc;
 510
 511         wcnss->pmu_cfg = mmio + data->pmu_offset;
 512         wcnss->spare_out = mmio + data->spare_offset;
 513
 514         ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs);
 515         if (ret)
 516                 goto free_rproc;
 517
 518         ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
 519         if (ret < 0)
 520                 goto free_rproc;
 521         wcnss->wdog_irq = ret;
 522
 523         ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
 524         if (ret < 0)
 525                 goto free_rproc;
 526         wcnss->fatal_irq = ret;
 527
 528         ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
 529         if (ret < 0)
 530                 goto free_rproc;
 531         wcnss->ready_irq = ret;
 532
 533         ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
 534         if (ret < 0)
 535                 goto free_rproc;
 536         wcnss->handover_irq = ret;
 537
 538         ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
 539         if (ret < 0)
 540                 goto free_rproc;
 541         wcnss->stop_ack_irq = ret;
 542
 543         if (wcnss->stop_ack_irq) {
 544                 wcnss->state = qcom_smem_state_get(&pdev->dev, "stop",
 545                                                    &wcnss->stop_bit);
 546                 if (IS_ERR(wcnss->state)) {
 547                         ret = PTR_ERR(wcnss->state);
 548                         goto free_rproc;
 549                 }
 550         }
 551
 552         qcom_add_smd_subdev(rproc, &wcnss->smd_subdev);
 553
 554         ret = rproc_add(rproc);
 555         if (ret)
 556                 goto free_rproc;
 557
 558         return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
 559
 560 free_rproc:
 561         rproc_free(rproc);
 562
 563         return ret;
 564 }
 565
 566 static int wcnss_remove(struct platform_device *pdev)
 567 {
 568         struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);
 569
 570         of_platform_depopulate(&pdev->dev);
 571
 572         qcom_smem_state_put(wcnss->state);
 573         rproc_del(wcnss->rproc);
 574
 575         qcom_remove_smd_subdev(wcnss->rproc, &wcnss->smd_subdev);
 576         rproc_free(wcnss->rproc);
 577
 578         return 0;
 579 }
 580
 581 static const struct of_device_id wcnss_of_match[] = {
 582         { .compatible = "qcom,riva-pil", &riva_data },
 583         { .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
 584         { .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
 585         { },
 586 };
 587 MODULE_DEVICE_TABLE(of, wcnss_of_match);
 588
 589 static struct platform_driver wcnss_driver = {
 590         .probe = wcnss_probe,
 591         .remove = wcnss_remove,
 592         .driver = {
 593                 .name = "qcom-wcnss-pil",
 594                 .of_match_table = wcnss_of_match,
 595         },
 596 };
 597
 598 static int __init wcnss_init(void)
 599 {
 600         int ret;
 601
 602         ret = platform_driver_register(&wcnss_driver);
 603         if (ret)
 604                 return ret;
 605
 606         ret = platform_driver_register(&qcom_iris_driver);
 607         if (ret)
 608                 platform_driver_unregister(&wcnss_driver);
 609
 610         return ret;
 611 }
 612 module_init(wcnss_init);
 613
 614 static void __exit wcnss_exit(void)
 615 {
 616         platform_driver_unregister(&qcom_iris_driver);
 617         platform_driver_unregister(&wcnss_driver);
 618 }
 619 module_exit(wcnss_exit);
 620
 621 MODULE_DESCRIPTION("Qualcomm Peripherial Image Loader for Wireless Subsystem");
 622 MODULE_LICENSE("GPL v2");