2 * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
4 * Copyright (C) 2016 Linaro Ltd
5 * Copyright (C) 2014 Sony Mobile Communications AB
6 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/firmware.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
25 #include <linux/of_address.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/qcom_scm.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/remoteproc.h>
31 #include <linux/soc/qcom/mdt_loader.h>
32 #include <linux/soc/qcom/smem.h>
33 #include <linux/soc/qcom/smem_state.h>
34 #include <linux/rpmsg/qcom_smd.h>
36 #include "qcom_common.h"
37 #include "remoteproc_internal.h"
38 #include "qcom_wcnss.h"
40 #define WCNSS_CRASH_REASON_SMEM 422
41 #define WCNSS_FIRMWARE_NAME "wcnss.mdt"
42 #define WCNSS_PAS_ID 6
44 #define WCNSS_SPARE_NVBIN_DLND BIT(25)
46 #define WCNSS_PMU_IRIS_XO_CFG BIT(3)
47 #define WCNSS_PMU_IRIS_XO_EN BIT(4)
48 #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5)
49 #define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */
51 #define WCNSS_PMU_IRIS_RESET BIT(7)
52 #define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */
53 #define WCNSS_PMU_IRIS_XO_READ BIT(9)
54 #define WCNSS_PMU_IRIS_XO_READ_STS BIT(10)
56 #define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1)
57 #define WCNSS_PMU_XO_MODE_19p2 0
58 #define WCNSS_PMU_XO_MODE_48 3
64 const struct wcnss_vreg_info
*vregs
;
72 void __iomem
*pmu_cfg
;
73 void __iomem
*spare_out
;
83 struct qcom_smem_state
*state
;
86 struct mutex iris_lock
;
87 struct qcom_iris
*iris
;
89 struct regulator_bulk_data
*vregs
;
92 struct completion start_done
;
93 struct completion stop_done
;
96 phys_addr_t mem_reloc
;
100 struct qcom_rproc_subdev smd_subdev
;
103 static const struct wcnss_data riva_data
= {
105 .spare_offset
= 0xb4,
107 .vregs
= (struct wcnss_vreg_info
[]) {
108 { "vddmx", 1050000, 1150000, 0 },
109 { "vddcx", 1050000, 1150000, 0 },
110 { "vddpx", 1800000, 1800000, 0 },
115 static const struct wcnss_data pronto_v1_data
= {
116 .pmu_offset
= 0x1004,
117 .spare_offset
= 0x1088,
119 .vregs
= (struct wcnss_vreg_info
[]) {
120 { "vddmx", 950000, 1150000, 0 },
121 { "vddcx", .super_turbo
= true},
122 { "vddpx", 1800000, 1800000, 0 },
127 static const struct wcnss_data pronto_v2_data
= {
128 .pmu_offset
= 0x1004,
129 .spare_offset
= 0x1088,
131 .vregs
= (struct wcnss_vreg_info
[]) {
132 { "vddmx", 1287500, 1287500, 0 },
133 { "vddcx", .super_turbo
= true },
134 { "vddpx", 1800000, 1800000, 0 },
139 void qcom_wcnss_assign_iris(struct qcom_wcnss
*wcnss
,
140 struct qcom_iris
*iris
,
143 mutex_lock(&wcnss
->iris_lock
);
146 wcnss
->use_48mhz_xo
= use_48mhz_xo
;
148 mutex_unlock(&wcnss
->iris_lock
);
151 static int wcnss_load(struct rproc
*rproc
, const struct firmware
*fw
)
153 struct qcom_wcnss
*wcnss
= (struct qcom_wcnss
*)rproc
->priv
;
155 return qcom_mdt_load(wcnss
->dev
, fw
, rproc
->firmware
, WCNSS_PAS_ID
,
156 wcnss
->mem_region
, wcnss
->mem_phys
, wcnss
->mem_size
);
159 static const struct rproc_fw_ops wcnss_fw_ops
= {
160 .find_rsc_table
= qcom_mdt_find_rsc_table
,
164 static void wcnss_indicate_nv_download(struct qcom_wcnss
*wcnss
)
168 /* Indicate NV download capability */
169 val
= readl(wcnss
->spare_out
);
170 val
|= WCNSS_SPARE_NVBIN_DLND
;
171 writel(val
, wcnss
->spare_out
);
174 static void wcnss_configure_iris(struct qcom_wcnss
*wcnss
)
178 /* Clear PMU cfg register */
179 writel(0, wcnss
->pmu_cfg
);
181 val
= WCNSS_PMU_GC_BUS_MUX_SEL_TOP
| WCNSS_PMU_IRIS_XO_EN
;
182 writel(val
, wcnss
->pmu_cfg
);
185 val
&= ~WCNSS_PMU_XO_MODE_MASK
;
186 if (wcnss
->use_48mhz_xo
)
187 val
|= WCNSS_PMU_XO_MODE_48
<< 1;
189 val
|= WCNSS_PMU_XO_MODE_19p2
<< 1;
190 writel(val
, wcnss
->pmu_cfg
);
193 val
|= WCNSS_PMU_IRIS_RESET
;
194 writel(val
, wcnss
->pmu_cfg
);
196 /* Wait for PMU.iris_reg_reset_sts */
197 while (readl(wcnss
->pmu_cfg
) & WCNSS_PMU_IRIS_RESET_STS
)
200 /* Clear IRIS reset */
201 val
&= ~WCNSS_PMU_IRIS_RESET
;
202 writel(val
, wcnss
->pmu_cfg
);
204 /* Start IRIS XO configuration */
205 val
|= WCNSS_PMU_IRIS_XO_CFG
;
206 writel(val
, wcnss
->pmu_cfg
);
208 /* Wait for XO configuration to finish */
209 while (readl(wcnss
->pmu_cfg
) & WCNSS_PMU_IRIS_XO_CFG_STS
)
212 /* Stop IRIS XO configuration */
213 val
&= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP
;
214 val
&= ~WCNSS_PMU_IRIS_XO_CFG
;
215 writel(val
, wcnss
->pmu_cfg
);
217 /* Add some delay for XO to settle */
221 static int wcnss_start(struct rproc
*rproc
)
223 struct qcom_wcnss
*wcnss
= (struct qcom_wcnss
*)rproc
->priv
;
226 mutex_lock(&wcnss
->iris_lock
);
228 dev_err(wcnss
->dev
, "no iris registered\n");
230 goto release_iris_lock
;
233 ret
= regulator_bulk_enable(wcnss
->num_vregs
, wcnss
->vregs
);
235 goto release_iris_lock
;
237 ret
= qcom_iris_enable(wcnss
->iris
);
239 goto disable_regulators
;
241 wcnss_indicate_nv_download(wcnss
);
242 wcnss_configure_iris(wcnss
);
244 ret
= qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID
);
247 "failed to authenticate image and release reset\n");
251 ret
= wait_for_completion_timeout(&wcnss
->start_done
,
252 msecs_to_jiffies(5000));
253 if (wcnss
->ready_irq
> 0 && ret
== 0) {
254 /* We have a ready_irq, but it didn't fire in time. */
255 dev_err(wcnss
->dev
, "start timed out\n");
256 qcom_scm_pas_shutdown(WCNSS_PAS_ID
);
264 qcom_iris_disable(wcnss
->iris
);
266 regulator_bulk_disable(wcnss
->num_vregs
, wcnss
->vregs
);
268 mutex_unlock(&wcnss
->iris_lock
);
273 static int wcnss_stop(struct rproc
*rproc
)
275 struct qcom_wcnss
*wcnss
= (struct qcom_wcnss
*)rproc
->priv
;
279 qcom_smem_state_update_bits(wcnss
->state
,
280 BIT(wcnss
->stop_bit
),
281 BIT(wcnss
->stop_bit
));
283 ret
= wait_for_completion_timeout(&wcnss
->stop_done
,
284 msecs_to_jiffies(5000));
286 dev_err(wcnss
->dev
, "timed out on wait\n");
288 qcom_smem_state_update_bits(wcnss
->state
,
289 BIT(wcnss
->stop_bit
),
293 ret
= qcom_scm_pas_shutdown(WCNSS_PAS_ID
);
295 dev_err(wcnss
->dev
, "failed to shutdown: %d\n", ret
);
300 static void *wcnss_da_to_va(struct rproc
*rproc
, u64 da
, int len
)
302 struct qcom_wcnss
*wcnss
= (struct qcom_wcnss
*)rproc
->priv
;
305 offset
= da
- wcnss
->mem_reloc
;
306 if (offset
< 0 || offset
+ len
> wcnss
->mem_size
)
309 return wcnss
->mem_region
+ offset
;
312 static const struct rproc_ops wcnss_ops
= {
313 .start
= wcnss_start
,
315 .da_to_va
= wcnss_da_to_va
,
318 static irqreturn_t
wcnss_wdog_interrupt(int irq
, void *dev
)
320 struct qcom_wcnss
*wcnss
= dev
;
322 rproc_report_crash(wcnss
->rproc
, RPROC_WATCHDOG
);
327 static irqreturn_t
wcnss_fatal_interrupt(int irq
, void *dev
)
329 struct qcom_wcnss
*wcnss
= dev
;
333 msg
= qcom_smem_get(QCOM_SMEM_HOST_ANY
, WCNSS_CRASH_REASON_SMEM
, &len
);
334 if (!IS_ERR(msg
) && len
> 0 && msg
[0])
335 dev_err(wcnss
->dev
, "fatal error received: %s\n", msg
);
337 rproc_report_crash(wcnss
->rproc
, RPROC_FATAL_ERROR
);
345 static irqreturn_t
wcnss_ready_interrupt(int irq
, void *dev
)
347 struct qcom_wcnss
*wcnss
= dev
;
349 complete(&wcnss
->start_done
);
354 static irqreturn_t
wcnss_handover_interrupt(int irq
, void *dev
)
357 * XXX: At this point we're supposed to release the resources that we
358 * have been holding on behalf of the WCNSS. Unfortunately this
359 * interrupt comes way before the other side seems to be done.
361 * So we're currently relying on the ready interrupt firing later then
362 * this and we just disable the resources at the end of wcnss_start().
368 static irqreturn_t
wcnss_stop_ack_interrupt(int irq
, void *dev
)
370 struct qcom_wcnss
*wcnss
= dev
;
372 complete(&wcnss
->stop_done
);
377 static int wcnss_init_regulators(struct qcom_wcnss
*wcnss
,
378 const struct wcnss_vreg_info
*info
,
381 struct regulator_bulk_data
*bulk
;
385 bulk
= devm_kcalloc(wcnss
->dev
,
386 num_vregs
, sizeof(struct regulator_bulk_data
),
391 for (i
= 0; i
< num_vregs
; i
++)
392 bulk
[i
].supply
= info
[i
].name
;
394 ret
= devm_regulator_bulk_get(wcnss
->dev
, num_vregs
, bulk
);
398 for (i
= 0; i
< num_vregs
; i
++) {
399 if (info
[i
].max_voltage
)
400 regulator_set_voltage(bulk
[i
].consumer
,
402 info
[i
].max_voltage
);
405 regulator_set_load(bulk
[i
].consumer
, info
[i
].load_uA
);
409 wcnss
->num_vregs
= num_vregs
;
414 static int wcnss_request_irq(struct qcom_wcnss
*wcnss
,
415 struct platform_device
*pdev
,
418 irq_handler_t thread_fn
)
422 ret
= platform_get_irq_byname(pdev
, name
);
423 if (ret
< 0 && optional
) {
424 dev_dbg(&pdev
->dev
, "no %s IRQ defined, ignoring\n", name
);
426 } else if (ret
< 0) {
427 dev_err(&pdev
->dev
, "no %s IRQ defined\n", name
);
431 ret
= devm_request_threaded_irq(&pdev
->dev
, ret
,
433 IRQF_TRIGGER_RISING
| IRQF_ONESHOT
,
436 dev_err(&pdev
->dev
, "request %s IRQ failed\n", name
);
441 static int wcnss_alloc_memory_region(struct qcom_wcnss
*wcnss
)
443 struct device_node
*node
;
447 node
= of_parse_phandle(wcnss
->dev
->of_node
, "memory-region", 0);
449 dev_err(wcnss
->dev
, "no memory-region specified\n");
453 ret
= of_address_to_resource(node
, 0, &r
);
457 wcnss
->mem_phys
= wcnss
->mem_reloc
= r
.start
;
458 wcnss
->mem_size
= resource_size(&r
);
459 wcnss
->mem_region
= devm_ioremap_wc(wcnss
->dev
, wcnss
->mem_phys
, wcnss
->mem_size
);
460 if (!wcnss
->mem_region
) {
461 dev_err(wcnss
->dev
, "unable to map memory region: %pa+%zx\n",
462 &r
.start
, wcnss
->mem_size
);
469 static int wcnss_probe(struct platform_device
*pdev
)
471 const struct wcnss_data
*data
;
472 struct qcom_wcnss
*wcnss
;
473 struct resource
*res
;
478 data
= of_device_get_match_data(&pdev
->dev
);
480 if (!qcom_scm_is_available())
481 return -EPROBE_DEFER
;
483 if (!qcom_scm_pas_supported(WCNSS_PAS_ID
)) {
484 dev_err(&pdev
->dev
, "PAS is not available for WCNSS\n");
488 rproc
= rproc_alloc(&pdev
->dev
, pdev
->name
, &wcnss_ops
,
489 WCNSS_FIRMWARE_NAME
, sizeof(*wcnss
));
491 dev_err(&pdev
->dev
, "unable to allocate remoteproc\n");
495 rproc
->fw_ops
= &wcnss_fw_ops
;
497 wcnss
= (struct qcom_wcnss
*)rproc
->priv
;
498 wcnss
->dev
= &pdev
->dev
;
499 wcnss
->rproc
= rproc
;
500 platform_set_drvdata(pdev
, wcnss
);
502 init_completion(&wcnss
->start_done
);
503 init_completion(&wcnss
->stop_done
);
505 mutex_init(&wcnss
->iris_lock
);
507 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "pmu");
508 mmio
= devm_ioremap_resource(&pdev
->dev
, res
);
514 ret
= wcnss_alloc_memory_region(wcnss
);
518 wcnss
->pmu_cfg
= mmio
+ data
->pmu_offset
;
519 wcnss
->spare_out
= mmio
+ data
->spare_offset
;
521 ret
= wcnss_init_regulators(wcnss
, data
->vregs
, data
->num_vregs
);
525 ret
= wcnss_request_irq(wcnss
, pdev
, "wdog", false, wcnss_wdog_interrupt
);
528 wcnss
->wdog_irq
= ret
;
530 ret
= wcnss_request_irq(wcnss
, pdev
, "fatal", false, wcnss_fatal_interrupt
);
533 wcnss
->fatal_irq
= ret
;
535 ret
= wcnss_request_irq(wcnss
, pdev
, "ready", true, wcnss_ready_interrupt
);
538 wcnss
->ready_irq
= ret
;
540 ret
= wcnss_request_irq(wcnss
, pdev
, "handover", true, wcnss_handover_interrupt
);
543 wcnss
->handover_irq
= ret
;
545 ret
= wcnss_request_irq(wcnss
, pdev
, "stop-ack", true, wcnss_stop_ack_interrupt
);
548 wcnss
->stop_ack_irq
= ret
;
550 if (wcnss
->stop_ack_irq
) {
551 wcnss
->state
= qcom_smem_state_get(&pdev
->dev
, "stop",
553 if (IS_ERR(wcnss
->state
)) {
554 ret
= PTR_ERR(wcnss
->state
);
559 qcom_add_smd_subdev(rproc
, &wcnss
->smd_subdev
);
561 ret
= rproc_add(rproc
);
565 return of_platform_populate(pdev
->dev
.of_node
, NULL
, NULL
, &pdev
->dev
);
573 static int wcnss_remove(struct platform_device
*pdev
)
575 struct qcom_wcnss
*wcnss
= platform_get_drvdata(pdev
);
577 of_platform_depopulate(&pdev
->dev
);
579 qcom_smem_state_put(wcnss
->state
);
580 rproc_del(wcnss
->rproc
);
582 qcom_remove_smd_subdev(wcnss
->rproc
, &wcnss
->smd_subdev
);
583 rproc_free(wcnss
->rproc
);
588 static const struct of_device_id wcnss_of_match
[] = {
589 { .compatible
= "qcom,riva-pil", &riva_data
},
590 { .compatible
= "qcom,pronto-v1-pil", &pronto_v1_data
},
591 { .compatible
= "qcom,pronto-v2-pil", &pronto_v2_data
},
594 MODULE_DEVICE_TABLE(of
, wcnss_of_match
);
596 static struct platform_driver wcnss_driver
= {
597 .probe
= wcnss_probe
,
598 .remove
= wcnss_remove
,
600 .name
= "qcom-wcnss-pil",
601 .of_match_table
= wcnss_of_match
,
605 static int __init
wcnss_init(void)
609 ret
= platform_driver_register(&wcnss_driver
);
613 ret
= platform_driver_register(&qcom_iris_driver
);
615 platform_driver_unregister(&wcnss_driver
);
619 module_init(wcnss_init
);
621 static void __exit
wcnss_exit(void)
623 platform_driver_unregister(&qcom_iris_driver
);
624 platform_driver_unregister(&wcnss_driver
);
626 module_exit(wcnss_exit
);
628 MODULE_DESCRIPTION("Qualcomm Peripherial Image Loader for Wireless Subsystem");
629 MODULE_LICENSE("GPL v2");