drivers/reset/reset-socfpga.c

   1 /*
   2  * Socfpga Reset Controller Driver
   3  *
   4  * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
   5  *
   6  * based on
   7  * Allwinner SoCs Reset Controller driver
   8  *
   9  * Copyright 2013 Maxime Ripard
  10  *
  11  * Maxime Ripard <maxime.ripard@free-electrons.com>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  */
  18
  19 #include <linux/err.h>
  20 #include <linux/io.h>
  21 #include <linux/init.h>
  22 #include <linux/of.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/reset-controller.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/types.h>
  27
  28 #define NR_BANKS                4
  29
  30 struct socfpga_reset_data {
  31         spinlock_t                      lock;
  32         void __iomem                    *membase;
  33         struct reset_controller_dev     rcdev;
  34 };
  35
  36 static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
  37                                 unsigned long id)
  38 {
  39         struct socfpga_reset_data *data = container_of(rcdev,
  40                                                      struct socfpga_reset_data,
  41                                                      rcdev);
  42         int bank = id / BITS_PER_LONG;
  43         int offset = id % BITS_PER_LONG;
  44         unsigned long flags;
  45         u32 reg;
  46
  47         spin_lock_irqsave(&data->lock, flags);
  48
  49         reg = readl(data->membase + (bank * NR_BANKS));
  50         writel(reg | BIT(offset), data->membase + (bank * NR_BANKS));
  51         spin_unlock_irqrestore(&data->lock, flags);
  52
  53         return 0;
  54 }
  55
  56 static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
  57                                   unsigned long id)
  58 {
  59         struct socfpga_reset_data *data = container_of(rcdev,
  60                                                      struct socfpga_reset_data,
  61                                                      rcdev);
  62
  63         int bank = id / BITS_PER_LONG;
  64         int offset = id % BITS_PER_LONG;
  65         unsigned long flags;
  66         u32 reg;
  67
  68         spin_lock_irqsave(&data->lock, flags);
  69
  70         reg = readl(data->membase + (bank * NR_BANKS));
  71         writel(reg & ~BIT(offset), data->membase + (bank * NR_BANKS));
  72
  73         spin_unlock_irqrestore(&data->lock, flags);
  74
  75         return 0;
  76 }
  77
  78 static int socfpga_reset_status(struct reset_controller_dev *rcdev,
  79                                 unsigned long id)
  80 {
  81         struct socfpga_reset_data *data = container_of(rcdev,
  82                                                 struct socfpga_reset_data, rcdev);
  83         int bank = id / BITS_PER_LONG;
  84         int offset = id % BITS_PER_LONG;
  85         u32 reg;
  86
  87         reg = readl(data->membase + (bank * NR_BANKS));
  88
  89         return !(reg & BIT(offset));
  90 }
  91
  92 static const struct reset_control_ops socfpga_reset_ops = {
  93         .assert         = socfpga_reset_assert,
  94         .deassert       = socfpga_reset_deassert,
  95         .status         = socfpga_reset_status,
  96 };
  97
  98 static int socfpga_reset_probe(struct platform_device *pdev)
  99 {
 100         struct socfpga_reset_data *data;
 101         struct resource *res;
 102         struct device *dev = &pdev->dev;
 103         struct device_node *np = dev->of_node;
 104         u32 modrst_offset;
 105
 106         /*
 107          * The binding was mainlined without the required property.
 108          * Do not continue, when we encounter an old DT.
 109          */
 110         if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
 111                 dev_err(&pdev->dev, "%s missing #reset-cells property\n",
 112                         pdev->dev.of_node->full_name);
 113                 return -EINVAL;
 114         }
 115
 116         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 117         if (!data)
 118                 return -ENOMEM;
 119
 120         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 121         data->membase = devm_ioremap_resource(&pdev->dev, res);
 122         if (IS_ERR(data->membase))
 123                 return PTR_ERR(data->membase);
 124
 125         if (of_property_read_u32(np, "altr,modrst-offset", &modrst_offset)) {
 126                 dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
 127                 modrst_offset = 0x10;
 128         }
 129         data->membase += modrst_offset;
 130
 131         spin_lock_init(&data->lock);
 132
 133         data->rcdev.owner = THIS_MODULE;
 134         data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
 135         data->rcdev.ops = &socfpga_reset_ops;
 136         data->rcdev.of_node = pdev->dev.of_node;
 137
 138         return devm_reset_controller_register(dev, &data->rcdev);
 139 }
 140
 141 static const struct of_device_id socfpga_reset_dt_ids[] = {
 142         { .compatible = "altr,rst-mgr", },
 143         { /* sentinel */ },
 144 };
 145
 146 static struct platform_driver socfpga_reset_driver = {
 147         .probe  = socfpga_reset_probe,
 148         .driver = {
 149                 .name           = "socfpga-reset",
 150                 .of_match_table = socfpga_reset_dt_ids,
 151         },
 152 };
 153 builtin_platform_driver(socfpga_reset_driver);