1 // SPDX-License-Identifier: GPL-2.0-only
3 * rtc-ds1305.c -- driver for DS1305 and DS1306 SPI RTC chips
5 * Copyright (C) 2008 David Brownell
7 #include <linux/kernel.h>
8 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/rtc.h>
12 #include <linux/workqueue.h>
14 #include <linux/spi/spi.h>
15 #include <linux/spi/ds1305.h>
16 #include <linux/module.h>
20 * Registers ... mask DS1305_WRITE into register address to write,
21 * otherwise you're reading it. All non-bitmask values are BCD.
23 #define DS1305_WRITE 0x80
26 /* RTC date/time ... the main special cases are that we:
27 * - Need fancy "hours" encoding in 12hour mode
28 * - Don't rely on the "day-of-week" field (or tm_wday)
29 * - Are a 21st-century clock (2000 <= year < 2100)
31 #define DS1305_RTC_LEN 7 /* bytes for RTC regs */
33 #define DS1305_SEC 0x00 /* register addresses */
34 #define DS1305_MIN 0x01
35 #define DS1305_HOUR 0x02
36 # define DS1305_HR_12 0x40 /* set == 12 hr mode */
37 # define DS1305_HR_PM 0x20 /* set == PM (12hr mode) */
38 #define DS1305_WDAY 0x03
39 #define DS1305_MDAY 0x04
40 #define DS1305_MON 0x05
41 #define DS1305_YEAR 0x06
44 /* The two alarms have only sec/min/hour/wday fields (ALM_LEN).
45 * DS1305_ALM_DISABLE disables a match field (some combos are bad).
47 * NOTE that since we don't use WDAY, we limit ourselves to alarms
48 * only one day into the future (vs potentially up to a week).
50 * NOTE ALSO that while we could generate once-a-second IRQs (UIE), we
51 * don't currently support them. We'd either need to do it only when
52 * no alarm is pending (not the standard model), or to use the second
53 * alarm (implying that this is a DS1305 not DS1306, *and* that either
54 * it's wired up a second IRQ we know, or that INTCN is set)
56 #define DS1305_ALM_LEN 4 /* bytes for ALM regs */
57 #define DS1305_ALM_DISABLE 0x80
59 #define DS1305_ALM0(r) (0x07 + (r)) /* register addresses */
60 #define DS1305_ALM1(r) (0x0b + (r))
63 /* three control registers */
64 #define DS1305_CONTROL_LEN 3 /* bytes of control regs */
66 #define DS1305_CONTROL 0x0f /* register addresses */
67 # define DS1305_nEOSC 0x80 /* low enables oscillator */
68 # define DS1305_WP 0x40 /* write protect */
69 # define DS1305_INTCN 0x04 /* clear == only int0 used */
70 # define DS1306_1HZ 0x04 /* enable 1Hz output */
71 # define DS1305_AEI1 0x02 /* enable ALM1 IRQ */
72 # define DS1305_AEI0 0x01 /* enable ALM0 IRQ */
73 #define DS1305_STATUS 0x10
74 /* status has just AEIx bits, mirrored as IRQFx */
75 #define DS1305_TRICKLE 0x11
76 /* trickle bits are defined in <linux/spi/ds1305.h> */
78 /* a bunch of NVRAM */
79 #define DS1305_NVRAM_LEN 96 /* bytes of NVRAM */
81 #define DS1305_NVRAM 0x20 /* register addresses */
85 struct spi_device
*spi
;
86 struct rtc_device
*rtc
;
88 struct work_struct work
;
91 #define FLAG_EXITING 0
94 u8 ctrl
[DS1305_CONTROL_LEN
];
98 /*----------------------------------------------------------------------*/
101 * Utilities ... tolerate 12-hour AM/PM notation in case of non-Linux
102 * software (like a bootloader) which may require it.
105 static unsigned bcd2hour(u8 bcd
)
107 if (bcd
& DS1305_HR_12
) {
110 bcd
&= ~DS1305_HR_12
;
111 if (bcd
& DS1305_HR_PM
) {
113 bcd
&= ~DS1305_HR_PM
;
115 hour
+= bcd2bin(bcd
);
121 static u8
hour2bcd(bool hr12
, int hour
)
126 return DS1305_HR_12
| bin2bcd(hour
);
128 return DS1305_HR_12
| DS1305_HR_PM
| bin2bcd(hour
);
130 return bin2bcd(hour
);
133 /*----------------------------------------------------------------------*/
136 * Interface to RTC framework
139 static int ds1305_alarm_irq_enable(struct device
*dev
, unsigned int enabled
)
141 struct ds1305
*ds1305
= dev_get_drvdata(dev
);
145 buf
[0] = DS1305_WRITE
| DS1305_CONTROL
;
146 buf
[1] = ds1305
->ctrl
[0];
149 if (ds1305
->ctrl
[0] & DS1305_AEI0
)
151 buf
[1] |= DS1305_AEI0
;
153 if (!(buf
[1] & DS1305_AEI0
))
155 buf
[1] &= ~DS1305_AEI0
;
157 err
= spi_write_then_read(ds1305
->spi
, buf
, sizeof(buf
), NULL
, 0);
159 ds1305
->ctrl
[0] = buf
[1];
167 * Get/set of date and time is pretty normal.
170 static int ds1305_get_time(struct device
*dev
, struct rtc_time
*time
)
172 struct ds1305
*ds1305
= dev_get_drvdata(dev
);
173 u8 addr
= DS1305_SEC
;
174 u8 buf
[DS1305_RTC_LEN
];
177 /* Use write-then-read to get all the date/time registers
178 * since dma from stack is nonportable
180 status
= spi_write_then_read(ds1305
->spi
, &addr
, sizeof(addr
),
185 dev_vdbg(dev
, "%s: %3ph, %4ph\n", "read", &buf
[0], &buf
[3]);
187 /* Decode the registers */
188 time
->tm_sec
= bcd2bin(buf
[DS1305_SEC
]);
189 time
->tm_min
= bcd2bin(buf
[DS1305_MIN
]);
190 time
->tm_hour
= bcd2hour(buf
[DS1305_HOUR
]);
191 time
->tm_wday
= buf
[DS1305_WDAY
] - 1;
192 time
->tm_mday
= bcd2bin(buf
[DS1305_MDAY
]);
193 time
->tm_mon
= bcd2bin(buf
[DS1305_MON
]) - 1;
194 time
->tm_year
= bcd2bin(buf
[DS1305_YEAR
]) + 100;
196 dev_vdbg(dev
, "%s secs=%d, mins=%d, "
197 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
198 "read", time
->tm_sec
, time
->tm_min
,
199 time
->tm_hour
, time
->tm_mday
,
200 time
->tm_mon
, time
->tm_year
, time
->tm_wday
);
205 static int ds1305_set_time(struct device
*dev
, struct rtc_time
*time
)
207 struct ds1305
*ds1305
= dev_get_drvdata(dev
);
208 u8 buf
[1 + DS1305_RTC_LEN
];
211 dev_vdbg(dev
, "%s secs=%d, mins=%d, "
212 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
213 "write", time
->tm_sec
, time
->tm_min
,
214 time
->tm_hour
, time
->tm_mday
,
215 time
->tm_mon
, time
->tm_year
, time
->tm_wday
);
217 /* Write registers starting at the first time/date address. */
218 *bp
++ = DS1305_WRITE
| DS1305_SEC
;
220 *bp
++ = bin2bcd(time
->tm_sec
);
221 *bp
++ = bin2bcd(time
->tm_min
);
222 *bp
++ = hour2bcd(ds1305
->hr12
, time
->tm_hour
);
223 *bp
++ = (time
->tm_wday
< 7) ? (time
->tm_wday
+ 1) : 1;
224 *bp
++ = bin2bcd(time
->tm_mday
);
225 *bp
++ = bin2bcd(time
->tm_mon
+ 1);
226 *bp
++ = bin2bcd(time
->tm_year
- 100);
228 dev_dbg(dev
, "%s: %3ph, %4ph\n", "write", &buf
[1], &buf
[4]);
230 /* use write-then-read since dma from stack is nonportable */
231 return spi_write_then_read(ds1305
->spi
, buf
, sizeof(buf
),
236 * Get/set of alarm is a bit funky:
238 * - First there's the inherent raciness of getting the (partitioned)
239 * status of an alarm that could trigger while we're reading parts
242 * - Second there's its limited range (we could increase it a bit by
243 * relying on WDAY), which means it will easily roll over.
245 * - Third there's the choice of two alarms and alarm signals.
246 * Here we use ALM0 and expect that nINT0 (open drain) is used;
247 * that's the only real option for DS1306 runtime alarms, and is
250 * - Fourth, there's also ALM1, and a second interrupt signal:
251 * + On DS1305 ALM1 uses nINT1 (when INTCN=1) else nINT0;
252 * + On DS1306 ALM1 only uses INT1 (an active high pulse)
253 * and it won't work when VCC1 is active.
255 * So to be most general, we should probably set both alarms to the
256 * same value, letting ALM1 be the wakeup event source on DS1306
257 * and handling several wiring options on DS1305.
259 * - Fifth, we support the polled mode (as well as possible; why not?)
260 * even when no interrupt line is wired to an IRQ.
264 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
266 static int ds1305_get_alarm(struct device
*dev
, struct rtc_wkalrm
*alm
)
268 struct ds1305
*ds1305
= dev_get_drvdata(dev
);
269 struct spi_device
*spi
= ds1305
->spi
;
272 u8 buf
[DS1305_ALM_LEN
];
274 /* Refresh control register cache BEFORE reading ALM0 registers,
275 * since reading alarm registers acks any pending IRQ. That
276 * makes returning "pending" status a bit of a lie, but that bit
277 * of EFI status is at best fragile anyway (given IRQ handlers).
279 addr
= DS1305_CONTROL
;
280 status
= spi_write_then_read(spi
, &addr
, sizeof(addr
),
281 ds1305
->ctrl
, sizeof(ds1305
->ctrl
));
285 alm
->enabled
= !!(ds1305
->ctrl
[0] & DS1305_AEI0
);
286 alm
->pending
= !!(ds1305
->ctrl
[1] & DS1305_AEI0
);
288 /* get and check ALM0 registers */
289 addr
= DS1305_ALM0(DS1305_SEC
);
290 status
= spi_write_then_read(spi
, &addr
, sizeof(addr
),
295 dev_vdbg(dev
, "%s: %02x %02x %02x %02x\n",
296 "alm0 read", buf
[DS1305_SEC
], buf
[DS1305_MIN
],
297 buf
[DS1305_HOUR
], buf
[DS1305_WDAY
]);
299 if ((DS1305_ALM_DISABLE
& buf
[DS1305_SEC
])
300 || (DS1305_ALM_DISABLE
& buf
[DS1305_MIN
])
301 || (DS1305_ALM_DISABLE
& buf
[DS1305_HOUR
]))
304 /* Stuff these values into alm->time and let RTC framework code
305 * fill in the rest ... and also handle rollover to tomorrow when
308 alm
->time
.tm_sec
= bcd2bin(buf
[DS1305_SEC
]);
309 alm
->time
.tm_min
= bcd2bin(buf
[DS1305_MIN
]);
310 alm
->time
.tm_hour
= bcd2hour(buf
[DS1305_HOUR
]);
316 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
318 static int ds1305_set_alarm(struct device
*dev
, struct rtc_wkalrm
*alm
)
320 struct ds1305
*ds1305
= dev_get_drvdata(dev
);
321 struct spi_device
*spi
= ds1305
->spi
;
322 unsigned long now
, later
;
325 u8 buf
[1 + DS1305_ALM_LEN
];
327 /* convert desired alarm to time_t */
328 later
= rtc_tm_to_time64(&alm
->time
);
330 /* Read current time as time_t */
331 status
= ds1305_get_time(dev
, &tm
);
334 now
= rtc_tm_to_time64(&tm
);
336 /* make sure alarm fires within the next 24 hours */
339 if ((later
- now
) > 24 * 60 * 60)
342 /* disable alarm if needed */
343 if (ds1305
->ctrl
[0] & DS1305_AEI0
) {
344 ds1305
->ctrl
[0] &= ~DS1305_AEI0
;
346 buf
[0] = DS1305_WRITE
| DS1305_CONTROL
;
347 buf
[1] = ds1305
->ctrl
[0];
348 status
= spi_write_then_read(ds1305
->spi
, buf
, 2, NULL
, 0);
354 buf
[0] = DS1305_WRITE
| DS1305_ALM0(DS1305_SEC
);
355 buf
[1 + DS1305_SEC
] = bin2bcd(alm
->time
.tm_sec
);
356 buf
[1 + DS1305_MIN
] = bin2bcd(alm
->time
.tm_min
);
357 buf
[1 + DS1305_HOUR
] = hour2bcd(ds1305
->hr12
, alm
->time
.tm_hour
);
358 buf
[1 + DS1305_WDAY
] = DS1305_ALM_DISABLE
;
360 dev_dbg(dev
, "%s: %02x %02x %02x %02x\n",
361 "alm0 write", buf
[1 + DS1305_SEC
], buf
[1 + DS1305_MIN
],
362 buf
[1 + DS1305_HOUR
], buf
[1 + DS1305_WDAY
]);
364 status
= spi_write_then_read(spi
, buf
, sizeof(buf
), NULL
, 0);
368 /* enable alarm if requested */
370 ds1305
->ctrl
[0] |= DS1305_AEI0
;
372 buf
[0] = DS1305_WRITE
| DS1305_CONTROL
;
373 buf
[1] = ds1305
->ctrl
[0];
374 status
= spi_write_then_read(ds1305
->spi
, buf
, 2, NULL
, 0);
380 #ifdef CONFIG_PROC_FS
382 static int ds1305_proc(struct device
*dev
, struct seq_file
*seq
)
384 struct ds1305
*ds1305
= dev_get_drvdata(dev
);
386 char *resistors
= "";
388 /* ctrl[2] is treated as read-only; no locking needed */
389 if ((ds1305
->ctrl
[2] & 0xf0) == DS1305_TRICKLE_MAGIC
) {
390 switch (ds1305
->ctrl
[2] & 0x0c) {
391 case DS1305_TRICKLE_DS2
:
392 diodes
= "2 diodes, ";
394 case DS1305_TRICKLE_DS1
:
395 diodes
= "1 diode, ";
400 switch (ds1305
->ctrl
[2] & 0x03) {
401 case DS1305_TRICKLE_2K
:
402 resistors
= "2k Ohm";
404 case DS1305_TRICKLE_4K
:
405 resistors
= "4k Ohm";
407 case DS1305_TRICKLE_8K
:
408 resistors
= "8k Ohm";
417 seq_printf(seq
, "trickle_charge\t: %s%s\n", diodes
, resistors
);
423 #define ds1305_proc NULL
426 static const struct rtc_class_ops ds1305_ops
= {
427 .read_time
= ds1305_get_time
,
428 .set_time
= ds1305_set_time
,
429 .read_alarm
= ds1305_get_alarm
,
430 .set_alarm
= ds1305_set_alarm
,
432 .alarm_irq_enable
= ds1305_alarm_irq_enable
,
435 static void ds1305_work(struct work_struct
*work
)
437 struct ds1305
*ds1305
= container_of(work
, struct ds1305
, work
);
438 struct spi_device
*spi
= ds1305
->spi
;
442 /* lock to protect ds1305->ctrl */
443 rtc_lock(ds1305
->rtc
);
445 /* Disable the IRQ, and clear its status ... for now, we "know"
446 * that if more than one alarm is active, they're in sync.
447 * Note that reading ALM data registers also clears IRQ status.
449 ds1305
->ctrl
[0] &= ~(DS1305_AEI1
| DS1305_AEI0
);
452 buf
[0] = DS1305_WRITE
| DS1305_CONTROL
;
453 buf
[1] = ds1305
->ctrl
[0];
456 status
= spi_write_then_read(spi
, buf
, sizeof(buf
),
459 dev_dbg(&spi
->dev
, "clear irq --> %d\n", status
);
461 rtc_unlock(ds1305
->rtc
);
463 if (!test_bit(FLAG_EXITING
, &ds1305
->flags
))
464 enable_irq(spi
->irq
);
466 rtc_update_irq(ds1305
->rtc
, 1, RTC_AF
| RTC_IRQF
);
470 * This "real" IRQ handler hands off to a workqueue mostly to allow
471 * mutex locking for ds1305->ctrl ... unlike I2C, we could issue async
472 * I/O requests in IRQ context (to clear the IRQ status).
474 static irqreturn_t
ds1305_irq(int irq
, void *p
)
476 struct ds1305
*ds1305
= p
;
479 schedule_work(&ds1305
->work
);
483 /*----------------------------------------------------------------------*/
486 * Interface for NVRAM
489 static void msg_init(struct spi_message
*m
, struct spi_transfer
*x
,
490 u8
*addr
, size_t count
, char *tx
, char *rx
)
493 memset(x
, 0, 2 * sizeof(*x
));
497 spi_message_add_tail(x
, m
);
504 spi_message_add_tail(x
, m
);
507 static int ds1305_nvram_read(void *priv
, unsigned int off
, void *buf
,
510 struct ds1305
*ds1305
= priv
;
511 struct spi_device
*spi
= ds1305
->spi
;
513 struct spi_message m
;
514 struct spi_transfer x
[2];
516 addr
= DS1305_NVRAM
+ off
;
517 msg_init(&m
, x
, &addr
, count
, NULL
, buf
);
519 return spi_sync(spi
, &m
);
522 static int ds1305_nvram_write(void *priv
, unsigned int off
, void *buf
,
525 struct ds1305
*ds1305
= priv
;
526 struct spi_device
*spi
= ds1305
->spi
;
528 struct spi_message m
;
529 struct spi_transfer x
[2];
531 addr
= (DS1305_WRITE
| DS1305_NVRAM
) + off
;
532 msg_init(&m
, x
, &addr
, count
, buf
, NULL
);
534 return spi_sync(spi
, &m
);
537 /*----------------------------------------------------------------------*/
540 * Interface to SPI stack
543 static int ds1305_probe(struct spi_device
*spi
)
545 struct ds1305
*ds1305
;
548 struct ds1305_platform_data
*pdata
= dev_get_platdata(&spi
->dev
);
549 bool write_ctrl
= false;
550 struct nvmem_config ds1305_nvmem_cfg
= {
551 .name
= "ds1305_nvram",
554 .size
= DS1305_NVRAM_LEN
,
555 .reg_read
= ds1305_nvram_read
,
556 .reg_write
= ds1305_nvram_write
,
559 /* Sanity check board setup data. This may be hooked up
560 * in 3wire mode, but we don't care. Note that unless
561 * there's an inverter in place, this needs SPI_CS_HIGH!
563 if ((spi
->bits_per_word
&& spi
->bits_per_word
!= 8)
564 || (spi
->max_speed_hz
> 2000000)
565 || !(spi
->mode
& SPI_CPHA
))
568 /* set up driver data */
569 ds1305
= devm_kzalloc(&spi
->dev
, sizeof(*ds1305
), GFP_KERNEL
);
573 spi_set_drvdata(spi
, ds1305
);
575 /* read and cache control registers */
576 addr
= DS1305_CONTROL
;
577 status
= spi_write_then_read(spi
, &addr
, sizeof(addr
),
578 ds1305
->ctrl
, sizeof(ds1305
->ctrl
));
580 dev_dbg(&spi
->dev
, "can't %s, %d\n",
585 dev_dbg(&spi
->dev
, "ctrl %s: %3ph\n", "read", ds1305
->ctrl
);
587 /* Sanity check register values ... partially compensating for the
588 * fact that SPI has no device handshake. A pullup on MISO would
589 * make these tests fail; but not all systems will have one. If
590 * some register is neither 0x00 nor 0xff, a chip is likely there.
592 if ((ds1305
->ctrl
[0] & 0x38) != 0 || (ds1305
->ctrl
[1] & 0xfc) != 0) {
593 dev_dbg(&spi
->dev
, "RTC chip is not present\n");
596 if (ds1305
->ctrl
[2] == 0)
597 dev_dbg(&spi
->dev
, "chip may not be present\n");
599 /* enable writes if needed ... if we were paranoid it would
600 * make sense to enable them only when absolutely necessary.
602 if (ds1305
->ctrl
[0] & DS1305_WP
) {
605 ds1305
->ctrl
[0] &= ~DS1305_WP
;
607 buf
[0] = DS1305_WRITE
| DS1305_CONTROL
;
608 buf
[1] = ds1305
->ctrl
[0];
609 status
= spi_write_then_read(spi
, buf
, sizeof(buf
), NULL
, 0);
611 dev_dbg(&spi
->dev
, "clear WP --> %d\n", status
);
616 /* on DS1305, maybe start oscillator; like most low power
617 * oscillators, it may take a second to stabilize
619 if (ds1305
->ctrl
[0] & DS1305_nEOSC
) {
620 ds1305
->ctrl
[0] &= ~DS1305_nEOSC
;
622 dev_warn(&spi
->dev
, "SET TIME!\n");
625 /* ack any pending IRQs */
626 if (ds1305
->ctrl
[1]) {
631 /* this may need one-time (re)init */
633 /* maybe enable trickle charge */
634 if (((ds1305
->ctrl
[2] & 0xf0) != DS1305_TRICKLE_MAGIC
)) {
635 ds1305
->ctrl
[2] = DS1305_TRICKLE_MAGIC
640 /* on DS1306, configure 1 Hz signal */
641 if (pdata
->is_ds1306
) {
643 if (!(ds1305
->ctrl
[0] & DS1306_1HZ
)) {
644 ds1305
->ctrl
[0] |= DS1306_1HZ
;
648 if (ds1305
->ctrl
[0] & DS1306_1HZ
) {
649 ds1305
->ctrl
[0] &= ~DS1306_1HZ
;
659 buf
[0] = DS1305_WRITE
| DS1305_CONTROL
;
660 buf
[1] = ds1305
->ctrl
[0];
661 buf
[2] = ds1305
->ctrl
[1];
662 buf
[3] = ds1305
->ctrl
[2];
663 status
= spi_write_then_read(spi
, buf
, sizeof(buf
), NULL
, 0);
665 dev_dbg(&spi
->dev
, "can't %s, %d\n",
670 dev_dbg(&spi
->dev
, "ctrl %s: %3ph\n", "write", ds1305
->ctrl
);
673 /* see if non-Linux software set up AM/PM mode */
675 status
= spi_write_then_read(spi
, &addr
, sizeof(addr
),
676 &value
, sizeof(value
));
678 dev_dbg(&spi
->dev
, "read HOUR --> %d\n", status
);
682 ds1305
->hr12
= (DS1305_HR_12
& value
) != 0;
684 dev_dbg(&spi
->dev
, "AM/PM\n");
686 /* register RTC ... from here on, ds1305->ctrl needs locking */
687 ds1305
->rtc
= devm_rtc_allocate_device(&spi
->dev
);
688 if (IS_ERR(ds1305
->rtc
))
689 return PTR_ERR(ds1305
->rtc
);
691 ds1305
->rtc
->ops
= &ds1305_ops
;
692 ds1305
->rtc
->range_min
= RTC_TIMESTAMP_BEGIN_2000
;
693 ds1305
->rtc
->range_max
= RTC_TIMESTAMP_END_2099
;
695 ds1305_nvmem_cfg
.priv
= ds1305
;
696 status
= devm_rtc_register_device(ds1305
->rtc
);
700 devm_rtc_nvmem_register(ds1305
->rtc
, &ds1305_nvmem_cfg
);
702 /* Maybe set up alarm IRQ; be ready to handle it triggering right
703 * away. NOTE that we don't share this. The signal is active low,
704 * and we can't ack it before a SPI message delay. We temporarily
705 * disable the IRQ until it's acked, which lets us work with more
706 * IRQ trigger modes (not all IRQ controllers can do falling edge).
709 INIT_WORK(&ds1305
->work
, ds1305_work
);
710 status
= devm_request_irq(&spi
->dev
, spi
->irq
, ds1305_irq
,
711 0, dev_name(&ds1305
->rtc
->dev
), ds1305
);
713 dev_err(&spi
->dev
, "request_irq %d --> %d\n",
716 device_set_wakeup_capable(&spi
->dev
, 1);
723 static int ds1305_remove(struct spi_device
*spi
)
725 struct ds1305
*ds1305
= spi_get_drvdata(spi
);
727 /* carefully shut down irq and workqueue, if present */
729 set_bit(FLAG_EXITING
, &ds1305
->flags
);
730 devm_free_irq(&spi
->dev
, spi
->irq
, ds1305
);
731 cancel_work_sync(&ds1305
->work
);
737 static struct spi_driver ds1305_driver
= {
738 .driver
.name
= "rtc-ds1305",
739 .probe
= ds1305_probe
,
740 .remove
= ds1305_remove
,
741 /* REVISIT add suspend/resume */
744 module_spi_driver(ds1305_driver
);
746 MODULE_DESCRIPTION("RTC driver for DS1305 and DS1306 chips");
747 MODULE_LICENSE("GPL");
748 MODULE_ALIAS("spi:rtc-ds1305");