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mtd: nand: atmel: Relax tADL_min constraint
[mirror_ubuntu-artful-kernel.git] / drivers / rtc / rtc-ds1307.c
1 /*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
7 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/acpi.h>
15 #include <linux/bcd.h>
16 #include <linux/i2c.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/rtc/ds1307.h>
21 #include <linux/rtc.h>
22 #include <linux/slab.h>
23 #include <linux/string.h>
24 #include <linux/hwmon.h>
25 #include <linux/hwmon-sysfs.h>
26 #include <linux/clk-provider.h>
27 #include <linux/regmap.h>
28
29 /*
30 * We can't determine type by probing, but if we expect pre-Linux code
31 * to have set the chip up as a clock (turning on the oscillator and
32 * setting the date and time), Linux can ignore the non-clock features.
33 * That's a natural job for a factory or repair bench.
34 */
35 enum ds_type {
36 ds_1307,
37 ds_1308,
38 ds_1337,
39 ds_1338,
40 ds_1339,
41 ds_1340,
42 ds_1388,
43 ds_3231,
44 m41t0,
45 m41t00,
46 mcp794xx,
47 rx_8025,
48 rx_8130,
49 last_ds_type /* always last */
50 /* rs5c372 too? different address... */
51 };
52
53
54 /* RTC registers don't differ much, except for the century flag */
55 #define DS1307_REG_SECS 0x00 /* 00-59 */
56 # define DS1307_BIT_CH 0x80
57 # define DS1340_BIT_nEOSC 0x80
58 # define MCP794XX_BIT_ST 0x80
59 #define DS1307_REG_MIN 0x01 /* 00-59 */
60 # define M41T0_BIT_OF 0x80
61 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
62 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
63 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
64 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
65 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
66 #define DS1307_REG_WDAY 0x03 /* 01-07 */
67 # define MCP794XX_BIT_VBATEN 0x08
68 #define DS1307_REG_MDAY 0x04 /* 01-31 */
69 #define DS1307_REG_MONTH 0x05 /* 01-12 */
70 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
71 #define DS1307_REG_YEAR 0x06 /* 00-99 */
72
73 /*
74 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
75 * start at 7, and they differ a LOT. Only control and status matter for
76 * basic RTC date and time functionality; be careful using them.
77 */
78 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
79 # define DS1307_BIT_OUT 0x80
80 # define DS1338_BIT_OSF 0x20
81 # define DS1307_BIT_SQWE 0x10
82 # define DS1307_BIT_RS1 0x02
83 # define DS1307_BIT_RS0 0x01
84 #define DS1337_REG_CONTROL 0x0e
85 # define DS1337_BIT_nEOSC 0x80
86 # define DS1339_BIT_BBSQI 0x20
87 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
88 # define DS1337_BIT_RS2 0x10
89 # define DS1337_BIT_RS1 0x08
90 # define DS1337_BIT_INTCN 0x04
91 # define DS1337_BIT_A2IE 0x02
92 # define DS1337_BIT_A1IE 0x01
93 #define DS1340_REG_CONTROL 0x07
94 # define DS1340_BIT_OUT 0x80
95 # define DS1340_BIT_FT 0x40
96 # define DS1340_BIT_CALIB_SIGN 0x20
97 # define DS1340_M_CALIBRATION 0x1f
98 #define DS1340_REG_FLAG 0x09
99 # define DS1340_BIT_OSF 0x80
100 #define DS1337_REG_STATUS 0x0f
101 # define DS1337_BIT_OSF 0x80
102 # define DS3231_BIT_EN32KHZ 0x08
103 # define DS1337_BIT_A2I 0x02
104 # define DS1337_BIT_A1I 0x01
105 #define DS1339_REG_ALARM1_SECS 0x07
106
107 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
108
109 #define RX8025_REG_CTRL1 0x0e
110 # define RX8025_BIT_2412 0x20
111 #define RX8025_REG_CTRL2 0x0f
112 # define RX8025_BIT_PON 0x10
113 # define RX8025_BIT_VDET 0x40
114 # define RX8025_BIT_XST 0x20
115
116
117 struct ds1307 {
118 u8 offset; /* register's offset */
119 u8 regs[11];
120 u16 nvram_offset;
121 struct nvmem_config nvmem_cfg;
122 enum ds_type type;
123 unsigned long flags;
124 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
125 #define HAS_ALARM 1 /* bit 1 == irq claimed */
126 struct device *dev;
127 struct regmap *regmap;
128 const char *name;
129 int irq;
130 struct rtc_device *rtc;
131 #ifdef CONFIG_COMMON_CLK
132 struct clk_hw clks[2];
133 #endif
134 };
135
136 struct chip_desc {
137 unsigned alarm:1;
138 u16 nvram_offset;
139 u16 nvram_size;
140 u8 century_reg;
141 u8 century_enable_bit;
142 u8 century_bit;
143 u16 trickle_charger_reg;
144 u8 trickle_charger_setup;
145 u8 (*do_trickle_setup)(struct ds1307 *, uint32_t,
146 bool);
147 };
148
149 static u8 do_trickle_setup_ds1339(struct ds1307 *, uint32_t ohms, bool diode);
150
151 static struct chip_desc chips[last_ds_type] = {
152 [ds_1307] = {
153 .nvram_offset = 8,
154 .nvram_size = 56,
155 },
156 [ds_1308] = {
157 .nvram_offset = 8,
158 .nvram_size = 56,
159 },
160 [ds_1337] = {
161 .alarm = 1,
162 .century_reg = DS1307_REG_MONTH,
163 .century_bit = DS1337_BIT_CENTURY,
164 },
165 [ds_1338] = {
166 .nvram_offset = 8,
167 .nvram_size = 56,
168 },
169 [ds_1339] = {
170 .alarm = 1,
171 .century_reg = DS1307_REG_MONTH,
172 .century_bit = DS1337_BIT_CENTURY,
173 .trickle_charger_reg = 0x10,
174 .do_trickle_setup = &do_trickle_setup_ds1339,
175 },
176 [ds_1340] = {
177 .century_reg = DS1307_REG_HOUR,
178 .century_enable_bit = DS1340_BIT_CENTURY_EN,
179 .century_bit = DS1340_BIT_CENTURY,
180 .trickle_charger_reg = 0x08,
181 },
182 [ds_1388] = {
183 .trickle_charger_reg = 0x0a,
184 },
185 [ds_3231] = {
186 .alarm = 1,
187 .century_reg = DS1307_REG_MONTH,
188 .century_bit = DS1337_BIT_CENTURY,
189 },
190 [rx_8130] = {
191 .alarm = 1,
192 /* this is battery backed SRAM */
193 .nvram_offset = 0x20,
194 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
195 },
196 [mcp794xx] = {
197 .alarm = 1,
198 /* this is battery backed SRAM */
199 .nvram_offset = 0x20,
200 .nvram_size = 0x40,
201 },
202 };
203
204 static const struct i2c_device_id ds1307_id[] = {
205 { "ds1307", ds_1307 },
206 { "ds1308", ds_1308 },
207 { "ds1337", ds_1337 },
208 { "ds1338", ds_1338 },
209 { "ds1339", ds_1339 },
210 { "ds1388", ds_1388 },
211 { "ds1340", ds_1340 },
212 { "ds3231", ds_3231 },
213 { "m41t0", m41t0 },
214 { "m41t00", m41t00 },
215 { "mcp7940x", mcp794xx },
216 { "mcp7941x", mcp794xx },
217 { "pt7c4338", ds_1307 },
218 { "rx8025", rx_8025 },
219 { "isl12057", ds_1337 },
220 { "rx8130", rx_8130 },
221 { }
222 };
223 MODULE_DEVICE_TABLE(i2c, ds1307_id);
224
225 #ifdef CONFIG_OF
226 static const struct of_device_id ds1307_of_match[] = {
227 {
228 .compatible = "dallas,ds1307",
229 .data = (void *)ds_1307
230 },
231 {
232 .compatible = "dallas,ds1308",
233 .data = (void *)ds_1308
234 },
235 {
236 .compatible = "dallas,ds1337",
237 .data = (void *)ds_1337
238 },
239 {
240 .compatible = "dallas,ds1338",
241 .data = (void *)ds_1338
242 },
243 {
244 .compatible = "dallas,ds1339",
245 .data = (void *)ds_1339
246 },
247 {
248 .compatible = "dallas,ds1388",
249 .data = (void *)ds_1388
250 },
251 {
252 .compatible = "dallas,ds1340",
253 .data = (void *)ds_1340
254 },
255 {
256 .compatible = "maxim,ds3231",
257 .data = (void *)ds_3231
258 },
259 {
260 .compatible = "st,m41t0",
261 .data = (void *)m41t00
262 },
263 {
264 .compatible = "st,m41t00",
265 .data = (void *)m41t00
266 },
267 {
268 .compatible = "microchip,mcp7940x",
269 .data = (void *)mcp794xx
270 },
271 {
272 .compatible = "microchip,mcp7941x",
273 .data = (void *)mcp794xx
274 },
275 {
276 .compatible = "pericom,pt7c4338",
277 .data = (void *)ds_1307
278 },
279 {
280 .compatible = "epson,rx8025",
281 .data = (void *)rx_8025
282 },
283 {
284 .compatible = "isil,isl12057",
285 .data = (void *)ds_1337
286 },
287 { }
288 };
289 MODULE_DEVICE_TABLE(of, ds1307_of_match);
290 #endif
291
292 #ifdef CONFIG_ACPI
293 static const struct acpi_device_id ds1307_acpi_ids[] = {
294 { .id = "DS1307", .driver_data = ds_1307 },
295 { .id = "DS1308", .driver_data = ds_1308 },
296 { .id = "DS1337", .driver_data = ds_1337 },
297 { .id = "DS1338", .driver_data = ds_1338 },
298 { .id = "DS1339", .driver_data = ds_1339 },
299 { .id = "DS1388", .driver_data = ds_1388 },
300 { .id = "DS1340", .driver_data = ds_1340 },
301 { .id = "DS3231", .driver_data = ds_3231 },
302 { .id = "M41T0", .driver_data = m41t0 },
303 { .id = "M41T00", .driver_data = m41t00 },
304 { .id = "MCP7940X", .driver_data = mcp794xx },
305 { .id = "MCP7941X", .driver_data = mcp794xx },
306 { .id = "PT7C4338", .driver_data = ds_1307 },
307 { .id = "RX8025", .driver_data = rx_8025 },
308 { .id = "ISL12057", .driver_data = ds_1337 },
309 { }
310 };
311 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
312 #endif
313
314 /*
315 * The ds1337 and ds1339 both have two alarms, but we only use the first
316 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
317 * signal; ds1339 chips have only one alarm signal.
318 */
319 static irqreturn_t ds1307_irq(int irq, void *dev_id)
320 {
321 struct ds1307 *ds1307 = dev_id;
322 struct mutex *lock = &ds1307->rtc->ops_lock;
323 int stat, ret;
324
325 mutex_lock(lock);
326 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
327 if (ret)
328 goto out;
329
330 if (stat & DS1337_BIT_A1I) {
331 stat &= ~DS1337_BIT_A1I;
332 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
333
334 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
335 DS1337_BIT_A1IE, 0);
336 if (ret)
337 goto out;
338
339 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
340 }
341
342 out:
343 mutex_unlock(lock);
344
345 return IRQ_HANDLED;
346 }
347
348 /*----------------------------------------------------------------------*/
349
350 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
351 {
352 struct ds1307 *ds1307 = dev_get_drvdata(dev);
353 int tmp, ret;
354 const struct chip_desc *chip = &chips[ds1307->type];
355
356 /* read the RTC date and time registers all at once */
357 ret = regmap_bulk_read(ds1307->regmap, ds1307->offset, ds1307->regs, 7);
358 if (ret) {
359 dev_err(dev, "%s error %d\n", "read", ret);
360 return ret;
361 }
362
363 dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
364
365 /* if oscillator fail bit is set, no data can be trusted */
366 if (ds1307->type == m41t0 &&
367 ds1307->regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
368 dev_warn_once(dev, "oscillator failed, set time!\n");
369 return -EINVAL;
370 }
371
372 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
373 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
374 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
375 t->tm_hour = bcd2bin(tmp);
376 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
377 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
378 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
379 t->tm_mon = bcd2bin(tmp) - 1;
380 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
381
382 if (ds1307->regs[chip->century_reg] & chip->century_bit &&
383 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
384 t->tm_year += 100;
385
386 dev_dbg(dev, "%s secs=%d, mins=%d, "
387 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
388 "read", t->tm_sec, t->tm_min,
389 t->tm_hour, t->tm_mday,
390 t->tm_mon, t->tm_year, t->tm_wday);
391
392 /* initial clock setting can be undefined */
393 return rtc_valid_tm(t);
394 }
395
396 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
397 {
398 struct ds1307 *ds1307 = dev_get_drvdata(dev);
399 const struct chip_desc *chip = &chips[ds1307->type];
400 int result;
401 int tmp;
402 u8 *buf = ds1307->regs;
403
404 dev_dbg(dev, "%s secs=%d, mins=%d, "
405 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
406 "write", t->tm_sec, t->tm_min,
407 t->tm_hour, t->tm_mday,
408 t->tm_mon, t->tm_year, t->tm_wday);
409
410 if (t->tm_year < 100)
411 return -EINVAL;
412
413 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
414 if (t->tm_year > (chip->century_bit ? 299 : 199))
415 return -EINVAL;
416 #else
417 if (t->tm_year > 199)
418 return -EINVAL;
419 #endif
420
421 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
422 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
423 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
424 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
425 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
426 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
427
428 /* assume 20YY not 19YY */
429 tmp = t->tm_year - 100;
430 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
431
432 if (chip->century_enable_bit)
433 buf[chip->century_reg] |= chip->century_enable_bit;
434 if (t->tm_year > 199 && chip->century_bit)
435 buf[chip->century_reg] |= chip->century_bit;
436
437 if (ds1307->type == mcp794xx) {
438 /*
439 * these bits were cleared when preparing the date/time
440 * values and need to be set again before writing the
441 * buffer out to the device.
442 */
443 buf[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
444 buf[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
445 }
446
447 dev_dbg(dev, "%s: %7ph\n", "write", buf);
448
449 result = regmap_bulk_write(ds1307->regmap, ds1307->offset, buf, 7);
450 if (result) {
451 dev_err(dev, "%s error %d\n", "write", result);
452 return result;
453 }
454 return 0;
455 }
456
457 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
458 {
459 struct ds1307 *ds1307 = dev_get_drvdata(dev);
460 int ret;
461
462 if (!test_bit(HAS_ALARM, &ds1307->flags))
463 return -EINVAL;
464
465 /* read all ALARM1, ALARM2, and status registers at once */
466 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
467 ds1307->regs, 9);
468 if (ret) {
469 dev_err(dev, "%s error %d\n", "alarm read", ret);
470 return ret;
471 }
472
473 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
474 &ds1307->regs[0], &ds1307->regs[4], &ds1307->regs[7]);
475
476 /*
477 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
478 * and that all four fields are checked matches
479 */
480 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
481 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
482 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
483 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
484
485 /* ... and status */
486 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
487 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
488
489 dev_dbg(dev, "%s secs=%d, mins=%d, "
490 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
491 "alarm read", t->time.tm_sec, t->time.tm_min,
492 t->time.tm_hour, t->time.tm_mday,
493 t->enabled, t->pending);
494
495 return 0;
496 }
497
498 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
499 {
500 struct ds1307 *ds1307 = dev_get_drvdata(dev);
501 unsigned char *buf = ds1307->regs;
502 u8 control, status;
503 int ret;
504
505 if (!test_bit(HAS_ALARM, &ds1307->flags))
506 return -EINVAL;
507
508 dev_dbg(dev, "%s secs=%d, mins=%d, "
509 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
510 "alarm set", t->time.tm_sec, t->time.tm_min,
511 t->time.tm_hour, t->time.tm_mday,
512 t->enabled, t->pending);
513
514 /* read current status of both alarms and the chip */
515 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, buf, 9);
516 if (ret) {
517 dev_err(dev, "%s error %d\n", "alarm write", ret);
518 return ret;
519 }
520 control = ds1307->regs[7];
521 status = ds1307->regs[8];
522
523 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
524 &ds1307->regs[0], &ds1307->regs[4], control, status);
525
526 /* set ALARM1, using 24 hour and day-of-month modes */
527 buf[0] = bin2bcd(t->time.tm_sec);
528 buf[1] = bin2bcd(t->time.tm_min);
529 buf[2] = bin2bcd(t->time.tm_hour);
530 buf[3] = bin2bcd(t->time.tm_mday);
531
532 /* set ALARM2 to non-garbage */
533 buf[4] = 0;
534 buf[5] = 0;
535 buf[6] = 0;
536
537 /* disable alarms */
538 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
539 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
540
541 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, buf, 9);
542 if (ret) {
543 dev_err(dev, "can't set alarm time\n");
544 return ret;
545 }
546
547 /* optionally enable ALARM1 */
548 if (t->enabled) {
549 dev_dbg(dev, "alarm IRQ armed\n");
550 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
551 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, buf[7]);
552 }
553
554 return 0;
555 }
556
557 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
558 {
559 struct ds1307 *ds1307 = dev_get_drvdata(dev);
560
561 if (!test_bit(HAS_ALARM, &ds1307->flags))
562 return -ENOTTY;
563
564 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
565 DS1337_BIT_A1IE,
566 enabled ? DS1337_BIT_A1IE : 0);
567 }
568
569 static const struct rtc_class_ops ds13xx_rtc_ops = {
570 .read_time = ds1307_get_time,
571 .set_time = ds1307_set_time,
572 .read_alarm = ds1337_read_alarm,
573 .set_alarm = ds1337_set_alarm,
574 .alarm_irq_enable = ds1307_alarm_irq_enable,
575 };
576
577 /*----------------------------------------------------------------------*/
578
579 /*
580 * Alarm support for rx8130 devices.
581 */
582
583 #define RX8130_REG_ALARM_MIN 0x07
584 #define RX8130_REG_ALARM_HOUR 0x08
585 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x09
586 #define RX8130_REG_EXTENSION 0x0c
587 #define RX8130_REG_EXTENSION_WADA (1 << 3)
588 #define RX8130_REG_FLAG 0x0d
589 #define RX8130_REG_FLAG_AF (1 << 3)
590 #define RX8130_REG_CONTROL0 0x0e
591 #define RX8130_REG_CONTROL0_AIE (1 << 3)
592
593 static irqreturn_t rx8130_irq(int irq, void *dev_id)
594 {
595 struct ds1307 *ds1307 = dev_id;
596 struct mutex *lock = &ds1307->rtc->ops_lock;
597 u8 ctl[3];
598 int ret;
599
600 mutex_lock(lock);
601
602 /* Read control registers. */
603 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
604 if (ret < 0)
605 goto out;
606 if (!(ctl[1] & RX8130_REG_FLAG_AF))
607 goto out;
608 ctl[1] &= ~RX8130_REG_FLAG_AF;
609 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
610
611 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
612 if (ret < 0)
613 goto out;
614
615 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
616
617 out:
618 mutex_unlock(lock);
619
620 return IRQ_HANDLED;
621 }
622
623 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
624 {
625 struct ds1307 *ds1307 = dev_get_drvdata(dev);
626 u8 ald[3], ctl[3];
627 int ret;
628
629 if (!test_bit(HAS_ALARM, &ds1307->flags))
630 return -EINVAL;
631
632 /* Read alarm registers. */
633 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 3);
634 if (ret < 0)
635 return ret;
636
637 /* Read control registers. */
638 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
639 if (ret < 0)
640 return ret;
641
642 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
643 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
644
645 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
646 t->time.tm_sec = -1;
647 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
648 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
649 t->time.tm_wday = -1;
650 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
651 t->time.tm_mon = -1;
652 t->time.tm_year = -1;
653 t->time.tm_yday = -1;
654 t->time.tm_isdst = -1;
655
656 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
657 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
658 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
659
660 return 0;
661 }
662
663 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
664 {
665 struct ds1307 *ds1307 = dev_get_drvdata(dev);
666 u8 ald[3], ctl[3];
667 int ret;
668
669 if (!test_bit(HAS_ALARM, &ds1307->flags))
670 return -EINVAL;
671
672 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
673 "enabled=%d pending=%d\n", __func__,
674 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
675 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
676 t->enabled, t->pending);
677
678 /* Read control registers. */
679 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
680 if (ret < 0)
681 return ret;
682
683 ctl[0] &= ~RX8130_REG_EXTENSION_WADA;
684 ctl[1] |= RX8130_REG_FLAG_AF;
685 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
686
687 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
688 if (ret < 0)
689 return ret;
690
691 /* Hardware alarm precision is 1 minute! */
692 ald[0] = bin2bcd(t->time.tm_min);
693 ald[1] = bin2bcd(t->time.tm_hour);
694 ald[2] = bin2bcd(t->time.tm_mday);
695
696 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 3);
697 if (ret < 0)
698 return ret;
699
700 if (!t->enabled)
701 return 0;
702
703 ctl[2] |= RX8130_REG_CONTROL0_AIE;
704
705 return regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
706 }
707
708 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
709 {
710 struct ds1307 *ds1307 = dev_get_drvdata(dev);
711 int ret, reg;
712
713 if (!test_bit(HAS_ALARM, &ds1307->flags))
714 return -EINVAL;
715
716 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
717 if (ret < 0)
718 return ret;
719
720 if (enabled)
721 reg |= RX8130_REG_CONTROL0_AIE;
722 else
723 reg &= ~RX8130_REG_CONTROL0_AIE;
724
725 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
726 }
727
728 static const struct rtc_class_ops rx8130_rtc_ops = {
729 .read_time = ds1307_get_time,
730 .set_time = ds1307_set_time,
731 .read_alarm = rx8130_read_alarm,
732 .set_alarm = rx8130_set_alarm,
733 .alarm_irq_enable = rx8130_alarm_irq_enable,
734 };
735
736 /*----------------------------------------------------------------------*/
737
738 /*
739 * Alarm support for mcp794xx devices.
740 */
741
742 #define MCP794XX_REG_WEEKDAY 0x3
743 #define MCP794XX_REG_WEEKDAY_WDAY_MASK 0x7
744 #define MCP794XX_REG_CONTROL 0x07
745 # define MCP794XX_BIT_ALM0_EN 0x10
746 # define MCP794XX_BIT_ALM1_EN 0x20
747 #define MCP794XX_REG_ALARM0_BASE 0x0a
748 #define MCP794XX_REG_ALARM0_CTRL 0x0d
749 #define MCP794XX_REG_ALARM1_BASE 0x11
750 #define MCP794XX_REG_ALARM1_CTRL 0x14
751 # define MCP794XX_BIT_ALMX_IF (1 << 3)
752 # define MCP794XX_BIT_ALMX_C0 (1 << 4)
753 # define MCP794XX_BIT_ALMX_C1 (1 << 5)
754 # define MCP794XX_BIT_ALMX_C2 (1 << 6)
755 # define MCP794XX_BIT_ALMX_POL (1 << 7)
756 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
757 MCP794XX_BIT_ALMX_C1 | \
758 MCP794XX_BIT_ALMX_C2)
759
760 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
761 {
762 struct ds1307 *ds1307 = dev_id;
763 struct mutex *lock = &ds1307->rtc->ops_lock;
764 int reg, ret;
765
766 mutex_lock(lock);
767
768 /* Check and clear alarm 0 interrupt flag. */
769 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
770 if (ret)
771 goto out;
772 if (!(reg & MCP794XX_BIT_ALMX_IF))
773 goto out;
774 reg &= ~MCP794XX_BIT_ALMX_IF;
775 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
776 if (ret)
777 goto out;
778
779 /* Disable alarm 0. */
780 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
781 MCP794XX_BIT_ALM0_EN, 0);
782 if (ret)
783 goto out;
784
785 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
786
787 out:
788 mutex_unlock(lock);
789
790 return IRQ_HANDLED;
791 }
792
793 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
794 {
795 struct ds1307 *ds1307 = dev_get_drvdata(dev);
796 u8 *regs = ds1307->regs;
797 int ret;
798
799 if (!test_bit(HAS_ALARM, &ds1307->flags))
800 return -EINVAL;
801
802 /* Read control and alarm 0 registers. */
803 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 10);
804 if (ret)
805 return ret;
806
807 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
808
809 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
810 t->time.tm_sec = bcd2bin(ds1307->regs[3] & 0x7f);
811 t->time.tm_min = bcd2bin(ds1307->regs[4] & 0x7f);
812 t->time.tm_hour = bcd2bin(ds1307->regs[5] & 0x3f);
813 t->time.tm_wday = bcd2bin(ds1307->regs[6] & 0x7) - 1;
814 t->time.tm_mday = bcd2bin(ds1307->regs[7] & 0x3f);
815 t->time.tm_mon = bcd2bin(ds1307->regs[8] & 0x1f) - 1;
816 t->time.tm_year = -1;
817 t->time.tm_yday = -1;
818 t->time.tm_isdst = -1;
819
820 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
821 "enabled=%d polarity=%d irq=%d match=%d\n", __func__,
822 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
823 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
824 !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_POL),
825 !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_IF),
826 (ds1307->regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
827
828 return 0;
829 }
830
831 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
832 {
833 struct ds1307 *ds1307 = dev_get_drvdata(dev);
834 unsigned char *regs = ds1307->regs;
835 int ret;
836
837 if (!test_bit(HAS_ALARM, &ds1307->flags))
838 return -EINVAL;
839
840 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
841 "enabled=%d pending=%d\n", __func__,
842 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
843 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
844 t->enabled, t->pending);
845
846 /* Read control and alarm 0 registers. */
847 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 10);
848 if (ret)
849 return ret;
850
851 /* Set alarm 0, using 24-hour and day-of-month modes. */
852 regs[3] = bin2bcd(t->time.tm_sec);
853 regs[4] = bin2bcd(t->time.tm_min);
854 regs[5] = bin2bcd(t->time.tm_hour);
855 regs[6] = bin2bcd(t->time.tm_wday + 1);
856 regs[7] = bin2bcd(t->time.tm_mday);
857 regs[8] = bin2bcd(t->time.tm_mon + 1);
858
859 /* Clear the alarm 0 interrupt flag. */
860 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
861 /* Set alarm match: second, minute, hour, day, date, month. */
862 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
863 /* Disable interrupt. We will not enable until completely programmed */
864 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
865
866 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 10);
867 if (ret)
868 return ret;
869
870 if (!t->enabled)
871 return 0;
872 regs[0] |= MCP794XX_BIT_ALM0_EN;
873 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
874 }
875
876 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
877 {
878 struct ds1307 *ds1307 = dev_get_drvdata(dev);
879
880 if (!test_bit(HAS_ALARM, &ds1307->flags))
881 return -EINVAL;
882
883 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
884 MCP794XX_BIT_ALM0_EN,
885 enabled ? MCP794XX_BIT_ALM0_EN : 0);
886 }
887
888 static const struct rtc_class_ops mcp794xx_rtc_ops = {
889 .read_time = ds1307_get_time,
890 .set_time = ds1307_set_time,
891 .read_alarm = mcp794xx_read_alarm,
892 .set_alarm = mcp794xx_set_alarm,
893 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
894 };
895
896 /*----------------------------------------------------------------------*/
897
898 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
899 size_t bytes)
900 {
901 struct ds1307 *ds1307 = priv;
902
903 return regmap_bulk_read(ds1307->regmap, ds1307->nvram_offset + offset,
904 val, bytes);
905 }
906
907 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
908 size_t bytes)
909 {
910 struct ds1307 *ds1307 = priv;
911
912 return regmap_bulk_write(ds1307->regmap, ds1307->nvram_offset + offset,
913 val, bytes);
914 }
915
916 /*----------------------------------------------------------------------*/
917
918 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307,
919 uint32_t ohms, bool diode)
920 {
921 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
922 DS1307_TRICKLE_CHARGER_NO_DIODE;
923
924 switch (ohms) {
925 case 250:
926 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
927 break;
928 case 2000:
929 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
930 break;
931 case 4000:
932 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
933 break;
934 default:
935 dev_warn(ds1307->dev,
936 "Unsupported ohm value %u in dt\n", ohms);
937 return 0;
938 }
939 return setup;
940 }
941
942 static void ds1307_trickle_init(struct ds1307 *ds1307,
943 struct chip_desc *chip)
944 {
945 uint32_t ohms = 0;
946 bool diode = true;
947
948 if (!chip->do_trickle_setup)
949 goto out;
950 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
951 &ohms))
952 goto out;
953 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
954 diode = false;
955 chip->trickle_charger_setup = chip->do_trickle_setup(ds1307,
956 ohms, diode);
957 out:
958 return;
959 }
960
961 /*----------------------------------------------------------------------*/
962
963 #ifdef CONFIG_RTC_DRV_DS1307_HWMON
964
965 /*
966 * Temperature sensor support for ds3231 devices.
967 */
968
969 #define DS3231_REG_TEMPERATURE 0x11
970
971 /*
972 * A user-initiated temperature conversion is not started by this function,
973 * so the temperature is updated once every 64 seconds.
974 */
975 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
976 {
977 struct ds1307 *ds1307 = dev_get_drvdata(dev);
978 u8 temp_buf[2];
979 s16 temp;
980 int ret;
981
982 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
983 temp_buf, sizeof(temp_buf));
984 if (ret)
985 return ret;
986 /*
987 * Temperature is represented as a 10-bit code with a resolution of
988 * 0.25 degree celsius and encoded in two's complement format.
989 */
990 temp = (temp_buf[0] << 8) | temp_buf[1];
991 temp >>= 6;
992 *mC = temp * 250;
993
994 return 0;
995 }
996
997 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
998 struct device_attribute *attr, char *buf)
999 {
1000 int ret;
1001 s32 temp;
1002
1003 ret = ds3231_hwmon_read_temp(dev, &temp);
1004 if (ret)
1005 return ret;
1006
1007 return sprintf(buf, "%d\n", temp);
1008 }
1009 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, ds3231_hwmon_show_temp,
1010 NULL, 0);
1011
1012 static struct attribute *ds3231_hwmon_attrs[] = {
1013 &sensor_dev_attr_temp1_input.dev_attr.attr,
1014 NULL,
1015 };
1016 ATTRIBUTE_GROUPS(ds3231_hwmon);
1017
1018 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1019 {
1020 struct device *dev;
1021
1022 if (ds1307->type != ds_3231)
1023 return;
1024
1025 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1026 ds1307, ds3231_hwmon_groups);
1027 if (IS_ERR(dev)) {
1028 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1029 PTR_ERR(dev));
1030 }
1031 }
1032
1033 #else
1034
1035 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1036 {
1037 }
1038
1039 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1040
1041 /*----------------------------------------------------------------------*/
1042
1043 /*
1044 * Square-wave output support for DS3231
1045 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1046 */
1047 #ifdef CONFIG_COMMON_CLK
1048
1049 enum {
1050 DS3231_CLK_SQW = 0,
1051 DS3231_CLK_32KHZ,
1052 };
1053
1054 #define clk_sqw_to_ds1307(clk) \
1055 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1056 #define clk_32khz_to_ds1307(clk) \
1057 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1058
1059 static int ds3231_clk_sqw_rates[] = {
1060 1,
1061 1024,
1062 4096,
1063 8192,
1064 };
1065
1066 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1067 {
1068 struct mutex *lock = &ds1307->rtc->ops_lock;
1069 int ret;
1070
1071 mutex_lock(lock);
1072 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1073 mask, value);
1074 mutex_unlock(lock);
1075
1076 return ret;
1077 }
1078
1079 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1080 unsigned long parent_rate)
1081 {
1082 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1083 int control, ret;
1084 int rate_sel = 0;
1085
1086 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1087 if (ret)
1088 return ret;
1089 if (control & DS1337_BIT_RS1)
1090 rate_sel += 1;
1091 if (control & DS1337_BIT_RS2)
1092 rate_sel += 2;
1093
1094 return ds3231_clk_sqw_rates[rate_sel];
1095 }
1096
1097 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1098 unsigned long *prate)
1099 {
1100 int i;
1101
1102 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1103 if (ds3231_clk_sqw_rates[i] <= rate)
1104 return ds3231_clk_sqw_rates[i];
1105 }
1106
1107 return 0;
1108 }
1109
1110 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1111 unsigned long parent_rate)
1112 {
1113 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1114 int control = 0;
1115 int rate_sel;
1116
1117 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1118 rate_sel++) {
1119 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1120 break;
1121 }
1122
1123 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1124 return -EINVAL;
1125
1126 if (rate_sel & 1)
1127 control |= DS1337_BIT_RS1;
1128 if (rate_sel & 2)
1129 control |= DS1337_BIT_RS2;
1130
1131 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1132 control);
1133 }
1134
1135 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1136 {
1137 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1138
1139 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1140 }
1141
1142 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1143 {
1144 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1145
1146 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1147 }
1148
1149 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1150 {
1151 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1152 int control, ret;
1153
1154 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1155 if (ret)
1156 return ret;
1157
1158 return !(control & DS1337_BIT_INTCN);
1159 }
1160
1161 static const struct clk_ops ds3231_clk_sqw_ops = {
1162 .prepare = ds3231_clk_sqw_prepare,
1163 .unprepare = ds3231_clk_sqw_unprepare,
1164 .is_prepared = ds3231_clk_sqw_is_prepared,
1165 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1166 .round_rate = ds3231_clk_sqw_round_rate,
1167 .set_rate = ds3231_clk_sqw_set_rate,
1168 };
1169
1170 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1171 unsigned long parent_rate)
1172 {
1173 return 32768;
1174 }
1175
1176 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1177 {
1178 struct mutex *lock = &ds1307->rtc->ops_lock;
1179 int ret;
1180
1181 mutex_lock(lock);
1182 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1183 DS3231_BIT_EN32KHZ,
1184 enable ? DS3231_BIT_EN32KHZ : 0);
1185 mutex_unlock(lock);
1186
1187 return ret;
1188 }
1189
1190 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1191 {
1192 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1193
1194 return ds3231_clk_32khz_control(ds1307, true);
1195 }
1196
1197 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1198 {
1199 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1200
1201 ds3231_clk_32khz_control(ds1307, false);
1202 }
1203
1204 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1205 {
1206 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1207 int status, ret;
1208
1209 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1210 if (ret)
1211 return ret;
1212
1213 return !!(status & DS3231_BIT_EN32KHZ);
1214 }
1215
1216 static const struct clk_ops ds3231_clk_32khz_ops = {
1217 .prepare = ds3231_clk_32khz_prepare,
1218 .unprepare = ds3231_clk_32khz_unprepare,
1219 .is_prepared = ds3231_clk_32khz_is_prepared,
1220 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1221 };
1222
1223 static struct clk_init_data ds3231_clks_init[] = {
1224 [DS3231_CLK_SQW] = {
1225 .name = "ds3231_clk_sqw",
1226 .ops = &ds3231_clk_sqw_ops,
1227 },
1228 [DS3231_CLK_32KHZ] = {
1229 .name = "ds3231_clk_32khz",
1230 .ops = &ds3231_clk_32khz_ops,
1231 },
1232 };
1233
1234 static int ds3231_clks_register(struct ds1307 *ds1307)
1235 {
1236 struct device_node *node = ds1307->dev->of_node;
1237 struct clk_onecell_data *onecell;
1238 int i;
1239
1240 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1241 if (!onecell)
1242 return -ENOMEM;
1243
1244 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1245 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1246 sizeof(onecell->clks[0]), GFP_KERNEL);
1247 if (!onecell->clks)
1248 return -ENOMEM;
1249
1250 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1251 struct clk_init_data init = ds3231_clks_init[i];
1252
1253 /*
1254 * Interrupt signal due to alarm conditions and square-wave
1255 * output share same pin, so don't initialize both.
1256 */
1257 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1258 continue;
1259
1260 /* optional override of the clockname */
1261 of_property_read_string_index(node, "clock-output-names", i,
1262 &init.name);
1263 ds1307->clks[i].init = &init;
1264
1265 onecell->clks[i] = devm_clk_register(ds1307->dev,
1266 &ds1307->clks[i]);
1267 if (IS_ERR(onecell->clks[i]))
1268 return PTR_ERR(onecell->clks[i]);
1269 }
1270
1271 if (!node)
1272 return 0;
1273
1274 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1275
1276 return 0;
1277 }
1278
1279 static void ds1307_clks_register(struct ds1307 *ds1307)
1280 {
1281 int ret;
1282
1283 if (ds1307->type != ds_3231)
1284 return;
1285
1286 ret = ds3231_clks_register(ds1307);
1287 if (ret) {
1288 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1289 ret);
1290 }
1291 }
1292
1293 #else
1294
1295 static void ds1307_clks_register(struct ds1307 *ds1307)
1296 {
1297 }
1298
1299 #endif /* CONFIG_COMMON_CLK */
1300
1301 static const struct regmap_config regmap_config = {
1302 .reg_bits = 8,
1303 .val_bits = 8,
1304 .max_register = 0x12,
1305 };
1306
1307 static int ds1307_probe(struct i2c_client *client,
1308 const struct i2c_device_id *id)
1309 {
1310 struct ds1307 *ds1307;
1311 int err = -ENODEV;
1312 int tmp, wday;
1313 struct chip_desc *chip;
1314 bool want_irq = false;
1315 bool ds1307_can_wakeup_device = false;
1316 unsigned char *buf;
1317 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1318 struct rtc_time tm;
1319 unsigned long timestamp;
1320
1321 irq_handler_t irq_handler = ds1307_irq;
1322
1323 static const int bbsqi_bitpos[] = {
1324 [ds_1337] = 0,
1325 [ds_1339] = DS1339_BIT_BBSQI,
1326 [ds_3231] = DS3231_BIT_BBSQW,
1327 };
1328 const struct rtc_class_ops *rtc_ops = &ds13xx_rtc_ops;
1329
1330 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1331 if (!ds1307)
1332 return -ENOMEM;
1333
1334 dev_set_drvdata(&client->dev, ds1307);
1335 ds1307->dev = &client->dev;
1336 ds1307->name = client->name;
1337 ds1307->irq = client->irq;
1338
1339 ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1340 if (IS_ERR(ds1307->regmap)) {
1341 dev_err(ds1307->dev, "regmap allocation failed\n");
1342 return PTR_ERR(ds1307->regmap);
1343 }
1344
1345 i2c_set_clientdata(client, ds1307);
1346
1347 if (client->dev.of_node) {
1348 ds1307->type = (enum ds_type)
1349 of_device_get_match_data(&client->dev);
1350 chip = &chips[ds1307->type];
1351 } else if (id) {
1352 chip = &chips[id->driver_data];
1353 ds1307->type = id->driver_data;
1354 } else {
1355 const struct acpi_device_id *acpi_id;
1356
1357 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1358 ds1307->dev);
1359 if (!acpi_id)
1360 return -ENODEV;
1361 chip = &chips[acpi_id->driver_data];
1362 ds1307->type = acpi_id->driver_data;
1363 }
1364
1365 if (!pdata)
1366 ds1307_trickle_init(ds1307, chip);
1367 else if (pdata->trickle_charger_setup)
1368 chip->trickle_charger_setup = pdata->trickle_charger_setup;
1369
1370 if (chip->trickle_charger_setup && chip->trickle_charger_reg) {
1371 dev_dbg(ds1307->dev,
1372 "writing trickle charger info 0x%x to 0x%x\n",
1373 DS13XX_TRICKLE_CHARGER_MAGIC | chip->trickle_charger_setup,
1374 chip->trickle_charger_reg);
1375 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1376 DS13XX_TRICKLE_CHARGER_MAGIC |
1377 chip->trickle_charger_setup);
1378 }
1379
1380 buf = ds1307->regs;
1381
1382 #ifdef CONFIG_OF
1383 /*
1384 * For devices with no IRQ directly connected to the SoC, the RTC chip
1385 * can be forced as a wakeup source by stating that explicitly in
1386 * the device's .dts file using the "wakeup-source" boolean property.
1387 * If the "wakeup-source" property is set, don't request an IRQ.
1388 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1389 * if supported by the RTC.
1390 */
1391 if (of_property_read_bool(client->dev.of_node, "wakeup-source")) {
1392 ds1307_can_wakeup_device = true;
1393 }
1394 /* Intersil ISL12057 DT backward compatibility */
1395 if (of_property_read_bool(client->dev.of_node,
1396 "isil,irq2-can-wakeup-machine")) {
1397 ds1307_can_wakeup_device = true;
1398 }
1399 #endif
1400
1401 switch (ds1307->type) {
1402 case ds_1337:
1403 case ds_1339:
1404 case ds_3231:
1405 /* get registers that the "rtc" read below won't read... */
1406 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1407 buf, 2);
1408 if (err) {
1409 dev_dbg(ds1307->dev, "read error %d\n", err);
1410 goto exit;
1411 }
1412
1413 /* oscillator off? turn it on, so clock can tick. */
1414 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
1415 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
1416
1417 /*
1418 * Using IRQ or defined as wakeup-source?
1419 * Disable the square wave and both alarms.
1420 * For some variants, be sure alarms can trigger when we're
1421 * running on Vbackup (BBSQI/BBSQW)
1422 */
1423 if (chip->alarm && (ds1307->irq > 0 ||
1424 ds1307_can_wakeup_device)) {
1425 ds1307->regs[0] |= DS1337_BIT_INTCN
1426 | bbsqi_bitpos[ds1307->type];
1427 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1428
1429 want_irq = true;
1430 }
1431
1432 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1433 ds1307->regs[0]);
1434
1435 /* oscillator fault? clear flag, and warn */
1436 if (ds1307->regs[1] & DS1337_BIT_OSF) {
1437 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1438 ds1307->regs[1] & ~DS1337_BIT_OSF);
1439 dev_warn(ds1307->dev, "SET TIME!\n");
1440 }
1441 break;
1442
1443 case rx_8025:
1444 err = regmap_bulk_read(ds1307->regmap,
1445 RX8025_REG_CTRL1 << 4 | 0x08, buf, 2);
1446 if (err) {
1447 dev_dbg(ds1307->dev, "read error %d\n", err);
1448 goto exit;
1449 }
1450
1451 /* oscillator off? turn it on, so clock can tick. */
1452 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
1453 ds1307->regs[1] |= RX8025_BIT_XST;
1454 regmap_write(ds1307->regmap,
1455 RX8025_REG_CTRL2 << 4 | 0x08,
1456 ds1307->regs[1]);
1457 dev_warn(ds1307->dev,
1458 "oscillator stop detected - SET TIME!\n");
1459 }
1460
1461 if (ds1307->regs[1] & RX8025_BIT_PON) {
1462 ds1307->regs[1] &= ~RX8025_BIT_PON;
1463 regmap_write(ds1307->regmap,
1464 RX8025_REG_CTRL2 << 4 | 0x08,
1465 ds1307->regs[1]);
1466 dev_warn(ds1307->dev, "power-on detected\n");
1467 }
1468
1469 if (ds1307->regs[1] & RX8025_BIT_VDET) {
1470 ds1307->regs[1] &= ~RX8025_BIT_VDET;
1471 regmap_write(ds1307->regmap,
1472 RX8025_REG_CTRL2 << 4 | 0x08,
1473 ds1307->regs[1]);
1474 dev_warn(ds1307->dev, "voltage drop detected\n");
1475 }
1476
1477 /* make sure we are running in 24hour mode */
1478 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
1479 u8 hour;
1480
1481 /* switch to 24 hour mode */
1482 regmap_write(ds1307->regmap,
1483 RX8025_REG_CTRL1 << 4 | 0x08,
1484 ds1307->regs[0] | RX8025_BIT_2412);
1485
1486 err = regmap_bulk_read(ds1307->regmap,
1487 RX8025_REG_CTRL1 << 4 | 0x08,
1488 buf, 2);
1489 if (err) {
1490 dev_dbg(ds1307->dev, "read error %d\n", err);
1491 goto exit;
1492 }
1493
1494 /* correct hour */
1495 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
1496 if (hour == 12)
1497 hour = 0;
1498 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1499 hour += 12;
1500
1501 regmap_write(ds1307->regmap,
1502 DS1307_REG_HOUR << 4 | 0x08, hour);
1503 }
1504 break;
1505 case rx_8130:
1506 ds1307->offset = 0x10; /* Seconds starts at 0x10 */
1507 rtc_ops = &rx8130_rtc_ops;
1508 if (chip->alarm && ds1307->irq > 0) {
1509 irq_handler = rx8130_irq;
1510 want_irq = true;
1511 }
1512 break;
1513 case ds_1388:
1514 ds1307->offset = 1; /* Seconds starts at 1 */
1515 break;
1516 case mcp794xx:
1517 rtc_ops = &mcp794xx_rtc_ops;
1518 if (chip->alarm && (ds1307->irq > 0 ||
1519 ds1307_can_wakeup_device)) {
1520 irq_handler = mcp794xx_irq;
1521 want_irq = true;
1522 }
1523 break;
1524 default:
1525 break;
1526 }
1527
1528 read_rtc:
1529 /* read RTC registers */
1530 err = regmap_bulk_read(ds1307->regmap, ds1307->offset, buf, 8);
1531 if (err) {
1532 dev_dbg(ds1307->dev, "read error %d\n", err);
1533 goto exit;
1534 }
1535
1536 /*
1537 * minimal sanity checking; some chips (like DS1340) don't
1538 * specify the extra bits as must-be-zero, but there are
1539 * still a few values that are clearly out-of-range.
1540 */
1541 tmp = ds1307->regs[DS1307_REG_SECS];
1542 switch (ds1307->type) {
1543 case ds_1307:
1544 case m41t0:
1545 case m41t00:
1546 /* clock halted? turn it on, so clock can tick. */
1547 if (tmp & DS1307_BIT_CH) {
1548 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1549 dev_warn(ds1307->dev, "SET TIME!\n");
1550 goto read_rtc;
1551 }
1552 break;
1553 case ds_1308:
1554 case ds_1338:
1555 /* clock halted? turn it on, so clock can tick. */
1556 if (tmp & DS1307_BIT_CH)
1557 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1558
1559 /* oscillator fault? clear flag, and warn */
1560 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1561 regmap_write(ds1307->regmap, DS1307_REG_CONTROL,
1562 ds1307->regs[DS1307_REG_CONTROL] &
1563 ~DS1338_BIT_OSF);
1564 dev_warn(ds1307->dev, "SET TIME!\n");
1565 goto read_rtc;
1566 }
1567 break;
1568 case ds_1340:
1569 /* clock halted? turn it on, so clock can tick. */
1570 if (tmp & DS1340_BIT_nEOSC)
1571 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1572
1573 err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
1574 if (err) {
1575 dev_dbg(ds1307->dev, "read error %d\n", err);
1576 goto exit;
1577 }
1578
1579 /* oscillator fault? clear flag, and warn */
1580 if (tmp & DS1340_BIT_OSF) {
1581 regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0);
1582 dev_warn(ds1307->dev, "SET TIME!\n");
1583 }
1584 break;
1585 case mcp794xx:
1586 /* make sure that the backup battery is enabled */
1587 if (!(ds1307->regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1588 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1589 ds1307->regs[DS1307_REG_WDAY] |
1590 MCP794XX_BIT_VBATEN);
1591 }
1592
1593 /* clock halted? turn it on, so clock can tick. */
1594 if (!(tmp & MCP794XX_BIT_ST)) {
1595 regmap_write(ds1307->regmap, DS1307_REG_SECS,
1596 MCP794XX_BIT_ST);
1597 dev_warn(ds1307->dev, "SET TIME!\n");
1598 goto read_rtc;
1599 }
1600
1601 break;
1602 default:
1603 break;
1604 }
1605
1606 tmp = ds1307->regs[DS1307_REG_HOUR];
1607 switch (ds1307->type) {
1608 case ds_1340:
1609 case m41t0:
1610 case m41t00:
1611 /*
1612 * NOTE: ignores century bits; fix before deploying
1613 * systems that will run through year 2100.
1614 */
1615 break;
1616 case rx_8025:
1617 break;
1618 default:
1619 if (!(tmp & DS1307_BIT_12HR))
1620 break;
1621
1622 /*
1623 * Be sure we're in 24 hour mode. Multi-master systems
1624 * take note...
1625 */
1626 tmp = bcd2bin(tmp & 0x1f);
1627 if (tmp == 12)
1628 tmp = 0;
1629 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1630 tmp += 12;
1631 regmap_write(ds1307->regmap, ds1307->offset + DS1307_REG_HOUR,
1632 bin2bcd(tmp));
1633 }
1634
1635 /*
1636 * Some IPs have weekday reset value = 0x1 which might not correct
1637 * hence compute the wday using the current date/month/year values
1638 */
1639 ds1307_get_time(ds1307->dev, &tm);
1640 wday = tm.tm_wday;
1641 timestamp = rtc_tm_to_time64(&tm);
1642 rtc_time64_to_tm(timestamp, &tm);
1643
1644 /*
1645 * Check if reset wday is different from the computed wday
1646 * If different then set the wday which we computed using
1647 * timestamp
1648 */
1649 if (wday != tm.tm_wday)
1650 regmap_update_bits(ds1307->regmap, MCP794XX_REG_WEEKDAY,
1651 MCP794XX_REG_WEEKDAY_WDAY_MASK,
1652 tm.tm_wday + 1);
1653
1654 if (want_irq) {
1655 device_set_wakeup_capable(ds1307->dev, true);
1656 set_bit(HAS_ALARM, &ds1307->flags);
1657 }
1658
1659 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1660 if (IS_ERR(ds1307->rtc)) {
1661 return PTR_ERR(ds1307->rtc);
1662 }
1663
1664 if (ds1307_can_wakeup_device && ds1307->irq <= 0) {
1665 /* Disable request for an IRQ */
1666 want_irq = false;
1667 dev_info(ds1307->dev,
1668 "'wakeup-source' is set, request for an IRQ is disabled!\n");
1669 /* We cannot support UIE mode if we do not have an IRQ line */
1670 ds1307->rtc->uie_unsupported = 1;
1671 }
1672
1673 if (want_irq) {
1674 err = devm_request_threaded_irq(ds1307->dev,
1675 ds1307->irq, NULL, irq_handler,
1676 IRQF_SHARED | IRQF_ONESHOT,
1677 ds1307->name, ds1307);
1678 if (err) {
1679 client->irq = 0;
1680 device_set_wakeup_capable(ds1307->dev, false);
1681 clear_bit(HAS_ALARM, &ds1307->flags);
1682 dev_err(ds1307->dev, "unable to request IRQ!\n");
1683 } else
1684 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1685 }
1686
1687 if (chip->nvram_size) {
1688 ds1307->nvmem_cfg.name = "ds1307_nvram";
1689 ds1307->nvmem_cfg.word_size = 1;
1690 ds1307->nvmem_cfg.stride = 1;
1691 ds1307->nvmem_cfg.size = chip->nvram_size;
1692 ds1307->nvmem_cfg.reg_read = ds1307_nvram_read;
1693 ds1307->nvmem_cfg.reg_write = ds1307_nvram_write;
1694 ds1307->nvmem_cfg.priv = ds1307;
1695 ds1307->nvram_offset = chip->nvram_offset;
1696
1697 ds1307->rtc->nvmem_config = &ds1307->nvmem_cfg;
1698 ds1307->rtc->nvram_old_abi = true;
1699 }
1700
1701 ds1307->rtc->ops = rtc_ops;
1702 err = rtc_register_device(ds1307->rtc);
1703 if (err)
1704 return err;
1705
1706 ds1307_hwmon_register(ds1307);
1707 ds1307_clks_register(ds1307);
1708
1709 return 0;
1710
1711 exit:
1712 return err;
1713 }
1714
1715 static struct i2c_driver ds1307_driver = {
1716 .driver = {
1717 .name = "rtc-ds1307",
1718 .of_match_table = of_match_ptr(ds1307_of_match),
1719 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1720 },
1721 .probe = ds1307_probe,
1722 .id_table = ds1307_id,
1723 };
1724
1725 module_i2c_driver(ds1307_driver);
1726
1727 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1728 MODULE_LICENSE("GPL");
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