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[mirror_ubuntu-hirsute-kernel.git] / drivers / rtc / rtc-ds1307.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
4 *
5 * Copyright (C) 2005 James Chapman (ds1337 core)
6 * Copyright (C) 2006 David Brownell
7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
9 */
10
11 #include <linux/bcd.h>
12 #include <linux/i2c.h>
13 #include <linux/init.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/module.h>
16 #include <linux/property.h>
17 #include <linux/rtc/ds1307.h>
18 #include <linux/rtc.h>
19 #include <linux/slab.h>
20 #include <linux/string.h>
21 #include <linux/hwmon.h>
22 #include <linux/hwmon-sysfs.h>
23 #include <linux/clk-provider.h>
24 #include <linux/regmap.h>
25 #include <linux/watchdog.h>
26
27 /*
28 * We can't determine type by probing, but if we expect pre-Linux code
29 * to have set the chip up as a clock (turning on the oscillator and
30 * setting the date and time), Linux can ignore the non-clock features.
31 * That's a natural job for a factory or repair bench.
32 */
33 enum ds_type {
34 unknown_ds_type, /* always first and 0 */
35 ds_1307,
36 ds_1308,
37 ds_1337,
38 ds_1338,
39 ds_1339,
40 ds_1340,
41 ds_1341,
42 ds_1388,
43 ds_3231,
44 m41t0,
45 m41t00,
46 m41t11,
47 mcp794xx,
48 rx_8025,
49 rx_8130,
50 last_ds_type /* always last */
51 /* rs5c372 too? different address... */
52 };
53
54 /* RTC registers don't differ much, except for the century flag */
55 #define DS1307_REG_SECS 0x00 /* 00-59 */
56 # define DS1307_BIT_CH 0x80
57 # define DS1340_BIT_nEOSC 0x80
58 # define MCP794XX_BIT_ST 0x80
59 #define DS1307_REG_MIN 0x01 /* 00-59 */
60 # define M41T0_BIT_OF 0x80
61 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
62 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
63 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
64 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
65 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
66 #define DS1307_REG_WDAY 0x03 /* 01-07 */
67 # define MCP794XX_BIT_VBATEN 0x08
68 #define DS1307_REG_MDAY 0x04 /* 01-31 */
69 #define DS1307_REG_MONTH 0x05 /* 01-12 */
70 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
71 #define DS1307_REG_YEAR 0x06 /* 00-99 */
72
73 /*
74 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
75 * start at 7, and they differ a LOT. Only control and status matter for
76 * basic RTC date and time functionality; be careful using them.
77 */
78 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
79 # define DS1307_BIT_OUT 0x80
80 # define DS1338_BIT_OSF 0x20
81 # define DS1307_BIT_SQWE 0x10
82 # define DS1307_BIT_RS1 0x02
83 # define DS1307_BIT_RS0 0x01
84 #define DS1337_REG_CONTROL 0x0e
85 # define DS1337_BIT_nEOSC 0x80
86 # define DS1339_BIT_BBSQI 0x20
87 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
88 # define DS1337_BIT_RS2 0x10
89 # define DS1337_BIT_RS1 0x08
90 # define DS1337_BIT_INTCN 0x04
91 # define DS1337_BIT_A2IE 0x02
92 # define DS1337_BIT_A1IE 0x01
93 #define DS1340_REG_CONTROL 0x07
94 # define DS1340_BIT_OUT 0x80
95 # define DS1340_BIT_FT 0x40
96 # define DS1340_BIT_CALIB_SIGN 0x20
97 # define DS1340_M_CALIBRATION 0x1f
98 #define DS1340_REG_FLAG 0x09
99 # define DS1340_BIT_OSF 0x80
100 #define DS1337_REG_STATUS 0x0f
101 # define DS1337_BIT_OSF 0x80
102 # define DS3231_BIT_EN32KHZ 0x08
103 # define DS1337_BIT_A2I 0x02
104 # define DS1337_BIT_A1I 0x01
105 #define DS1339_REG_ALARM1_SECS 0x07
106
107 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
108
109 #define RX8025_REG_CTRL1 0x0e
110 # define RX8025_BIT_2412 0x20
111 #define RX8025_REG_CTRL2 0x0f
112 # define RX8025_BIT_PON 0x10
113 # define RX8025_BIT_VDET 0x40
114 # define RX8025_BIT_XST 0x20
115
116 #define RX8130_REG_ALARM_MIN 0x17
117 #define RX8130_REG_ALARM_HOUR 0x18
118 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
119 #define RX8130_REG_EXTENSION 0x1c
120 #define RX8130_REG_EXTENSION_WADA BIT(3)
121 #define RX8130_REG_FLAG 0x1d
122 #define RX8130_REG_FLAG_VLF BIT(1)
123 #define RX8130_REG_FLAG_AF BIT(3)
124 #define RX8130_REG_CONTROL0 0x1e
125 #define RX8130_REG_CONTROL0_AIE BIT(3)
126 #define RX8130_REG_CONTROL1 0x1f
127 #define RX8130_REG_CONTROL1_INIEN BIT(4)
128 #define RX8130_REG_CONTROL1_CHGEN BIT(5)
129
130 #define MCP794XX_REG_CONTROL 0x07
131 # define MCP794XX_BIT_ALM0_EN 0x10
132 # define MCP794XX_BIT_ALM1_EN 0x20
133 #define MCP794XX_REG_ALARM0_BASE 0x0a
134 #define MCP794XX_REG_ALARM0_CTRL 0x0d
135 #define MCP794XX_REG_ALARM1_BASE 0x11
136 #define MCP794XX_REG_ALARM1_CTRL 0x14
137 # define MCP794XX_BIT_ALMX_IF BIT(3)
138 # define MCP794XX_BIT_ALMX_C0 BIT(4)
139 # define MCP794XX_BIT_ALMX_C1 BIT(5)
140 # define MCP794XX_BIT_ALMX_C2 BIT(6)
141 # define MCP794XX_BIT_ALMX_POL BIT(7)
142 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
143 MCP794XX_BIT_ALMX_C1 | \
144 MCP794XX_BIT_ALMX_C2)
145
146 #define M41TXX_REG_CONTROL 0x07
147 # define M41TXX_BIT_OUT BIT(7)
148 # define M41TXX_BIT_FT BIT(6)
149 # define M41TXX_BIT_CALIB_SIGN BIT(5)
150 # define M41TXX_M_CALIBRATION GENMASK(4, 0)
151
152 #define DS1388_REG_WDOG_HUN_SECS 0x08
153 #define DS1388_REG_WDOG_SECS 0x09
154 #define DS1388_REG_FLAG 0x0b
155 # define DS1388_BIT_WF BIT(6)
156 # define DS1388_BIT_OSF BIT(7)
157 #define DS1388_REG_CONTROL 0x0c
158 # define DS1388_BIT_RST BIT(0)
159 # define DS1388_BIT_WDE BIT(1)
160 # define DS1388_BIT_nEOSC BIT(7)
161
162 /* negative offset step is -2.034ppm */
163 #define M41TXX_NEG_OFFSET_STEP_PPB 2034
164 /* positive offset step is +4.068ppm */
165 #define M41TXX_POS_OFFSET_STEP_PPB 4068
166 /* Min and max values supported with 'offset' interface by M41TXX */
167 #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
168 #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
169
170 struct ds1307 {
171 enum ds_type type;
172 unsigned long flags;
173 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
174 #define HAS_ALARM 1 /* bit 1 == irq claimed */
175 struct device *dev;
176 struct regmap *regmap;
177 const char *name;
178 struct rtc_device *rtc;
179 #ifdef CONFIG_COMMON_CLK
180 struct clk_hw clks[2];
181 #endif
182 };
183
184 struct chip_desc {
185 unsigned alarm:1;
186 u16 nvram_offset;
187 u16 nvram_size;
188 u8 offset; /* register's offset */
189 u8 century_reg;
190 u8 century_enable_bit;
191 u8 century_bit;
192 u8 bbsqi_bit;
193 irq_handler_t irq_handler;
194 const struct rtc_class_ops *rtc_ops;
195 u16 trickle_charger_reg;
196 u8 (*do_trickle_setup)(struct ds1307 *, u32,
197 bool);
198 /* Does the RTC require trickle-resistor-ohms to select the value of
199 * the resistor between Vcc and Vbackup?
200 */
201 bool requires_trickle_resistor;
202 /* Some RTC's batteries and supercaps were charged by default, others
203 * allow charging but were not configured previously to do so.
204 * Remember this behavior to stay backwards compatible.
205 */
206 bool charge_default;
207 };
208
209 static const struct chip_desc chips[last_ds_type];
210
211 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
212 {
213 struct ds1307 *ds1307 = dev_get_drvdata(dev);
214 int tmp, ret;
215 const struct chip_desc *chip = &chips[ds1307->type];
216 u8 regs[7];
217
218 if (ds1307->type == rx_8130) {
219 unsigned int regflag;
220 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);
221 if (ret) {
222 dev_err(dev, "%s error %d\n", "read", ret);
223 return ret;
224 }
225
226 if (regflag & RX8130_REG_FLAG_VLF) {
227 dev_warn_once(dev, "oscillator failed, set time!\n");
228 return -EINVAL;
229 }
230 }
231
232 /* read the RTC date and time registers all at once */
233 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
234 sizeof(regs));
235 if (ret) {
236 dev_err(dev, "%s error %d\n", "read", ret);
237 return ret;
238 }
239
240 dev_dbg(dev, "%s: %7ph\n", "read", regs);
241
242 /* if oscillator fail bit is set, no data can be trusted */
243 if (ds1307->type == m41t0 &&
244 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
245 dev_warn_once(dev, "oscillator failed, set time!\n");
246 return -EINVAL;
247 }
248
249 tmp = regs[DS1307_REG_SECS];
250 switch (ds1307->type) {
251 case ds_1307:
252 case m41t0:
253 case m41t00:
254 case m41t11:
255 if (tmp & DS1307_BIT_CH)
256 return -EINVAL;
257 break;
258 case ds_1308:
259 case ds_1338:
260 if (tmp & DS1307_BIT_CH)
261 return -EINVAL;
262
263 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
264 if (ret)
265 return ret;
266 if (tmp & DS1338_BIT_OSF)
267 return -EINVAL;
268 break;
269 case ds_1340:
270 if (tmp & DS1340_BIT_nEOSC)
271 return -EINVAL;
272
273 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
274 if (ret)
275 return ret;
276 if (tmp & DS1340_BIT_OSF)
277 return -EINVAL;
278 break;
279 case ds_1388:
280 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
281 if (ret)
282 return ret;
283 if (tmp & DS1388_BIT_OSF)
284 return -EINVAL;
285 break;
286 case mcp794xx:
287 if (!(tmp & MCP794XX_BIT_ST))
288 return -EINVAL;
289
290 break;
291 default:
292 break;
293 }
294
295 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
296 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
297 tmp = regs[DS1307_REG_HOUR] & 0x3f;
298 t->tm_hour = bcd2bin(tmp);
299 /* rx8130 is bit position, not BCD */
300 if (ds1307->type == rx_8130)
301 t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f);
302 else
303 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
304 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
305 tmp = regs[DS1307_REG_MONTH] & 0x1f;
306 t->tm_mon = bcd2bin(tmp) - 1;
307 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
308
309 if (regs[chip->century_reg] & chip->century_bit &&
310 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
311 t->tm_year += 100;
312
313 dev_dbg(dev, "%s secs=%d, mins=%d, "
314 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
315 "read", t->tm_sec, t->tm_min,
316 t->tm_hour, t->tm_mday,
317 t->tm_mon, t->tm_year, t->tm_wday);
318
319 return 0;
320 }
321
322 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
323 {
324 struct ds1307 *ds1307 = dev_get_drvdata(dev);
325 const struct chip_desc *chip = &chips[ds1307->type];
326 int result;
327 int tmp;
328 u8 regs[7];
329
330 dev_dbg(dev, "%s secs=%d, mins=%d, "
331 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
332 "write", t->tm_sec, t->tm_min,
333 t->tm_hour, t->tm_mday,
334 t->tm_mon, t->tm_year, t->tm_wday);
335
336 if (t->tm_year < 100)
337 return -EINVAL;
338
339 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
340 if (t->tm_year > (chip->century_bit ? 299 : 199))
341 return -EINVAL;
342 #else
343 if (t->tm_year > 199)
344 return -EINVAL;
345 #endif
346
347 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
348 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
349 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
350 /* rx8130 is bit position, not BCD */
351 if (ds1307->type == rx_8130)
352 regs[DS1307_REG_WDAY] = 1 << t->tm_wday;
353 else
354 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
355 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
356 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
357
358 /* assume 20YY not 19YY */
359 tmp = t->tm_year - 100;
360 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
361
362 if (chip->century_enable_bit)
363 regs[chip->century_reg] |= chip->century_enable_bit;
364 if (t->tm_year > 199 && chip->century_bit)
365 regs[chip->century_reg] |= chip->century_bit;
366
367 switch (ds1307->type) {
368 case ds_1308:
369 case ds_1338:
370 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
371 DS1338_BIT_OSF, 0);
372 break;
373 case ds_1340:
374 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
375 DS1340_BIT_OSF, 0);
376 break;
377 case ds_1388:
378 regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
379 DS1388_BIT_OSF, 0);
380 break;
381 case mcp794xx:
382 /*
383 * these bits were cleared when preparing the date/time
384 * values and need to be set again before writing the
385 * regsfer out to the device.
386 */
387 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
388 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
389 break;
390 default:
391 break;
392 }
393
394 dev_dbg(dev, "%s: %7ph\n", "write", regs);
395
396 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
397 sizeof(regs));
398 if (result) {
399 dev_err(dev, "%s error %d\n", "write", result);
400 return result;
401 }
402
403 if (ds1307->type == rx_8130) {
404 /* clear Voltage Loss Flag as data is available now */
405 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
406 ~(u8)RX8130_REG_FLAG_VLF);
407 if (result) {
408 dev_err(dev, "%s error %d\n", "write", result);
409 return result;
410 }
411 }
412
413 return 0;
414 }
415
416 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
417 {
418 struct ds1307 *ds1307 = dev_get_drvdata(dev);
419 int ret;
420 u8 regs[9];
421
422 if (!test_bit(HAS_ALARM, &ds1307->flags))
423 return -EINVAL;
424
425 /* read all ALARM1, ALARM2, and status registers at once */
426 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
427 regs, sizeof(regs));
428 if (ret) {
429 dev_err(dev, "%s error %d\n", "alarm read", ret);
430 return ret;
431 }
432
433 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
434 &regs[0], &regs[4], &regs[7]);
435
436 /*
437 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
438 * and that all four fields are checked matches
439 */
440 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
441 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
442 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
443 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
444
445 /* ... and status */
446 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
447 t->pending = !!(regs[8] & DS1337_BIT_A1I);
448
449 dev_dbg(dev, "%s secs=%d, mins=%d, "
450 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
451 "alarm read", t->time.tm_sec, t->time.tm_min,
452 t->time.tm_hour, t->time.tm_mday,
453 t->enabled, t->pending);
454
455 return 0;
456 }
457
458 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
459 {
460 struct ds1307 *ds1307 = dev_get_drvdata(dev);
461 unsigned char regs[9];
462 u8 control, status;
463 int ret;
464
465 if (!test_bit(HAS_ALARM, &ds1307->flags))
466 return -EINVAL;
467
468 dev_dbg(dev, "%s secs=%d, mins=%d, "
469 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
470 "alarm set", t->time.tm_sec, t->time.tm_min,
471 t->time.tm_hour, t->time.tm_mday,
472 t->enabled, t->pending);
473
474 /* read current status of both alarms and the chip */
475 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
476 sizeof(regs));
477 if (ret) {
478 dev_err(dev, "%s error %d\n", "alarm write", ret);
479 return ret;
480 }
481 control = regs[7];
482 status = regs[8];
483
484 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
485 &regs[0], &regs[4], control, status);
486
487 /* set ALARM1, using 24 hour and day-of-month modes */
488 regs[0] = bin2bcd(t->time.tm_sec);
489 regs[1] = bin2bcd(t->time.tm_min);
490 regs[2] = bin2bcd(t->time.tm_hour);
491 regs[3] = bin2bcd(t->time.tm_mday);
492
493 /* set ALARM2 to non-garbage */
494 regs[4] = 0;
495 regs[5] = 0;
496 regs[6] = 0;
497
498 /* disable alarms */
499 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
500 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
501
502 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
503 sizeof(regs));
504 if (ret) {
505 dev_err(dev, "can't set alarm time\n");
506 return ret;
507 }
508
509 /* optionally enable ALARM1 */
510 if (t->enabled) {
511 dev_dbg(dev, "alarm IRQ armed\n");
512 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
513 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
514 }
515
516 return 0;
517 }
518
519 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
520 {
521 struct ds1307 *ds1307 = dev_get_drvdata(dev);
522
523 if (!test_bit(HAS_ALARM, &ds1307->flags))
524 return -ENOTTY;
525
526 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
527 DS1337_BIT_A1IE,
528 enabled ? DS1337_BIT_A1IE : 0);
529 }
530
531 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
532 {
533 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
534 DS1307_TRICKLE_CHARGER_NO_DIODE;
535
536 setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
537
538 switch (ohms) {
539 case 250:
540 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
541 break;
542 case 2000:
543 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
544 break;
545 case 4000:
546 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
547 break;
548 default:
549 dev_warn(ds1307->dev,
550 "Unsupported ohm value %u in dt\n", ohms);
551 return 0;
552 }
553 return setup;
554 }
555
556 static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode)
557 {
558 /* make sure that the backup battery is enabled */
559 u8 setup = RX8130_REG_CONTROL1_INIEN;
560 if (diode)
561 setup |= RX8130_REG_CONTROL1_CHGEN;
562
563 return setup;
564 }
565
566 static irqreturn_t rx8130_irq(int irq, void *dev_id)
567 {
568 struct ds1307 *ds1307 = dev_id;
569 struct mutex *lock = &ds1307->rtc->ops_lock;
570 u8 ctl[3];
571 int ret;
572
573 mutex_lock(lock);
574
575 /* Read control registers. */
576 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
577 sizeof(ctl));
578 if (ret < 0)
579 goto out;
580 if (!(ctl[1] & RX8130_REG_FLAG_AF))
581 goto out;
582 ctl[1] &= ~RX8130_REG_FLAG_AF;
583 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
584
585 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
586 sizeof(ctl));
587 if (ret < 0)
588 goto out;
589
590 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
591
592 out:
593 mutex_unlock(lock);
594
595 return IRQ_HANDLED;
596 }
597
598 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
599 {
600 struct ds1307 *ds1307 = dev_get_drvdata(dev);
601 u8 ald[3], ctl[3];
602 int ret;
603
604 if (!test_bit(HAS_ALARM, &ds1307->flags))
605 return -EINVAL;
606
607 /* Read alarm registers. */
608 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
609 sizeof(ald));
610 if (ret < 0)
611 return ret;
612
613 /* Read control registers. */
614 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
615 sizeof(ctl));
616 if (ret < 0)
617 return ret;
618
619 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
620 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
621
622 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
623 t->time.tm_sec = -1;
624 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
625 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
626 t->time.tm_wday = -1;
627 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
628 t->time.tm_mon = -1;
629 t->time.tm_year = -1;
630 t->time.tm_yday = -1;
631 t->time.tm_isdst = -1;
632
633 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
634 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
635 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
636
637 return 0;
638 }
639
640 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
641 {
642 struct ds1307 *ds1307 = dev_get_drvdata(dev);
643 u8 ald[3], ctl[3];
644 int ret;
645
646 if (!test_bit(HAS_ALARM, &ds1307->flags))
647 return -EINVAL;
648
649 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
650 "enabled=%d pending=%d\n", __func__,
651 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
652 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
653 t->enabled, t->pending);
654
655 /* Read control registers. */
656 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
657 sizeof(ctl));
658 if (ret < 0)
659 return ret;
660
661 ctl[0] &= RX8130_REG_EXTENSION_WADA;
662 ctl[1] &= ~RX8130_REG_FLAG_AF;
663 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
664
665 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
666 sizeof(ctl));
667 if (ret < 0)
668 return ret;
669
670 /* Hardware alarm precision is 1 minute! */
671 ald[0] = bin2bcd(t->time.tm_min);
672 ald[1] = bin2bcd(t->time.tm_hour);
673 ald[2] = bin2bcd(t->time.tm_mday);
674
675 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
676 sizeof(ald));
677 if (ret < 0)
678 return ret;
679
680 if (!t->enabled)
681 return 0;
682
683 ctl[2] |= RX8130_REG_CONTROL0_AIE;
684
685 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
686 }
687
688 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
689 {
690 struct ds1307 *ds1307 = dev_get_drvdata(dev);
691 int ret, reg;
692
693 if (!test_bit(HAS_ALARM, &ds1307->flags))
694 return -EINVAL;
695
696 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
697 if (ret < 0)
698 return ret;
699
700 if (enabled)
701 reg |= RX8130_REG_CONTROL0_AIE;
702 else
703 reg &= ~RX8130_REG_CONTROL0_AIE;
704
705 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
706 }
707
708 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
709 {
710 struct ds1307 *ds1307 = dev_id;
711 struct mutex *lock = &ds1307->rtc->ops_lock;
712 int reg, ret;
713
714 mutex_lock(lock);
715
716 /* Check and clear alarm 0 interrupt flag. */
717 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
718 if (ret)
719 goto out;
720 if (!(reg & MCP794XX_BIT_ALMX_IF))
721 goto out;
722 reg &= ~MCP794XX_BIT_ALMX_IF;
723 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
724 if (ret)
725 goto out;
726
727 /* Disable alarm 0. */
728 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
729 MCP794XX_BIT_ALM0_EN, 0);
730 if (ret)
731 goto out;
732
733 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
734
735 out:
736 mutex_unlock(lock);
737
738 return IRQ_HANDLED;
739 }
740
741 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
742 {
743 struct ds1307 *ds1307 = dev_get_drvdata(dev);
744 u8 regs[10];
745 int ret;
746
747 if (!test_bit(HAS_ALARM, &ds1307->flags))
748 return -EINVAL;
749
750 /* Read control and alarm 0 registers. */
751 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
752 sizeof(regs));
753 if (ret)
754 return ret;
755
756 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
757
758 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
759 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
760 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
761 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
762 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
763 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
764 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
765 t->time.tm_year = -1;
766 t->time.tm_yday = -1;
767 t->time.tm_isdst = -1;
768
769 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
770 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
771 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
772 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
773 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
774 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
775 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
776
777 return 0;
778 }
779
780 /*
781 * We may have a random RTC weekday, therefore calculate alarm weekday based
782 * on current weekday we read from the RTC timekeeping regs
783 */
784 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
785 {
786 struct rtc_time tm_now;
787 int days_now, days_alarm, ret;
788
789 ret = ds1307_get_time(dev, &tm_now);
790 if (ret)
791 return ret;
792
793 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
794 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
795
796 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
797 }
798
799 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
800 {
801 struct ds1307 *ds1307 = dev_get_drvdata(dev);
802 unsigned char regs[10];
803 int wday, ret;
804
805 if (!test_bit(HAS_ALARM, &ds1307->flags))
806 return -EINVAL;
807
808 wday = mcp794xx_alm_weekday(dev, &t->time);
809 if (wday < 0)
810 return wday;
811
812 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
813 "enabled=%d pending=%d\n", __func__,
814 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
815 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
816 t->enabled, t->pending);
817
818 /* Read control and alarm 0 registers. */
819 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
820 sizeof(regs));
821 if (ret)
822 return ret;
823
824 /* Set alarm 0, using 24-hour and day-of-month modes. */
825 regs[3] = bin2bcd(t->time.tm_sec);
826 regs[4] = bin2bcd(t->time.tm_min);
827 regs[5] = bin2bcd(t->time.tm_hour);
828 regs[6] = wday;
829 regs[7] = bin2bcd(t->time.tm_mday);
830 regs[8] = bin2bcd(t->time.tm_mon + 1);
831
832 /* Clear the alarm 0 interrupt flag. */
833 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
834 /* Set alarm match: second, minute, hour, day, date, month. */
835 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
836 /* Disable interrupt. We will not enable until completely programmed */
837 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
838
839 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
840 sizeof(regs));
841 if (ret)
842 return ret;
843
844 if (!t->enabled)
845 return 0;
846 regs[0] |= MCP794XX_BIT_ALM0_EN;
847 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
848 }
849
850 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
851 {
852 struct ds1307 *ds1307 = dev_get_drvdata(dev);
853
854 if (!test_bit(HAS_ALARM, &ds1307->flags))
855 return -EINVAL;
856
857 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
858 MCP794XX_BIT_ALM0_EN,
859 enabled ? MCP794XX_BIT_ALM0_EN : 0);
860 }
861
862 static int m41txx_rtc_read_offset(struct device *dev, long *offset)
863 {
864 struct ds1307 *ds1307 = dev_get_drvdata(dev);
865 unsigned int ctrl_reg;
866 u8 val;
867
868 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
869
870 val = ctrl_reg & M41TXX_M_CALIBRATION;
871
872 /* check if positive */
873 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
874 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
875 else
876 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
877
878 return 0;
879 }
880
881 static int m41txx_rtc_set_offset(struct device *dev, long offset)
882 {
883 struct ds1307 *ds1307 = dev_get_drvdata(dev);
884 unsigned int ctrl_reg;
885
886 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
887 return -ERANGE;
888
889 if (offset >= 0) {
890 ctrl_reg = DIV_ROUND_CLOSEST(offset,
891 M41TXX_POS_OFFSET_STEP_PPB);
892 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
893 } else {
894 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
895 M41TXX_NEG_OFFSET_STEP_PPB);
896 }
897
898 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
899 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
900 ctrl_reg);
901 }
902
903 #ifdef CONFIG_WATCHDOG_CORE
904 static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
905 {
906 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
907 u8 regs[2];
908 int ret;
909
910 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
911 DS1388_BIT_WF, 0);
912 if (ret)
913 return ret;
914
915 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
916 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
917 if (ret)
918 return ret;
919
920 /*
921 * watchdog timeouts are measured in seconds. So ignore hundredths of
922 * seconds field.
923 */
924 regs[0] = 0;
925 regs[1] = bin2bcd(wdt_dev->timeout);
926
927 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
928 sizeof(regs));
929 if (ret)
930 return ret;
931
932 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
933 DS1388_BIT_WDE | DS1388_BIT_RST,
934 DS1388_BIT_WDE | DS1388_BIT_RST);
935 }
936
937 static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
938 {
939 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
940
941 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
942 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
943 }
944
945 static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
946 {
947 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
948 u8 regs[2];
949
950 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
951 sizeof(regs));
952 }
953
954 static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
955 unsigned int val)
956 {
957 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
958 u8 regs[2];
959
960 wdt_dev->timeout = val;
961 regs[0] = 0;
962 regs[1] = bin2bcd(wdt_dev->timeout);
963
964 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
965 sizeof(regs));
966 }
967 #endif
968
969 static const struct rtc_class_ops rx8130_rtc_ops = {
970 .read_time = ds1307_get_time,
971 .set_time = ds1307_set_time,
972 .read_alarm = rx8130_read_alarm,
973 .set_alarm = rx8130_set_alarm,
974 .alarm_irq_enable = rx8130_alarm_irq_enable,
975 };
976
977 static const struct rtc_class_ops mcp794xx_rtc_ops = {
978 .read_time = ds1307_get_time,
979 .set_time = ds1307_set_time,
980 .read_alarm = mcp794xx_read_alarm,
981 .set_alarm = mcp794xx_set_alarm,
982 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
983 };
984
985 static const struct rtc_class_ops m41txx_rtc_ops = {
986 .read_time = ds1307_get_time,
987 .set_time = ds1307_set_time,
988 .read_alarm = ds1337_read_alarm,
989 .set_alarm = ds1337_set_alarm,
990 .alarm_irq_enable = ds1307_alarm_irq_enable,
991 .read_offset = m41txx_rtc_read_offset,
992 .set_offset = m41txx_rtc_set_offset,
993 };
994
995 static const struct chip_desc chips[last_ds_type] = {
996 [ds_1307] = {
997 .nvram_offset = 8,
998 .nvram_size = 56,
999 },
1000 [ds_1308] = {
1001 .nvram_offset = 8,
1002 .nvram_size = 56,
1003 },
1004 [ds_1337] = {
1005 .alarm = 1,
1006 .century_reg = DS1307_REG_MONTH,
1007 .century_bit = DS1337_BIT_CENTURY,
1008 },
1009 [ds_1338] = {
1010 .nvram_offset = 8,
1011 .nvram_size = 56,
1012 },
1013 [ds_1339] = {
1014 .alarm = 1,
1015 .century_reg = DS1307_REG_MONTH,
1016 .century_bit = DS1337_BIT_CENTURY,
1017 .bbsqi_bit = DS1339_BIT_BBSQI,
1018 .trickle_charger_reg = 0x10,
1019 .do_trickle_setup = &do_trickle_setup_ds1339,
1020 .requires_trickle_resistor = true,
1021 .charge_default = true,
1022 },
1023 [ds_1340] = {
1024 .century_reg = DS1307_REG_HOUR,
1025 .century_enable_bit = DS1340_BIT_CENTURY_EN,
1026 .century_bit = DS1340_BIT_CENTURY,
1027 .do_trickle_setup = &do_trickle_setup_ds1339,
1028 .trickle_charger_reg = 0x08,
1029 .requires_trickle_resistor = true,
1030 .charge_default = true,
1031 },
1032 [ds_1341] = {
1033 .century_reg = DS1307_REG_MONTH,
1034 .century_bit = DS1337_BIT_CENTURY,
1035 },
1036 [ds_1388] = {
1037 .offset = 1,
1038 .trickle_charger_reg = 0x0a,
1039 },
1040 [ds_3231] = {
1041 .alarm = 1,
1042 .century_reg = DS1307_REG_MONTH,
1043 .century_bit = DS1337_BIT_CENTURY,
1044 .bbsqi_bit = DS3231_BIT_BBSQW,
1045 },
1046 [rx_8130] = {
1047 .alarm = 1,
1048 /* this is battery backed SRAM */
1049 .nvram_offset = 0x20,
1050 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
1051 .offset = 0x10,
1052 .irq_handler = rx8130_irq,
1053 .rtc_ops = &rx8130_rtc_ops,
1054 .trickle_charger_reg = RX8130_REG_CONTROL1,
1055 .do_trickle_setup = &do_trickle_setup_rx8130,
1056 },
1057 [m41t0] = {
1058 .rtc_ops = &m41txx_rtc_ops,
1059 },
1060 [m41t00] = {
1061 .rtc_ops = &m41txx_rtc_ops,
1062 },
1063 [m41t11] = {
1064 /* this is battery backed SRAM */
1065 .nvram_offset = 8,
1066 .nvram_size = 56,
1067 .rtc_ops = &m41txx_rtc_ops,
1068 },
1069 [mcp794xx] = {
1070 .alarm = 1,
1071 /* this is battery backed SRAM */
1072 .nvram_offset = 0x20,
1073 .nvram_size = 0x40,
1074 .irq_handler = mcp794xx_irq,
1075 .rtc_ops = &mcp794xx_rtc_ops,
1076 },
1077 };
1078
1079 static const struct i2c_device_id ds1307_id[] = {
1080 { "ds1307", ds_1307 },
1081 { "ds1308", ds_1308 },
1082 { "ds1337", ds_1337 },
1083 { "ds1338", ds_1338 },
1084 { "ds1339", ds_1339 },
1085 { "ds1388", ds_1388 },
1086 { "ds1340", ds_1340 },
1087 { "ds1341", ds_1341 },
1088 { "ds3231", ds_3231 },
1089 { "m41t0", m41t0 },
1090 { "m41t00", m41t00 },
1091 { "m41t11", m41t11 },
1092 { "mcp7940x", mcp794xx },
1093 { "mcp7941x", mcp794xx },
1094 { "pt7c4338", ds_1307 },
1095 { "rx8025", rx_8025 },
1096 { "isl12057", ds_1337 },
1097 { "rx8130", rx_8130 },
1098 { }
1099 };
1100 MODULE_DEVICE_TABLE(i2c, ds1307_id);
1101
1102 static const struct of_device_id ds1307_of_match[] = {
1103 {
1104 .compatible = "dallas,ds1307",
1105 .data = (void *)ds_1307
1106 },
1107 {
1108 .compatible = "dallas,ds1308",
1109 .data = (void *)ds_1308
1110 },
1111 {
1112 .compatible = "dallas,ds1337",
1113 .data = (void *)ds_1337
1114 },
1115 {
1116 .compatible = "dallas,ds1338",
1117 .data = (void *)ds_1338
1118 },
1119 {
1120 .compatible = "dallas,ds1339",
1121 .data = (void *)ds_1339
1122 },
1123 {
1124 .compatible = "dallas,ds1388",
1125 .data = (void *)ds_1388
1126 },
1127 {
1128 .compatible = "dallas,ds1340",
1129 .data = (void *)ds_1340
1130 },
1131 {
1132 .compatible = "dallas,ds1341",
1133 .data = (void *)ds_1341
1134 },
1135 {
1136 .compatible = "maxim,ds3231",
1137 .data = (void *)ds_3231
1138 },
1139 {
1140 .compatible = "st,m41t0",
1141 .data = (void *)m41t0
1142 },
1143 {
1144 .compatible = "st,m41t00",
1145 .data = (void *)m41t00
1146 },
1147 {
1148 .compatible = "st,m41t11",
1149 .data = (void *)m41t11
1150 },
1151 {
1152 .compatible = "microchip,mcp7940x",
1153 .data = (void *)mcp794xx
1154 },
1155 {
1156 .compatible = "microchip,mcp7941x",
1157 .data = (void *)mcp794xx
1158 },
1159 {
1160 .compatible = "pericom,pt7c4338",
1161 .data = (void *)ds_1307
1162 },
1163 {
1164 .compatible = "epson,rx8025",
1165 .data = (void *)rx_8025
1166 },
1167 {
1168 .compatible = "isil,isl12057",
1169 .data = (void *)ds_1337
1170 },
1171 {
1172 .compatible = "epson,rx8130",
1173 .data = (void *)rx_8130
1174 },
1175 { }
1176 };
1177 MODULE_DEVICE_TABLE(of, ds1307_of_match);
1178
1179 /*
1180 * The ds1337 and ds1339 both have two alarms, but we only use the first
1181 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
1182 * signal; ds1339 chips have only one alarm signal.
1183 */
1184 static irqreturn_t ds1307_irq(int irq, void *dev_id)
1185 {
1186 struct ds1307 *ds1307 = dev_id;
1187 struct mutex *lock = &ds1307->rtc->ops_lock;
1188 int stat, ret;
1189
1190 mutex_lock(lock);
1191 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1192 if (ret)
1193 goto out;
1194
1195 if (stat & DS1337_BIT_A1I) {
1196 stat &= ~DS1337_BIT_A1I;
1197 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1198
1199 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1200 DS1337_BIT_A1IE, 0);
1201 if (ret)
1202 goto out;
1203
1204 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1205 }
1206
1207 out:
1208 mutex_unlock(lock);
1209
1210 return IRQ_HANDLED;
1211 }
1212
1213 /*----------------------------------------------------------------------*/
1214
1215 static const struct rtc_class_ops ds13xx_rtc_ops = {
1216 .read_time = ds1307_get_time,
1217 .set_time = ds1307_set_time,
1218 .read_alarm = ds1337_read_alarm,
1219 .set_alarm = ds1337_set_alarm,
1220 .alarm_irq_enable = ds1307_alarm_irq_enable,
1221 };
1222
1223 static ssize_t frequency_test_store(struct device *dev,
1224 struct device_attribute *attr,
1225 const char *buf, size_t count)
1226 {
1227 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1228 bool freq_test_en;
1229 int ret;
1230
1231 ret = kstrtobool(buf, &freq_test_en);
1232 if (ret) {
1233 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1234 return ret;
1235 }
1236
1237 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1238 freq_test_en ? M41TXX_BIT_FT : 0);
1239
1240 return count;
1241 }
1242
1243 static ssize_t frequency_test_show(struct device *dev,
1244 struct device_attribute *attr,
1245 char *buf)
1246 {
1247 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1248 unsigned int ctrl_reg;
1249
1250 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1251
1252 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
1253 "off\n");
1254 }
1255
1256 static DEVICE_ATTR_RW(frequency_test);
1257
1258 static struct attribute *rtc_freq_test_attrs[] = {
1259 &dev_attr_frequency_test.attr,
1260 NULL,
1261 };
1262
1263 static const struct attribute_group rtc_freq_test_attr_group = {
1264 .attrs = rtc_freq_test_attrs,
1265 };
1266
1267 static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1268 {
1269 int err;
1270
1271 switch (ds1307->type) {
1272 case m41t0:
1273 case m41t00:
1274 case m41t11:
1275 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1276 if (err)
1277 return err;
1278 break;
1279 default:
1280 break;
1281 }
1282
1283 return 0;
1284 }
1285
1286 /*----------------------------------------------------------------------*/
1287
1288 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1289 size_t bytes)
1290 {
1291 struct ds1307 *ds1307 = priv;
1292 const struct chip_desc *chip = &chips[ds1307->type];
1293
1294 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
1295 val, bytes);
1296 }
1297
1298 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1299 size_t bytes)
1300 {
1301 struct ds1307 *ds1307 = priv;
1302 const struct chip_desc *chip = &chips[ds1307->type];
1303
1304 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
1305 val, bytes);
1306 }
1307
1308 /*----------------------------------------------------------------------*/
1309
1310 static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1311 const struct chip_desc *chip)
1312 {
1313 u32 ohms, chargeable;
1314 bool diode = chip->charge_default;
1315
1316 if (!chip->do_trickle_setup)
1317 return 0;
1318
1319 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1320 &ohms) && chip->requires_trickle_resistor)
1321 return 0;
1322
1323 /* aux-voltage-chargeable takes precedence over the deprecated
1324 * trickle-diode-disable
1325 */
1326 if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable",
1327 &chargeable)) {
1328 switch (chargeable) {
1329 case 0:
1330 diode = false;
1331 break;
1332 case 1:
1333 diode = true;
1334 break;
1335 default:
1336 dev_warn(ds1307->dev,
1337 "unsupported aux-voltage-chargeable value\n");
1338 break;
1339 }
1340 } else if (device_property_read_bool(ds1307->dev,
1341 "trickle-diode-disable")) {
1342 diode = false;
1343 }
1344
1345 return chip->do_trickle_setup(ds1307, ohms, diode);
1346 }
1347
1348 /*----------------------------------------------------------------------*/
1349
1350 #if IS_REACHABLE(CONFIG_HWMON)
1351
1352 /*
1353 * Temperature sensor support for ds3231 devices.
1354 */
1355
1356 #define DS3231_REG_TEMPERATURE 0x11
1357
1358 /*
1359 * A user-initiated temperature conversion is not started by this function,
1360 * so the temperature is updated once every 64 seconds.
1361 */
1362 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1363 {
1364 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1365 u8 temp_buf[2];
1366 s16 temp;
1367 int ret;
1368
1369 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1370 temp_buf, sizeof(temp_buf));
1371 if (ret)
1372 return ret;
1373 /*
1374 * Temperature is represented as a 10-bit code with a resolution of
1375 * 0.25 degree celsius and encoded in two's complement format.
1376 */
1377 temp = (temp_buf[0] << 8) | temp_buf[1];
1378 temp >>= 6;
1379 *mC = temp * 250;
1380
1381 return 0;
1382 }
1383
1384 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1385 struct device_attribute *attr, char *buf)
1386 {
1387 int ret;
1388 s32 temp;
1389
1390 ret = ds3231_hwmon_read_temp(dev, &temp);
1391 if (ret)
1392 return ret;
1393
1394 return sprintf(buf, "%d\n", temp);
1395 }
1396 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1397 NULL, 0);
1398
1399 static struct attribute *ds3231_hwmon_attrs[] = {
1400 &sensor_dev_attr_temp1_input.dev_attr.attr,
1401 NULL,
1402 };
1403 ATTRIBUTE_GROUPS(ds3231_hwmon);
1404
1405 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1406 {
1407 struct device *dev;
1408
1409 if (ds1307->type != ds_3231)
1410 return;
1411
1412 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1413 ds1307,
1414 ds3231_hwmon_groups);
1415 if (IS_ERR(dev)) {
1416 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1417 PTR_ERR(dev));
1418 }
1419 }
1420
1421 #else
1422
1423 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1424 {
1425 }
1426
1427 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1428
1429 /*----------------------------------------------------------------------*/
1430
1431 /*
1432 * Square-wave output support for DS3231
1433 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1434 */
1435 #ifdef CONFIG_COMMON_CLK
1436
1437 enum {
1438 DS3231_CLK_SQW = 0,
1439 DS3231_CLK_32KHZ,
1440 };
1441
1442 #define clk_sqw_to_ds1307(clk) \
1443 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1444 #define clk_32khz_to_ds1307(clk) \
1445 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1446
1447 static int ds3231_clk_sqw_rates[] = {
1448 1,
1449 1024,
1450 4096,
1451 8192,
1452 };
1453
1454 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1455 {
1456 struct mutex *lock = &ds1307->rtc->ops_lock;
1457 int ret;
1458
1459 mutex_lock(lock);
1460 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1461 mask, value);
1462 mutex_unlock(lock);
1463
1464 return ret;
1465 }
1466
1467 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1468 unsigned long parent_rate)
1469 {
1470 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1471 int control, ret;
1472 int rate_sel = 0;
1473
1474 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1475 if (ret)
1476 return ret;
1477 if (control & DS1337_BIT_RS1)
1478 rate_sel += 1;
1479 if (control & DS1337_BIT_RS2)
1480 rate_sel += 2;
1481
1482 return ds3231_clk_sqw_rates[rate_sel];
1483 }
1484
1485 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1486 unsigned long *prate)
1487 {
1488 int i;
1489
1490 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1491 if (ds3231_clk_sqw_rates[i] <= rate)
1492 return ds3231_clk_sqw_rates[i];
1493 }
1494
1495 return 0;
1496 }
1497
1498 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1499 unsigned long parent_rate)
1500 {
1501 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1502 int control = 0;
1503 int rate_sel;
1504
1505 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1506 rate_sel++) {
1507 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1508 break;
1509 }
1510
1511 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1512 return -EINVAL;
1513
1514 if (rate_sel & 1)
1515 control |= DS1337_BIT_RS1;
1516 if (rate_sel & 2)
1517 control |= DS1337_BIT_RS2;
1518
1519 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1520 control);
1521 }
1522
1523 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1524 {
1525 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1526
1527 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1528 }
1529
1530 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1531 {
1532 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1533
1534 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1535 }
1536
1537 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1538 {
1539 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1540 int control, ret;
1541
1542 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1543 if (ret)
1544 return ret;
1545
1546 return !(control & DS1337_BIT_INTCN);
1547 }
1548
1549 static const struct clk_ops ds3231_clk_sqw_ops = {
1550 .prepare = ds3231_clk_sqw_prepare,
1551 .unprepare = ds3231_clk_sqw_unprepare,
1552 .is_prepared = ds3231_clk_sqw_is_prepared,
1553 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1554 .round_rate = ds3231_clk_sqw_round_rate,
1555 .set_rate = ds3231_clk_sqw_set_rate,
1556 };
1557
1558 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1559 unsigned long parent_rate)
1560 {
1561 return 32768;
1562 }
1563
1564 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1565 {
1566 struct mutex *lock = &ds1307->rtc->ops_lock;
1567 int ret;
1568
1569 mutex_lock(lock);
1570 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1571 DS3231_BIT_EN32KHZ,
1572 enable ? DS3231_BIT_EN32KHZ : 0);
1573 mutex_unlock(lock);
1574
1575 return ret;
1576 }
1577
1578 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1579 {
1580 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1581
1582 return ds3231_clk_32khz_control(ds1307, true);
1583 }
1584
1585 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1586 {
1587 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1588
1589 ds3231_clk_32khz_control(ds1307, false);
1590 }
1591
1592 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1593 {
1594 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1595 int status, ret;
1596
1597 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1598 if (ret)
1599 return ret;
1600
1601 return !!(status & DS3231_BIT_EN32KHZ);
1602 }
1603
1604 static const struct clk_ops ds3231_clk_32khz_ops = {
1605 .prepare = ds3231_clk_32khz_prepare,
1606 .unprepare = ds3231_clk_32khz_unprepare,
1607 .is_prepared = ds3231_clk_32khz_is_prepared,
1608 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1609 };
1610
1611 static const char *ds3231_clks_names[] = {
1612 [DS3231_CLK_SQW] = "ds3231_clk_sqw",
1613 [DS3231_CLK_32KHZ] = "ds3231_clk_32khz",
1614 };
1615
1616 static struct clk_init_data ds3231_clks_init[] = {
1617 [DS3231_CLK_SQW] = {
1618 .ops = &ds3231_clk_sqw_ops,
1619 },
1620 [DS3231_CLK_32KHZ] = {
1621 .ops = &ds3231_clk_32khz_ops,
1622 },
1623 };
1624
1625 static int ds3231_clks_register(struct ds1307 *ds1307)
1626 {
1627 struct device_node *node = ds1307->dev->of_node;
1628 struct clk_onecell_data *onecell;
1629 int i;
1630
1631 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1632 if (!onecell)
1633 return -ENOMEM;
1634
1635 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1636 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1637 sizeof(onecell->clks[0]), GFP_KERNEL);
1638 if (!onecell->clks)
1639 return -ENOMEM;
1640
1641 /* optional override of the clockname */
1642 device_property_read_string_array(ds1307->dev, "clock-output-names",
1643 ds3231_clks_names,
1644 ARRAY_SIZE(ds3231_clks_names));
1645
1646 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1647 struct clk_init_data init = ds3231_clks_init[i];
1648
1649 /*
1650 * Interrupt signal due to alarm conditions and square-wave
1651 * output share same pin, so don't initialize both.
1652 */
1653 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1654 continue;
1655
1656 init.name = ds3231_clks_names[i];
1657 ds1307->clks[i].init = &init;
1658
1659 onecell->clks[i] = devm_clk_register(ds1307->dev,
1660 &ds1307->clks[i]);
1661 if (IS_ERR(onecell->clks[i]))
1662 return PTR_ERR(onecell->clks[i]);
1663 }
1664
1665 if (node)
1666 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1667
1668 return 0;
1669 }
1670
1671 static void ds1307_clks_register(struct ds1307 *ds1307)
1672 {
1673 int ret;
1674
1675 if (ds1307->type != ds_3231)
1676 return;
1677
1678 ret = ds3231_clks_register(ds1307);
1679 if (ret) {
1680 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1681 ret);
1682 }
1683 }
1684
1685 #else
1686
1687 static void ds1307_clks_register(struct ds1307 *ds1307)
1688 {
1689 }
1690
1691 #endif /* CONFIG_COMMON_CLK */
1692
1693 #ifdef CONFIG_WATCHDOG_CORE
1694 static const struct watchdog_info ds1388_wdt_info = {
1695 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
1696 .identity = "DS1388 watchdog",
1697 };
1698
1699 static const struct watchdog_ops ds1388_wdt_ops = {
1700 .owner = THIS_MODULE,
1701 .start = ds1388_wdt_start,
1702 .stop = ds1388_wdt_stop,
1703 .ping = ds1388_wdt_ping,
1704 .set_timeout = ds1388_wdt_set_timeout,
1705
1706 };
1707
1708 static void ds1307_wdt_register(struct ds1307 *ds1307)
1709 {
1710 struct watchdog_device *wdt;
1711 int err;
1712 int val;
1713
1714 if (ds1307->type != ds_1388)
1715 return;
1716
1717 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
1718 if (!wdt)
1719 return;
1720
1721 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
1722 if (!err && val & DS1388_BIT_WF)
1723 wdt->bootstatus = WDIOF_CARDRESET;
1724
1725 wdt->info = &ds1388_wdt_info;
1726 wdt->ops = &ds1388_wdt_ops;
1727 wdt->timeout = 99;
1728 wdt->max_timeout = 99;
1729 wdt->min_timeout = 1;
1730
1731 watchdog_init_timeout(wdt, 0, ds1307->dev);
1732 watchdog_set_drvdata(wdt, ds1307);
1733 devm_watchdog_register_device(ds1307->dev, wdt);
1734 }
1735 #else
1736 static void ds1307_wdt_register(struct ds1307 *ds1307)
1737 {
1738 }
1739 #endif /* CONFIG_WATCHDOG_CORE */
1740
1741 static const struct regmap_config regmap_config = {
1742 .reg_bits = 8,
1743 .val_bits = 8,
1744 };
1745
1746 static int ds1307_probe(struct i2c_client *client,
1747 const struct i2c_device_id *id)
1748 {
1749 struct ds1307 *ds1307;
1750 const void *match;
1751 int err = -ENODEV;
1752 int tmp;
1753 const struct chip_desc *chip;
1754 bool want_irq;
1755 bool ds1307_can_wakeup_device = false;
1756 unsigned char regs[8];
1757 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1758 u8 trickle_charger_setup = 0;
1759
1760 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1761 if (!ds1307)
1762 return -ENOMEM;
1763
1764 dev_set_drvdata(&client->dev, ds1307);
1765 ds1307->dev = &client->dev;
1766 ds1307->name = client->name;
1767
1768 ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1769 if (IS_ERR(ds1307->regmap)) {
1770 dev_err(ds1307->dev, "regmap allocation failed\n");
1771 return PTR_ERR(ds1307->regmap);
1772 }
1773
1774 i2c_set_clientdata(client, ds1307);
1775
1776 match = device_get_match_data(&client->dev);
1777 if (match) {
1778 ds1307->type = (enum ds_type)match;
1779 chip = &chips[ds1307->type];
1780 } else if (id) {
1781 chip = &chips[id->driver_data];
1782 ds1307->type = id->driver_data;
1783 } else {
1784 return -ENODEV;
1785 }
1786
1787 want_irq = client->irq > 0 && chip->alarm;
1788
1789 if (!pdata)
1790 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1791 else if (pdata->trickle_charger_setup)
1792 trickle_charger_setup = pdata->trickle_charger_setup;
1793
1794 if (trickle_charger_setup && chip->trickle_charger_reg) {
1795 dev_dbg(ds1307->dev,
1796 "writing trickle charger info 0x%x to 0x%x\n",
1797 trickle_charger_setup, chip->trickle_charger_reg);
1798 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1799 trickle_charger_setup);
1800 }
1801
1802 /*
1803 * For devices with no IRQ directly connected to the SoC, the RTC chip
1804 * can be forced as a wakeup source by stating that explicitly in
1805 * the device's .dts file using the "wakeup-source" boolean property.
1806 * If the "wakeup-source" property is set, don't request an IRQ.
1807 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1808 * if supported by the RTC.
1809 */
1810 if (chip->alarm && device_property_read_bool(&client->dev, "wakeup-source"))
1811 ds1307_can_wakeup_device = true;
1812
1813 switch (ds1307->type) {
1814 case ds_1337:
1815 case ds_1339:
1816 case ds_1341:
1817 case ds_3231:
1818 /* get registers that the "rtc" read below won't read... */
1819 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1820 regs, 2);
1821 if (err) {
1822 dev_dbg(ds1307->dev, "read error %d\n", err);
1823 goto exit;
1824 }
1825
1826 /* oscillator off? turn it on, so clock can tick. */
1827 if (regs[0] & DS1337_BIT_nEOSC)
1828 regs[0] &= ~DS1337_BIT_nEOSC;
1829
1830 /*
1831 * Using IRQ or defined as wakeup-source?
1832 * Disable the square wave and both alarms.
1833 * For some variants, be sure alarms can trigger when we're
1834 * running on Vbackup (BBSQI/BBSQW)
1835 */
1836 if (want_irq || ds1307_can_wakeup_device) {
1837 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1838 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1839 }
1840
1841 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1842 regs[0]);
1843
1844 /* oscillator fault? clear flag, and warn */
1845 if (regs[1] & DS1337_BIT_OSF) {
1846 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1847 regs[1] & ~DS1337_BIT_OSF);
1848 dev_warn(ds1307->dev, "SET TIME!\n");
1849 }
1850 break;
1851
1852 case rx_8025:
1853 err = regmap_bulk_read(ds1307->regmap,
1854 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1855 if (err) {
1856 dev_dbg(ds1307->dev, "read error %d\n", err);
1857 goto exit;
1858 }
1859
1860 /* oscillator off? turn it on, so clock can tick. */
1861 if (!(regs[1] & RX8025_BIT_XST)) {
1862 regs[1] |= RX8025_BIT_XST;
1863 regmap_write(ds1307->regmap,
1864 RX8025_REG_CTRL2 << 4 | 0x08,
1865 regs[1]);
1866 dev_warn(ds1307->dev,
1867 "oscillator stop detected - SET TIME!\n");
1868 }
1869
1870 if (regs[1] & RX8025_BIT_PON) {
1871 regs[1] &= ~RX8025_BIT_PON;
1872 regmap_write(ds1307->regmap,
1873 RX8025_REG_CTRL2 << 4 | 0x08,
1874 regs[1]);
1875 dev_warn(ds1307->dev, "power-on detected\n");
1876 }
1877
1878 if (regs[1] & RX8025_BIT_VDET) {
1879 regs[1] &= ~RX8025_BIT_VDET;
1880 regmap_write(ds1307->regmap,
1881 RX8025_REG_CTRL2 << 4 | 0x08,
1882 regs[1]);
1883 dev_warn(ds1307->dev, "voltage drop detected\n");
1884 }
1885
1886 /* make sure we are running in 24hour mode */
1887 if (!(regs[0] & RX8025_BIT_2412)) {
1888 u8 hour;
1889
1890 /* switch to 24 hour mode */
1891 regmap_write(ds1307->regmap,
1892 RX8025_REG_CTRL1 << 4 | 0x08,
1893 regs[0] | RX8025_BIT_2412);
1894
1895 err = regmap_bulk_read(ds1307->regmap,
1896 RX8025_REG_CTRL1 << 4 | 0x08,
1897 regs, 2);
1898 if (err) {
1899 dev_dbg(ds1307->dev, "read error %d\n", err);
1900 goto exit;
1901 }
1902
1903 /* correct hour */
1904 hour = bcd2bin(regs[DS1307_REG_HOUR]);
1905 if (hour == 12)
1906 hour = 0;
1907 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1908 hour += 12;
1909
1910 regmap_write(ds1307->regmap,
1911 DS1307_REG_HOUR << 4 | 0x08, hour);
1912 }
1913 break;
1914 case ds_1388:
1915 err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp);
1916 if (err) {
1917 dev_dbg(ds1307->dev, "read error %d\n", err);
1918 goto exit;
1919 }
1920
1921 /* oscillator off? turn it on, so clock can tick. */
1922 if (tmp & DS1388_BIT_nEOSC) {
1923 tmp &= ~DS1388_BIT_nEOSC;
1924 regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp);
1925 }
1926 break;
1927 default:
1928 break;
1929 }
1930
1931 /* read RTC registers */
1932 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1933 sizeof(regs));
1934 if (err) {
1935 dev_dbg(ds1307->dev, "read error %d\n", err);
1936 goto exit;
1937 }
1938
1939 if (ds1307->type == mcp794xx &&
1940 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1941 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1942 regs[DS1307_REG_WDAY] |
1943 MCP794XX_BIT_VBATEN);
1944 }
1945
1946 tmp = regs[DS1307_REG_HOUR];
1947 switch (ds1307->type) {
1948 case ds_1340:
1949 case m41t0:
1950 case m41t00:
1951 case m41t11:
1952 /*
1953 * NOTE: ignores century bits; fix before deploying
1954 * systems that will run through year 2100.
1955 */
1956 break;
1957 case rx_8025:
1958 break;
1959 default:
1960 if (!(tmp & DS1307_BIT_12HR))
1961 break;
1962
1963 /*
1964 * Be sure we're in 24 hour mode. Multi-master systems
1965 * take note...
1966 */
1967 tmp = bcd2bin(tmp & 0x1f);
1968 if (tmp == 12)
1969 tmp = 0;
1970 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1971 tmp += 12;
1972 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1973 bin2bcd(tmp));
1974 }
1975
1976 if (want_irq || ds1307_can_wakeup_device) {
1977 device_set_wakeup_capable(ds1307->dev, true);
1978 set_bit(HAS_ALARM, &ds1307->flags);
1979 }
1980
1981 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1982 if (IS_ERR(ds1307->rtc))
1983 return PTR_ERR(ds1307->rtc);
1984
1985 if (ds1307_can_wakeup_device && !want_irq) {
1986 dev_info(ds1307->dev,
1987 "'wakeup-source' is set, request for an IRQ is disabled!\n");
1988 /* We cannot support UIE mode if we do not have an IRQ line */
1989 ds1307->rtc->uie_unsupported = 1;
1990 }
1991
1992 if (want_irq) {
1993 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1994 chip->irq_handler ?: ds1307_irq,
1995 IRQF_SHARED | IRQF_ONESHOT,
1996 ds1307->name, ds1307);
1997 if (err) {
1998 client->irq = 0;
1999 device_set_wakeup_capable(ds1307->dev, false);
2000 clear_bit(HAS_ALARM, &ds1307->flags);
2001 dev_err(ds1307->dev, "unable to request IRQ!\n");
2002 } else {
2003 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
2004 }
2005 }
2006
2007 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
2008 err = ds1307_add_frequency_test(ds1307);
2009 if (err)
2010 return err;
2011
2012 err = devm_rtc_register_device(ds1307->rtc);
2013 if (err)
2014 return err;
2015
2016 if (chip->nvram_size) {
2017 struct nvmem_config nvmem_cfg = {
2018 .name = "ds1307_nvram",
2019 .word_size = 1,
2020 .stride = 1,
2021 .size = chip->nvram_size,
2022 .reg_read = ds1307_nvram_read,
2023 .reg_write = ds1307_nvram_write,
2024 .priv = ds1307,
2025 };
2026
2027 devm_rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
2028 }
2029
2030 ds1307_hwmon_register(ds1307);
2031 ds1307_clks_register(ds1307);
2032 ds1307_wdt_register(ds1307);
2033
2034 return 0;
2035
2036 exit:
2037 return err;
2038 }
2039
2040 static struct i2c_driver ds1307_driver = {
2041 .driver = {
2042 .name = "rtc-ds1307",
2043 .of_match_table = ds1307_of_match,
2044 },
2045 .probe = ds1307_probe,
2046 .id_table = ds1307_id,
2047 };
2048
2049 module_i2c_driver(ds1307_driver);
2050
2051 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
2052 MODULE_LICENSE("GPL");
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