2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
7 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/bcd.h>
15 #include <linux/i2c.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/rtc/ds1307.h>
19 #include <linux/rtc.h>
20 #include <linux/slab.h>
21 #include <linux/string.h>
22 #include <linux/hwmon.h>
23 #include <linux/hwmon-sysfs.h>
24 #include <linux/clk-provider.h>
27 * We can't determine type by probing, but if we expect pre-Linux code
28 * to have set the chip up as a clock (turning on the oscillator and
29 * setting the date and time), Linux can ignore the non-clock features.
30 * That's a natural job for a factory or repair bench.
43 last_ds_type
/* always last */
44 /* rs5c372 too? different address... */
48 /* RTC registers don't differ much, except for the century flag */
49 #define DS1307_REG_SECS 0x00 /* 00-59 */
50 # define DS1307_BIT_CH 0x80
51 # define DS1340_BIT_nEOSC 0x80
52 # define MCP794XX_BIT_ST 0x80
53 #define DS1307_REG_MIN 0x01 /* 00-59 */
54 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
55 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
56 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
57 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
58 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
59 #define DS1307_REG_WDAY 0x03 /* 01-07 */
60 # define MCP794XX_BIT_VBATEN 0x08
61 #define DS1307_REG_MDAY 0x04 /* 01-31 */
62 #define DS1307_REG_MONTH 0x05 /* 01-12 */
63 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
64 #define DS1307_REG_YEAR 0x06 /* 00-99 */
67 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
68 * start at 7, and they differ a LOT. Only control and status matter for
69 * basic RTC date and time functionality; be careful using them.
71 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
72 # define DS1307_BIT_OUT 0x80
73 # define DS1338_BIT_OSF 0x20
74 # define DS1307_BIT_SQWE 0x10
75 # define DS1307_BIT_RS1 0x02
76 # define DS1307_BIT_RS0 0x01
77 #define DS1337_REG_CONTROL 0x0e
78 # define DS1337_BIT_nEOSC 0x80
79 # define DS1339_BIT_BBSQI 0x20
80 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
81 # define DS1337_BIT_RS2 0x10
82 # define DS1337_BIT_RS1 0x08
83 # define DS1337_BIT_INTCN 0x04
84 # define DS1337_BIT_A2IE 0x02
85 # define DS1337_BIT_A1IE 0x01
86 #define DS1340_REG_CONTROL 0x07
87 # define DS1340_BIT_OUT 0x80
88 # define DS1340_BIT_FT 0x40
89 # define DS1340_BIT_CALIB_SIGN 0x20
90 # define DS1340_M_CALIBRATION 0x1f
91 #define DS1340_REG_FLAG 0x09
92 # define DS1340_BIT_OSF 0x80
93 #define DS1337_REG_STATUS 0x0f
94 # define DS1337_BIT_OSF 0x80
95 # define DS3231_BIT_EN32KHZ 0x08
96 # define DS1337_BIT_A2I 0x02
97 # define DS1337_BIT_A1I 0x01
98 #define DS1339_REG_ALARM1_SECS 0x07
100 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
102 #define RX8025_REG_CTRL1 0x0e
103 # define RX8025_BIT_2412 0x20
104 #define RX8025_REG_CTRL2 0x0f
105 # define RX8025_BIT_PON 0x10
106 # define RX8025_BIT_VDET 0x40
107 # define RX8025_BIT_XST 0x20
111 u8 offset
; /* register's offset */
114 struct bin_attribute
*nvram
;
117 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
118 #define HAS_ALARM 1 /* bit 1 == irq claimed */
119 struct i2c_client
*client
;
120 struct rtc_device
*rtc
;
121 s32 (*read_block_data
)(const struct i2c_client
*client
, u8 command
,
122 u8 length
, u8
*values
);
123 s32 (*write_block_data
)(const struct i2c_client
*client
, u8 command
,
124 u8 length
, const u8
*values
);
125 #ifdef CONFIG_COMMON_CLK
126 struct clk_hw clks
[2];
134 u16 trickle_charger_reg
;
135 u8 trickle_charger_setup
;
136 u8 (*do_trickle_setup
)(struct i2c_client
*, uint32_t, bool);
139 static u8
do_trickle_setup_ds1339(struct i2c_client
*,
140 uint32_t ohms
, bool diode
);
142 static struct chip_desc chips
[last_ds_type
] = {
156 .trickle_charger_reg
= 0x10,
157 .do_trickle_setup
= &do_trickle_setup_ds1339
,
160 .trickle_charger_reg
= 0x08,
163 .trickle_charger_reg
= 0x0a,
170 /* this is battery backed SRAM */
171 .nvram_offset
= 0x20,
176 static const struct i2c_device_id ds1307_id
[] = {
177 { "ds1307", ds_1307
},
178 { "ds1337", ds_1337
},
179 { "ds1338", ds_1338
},
180 { "ds1339", ds_1339
},
181 { "ds1388", ds_1388
},
182 { "ds1340", ds_1340
},
183 { "ds3231", ds_3231
},
184 { "m41t00", m41t00
},
185 { "mcp7940x", mcp794xx
},
186 { "mcp7941x", mcp794xx
},
187 { "pt7c4338", ds_1307
},
188 { "rx8025", rx_8025
},
191 MODULE_DEVICE_TABLE(i2c
, ds1307_id
);
193 /*----------------------------------------------------------------------*/
195 #define BLOCK_DATA_MAX_TRIES 10
197 static s32
ds1307_read_block_data_once(const struct i2c_client
*client
,
198 u8 command
, u8 length
, u8
*values
)
202 for (i
= 0; i
< length
; i
++) {
203 data
= i2c_smbus_read_byte_data(client
, command
+ i
);
211 static s32
ds1307_read_block_data(const struct i2c_client
*client
, u8 command
,
212 u8 length
, u8
*values
)
218 dev_dbg(&client
->dev
, "ds1307_read_block_data (length=%d)\n", length
);
219 ret
= ds1307_read_block_data_once(client
, command
, length
, values
);
223 if (++tries
> BLOCK_DATA_MAX_TRIES
) {
224 dev_err(&client
->dev
,
225 "ds1307_read_block_data failed\n");
228 memcpy(oldvalues
, values
, length
);
229 ret
= ds1307_read_block_data_once(client
, command
, length
,
233 } while (memcmp(oldvalues
, values
, length
));
237 static s32
ds1307_write_block_data(const struct i2c_client
*client
, u8 command
,
238 u8 length
, const u8
*values
)
243 dev_dbg(&client
->dev
, "ds1307_write_block_data (length=%d)\n", length
);
247 if (++tries
> BLOCK_DATA_MAX_TRIES
) {
248 dev_err(&client
->dev
,
249 "ds1307_write_block_data failed\n");
252 for (i
= 0; i
< length
; i
++) {
253 ret
= i2c_smbus_write_byte_data(client
, command
+ i
,
258 ret
= ds1307_read_block_data_once(client
, command
, length
,
262 } while (memcmp(currvalues
, values
, length
));
266 /*----------------------------------------------------------------------*/
268 /* These RTC devices are not designed to be connected to a SMbus adapter.
269 SMbus limits block operations length to 32 bytes, whereas it's not
270 limited on I2C buses. As a result, accesses may exceed 32 bytes;
271 in that case, split them into smaller blocks */
273 static s32
ds1307_native_smbus_write_block_data(const struct i2c_client
*client
,
274 u8 command
, u8 length
, const u8
*values
)
278 if (length
<= I2C_SMBUS_BLOCK_MAX
)
279 return i2c_smbus_write_i2c_block_data(client
,
280 command
, length
, values
);
282 while (suboffset
< length
) {
283 s32 retval
= i2c_smbus_write_i2c_block_data(client
,
285 min(I2C_SMBUS_BLOCK_MAX
, length
- suboffset
),
290 suboffset
+= I2C_SMBUS_BLOCK_MAX
;
295 static s32
ds1307_native_smbus_read_block_data(const struct i2c_client
*client
,
296 u8 command
, u8 length
, u8
*values
)
300 if (length
<= I2C_SMBUS_BLOCK_MAX
)
301 return i2c_smbus_read_i2c_block_data(client
,
302 command
, length
, values
);
304 while (suboffset
< length
) {
305 s32 retval
= i2c_smbus_read_i2c_block_data(client
,
307 min(I2C_SMBUS_BLOCK_MAX
, length
- suboffset
),
312 suboffset
+= I2C_SMBUS_BLOCK_MAX
;
317 /*----------------------------------------------------------------------*/
320 * The ds1337 and ds1339 both have two alarms, but we only use the first
321 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
322 * signal; ds1339 chips have only one alarm signal.
324 static irqreturn_t
ds1307_irq(int irq
, void *dev_id
)
326 struct i2c_client
*client
= dev_id
;
327 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
328 struct mutex
*lock
= &ds1307
->rtc
->ops_lock
;
332 stat
= i2c_smbus_read_byte_data(client
, DS1337_REG_STATUS
);
336 if (stat
& DS1337_BIT_A1I
) {
337 stat
&= ~DS1337_BIT_A1I
;
338 i2c_smbus_write_byte_data(client
, DS1337_REG_STATUS
, stat
);
340 control
= i2c_smbus_read_byte_data(client
, DS1337_REG_CONTROL
);
344 control
&= ~DS1337_BIT_A1IE
;
345 i2c_smbus_write_byte_data(client
, DS1337_REG_CONTROL
, control
);
347 rtc_update_irq(ds1307
->rtc
, 1, RTC_AF
| RTC_IRQF
);
356 /*----------------------------------------------------------------------*/
358 static int ds1307_get_time(struct device
*dev
, struct rtc_time
*t
)
360 struct ds1307
*ds1307
= dev_get_drvdata(dev
);
363 /* read the RTC date and time registers all at once */
364 tmp
= ds1307
->read_block_data(ds1307
->client
,
365 ds1307
->offset
, 7, ds1307
->regs
);
367 dev_err(dev
, "%s error %d\n", "read", tmp
);
371 dev_dbg(dev
, "%s: %7ph\n", "read", ds1307
->regs
);
373 t
->tm_sec
= bcd2bin(ds1307
->regs
[DS1307_REG_SECS
] & 0x7f);
374 t
->tm_min
= bcd2bin(ds1307
->regs
[DS1307_REG_MIN
] & 0x7f);
375 tmp
= ds1307
->regs
[DS1307_REG_HOUR
] & 0x3f;
376 t
->tm_hour
= bcd2bin(tmp
);
377 t
->tm_wday
= bcd2bin(ds1307
->regs
[DS1307_REG_WDAY
] & 0x07) - 1;
378 t
->tm_mday
= bcd2bin(ds1307
->regs
[DS1307_REG_MDAY
] & 0x3f);
379 tmp
= ds1307
->regs
[DS1307_REG_MONTH
] & 0x1f;
380 t
->tm_mon
= bcd2bin(tmp
) - 1;
382 /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
383 t
->tm_year
= bcd2bin(ds1307
->regs
[DS1307_REG_YEAR
]) + 100;
385 dev_dbg(dev
, "%s secs=%d, mins=%d, "
386 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
387 "read", t
->tm_sec
, t
->tm_min
,
388 t
->tm_hour
, t
->tm_mday
,
389 t
->tm_mon
, t
->tm_year
, t
->tm_wday
);
391 /* initial clock setting can be undefined */
392 return rtc_valid_tm(t
);
395 static int ds1307_set_time(struct device
*dev
, struct rtc_time
*t
)
397 struct ds1307
*ds1307
= dev_get_drvdata(dev
);
400 u8
*buf
= ds1307
->regs
;
402 dev_dbg(dev
, "%s secs=%d, mins=%d, "
403 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
404 "write", t
->tm_sec
, t
->tm_min
,
405 t
->tm_hour
, t
->tm_mday
,
406 t
->tm_mon
, t
->tm_year
, t
->tm_wday
);
408 buf
[DS1307_REG_SECS
] = bin2bcd(t
->tm_sec
);
409 buf
[DS1307_REG_MIN
] = bin2bcd(t
->tm_min
);
410 buf
[DS1307_REG_HOUR
] = bin2bcd(t
->tm_hour
);
411 buf
[DS1307_REG_WDAY
] = bin2bcd(t
->tm_wday
+ 1);
412 buf
[DS1307_REG_MDAY
] = bin2bcd(t
->tm_mday
);
413 buf
[DS1307_REG_MONTH
] = bin2bcd(t
->tm_mon
+ 1);
415 /* assume 20YY not 19YY */
416 tmp
= t
->tm_year
- 100;
417 buf
[DS1307_REG_YEAR
] = bin2bcd(tmp
);
419 switch (ds1307
->type
) {
423 buf
[DS1307_REG_MONTH
] |= DS1337_BIT_CENTURY
;
426 buf
[DS1307_REG_HOUR
] |= DS1340_BIT_CENTURY_EN
427 | DS1340_BIT_CENTURY
;
431 * these bits were cleared when preparing the date/time
432 * values and need to be set again before writing the
433 * buffer out to the device.
435 buf
[DS1307_REG_SECS
] |= MCP794XX_BIT_ST
;
436 buf
[DS1307_REG_WDAY
] |= MCP794XX_BIT_VBATEN
;
442 dev_dbg(dev
, "%s: %7ph\n", "write", buf
);
444 result
= ds1307
->write_block_data(ds1307
->client
,
445 ds1307
->offset
, 7, buf
);
447 dev_err(dev
, "%s error %d\n", "write", result
);
453 static int ds1337_read_alarm(struct device
*dev
, struct rtc_wkalrm
*t
)
455 struct i2c_client
*client
= to_i2c_client(dev
);
456 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
459 if (!test_bit(HAS_ALARM
, &ds1307
->flags
))
462 /* read all ALARM1, ALARM2, and status registers at once */
463 ret
= ds1307
->read_block_data(client
,
464 DS1339_REG_ALARM1_SECS
, 9, ds1307
->regs
);
466 dev_err(dev
, "%s error %d\n", "alarm read", ret
);
470 dev_dbg(dev
, "%s: %4ph, %3ph, %2ph\n", "alarm read",
471 &ds1307
->regs
[0], &ds1307
->regs
[4], &ds1307
->regs
[7]);
474 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
475 * and that all four fields are checked matches
477 t
->time
.tm_sec
= bcd2bin(ds1307
->regs
[0] & 0x7f);
478 t
->time
.tm_min
= bcd2bin(ds1307
->regs
[1] & 0x7f);
479 t
->time
.tm_hour
= bcd2bin(ds1307
->regs
[2] & 0x3f);
480 t
->time
.tm_mday
= bcd2bin(ds1307
->regs
[3] & 0x3f);
482 t
->time
.tm_year
= -1;
483 t
->time
.tm_wday
= -1;
484 t
->time
.tm_yday
= -1;
485 t
->time
.tm_isdst
= -1;
488 t
->enabled
= !!(ds1307
->regs
[7] & DS1337_BIT_A1IE
);
489 t
->pending
= !!(ds1307
->regs
[8] & DS1337_BIT_A1I
);
491 dev_dbg(dev
, "%s secs=%d, mins=%d, "
492 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
493 "alarm read", t
->time
.tm_sec
, t
->time
.tm_min
,
494 t
->time
.tm_hour
, t
->time
.tm_mday
,
495 t
->enabled
, t
->pending
);
500 static int ds1337_set_alarm(struct device
*dev
, struct rtc_wkalrm
*t
)
502 struct i2c_client
*client
= to_i2c_client(dev
);
503 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
504 unsigned char *buf
= ds1307
->regs
;
508 if (!test_bit(HAS_ALARM
, &ds1307
->flags
))
511 dev_dbg(dev
, "%s secs=%d, mins=%d, "
512 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
513 "alarm set", t
->time
.tm_sec
, t
->time
.tm_min
,
514 t
->time
.tm_hour
, t
->time
.tm_mday
,
515 t
->enabled
, t
->pending
);
517 /* read current status of both alarms and the chip */
518 ret
= ds1307
->read_block_data(client
,
519 DS1339_REG_ALARM1_SECS
, 9, buf
);
521 dev_err(dev
, "%s error %d\n", "alarm write", ret
);
524 control
= ds1307
->regs
[7];
525 status
= ds1307
->regs
[8];
527 dev_dbg(dev
, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
528 &ds1307
->regs
[0], &ds1307
->regs
[4], control
, status
);
530 /* set ALARM1, using 24 hour and day-of-month modes */
531 buf
[0] = bin2bcd(t
->time
.tm_sec
);
532 buf
[1] = bin2bcd(t
->time
.tm_min
);
533 buf
[2] = bin2bcd(t
->time
.tm_hour
);
534 buf
[3] = bin2bcd(t
->time
.tm_mday
);
536 /* set ALARM2 to non-garbage */
541 /* optionally enable ALARM1 */
542 buf
[7] = control
& ~(DS1337_BIT_A1IE
| DS1337_BIT_A2IE
);
544 dev_dbg(dev
, "alarm IRQ armed\n");
545 buf
[7] |= DS1337_BIT_A1IE
; /* only ALARM1 is used */
547 buf
[8] = status
& ~(DS1337_BIT_A1I
| DS1337_BIT_A2I
);
549 ret
= ds1307
->write_block_data(client
,
550 DS1339_REG_ALARM1_SECS
, 9, buf
);
552 dev_err(dev
, "can't set alarm time\n");
559 static int ds1307_alarm_irq_enable(struct device
*dev
, unsigned int enabled
)
561 struct i2c_client
*client
= to_i2c_client(dev
);
562 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
565 if (!test_bit(HAS_ALARM
, &ds1307
->flags
))
568 ret
= i2c_smbus_read_byte_data(client
, DS1337_REG_CONTROL
);
573 ret
|= DS1337_BIT_A1IE
;
575 ret
&= ~DS1337_BIT_A1IE
;
577 ret
= i2c_smbus_write_byte_data(client
, DS1337_REG_CONTROL
, ret
);
584 static const struct rtc_class_ops ds13xx_rtc_ops
= {
585 .read_time
= ds1307_get_time
,
586 .set_time
= ds1307_set_time
,
587 .read_alarm
= ds1337_read_alarm
,
588 .set_alarm
= ds1337_set_alarm
,
589 .alarm_irq_enable
= ds1307_alarm_irq_enable
,
592 /*----------------------------------------------------------------------*/
595 * Alarm support for mcp794xx devices.
598 #define MCP794XX_REG_CONTROL 0x07
599 # define MCP794XX_BIT_ALM0_EN 0x10
600 # define MCP794XX_BIT_ALM1_EN 0x20
601 #define MCP794XX_REG_ALARM0_BASE 0x0a
602 #define MCP794XX_REG_ALARM0_CTRL 0x0d
603 #define MCP794XX_REG_ALARM1_BASE 0x11
604 #define MCP794XX_REG_ALARM1_CTRL 0x14
605 # define MCP794XX_BIT_ALMX_IF (1 << 3)
606 # define MCP794XX_BIT_ALMX_C0 (1 << 4)
607 # define MCP794XX_BIT_ALMX_C1 (1 << 5)
608 # define MCP794XX_BIT_ALMX_C2 (1 << 6)
609 # define MCP794XX_BIT_ALMX_POL (1 << 7)
610 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
611 MCP794XX_BIT_ALMX_C1 | \
612 MCP794XX_BIT_ALMX_C2)
614 static irqreturn_t
mcp794xx_irq(int irq
, void *dev_id
)
616 struct i2c_client
*client
= dev_id
;
617 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
618 struct mutex
*lock
= &ds1307
->rtc
->ops_lock
;
623 /* Check and clear alarm 0 interrupt flag. */
624 reg
= i2c_smbus_read_byte_data(client
, MCP794XX_REG_ALARM0_CTRL
);
627 if (!(reg
& MCP794XX_BIT_ALMX_IF
))
629 reg
&= ~MCP794XX_BIT_ALMX_IF
;
630 ret
= i2c_smbus_write_byte_data(client
, MCP794XX_REG_ALARM0_CTRL
, reg
);
634 /* Disable alarm 0. */
635 reg
= i2c_smbus_read_byte_data(client
, MCP794XX_REG_CONTROL
);
638 reg
&= ~MCP794XX_BIT_ALM0_EN
;
639 ret
= i2c_smbus_write_byte_data(client
, MCP794XX_REG_CONTROL
, reg
);
643 rtc_update_irq(ds1307
->rtc
, 1, RTC_AF
| RTC_IRQF
);
651 static int mcp794xx_read_alarm(struct device
*dev
, struct rtc_wkalrm
*t
)
653 struct i2c_client
*client
= to_i2c_client(dev
);
654 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
655 u8
*regs
= ds1307
->regs
;
658 if (!test_bit(HAS_ALARM
, &ds1307
->flags
))
661 /* Read control and alarm 0 registers. */
662 ret
= ds1307
->read_block_data(client
, MCP794XX_REG_CONTROL
, 10, regs
);
666 t
->enabled
= !!(regs
[0] & MCP794XX_BIT_ALM0_EN
);
668 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
669 t
->time
.tm_sec
= bcd2bin(ds1307
->regs
[3] & 0x7f);
670 t
->time
.tm_min
= bcd2bin(ds1307
->regs
[4] & 0x7f);
671 t
->time
.tm_hour
= bcd2bin(ds1307
->regs
[5] & 0x3f);
672 t
->time
.tm_wday
= bcd2bin(ds1307
->regs
[6] & 0x7) - 1;
673 t
->time
.tm_mday
= bcd2bin(ds1307
->regs
[7] & 0x3f);
674 t
->time
.tm_mon
= bcd2bin(ds1307
->regs
[8] & 0x1f) - 1;
675 t
->time
.tm_year
= -1;
676 t
->time
.tm_yday
= -1;
677 t
->time
.tm_isdst
= -1;
679 dev_dbg(dev
, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
680 "enabled=%d polarity=%d irq=%d match=%d\n", __func__
,
681 t
->time
.tm_sec
, t
->time
.tm_min
, t
->time
.tm_hour
,
682 t
->time
.tm_wday
, t
->time
.tm_mday
, t
->time
.tm_mon
, t
->enabled
,
683 !!(ds1307
->regs
[6] & MCP794XX_BIT_ALMX_POL
),
684 !!(ds1307
->regs
[6] & MCP794XX_BIT_ALMX_IF
),
685 (ds1307
->regs
[6] & MCP794XX_MSK_ALMX_MATCH
) >> 4);
690 static int mcp794xx_set_alarm(struct device
*dev
, struct rtc_wkalrm
*t
)
692 struct i2c_client
*client
= to_i2c_client(dev
);
693 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
694 unsigned char *regs
= ds1307
->regs
;
697 if (!test_bit(HAS_ALARM
, &ds1307
->flags
))
700 dev_dbg(dev
, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
701 "enabled=%d pending=%d\n", __func__
,
702 t
->time
.tm_sec
, t
->time
.tm_min
, t
->time
.tm_hour
,
703 t
->time
.tm_wday
, t
->time
.tm_mday
, t
->time
.tm_mon
,
704 t
->enabled
, t
->pending
);
706 /* Read control and alarm 0 registers. */
707 ret
= ds1307
->read_block_data(client
, MCP794XX_REG_CONTROL
, 10, regs
);
711 /* Set alarm 0, using 24-hour and day-of-month modes. */
712 regs
[3] = bin2bcd(t
->time
.tm_sec
);
713 regs
[4] = bin2bcd(t
->time
.tm_min
);
714 regs
[5] = bin2bcd(t
->time
.tm_hour
);
715 regs
[6] = bin2bcd(t
->time
.tm_wday
+ 1);
716 regs
[7] = bin2bcd(t
->time
.tm_mday
);
717 regs
[8] = bin2bcd(t
->time
.tm_mon
+ 1);
719 /* Clear the alarm 0 interrupt flag. */
720 regs
[6] &= ~MCP794XX_BIT_ALMX_IF
;
721 /* Set alarm match: second, minute, hour, day, date, month. */
722 regs
[6] |= MCP794XX_MSK_ALMX_MATCH
;
723 /* Disable interrupt. We will not enable until completely programmed */
724 regs
[0] &= ~MCP794XX_BIT_ALM0_EN
;
726 ret
= ds1307
->write_block_data(client
, MCP794XX_REG_CONTROL
, 10, regs
);
732 regs
[0] |= MCP794XX_BIT_ALM0_EN
;
733 return i2c_smbus_write_byte_data(client
, MCP794XX_REG_CONTROL
, regs
[0]);
736 static int mcp794xx_alarm_irq_enable(struct device
*dev
, unsigned int enabled
)
738 struct i2c_client
*client
= to_i2c_client(dev
);
739 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
742 if (!test_bit(HAS_ALARM
, &ds1307
->flags
))
745 reg
= i2c_smbus_read_byte_data(client
, MCP794XX_REG_CONTROL
);
750 reg
|= MCP794XX_BIT_ALM0_EN
;
752 reg
&= ~MCP794XX_BIT_ALM0_EN
;
754 return i2c_smbus_write_byte_data(client
, MCP794XX_REG_CONTROL
, reg
);
757 static const struct rtc_class_ops mcp794xx_rtc_ops
= {
758 .read_time
= ds1307_get_time
,
759 .set_time
= ds1307_set_time
,
760 .read_alarm
= mcp794xx_read_alarm
,
761 .set_alarm
= mcp794xx_set_alarm
,
762 .alarm_irq_enable
= mcp794xx_alarm_irq_enable
,
765 /*----------------------------------------------------------------------*/
768 ds1307_nvram_read(struct file
*filp
, struct kobject
*kobj
,
769 struct bin_attribute
*attr
,
770 char *buf
, loff_t off
, size_t count
)
772 struct i2c_client
*client
;
773 struct ds1307
*ds1307
;
776 client
= kobj_to_i2c_client(kobj
);
777 ds1307
= i2c_get_clientdata(client
);
779 result
= ds1307
->read_block_data(client
, ds1307
->nvram_offset
+ off
,
782 dev_err(&client
->dev
, "%s error %d\n", "nvram read", result
);
787 ds1307_nvram_write(struct file
*filp
, struct kobject
*kobj
,
788 struct bin_attribute
*attr
,
789 char *buf
, loff_t off
, size_t count
)
791 struct i2c_client
*client
;
792 struct ds1307
*ds1307
;
795 client
= kobj_to_i2c_client(kobj
);
796 ds1307
= i2c_get_clientdata(client
);
798 result
= ds1307
->write_block_data(client
, ds1307
->nvram_offset
+ off
,
801 dev_err(&client
->dev
, "%s error %d\n", "nvram write", result
);
808 /*----------------------------------------------------------------------*/
810 static u8
do_trickle_setup_ds1339(struct i2c_client
*client
,
811 uint32_t ohms
, bool diode
)
813 u8 setup
= (diode
) ? DS1307_TRICKLE_CHARGER_DIODE
:
814 DS1307_TRICKLE_CHARGER_NO_DIODE
;
818 setup
|= DS1307_TRICKLE_CHARGER_250_OHM
;
821 setup
|= DS1307_TRICKLE_CHARGER_2K_OHM
;
824 setup
|= DS1307_TRICKLE_CHARGER_4K_OHM
;
827 dev_warn(&client
->dev
,
828 "Unsupported ohm value %u in dt\n", ohms
);
834 static void ds1307_trickle_of_init(struct i2c_client
*client
,
835 struct chip_desc
*chip
)
840 if (!chip
->do_trickle_setup
)
842 if (of_property_read_u32(client
->dev
.of_node
, "trickle-resistor-ohms" , &ohms
))
844 if (of_property_read_bool(client
->dev
.of_node
, "trickle-diode-disable"))
846 chip
->trickle_charger_setup
= chip
->do_trickle_setup(client
,
852 /*----------------------------------------------------------------------*/
854 #ifdef CONFIG_RTC_DRV_DS1307_HWMON
857 * Temperature sensor support for ds3231 devices.
860 #define DS3231_REG_TEMPERATURE 0x11
863 * A user-initiated temperature conversion is not started by this function,
864 * so the temperature is updated once every 64 seconds.
866 static int ds3231_hwmon_read_temp(struct device
*dev
, s32
*mC
)
868 struct ds1307
*ds1307
= dev_get_drvdata(dev
);
873 ret
= ds1307
->read_block_data(ds1307
->client
, DS3231_REG_TEMPERATURE
,
874 sizeof(temp_buf
), temp_buf
);
877 if (ret
!= sizeof(temp_buf
))
881 * Temperature is represented as a 10-bit code with a resolution of
882 * 0.25 degree celsius and encoded in two's complement format.
884 temp
= (temp_buf
[0] << 8) | temp_buf
[1];
891 static ssize_t
ds3231_hwmon_show_temp(struct device
*dev
,
892 struct device_attribute
*attr
, char *buf
)
897 ret
= ds3231_hwmon_read_temp(dev
, &temp
);
901 return sprintf(buf
, "%d\n", temp
);
903 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, ds3231_hwmon_show_temp
,
906 static struct attribute
*ds3231_hwmon_attrs
[] = {
907 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
910 ATTRIBUTE_GROUPS(ds3231_hwmon
);
912 static void ds1307_hwmon_register(struct ds1307
*ds1307
)
916 if (ds1307
->type
!= ds_3231
)
919 dev
= devm_hwmon_device_register_with_groups(&ds1307
->client
->dev
,
920 ds1307
->client
->name
,
921 ds1307
, ds3231_hwmon_groups
);
923 dev_warn(&ds1307
->client
->dev
,
924 "unable to register hwmon device %ld\n", PTR_ERR(dev
));
930 static void ds1307_hwmon_register(struct ds1307
*ds1307
)
934 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
936 /*----------------------------------------------------------------------*/
939 * Square-wave output support for DS3231
940 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
942 #ifdef CONFIG_COMMON_CLK
949 #define clk_sqw_to_ds1307(clk) \
950 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
951 #define clk_32khz_to_ds1307(clk) \
952 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
954 static int ds3231_clk_sqw_rates
[] = {
961 static int ds1337_write_control(struct ds1307
*ds1307
, u8 mask
, u8 value
)
963 struct i2c_client
*client
= ds1307
->client
;
964 struct mutex
*lock
= &ds1307
->rtc
->ops_lock
;
970 control
= i2c_smbus_read_byte_data(client
, DS1337_REG_CONTROL
);
979 ret
= i2c_smbus_write_byte_data(client
, DS1337_REG_CONTROL
, control
);
986 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw
*hw
,
987 unsigned long parent_rate
)
989 struct ds1307
*ds1307
= clk_sqw_to_ds1307(hw
);
993 control
= i2c_smbus_read_byte_data(ds1307
->client
, DS1337_REG_CONTROL
);
996 if (control
& DS1337_BIT_RS1
)
998 if (control
& DS1337_BIT_RS2
)
1001 return ds3231_clk_sqw_rates
[rate_sel
];
1004 static long ds3231_clk_sqw_round_rate(struct clk_hw
*hw
, unsigned long rate
,
1005 unsigned long *prate
)
1009 for (i
= ARRAY_SIZE(ds3231_clk_sqw_rates
) - 1; i
>= 0; i
--) {
1010 if (ds3231_clk_sqw_rates
[i
] <= rate
)
1011 return ds3231_clk_sqw_rates
[i
];
1017 static int ds3231_clk_sqw_set_rate(struct clk_hw
*hw
, unsigned long rate
,
1018 unsigned long parent_rate
)
1020 struct ds1307
*ds1307
= clk_sqw_to_ds1307(hw
);
1024 for (rate_sel
= 0; rate_sel
< ARRAY_SIZE(ds3231_clk_sqw_rates
);
1026 if (ds3231_clk_sqw_rates
[rate_sel
] == rate
)
1030 if (rate_sel
== ARRAY_SIZE(ds3231_clk_sqw_rates
))
1034 control
|= DS1337_BIT_RS1
;
1036 control
|= DS1337_BIT_RS2
;
1038 return ds1337_write_control(ds1307
, DS1337_BIT_RS1
| DS1337_BIT_RS2
,
1042 static int ds3231_clk_sqw_prepare(struct clk_hw
*hw
)
1044 struct ds1307
*ds1307
= clk_sqw_to_ds1307(hw
);
1046 return ds1337_write_control(ds1307
, DS1337_BIT_INTCN
, 0);
1049 static void ds3231_clk_sqw_unprepare(struct clk_hw
*hw
)
1051 struct ds1307
*ds1307
= clk_sqw_to_ds1307(hw
);
1053 ds1337_write_control(ds1307
, DS1337_BIT_INTCN
, DS1337_BIT_INTCN
);
1056 static int ds3231_clk_sqw_is_prepared(struct clk_hw
*hw
)
1058 struct ds1307
*ds1307
= clk_sqw_to_ds1307(hw
);
1061 control
= i2c_smbus_read_byte_data(ds1307
->client
, DS1337_REG_CONTROL
);
1065 return !(control
& DS1337_BIT_INTCN
);
1068 static const struct clk_ops ds3231_clk_sqw_ops
= {
1069 .prepare
= ds3231_clk_sqw_prepare
,
1070 .unprepare
= ds3231_clk_sqw_unprepare
,
1071 .is_prepared
= ds3231_clk_sqw_is_prepared
,
1072 .recalc_rate
= ds3231_clk_sqw_recalc_rate
,
1073 .round_rate
= ds3231_clk_sqw_round_rate
,
1074 .set_rate
= ds3231_clk_sqw_set_rate
,
1077 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw
*hw
,
1078 unsigned long parent_rate
)
1083 static int ds3231_clk_32khz_control(struct ds1307
*ds1307
, bool enable
)
1085 struct i2c_client
*client
= ds1307
->client
;
1086 struct mutex
*lock
= &ds1307
->rtc
->ops_lock
;
1092 status
= i2c_smbus_read_byte_data(client
, DS1337_REG_STATUS
);
1099 status
|= DS3231_BIT_EN32KHZ
;
1101 status
&= ~DS3231_BIT_EN32KHZ
;
1103 ret
= i2c_smbus_write_byte_data(client
, DS1337_REG_STATUS
, status
);
1110 static int ds3231_clk_32khz_prepare(struct clk_hw
*hw
)
1112 struct ds1307
*ds1307
= clk_32khz_to_ds1307(hw
);
1114 return ds3231_clk_32khz_control(ds1307
, true);
1117 static void ds3231_clk_32khz_unprepare(struct clk_hw
*hw
)
1119 struct ds1307
*ds1307
= clk_32khz_to_ds1307(hw
);
1121 ds3231_clk_32khz_control(ds1307
, false);
1124 static int ds3231_clk_32khz_is_prepared(struct clk_hw
*hw
)
1126 struct ds1307
*ds1307
= clk_32khz_to_ds1307(hw
);
1129 status
= i2c_smbus_read_byte_data(ds1307
->client
, DS1337_REG_STATUS
);
1133 return !!(status
& DS3231_BIT_EN32KHZ
);
1136 static const struct clk_ops ds3231_clk_32khz_ops
= {
1137 .prepare
= ds3231_clk_32khz_prepare
,
1138 .unprepare
= ds3231_clk_32khz_unprepare
,
1139 .is_prepared
= ds3231_clk_32khz_is_prepared
,
1140 .recalc_rate
= ds3231_clk_32khz_recalc_rate
,
1143 static struct clk_init_data ds3231_clks_init
[] = {
1144 [DS3231_CLK_SQW
] = {
1145 .name
= "ds3231_clk_sqw",
1146 .ops
= &ds3231_clk_sqw_ops
,
1147 .flags
= CLK_IS_ROOT
,
1149 [DS3231_CLK_32KHZ
] = {
1150 .name
= "ds3231_clk_32khz",
1151 .ops
= &ds3231_clk_32khz_ops
,
1152 .flags
= CLK_IS_ROOT
,
1156 static int ds3231_clks_register(struct ds1307
*ds1307
)
1158 struct i2c_client
*client
= ds1307
->client
;
1159 struct device_node
*node
= client
->dev
.of_node
;
1160 struct clk_onecell_data
*onecell
;
1163 onecell
= devm_kzalloc(&client
->dev
, sizeof(*onecell
), GFP_KERNEL
);
1167 onecell
->clk_num
= ARRAY_SIZE(ds3231_clks_init
);
1168 onecell
->clks
= devm_kcalloc(&client
->dev
, onecell
->clk_num
,
1169 sizeof(onecell
->clks
[0]), GFP_KERNEL
);
1173 for (i
= 0; i
< ARRAY_SIZE(ds3231_clks_init
); i
++) {
1174 struct clk_init_data init
= ds3231_clks_init
[i
];
1177 * Interrupt signal due to alarm conditions and square-wave
1178 * output share same pin, so don't initialize both.
1180 if (i
== DS3231_CLK_SQW
&& test_bit(HAS_ALARM
, &ds1307
->flags
))
1183 /* optional override of the clockname */
1184 of_property_read_string_index(node
, "clock-output-names", i
,
1186 ds1307
->clks
[i
].init
= &init
;
1188 onecell
->clks
[i
] = devm_clk_register(&client
->dev
,
1190 if (IS_ERR(onecell
->clks
[i
]))
1191 return PTR_ERR(onecell
->clks
[i
]);
1197 of_clk_add_provider(node
, of_clk_src_onecell_get
, onecell
);
1202 static void ds1307_clks_register(struct ds1307
*ds1307
)
1206 if (ds1307
->type
!= ds_3231
)
1209 ret
= ds3231_clks_register(ds1307
);
1211 dev_warn(&ds1307
->client
->dev
,
1212 "unable to register clock device %d\n", ret
);
1218 static void ds1307_clks_register(struct ds1307
*ds1307
)
1222 #endif /* CONFIG_COMMON_CLK */
1224 static int ds1307_probe(struct i2c_client
*client
,
1225 const struct i2c_device_id
*id
)
1227 struct ds1307
*ds1307
;
1230 struct chip_desc
*chip
= &chips
[id
->driver_data
];
1231 struct i2c_adapter
*adapter
= to_i2c_adapter(client
->dev
.parent
);
1232 bool want_irq
= false;
1233 bool ds1307_can_wakeup_device
= false;
1235 struct ds1307_platform_data
*pdata
= dev_get_platdata(&client
->dev
);
1236 irq_handler_t irq_handler
= ds1307_irq
;
1238 static const int bbsqi_bitpos
[] = {
1240 [ds_1339
] = DS1339_BIT_BBSQI
,
1241 [ds_3231
] = DS3231_BIT_BBSQW
,
1243 const struct rtc_class_ops
*rtc_ops
= &ds13xx_rtc_ops
;
1245 if (!i2c_check_functionality(adapter
, I2C_FUNC_SMBUS_BYTE_DATA
)
1246 && !i2c_check_functionality(adapter
, I2C_FUNC_SMBUS_I2C_BLOCK
))
1249 ds1307
= devm_kzalloc(&client
->dev
, sizeof(struct ds1307
), GFP_KERNEL
);
1253 i2c_set_clientdata(client
, ds1307
);
1255 ds1307
->client
= client
;
1256 ds1307
->type
= id
->driver_data
;
1258 if (!pdata
&& client
->dev
.of_node
)
1259 ds1307_trickle_of_init(client
, chip
);
1260 else if (pdata
&& pdata
->trickle_charger_setup
)
1261 chip
->trickle_charger_setup
= pdata
->trickle_charger_setup
;
1263 if (chip
->trickle_charger_setup
&& chip
->trickle_charger_reg
) {
1264 dev_dbg(&client
->dev
, "writing trickle charger info 0x%x to 0x%x\n",
1265 DS13XX_TRICKLE_CHARGER_MAGIC
| chip
->trickle_charger_setup
,
1266 chip
->trickle_charger_reg
);
1267 i2c_smbus_write_byte_data(client
, chip
->trickle_charger_reg
,
1268 DS13XX_TRICKLE_CHARGER_MAGIC
|
1269 chip
->trickle_charger_setup
);
1273 if (i2c_check_functionality(adapter
, I2C_FUNC_SMBUS_I2C_BLOCK
)) {
1274 ds1307
->read_block_data
= ds1307_native_smbus_read_block_data
;
1275 ds1307
->write_block_data
= ds1307_native_smbus_write_block_data
;
1277 ds1307
->read_block_data
= ds1307_read_block_data
;
1278 ds1307
->write_block_data
= ds1307_write_block_data
;
1283 * For devices with no IRQ directly connected to the SoC, the RTC chip
1284 * can be forced as a wakeup source by stating that explicitly in
1285 * the device's .dts file using the "wakeup-source" boolean property.
1286 * If the "wakeup-source" property is set, don't request an IRQ.
1287 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1288 * if supported by the RTC.
1290 if (of_property_read_bool(client
->dev
.of_node
, "wakeup-source")) {
1291 ds1307_can_wakeup_device
= true;
1295 switch (ds1307
->type
) {
1299 /* get registers that the "rtc" read below won't read... */
1300 tmp
= ds1307
->read_block_data(ds1307
->client
,
1301 DS1337_REG_CONTROL
, 2, buf
);
1303 dev_dbg(&client
->dev
, "read error %d\n", tmp
);
1308 /* oscillator off? turn it on, so clock can tick. */
1309 if (ds1307
->regs
[0] & DS1337_BIT_nEOSC
)
1310 ds1307
->regs
[0] &= ~DS1337_BIT_nEOSC
;
1313 * Using IRQ or defined as wakeup-source?
1314 * Disable the square wave and both alarms.
1315 * For some variants, be sure alarms can trigger when we're
1316 * running on Vbackup (BBSQI/BBSQW)
1318 if (chip
->alarm
&& (ds1307
->client
->irq
> 0 ||
1319 ds1307_can_wakeup_device
)) {
1320 ds1307
->regs
[0] |= DS1337_BIT_INTCN
1321 | bbsqi_bitpos
[ds1307
->type
];
1322 ds1307
->regs
[0] &= ~(DS1337_BIT_A2IE
| DS1337_BIT_A1IE
);
1327 i2c_smbus_write_byte_data(client
, DS1337_REG_CONTROL
,
1330 /* oscillator fault? clear flag, and warn */
1331 if (ds1307
->regs
[1] & DS1337_BIT_OSF
) {
1332 i2c_smbus_write_byte_data(client
, DS1337_REG_STATUS
,
1333 ds1307
->regs
[1] & ~DS1337_BIT_OSF
);
1334 dev_warn(&client
->dev
, "SET TIME!\n");
1339 tmp
= i2c_smbus_read_i2c_block_data(ds1307
->client
,
1340 RX8025_REG_CTRL1
<< 4 | 0x08, 2, buf
);
1342 dev_dbg(&client
->dev
, "read error %d\n", tmp
);
1347 /* oscillator off? turn it on, so clock can tick. */
1348 if (!(ds1307
->regs
[1] & RX8025_BIT_XST
)) {
1349 ds1307
->regs
[1] |= RX8025_BIT_XST
;
1350 i2c_smbus_write_byte_data(client
,
1351 RX8025_REG_CTRL2
<< 4 | 0x08,
1353 dev_warn(&client
->dev
,
1354 "oscillator stop detected - SET TIME!\n");
1357 if (ds1307
->regs
[1] & RX8025_BIT_PON
) {
1358 ds1307
->regs
[1] &= ~RX8025_BIT_PON
;
1359 i2c_smbus_write_byte_data(client
,
1360 RX8025_REG_CTRL2
<< 4 | 0x08,
1362 dev_warn(&client
->dev
, "power-on detected\n");
1365 if (ds1307
->regs
[1] & RX8025_BIT_VDET
) {
1366 ds1307
->regs
[1] &= ~RX8025_BIT_VDET
;
1367 i2c_smbus_write_byte_data(client
,
1368 RX8025_REG_CTRL2
<< 4 | 0x08,
1370 dev_warn(&client
->dev
, "voltage drop detected\n");
1373 /* make sure we are running in 24hour mode */
1374 if (!(ds1307
->regs
[0] & RX8025_BIT_2412
)) {
1377 /* switch to 24 hour mode */
1378 i2c_smbus_write_byte_data(client
,
1379 RX8025_REG_CTRL1
<< 4 | 0x08,
1383 tmp
= i2c_smbus_read_i2c_block_data(ds1307
->client
,
1384 RX8025_REG_CTRL1
<< 4 | 0x08, 2, buf
);
1386 dev_dbg(&client
->dev
, "read error %d\n", tmp
);
1392 hour
= bcd2bin(ds1307
->regs
[DS1307_REG_HOUR
]);
1395 if (ds1307
->regs
[DS1307_REG_HOUR
] & DS1307_BIT_PM
)
1398 i2c_smbus_write_byte_data(client
,
1399 DS1307_REG_HOUR
<< 4 | 0x08,
1404 ds1307
->offset
= 1; /* Seconds starts at 1 */
1407 rtc_ops
= &mcp794xx_rtc_ops
;
1408 if (ds1307
->client
->irq
> 0 && chip
->alarm
) {
1409 irq_handler
= mcp794xx_irq
;
1418 /* read RTC registers */
1419 tmp
= ds1307
->read_block_data(ds1307
->client
, ds1307
->offset
, 8, buf
);
1421 dev_dbg(&client
->dev
, "read error %d\n", tmp
);
1427 * minimal sanity checking; some chips (like DS1340) don't
1428 * specify the extra bits as must-be-zero, but there are
1429 * still a few values that are clearly out-of-range.
1431 tmp
= ds1307
->regs
[DS1307_REG_SECS
];
1432 switch (ds1307
->type
) {
1435 /* clock halted? turn it on, so clock can tick. */
1436 if (tmp
& DS1307_BIT_CH
) {
1437 i2c_smbus_write_byte_data(client
, DS1307_REG_SECS
, 0);
1438 dev_warn(&client
->dev
, "SET TIME!\n");
1443 /* clock halted? turn it on, so clock can tick. */
1444 if (tmp
& DS1307_BIT_CH
)
1445 i2c_smbus_write_byte_data(client
, DS1307_REG_SECS
, 0);
1447 /* oscillator fault? clear flag, and warn */
1448 if (ds1307
->regs
[DS1307_REG_CONTROL
] & DS1338_BIT_OSF
) {
1449 i2c_smbus_write_byte_data(client
, DS1307_REG_CONTROL
,
1450 ds1307
->regs
[DS1307_REG_CONTROL
]
1452 dev_warn(&client
->dev
, "SET TIME!\n");
1457 /* clock halted? turn it on, so clock can tick. */
1458 if (tmp
& DS1340_BIT_nEOSC
)
1459 i2c_smbus_write_byte_data(client
, DS1307_REG_SECS
, 0);
1461 tmp
= i2c_smbus_read_byte_data(client
, DS1340_REG_FLAG
);
1463 dev_dbg(&client
->dev
, "read error %d\n", tmp
);
1468 /* oscillator fault? clear flag, and warn */
1469 if (tmp
& DS1340_BIT_OSF
) {
1470 i2c_smbus_write_byte_data(client
, DS1340_REG_FLAG
, 0);
1471 dev_warn(&client
->dev
, "SET TIME!\n");
1475 /* make sure that the backup battery is enabled */
1476 if (!(ds1307
->regs
[DS1307_REG_WDAY
] & MCP794XX_BIT_VBATEN
)) {
1477 i2c_smbus_write_byte_data(client
, DS1307_REG_WDAY
,
1478 ds1307
->regs
[DS1307_REG_WDAY
]
1479 | MCP794XX_BIT_VBATEN
);
1482 /* clock halted? turn it on, so clock can tick. */
1483 if (!(tmp
& MCP794XX_BIT_ST
)) {
1484 i2c_smbus_write_byte_data(client
, DS1307_REG_SECS
,
1486 dev_warn(&client
->dev
, "SET TIME!\n");
1495 tmp
= ds1307
->regs
[DS1307_REG_HOUR
];
1496 switch (ds1307
->type
) {
1500 * NOTE: ignores century bits; fix before deploying
1501 * systems that will run through year 2100.
1507 if (!(tmp
& DS1307_BIT_12HR
))
1511 * Be sure we're in 24 hour mode. Multi-master systems
1514 tmp
= bcd2bin(tmp
& 0x1f);
1517 if (ds1307
->regs
[DS1307_REG_HOUR
] & DS1307_BIT_PM
)
1519 i2c_smbus_write_byte_data(client
,
1520 ds1307
->offset
+ DS1307_REG_HOUR
,
1525 device_set_wakeup_capable(&client
->dev
, true);
1526 set_bit(HAS_ALARM
, &ds1307
->flags
);
1528 ds1307
->rtc
= devm_rtc_device_register(&client
->dev
, client
->name
,
1529 rtc_ops
, THIS_MODULE
);
1530 if (IS_ERR(ds1307
->rtc
)) {
1531 return PTR_ERR(ds1307
->rtc
);
1534 if (ds1307_can_wakeup_device
) {
1535 /* Disable request for an IRQ */
1537 dev_info(&client
->dev
, "'wakeup-source' is set, request for an IRQ is disabled!\n");
1538 /* We cannot support UIE mode if we do not have an IRQ line */
1539 ds1307
->rtc
->uie_unsupported
= 1;
1543 err
= devm_request_threaded_irq(&client
->dev
,
1544 client
->irq
, NULL
, irq_handler
,
1545 IRQF_SHARED
| IRQF_ONESHOT
,
1546 ds1307
->rtc
->name
, client
);
1549 device_set_wakeup_capable(&client
->dev
, false);
1550 clear_bit(HAS_ALARM
, &ds1307
->flags
);
1551 dev_err(&client
->dev
, "unable to request IRQ!\n");
1553 dev_dbg(&client
->dev
, "got IRQ %d\n", client
->irq
);
1556 if (chip
->nvram_size
) {
1558 ds1307
->nvram
= devm_kzalloc(&client
->dev
,
1559 sizeof(struct bin_attribute
),
1561 if (!ds1307
->nvram
) {
1562 dev_err(&client
->dev
, "cannot allocate memory for nvram sysfs\n");
1565 ds1307
->nvram
->attr
.name
= "nvram";
1566 ds1307
->nvram
->attr
.mode
= S_IRUGO
| S_IWUSR
;
1568 sysfs_bin_attr_init(ds1307
->nvram
);
1570 ds1307
->nvram
->read
= ds1307_nvram_read
;
1571 ds1307
->nvram
->write
= ds1307_nvram_write
;
1572 ds1307
->nvram
->size
= chip
->nvram_size
;
1573 ds1307
->nvram_offset
= chip
->nvram_offset
;
1575 err
= sysfs_create_bin_file(&client
->dev
.kobj
,
1578 dev_err(&client
->dev
,
1579 "unable to create sysfs file: %s\n",
1580 ds1307
->nvram
->attr
.name
);
1582 set_bit(HAS_NVRAM
, &ds1307
->flags
);
1583 dev_info(&client
->dev
, "%zu bytes nvram\n",
1584 ds1307
->nvram
->size
);
1589 ds1307_hwmon_register(ds1307
);
1590 ds1307_clks_register(ds1307
);
1598 static int ds1307_remove(struct i2c_client
*client
)
1600 struct ds1307
*ds1307
= i2c_get_clientdata(client
);
1602 if (test_and_clear_bit(HAS_NVRAM
, &ds1307
->flags
))
1603 sysfs_remove_bin_file(&client
->dev
.kobj
, ds1307
->nvram
);
1608 static struct i2c_driver ds1307_driver
= {
1610 .name
= "rtc-ds1307",
1612 .probe
= ds1307_probe
,
1613 .remove
= ds1307_remove
,
1614 .id_table
= ds1307_id
,
1617 module_i2c_driver(ds1307_driver
);
1619 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1620 MODULE_LICENSE("GPL");