1 // SPDX-License-Identifier: GPL-2.0
3 * Real Time Clock (RTC) Driver for i.MX53
4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
5 * Copyright (c) 2017 Beckhoff Automation GmbH & Co. KG
10 #include <linux/module.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_wakeirq.h>
14 #include <linux/rtc.h>
16 #define SRTC_LPPDR_INIT 0x41736166 /* init for glitch detect */
18 #define SRTC_LPCR_EN_LP BIT(3) /* lp enable */
19 #define SRTC_LPCR_WAE BIT(4) /* lp wakeup alarm enable */
20 #define SRTC_LPCR_ALP BIT(7) /* lp alarm flag */
21 #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
22 #define SRTC_LPCR_NVE BIT(14) /* lp non valid state exit bit */
23 #define SRTC_LPCR_IE BIT(15) /* lp init state exit bit */
25 #define SRTC_LPSR_ALP BIT(3) /* lp alarm flag */
26 #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
27 #define SRTC_LPSR_IES BIT(15) /* lp init state exit status */
29 #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
30 #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
31 #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
32 #define SRTC_LPCR 0x10 /* LP Control Reg */
33 #define SRTC_LPSR 0x14 /* LP Status Reg */
34 #define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
36 /* max. number of retries to read registers, 120 was max during test */
37 #define REG_READ_TIMEOUT 2000
40 struct rtc_device
*rtc
;
43 spinlock_t lock
; /* protects register access */
48 * This function does write synchronization for writes to the lp srtc block.
49 * To take care of the asynchronous CKIL clock, all writes from the IP domain
50 * will be synchronized to the CKIL domain.
51 * The caller should hold the pdata->lock
53 static void mxc_rtc_sync_lp_locked(struct device
*dev
, void __iomem
*ioaddr
)
57 /* Wait for 3 CKIL cycles */
58 for (i
= 0; i
< 3; i
++) {
59 const u32 count
= readl(ioaddr
+ SRTC_LPSCLR
);
60 unsigned int timeout
= REG_READ_TIMEOUT
;
62 while ((readl(ioaddr
+ SRTC_LPSCLR
)) == count
) {
64 dev_err_once(dev
, "SRTC_LPSCLR stuck! Check your hw.\n");
71 /* This function is the RTC interrupt service routine. */
72 static irqreturn_t
mxc_rtc_interrupt(int irq
, void *dev_id
)
74 struct device
*dev
= dev_id
;
75 struct mxc_rtc_data
*pdata
= dev_get_drvdata(dev
);
76 void __iomem
*ioaddr
= pdata
->ioaddr
;
80 spin_lock(&pdata
->lock
);
81 if (clk_enable(pdata
->clk
)) {
82 spin_unlock(&pdata
->lock
);
86 lp_status
= readl(ioaddr
+ SRTC_LPSR
);
87 lp_cr
= readl(ioaddr
+ SRTC_LPCR
);
89 /* update irq data & counter */
90 if (lp_status
& SRTC_LPSR_ALP
) {
91 if (lp_cr
& SRTC_LPCR_ALP
)
92 rtc_update_irq(pdata
->rtc
, 1, RTC_AF
| RTC_IRQF
);
94 /* disable further lp alarm interrupts */
95 lp_cr
&= ~(SRTC_LPCR_ALP
| SRTC_LPCR_WAE
);
98 /* Update interrupt enables */
99 writel(lp_cr
, ioaddr
+ SRTC_LPCR
);
101 /* clear interrupt status */
102 writel(lp_status
, ioaddr
+ SRTC_LPSR
);
104 mxc_rtc_sync_lp_locked(dev
, ioaddr
);
105 clk_disable(pdata
->clk
);
106 spin_unlock(&pdata
->lock
);
111 * Enable clk and aquire spinlock
112 * @return 0 if successful; non-zero otherwise.
114 static int mxc_rtc_lock(struct mxc_rtc_data
*const pdata
)
118 spin_lock_irq(&pdata
->lock
);
119 ret
= clk_enable(pdata
->clk
);
121 spin_unlock_irq(&pdata
->lock
);
127 static int mxc_rtc_unlock(struct mxc_rtc_data
*const pdata
)
129 clk_disable(pdata
->clk
);
130 spin_unlock_irq(&pdata
->lock
);
135 * This function reads the current RTC time into tm in Gregorian date.
137 * @param tm contains the RTC time value upon return
139 * @return 0 if successful; non-zero otherwise.
141 static int mxc_rtc_read_time(struct device
*dev
, struct rtc_time
*tm
)
143 struct mxc_rtc_data
*pdata
= dev_get_drvdata(dev
);
144 const int clk_failed
= clk_enable(pdata
->clk
);
147 const time64_t now
= readl(pdata
->ioaddr
+ SRTC_LPSCMR
);
149 rtc_time64_to_tm(now
, tm
);
150 clk_disable(pdata
->clk
);
157 * This function sets the internal RTC time based on tm in Gregorian date.
159 * @param tm the time value to be set in the RTC
161 * @return 0 if successful; non-zero otherwise.
163 static int mxc_rtc_set_time(struct device
*dev
, struct rtc_time
*tm
)
165 struct mxc_rtc_data
*pdata
= dev_get_drvdata(dev
);
166 time64_t time
= rtc_tm_to_time64(tm
);
169 ret
= mxc_rtc_lock(pdata
);
173 writel(time
, pdata
->ioaddr
+ SRTC_LPSCMR
);
174 mxc_rtc_sync_lp_locked(dev
, pdata
->ioaddr
);
175 return mxc_rtc_unlock(pdata
);
179 * This function reads the current alarm value into the passed in \b alrm
180 * argument. It updates the \b alrm's pending field value based on the whether
181 * an alarm interrupt occurs or not.
183 * @param alrm contains the RTC alarm value upon return
185 * @return 0 if successful; non-zero otherwise.
187 static int mxc_rtc_read_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
189 struct mxc_rtc_data
*pdata
= dev_get_drvdata(dev
);
190 void __iomem
*ioaddr
= pdata
->ioaddr
;
193 ret
= mxc_rtc_lock(pdata
);
197 rtc_time64_to_tm(readl(ioaddr
+ SRTC_LPSAR
), &alrm
->time
);
198 alrm
->pending
= !!(readl(ioaddr
+ SRTC_LPSR
) & SRTC_LPSR_ALP
);
199 return mxc_rtc_unlock(pdata
);
203 * Enable/Disable alarm interrupt
204 * The caller should hold the pdata->lock
206 static void mxc_rtc_alarm_irq_enable_locked(struct mxc_rtc_data
*pdata
,
209 u32 lp_cr
= readl(pdata
->ioaddr
+ SRTC_LPCR
);
212 lp_cr
|= (SRTC_LPCR_ALP
| SRTC_LPCR_WAE
);
214 lp_cr
&= ~(SRTC_LPCR_ALP
| SRTC_LPCR_WAE
);
216 writel(lp_cr
, pdata
->ioaddr
+ SRTC_LPCR
);
219 static int mxc_rtc_alarm_irq_enable(struct device
*dev
, unsigned int enable
)
221 struct mxc_rtc_data
*pdata
= dev_get_drvdata(dev
);
222 int ret
= mxc_rtc_lock(pdata
);
227 mxc_rtc_alarm_irq_enable_locked(pdata
, enable
);
228 return mxc_rtc_unlock(pdata
);
232 * This function sets the RTC alarm based on passed in alrm.
234 * @param alrm the alarm value to be set in the RTC
236 * @return 0 if successful; non-zero otherwise.
238 static int mxc_rtc_set_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
240 const time64_t time
= rtc_tm_to_time64(&alrm
->time
);
241 struct mxc_rtc_data
*pdata
= dev_get_drvdata(dev
);
242 int ret
= mxc_rtc_lock(pdata
);
247 writel((u32
)time
, pdata
->ioaddr
+ SRTC_LPSAR
);
249 /* clear alarm interrupt status bit */
250 writel(SRTC_LPSR_ALP
, pdata
->ioaddr
+ SRTC_LPSR
);
251 mxc_rtc_sync_lp_locked(dev
, pdata
->ioaddr
);
253 mxc_rtc_alarm_irq_enable_locked(pdata
, alrm
->enabled
);
254 mxc_rtc_sync_lp_locked(dev
, pdata
->ioaddr
);
255 mxc_rtc_unlock(pdata
);
259 static const struct rtc_class_ops mxc_rtc_ops
= {
260 .read_time
= mxc_rtc_read_time
,
261 .set_time
= mxc_rtc_set_time
,
262 .read_alarm
= mxc_rtc_read_alarm
,
263 .set_alarm
= mxc_rtc_set_alarm
,
264 .alarm_irq_enable
= mxc_rtc_alarm_irq_enable
,
267 static int mxc_rtc_wait_for_flag(void __iomem
*ioaddr
, int flag
)
269 unsigned int timeout
= REG_READ_TIMEOUT
;
271 while (!(readl(ioaddr
) & flag
)) {
278 static int mxc_rtc_probe(struct platform_device
*pdev
)
280 struct mxc_rtc_data
*pdata
;
281 void __iomem
*ioaddr
;
284 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
288 pdata
->ioaddr
= devm_platform_ioremap_resource(pdev
, 0);
289 if (IS_ERR(pdata
->ioaddr
))
290 return PTR_ERR(pdata
->ioaddr
);
292 ioaddr
= pdata
->ioaddr
;
294 pdata
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
295 if (IS_ERR(pdata
->clk
)) {
296 dev_err(&pdev
->dev
, "unable to get rtc clock!\n");
297 return PTR_ERR(pdata
->clk
);
300 spin_lock_init(&pdata
->lock
);
301 pdata
->irq
= platform_get_irq(pdev
, 0);
305 device_init_wakeup(&pdev
->dev
, 1);
306 ret
= dev_pm_set_wake_irq(&pdev
->dev
, pdata
->irq
);
308 dev_err(&pdev
->dev
, "failed to enable irq wake\n");
310 ret
= clk_prepare_enable(pdata
->clk
);
313 /* initialize glitch detect */
314 writel(SRTC_LPPDR_INIT
, ioaddr
+ SRTC_LPPDR
);
316 /* clear lp interrupt status */
317 writel(0xFFFFFFFF, ioaddr
+ SRTC_LPSR
);
319 /* move out of init state */
320 writel((SRTC_LPCR_IE
| SRTC_LPCR_NSA
), ioaddr
+ SRTC_LPCR
);
321 ret
= mxc_rtc_wait_for_flag(ioaddr
+ SRTC_LPSR
, SRTC_LPSR_IES
);
323 dev_err(&pdev
->dev
, "Timeout waiting for SRTC_LPSR_IES\n");
324 clk_disable_unprepare(pdata
->clk
);
328 /* move out of non-valid state */
329 writel((SRTC_LPCR_IE
| SRTC_LPCR_NVE
| SRTC_LPCR_NSA
|
330 SRTC_LPCR_EN_LP
), ioaddr
+ SRTC_LPCR
);
331 ret
= mxc_rtc_wait_for_flag(ioaddr
+ SRTC_LPSR
, SRTC_LPSR_NVES
);
333 dev_err(&pdev
->dev
, "Timeout waiting for SRTC_LPSR_NVES\n");
334 clk_disable_unprepare(pdata
->clk
);
338 pdata
->rtc
= devm_rtc_allocate_device(&pdev
->dev
);
339 if (IS_ERR(pdata
->rtc
))
340 return PTR_ERR(pdata
->rtc
);
342 pdata
->rtc
->ops
= &mxc_rtc_ops
;
343 pdata
->rtc
->range_max
= U32_MAX
;
345 clk_disable(pdata
->clk
);
346 platform_set_drvdata(pdev
, pdata
);
348 devm_request_irq(&pdev
->dev
, pdata
->irq
, mxc_rtc_interrupt
, 0,
349 pdev
->name
, &pdev
->dev
);
351 dev_err(&pdev
->dev
, "interrupt not available.\n");
352 clk_unprepare(pdata
->clk
);
356 ret
= devm_rtc_register_device(pdata
->rtc
);
358 clk_unprepare(pdata
->clk
);
363 static int mxc_rtc_remove(struct platform_device
*pdev
)
365 struct mxc_rtc_data
*pdata
= platform_get_drvdata(pdev
);
367 clk_disable_unprepare(pdata
->clk
);
371 static const struct of_device_id mxc_ids
[] = {
372 { .compatible
= "fsl,imx53-rtc", },
376 static struct platform_driver mxc_rtc_driver
= {
378 .name
= "mxc_rtc_v2",
379 .of_match_table
= mxc_ids
,
381 .probe
= mxc_rtc_probe
,
382 .remove
= mxc_rtc_remove
,
385 module_platform_driver(mxc_rtc_driver
);
387 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
388 MODULE_DESCRIPTION("Real Time Clock (RTC) Driver for i.MX53");
389 MODULE_LICENSE("GPL");