drivers/rtc/rtc-pcf85063.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * An I2C driver for the PCF85063 RTC
   4  * Copyright 2014 Rose Technology
   5  *
   6  * Author: Søren Andersen <san@rosetechnology.dk>
   7  * Maintainers: http://www.nslu2-linux.org/
   8  *
   9  * Copyright (C) 2019 Micro Crystal AG
  10  * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
  11  */
  12 #include <linux/clk-provider.h>
  13 #include <linux/i2c.h>
  14 #include <linux/bcd.h>
  15 #include <linux/rtc.h>
  16 #include <linux/module.h>
  17 #include <linux/of_device.h>
  18 #include <linux/pm_wakeirq.h>
  19 #include <linux/regmap.h>
  20
  21 /*
  22  * Information for this driver was pulled from the following datasheets.
  23  *
  24  *  https://www.nxp.com/docs/en/data-sheet/PCF85063A.pdf
  25  *  https://www.nxp.com/docs/en/data-sheet/PCF85063TP.pdf
  26  *
  27  *  PCF85063A -- Rev. 7 — 30 March 2018
  28  *  PCF85063TP -- Rev. 4 — 6 May 2015
  29  *
  30  *  https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
  31  *  RV8263 -- Rev. 1.0 — January 2019
  32  */
  33
  34 #define PCF85063_REG_CTRL1              0x00 /* status */
  35 #define PCF85063_REG_CTRL1_CAP_SEL      BIT(0)
  36 #define PCF85063_REG_CTRL1_STOP         BIT(5)
  37
  38 #define PCF85063_REG_CTRL2              0x01
  39 #define PCF85063_CTRL2_AF               BIT(6)
  40 #define PCF85063_CTRL2_AIE              BIT(7)
  41
  42 #define PCF85063_REG_OFFSET             0x02
  43 #define PCF85063_OFFSET_SIGN_BIT        6       /* 2's complement sign bit */
  44 #define PCF85063_OFFSET_MODE            BIT(7)
  45 #define PCF85063_OFFSET_STEP0           4340
  46 #define PCF85063_OFFSET_STEP1           4069
  47
  48 #define PCF85063_REG_CLKO_F_MASK        0x07 /* frequency mask */
  49 #define PCF85063_REG_CLKO_F_32768HZ     0x00
  50 #define PCF85063_REG_CLKO_F_OFF         0x07
  51
  52 #define PCF85063_REG_RAM                0x03
  53
  54 #define PCF85063_REG_SC                 0x04 /* datetime */
  55 #define PCF85063_REG_SC_OS              0x80
  56
  57 #define PCF85063_REG_ALM_S              0x0b
  58 #define PCF85063_AEN                    BIT(7)
  59
  60 struct pcf85063_config {
  61         struct regmap_config regmap;
  62         unsigned has_alarms:1;
  63         unsigned force_cap_7000:1;
  64 };
  65
  66 struct pcf85063 {
  67         struct rtc_device       *rtc;
  68         struct regmap           *regmap;
  69 #ifdef CONFIG_COMMON_CLK
  70         struct clk_hw           clkout_hw;
  71 #endif
  72 };
  73
  74 static int pcf85063_rtc_read_time(struct device *dev, struct rtc_time *tm)
  75 {
  76         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
  77         int rc;
  78         u8 regs[7];
  79
  80         /*
  81          * while reading, the time/date registers are blocked and not updated
  82          * anymore until the access is finished. To not lose a second
  83          * event, the access must be finished within one second. So, read all
  84          * time/date registers in one turn.
  85          */
  86         rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
  87                               sizeof(regs));
  88         if (rc)
  89                 return rc;
  90
  91         /* if the clock has lost its power it makes no sense to use its time */
  92         if (regs[0] & PCF85063_REG_SC_OS) {
  93                 dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
  94                 return -EINVAL;
  95         }
  96
  97         tm->tm_sec = bcd2bin(regs[0] & 0x7F);
  98         tm->tm_min = bcd2bin(regs[1] & 0x7F);
  99         tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
 100         tm->tm_mday = bcd2bin(regs[3] & 0x3F);
 101         tm->tm_wday = regs[4] & 0x07;
 102         tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
 103         tm->tm_year = bcd2bin(regs[6]);
 104         tm->tm_year += 100;
 105
 106         return 0;
 107 }
 108
 109 static int pcf85063_rtc_set_time(struct device *dev, struct rtc_time *tm)
 110 {
 111         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 112         int rc;
 113         u8 regs[7];
 114
 115         /*
 116          * to accurately set the time, reset the divider chain and keep it in
 117          * reset state until all time/date registers are written
 118          */
 119         rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
 120                                 PCF85063_REG_CTRL1_STOP,
 121                                 PCF85063_REG_CTRL1_STOP);
 122         if (rc)
 123                 return rc;
 124
 125         /* hours, minutes and seconds */
 126         regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */
 127
 128         regs[1] = bin2bcd(tm->tm_min);
 129         regs[2] = bin2bcd(tm->tm_hour);
 130
 131         /* Day of month, 1 - 31 */
 132         regs[3] = bin2bcd(tm->tm_mday);
 133
 134         /* Day, 0 - 6 */
 135         regs[4] = tm->tm_wday & 0x07;
 136
 137         /* month, 1 - 12 */
 138         regs[5] = bin2bcd(tm->tm_mon + 1);
 139
 140         /* year and century */
 141         regs[6] = bin2bcd(tm->tm_year - 100);
 142
 143         /* write all registers at once */
 144         rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
 145                                regs, sizeof(regs));
 146         if (rc)
 147                 return rc;
 148
 149         /*
 150          * Write the control register as a separate action since the size of
 151          * the register space is different between the PCF85063TP and
 152          * PCF85063A devices.  The rollover point can not be used.
 153          */
 154         return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
 155                                   PCF85063_REG_CTRL1_STOP, 0);
 156 }
 157
 158 static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 159 {
 160         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 161         u8 buf[4];
 162         unsigned int val;
 163         int ret;
 164
 165         ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
 166                                buf, sizeof(buf));
 167         if (ret)
 168                 return ret;
 169
 170         alrm->time.tm_sec = bcd2bin(buf[0]);
 171         alrm->time.tm_min = bcd2bin(buf[1]);
 172         alrm->time.tm_hour = bcd2bin(buf[2]);
 173         alrm->time.tm_mday = bcd2bin(buf[3]);
 174
 175         ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
 176         if (ret)
 177                 return ret;
 178
 179         alrm->enabled =  !!(val & PCF85063_CTRL2_AIE);
 180
 181         return 0;
 182 }
 183
 184 static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 185 {
 186         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 187         u8 buf[5];
 188         int ret;
 189
 190         buf[0] = bin2bcd(alrm->time.tm_sec);
 191         buf[1] = bin2bcd(alrm->time.tm_min);
 192         buf[2] = bin2bcd(alrm->time.tm_hour);
 193         buf[3] = bin2bcd(alrm->time.tm_mday);
 194         buf[4] = PCF85063_AEN; /* Do not match on week day */
 195
 196         ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
 197                                  PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 0);
 198         if (ret)
 199                 return ret;
 200
 201         ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
 202                                 buf, sizeof(buf));
 203         if (ret)
 204                 return ret;
 205
 206         return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
 207                                   PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
 208                                   alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
 209 }
 210
 211 static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
 212                                          unsigned int enabled)
 213 {
 214         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 215
 216         return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
 217                                   PCF85063_CTRL2_AIE,
 218                                   enabled ? PCF85063_CTRL2_AIE : 0);
 219 }
 220
 221 static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
 222 {
 223         struct pcf85063 *pcf85063 = dev_id;
 224         unsigned int val;
 225         int err;
 226
 227         err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
 228         if (err)
 229                 return IRQ_NONE;
 230
 231         if (val & PCF85063_CTRL2_AF) {
 232                 rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF | RTC_AF);
 233                 regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
 234                                    PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
 235                                    0);
 236                 return IRQ_HANDLED;
 237         }
 238
 239         return IRQ_NONE;
 240 }
 241
 242 static int pcf85063_read_offset(struct device *dev, long *offset)
 243 {
 244         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 245         long val;
 246         u32 reg;
 247         int ret;
 248
 249         ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &reg);
 250         if (ret < 0)
 251                 return ret;
 252
 253         val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
 254                             PCF85063_OFFSET_SIGN_BIT);
 255
 256         if (reg & PCF85063_OFFSET_MODE)
 257                 *offset = val * PCF85063_OFFSET_STEP1;
 258         else
 259                 *offset = val * PCF85063_OFFSET_STEP0;
 260
 261         return 0;
 262 }
 263
 264 static int pcf85063_set_offset(struct device *dev, long offset)
 265 {
 266         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 267         s8 mode0, mode1, reg;
 268         unsigned int error0, error1;
 269
 270         if (offset > PCF85063_OFFSET_STEP0 * 63)
 271                 return -ERANGE;
 272         if (offset < PCF85063_OFFSET_STEP0 * -64)
 273                 return -ERANGE;
 274
 275         mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
 276         mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);
 277
 278         error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
 279         error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
 280         if (mode1 > 63 || mode1 < -64 || error0 < error1)
 281                 reg = mode0 & ~PCF85063_OFFSET_MODE;
 282         else
 283                 reg = mode1 | PCF85063_OFFSET_MODE;
 284
 285         return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
 286 }
 287
 288 static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
 289                           unsigned long arg)
 290 {
 291         struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 292         int status, ret = 0;
 293
 294         switch (cmd) {
 295         case RTC_VL_READ:
 296                 ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
 297                 if (ret < 0)
 298                         return ret;
 299
 300                 status = status & PCF85063_REG_SC_OS ? RTC_VL_DATA_INVALID : 0;
 301
 302                 return put_user(status, (unsigned int __user *)arg);
 303
 304         default:
 305                 return -ENOIOCTLCMD;
 306         }
 307 }
 308
 309 static const struct rtc_class_ops pcf85063_rtc_ops = {
 310         .read_time      = pcf85063_rtc_read_time,
 311         .set_time       = pcf85063_rtc_set_time,
 312         .read_offset    = pcf85063_read_offset,
 313         .set_offset     = pcf85063_set_offset,
 314         .read_alarm     = pcf85063_rtc_read_alarm,
 315         .set_alarm      = pcf85063_rtc_set_alarm,
 316         .alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
 317         .ioctl          = pcf85063_ioctl,
 318 };
 319
 320 static int pcf85063_nvmem_read(void *priv, unsigned int offset,
 321                                void *val, size_t bytes)
 322 {
 323         return regmap_read(priv, PCF85063_REG_RAM, val);
 324 }
 325
 326 static int pcf85063_nvmem_write(void *priv, unsigned int offset,
 327                                 void *val, size_t bytes)
 328 {
 329         return regmap_write(priv, PCF85063_REG_RAM, *(u8 *)val);
 330 }
 331
 332 static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
 333                                      const struct device_node *np,
 334                                      unsigned int force_cap)
 335 {
 336         u32 load = 7000;
 337         u8 reg = 0;
 338
 339         if (force_cap)
 340                 load = force_cap;
 341         else
 342                 of_property_read_u32(np, "quartz-load-femtofarads", &load);
 343
 344         switch (load) {
 345         default:
 346                 dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
 347                          load);
 348                 fallthrough;
 349         case 7000:
 350                 break;
 351         case 12500:
 352                 reg = PCF85063_REG_CTRL1_CAP_SEL;
 353                 break;
 354         }
 355
 356         return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
 357                                   PCF85063_REG_CTRL1_CAP_SEL, reg);
 358 }
 359
 360 #ifdef CONFIG_COMMON_CLK
 361 /*
 362  * Handling of the clkout
 363  */
 364
 365 #define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)
 366
 367 static int clkout_rates[] = {
 368         32768,
 369         16384,
 370         8192,
 371         4096,
 372         2048,
 373         1024,
 374         1,
 375         0
 376 };
 377
 378 static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw *hw,
 379                                                  unsigned long parent_rate)
 380 {
 381         struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
 382         unsigned int buf;
 383         int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
 384
 385         if (ret < 0)
 386                 return 0;
 387
 388         buf &= PCF85063_REG_CLKO_F_MASK;
 389         return clkout_rates[buf];
 390 }
 391
 392 static long pcf85063_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
 393                                        unsigned long *prate)
 394 {
 395         int i;
 396
 397         for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
 398                 if (clkout_rates[i] <= rate)
 399                         return clkout_rates[i];
 400
 401         return 0;
 402 }
 403
 404 static int pcf85063_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
 405                                     unsigned long parent_rate)
 406 {
 407         struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
 408         int i;
 409
 410         for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
 411                 if (clkout_rates[i] == rate)
 412                         return regmap_update_bits(pcf85063->regmap,
 413                                 PCF85063_REG_CTRL2,
 414                                 PCF85063_REG_CLKO_F_MASK, i);
 415
 416         return -EINVAL;
 417 }
 418
 419 static int pcf85063_clkout_control(struct clk_hw *hw, bool enable)
 420 {
 421         struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
 422         unsigned int buf;
 423         int ret;
 424
 425         ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &buf);
 426         if (ret < 0)
 427                 return ret;
 428         buf &= PCF85063_REG_CLKO_F_MASK;
 429
 430         if (enable) {
 431                 if (buf == PCF85063_REG_CLKO_F_OFF)
 432                         buf = PCF85063_REG_CLKO_F_32768HZ;
 433                 else
 434                         return 0;
 435         } else {
 436                 if (buf != PCF85063_REG_CLKO_F_OFF)
 437                         buf = PCF85063_REG_CLKO_F_OFF;
 438                 else
 439                         return 0;
 440         }
 441
 442         return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
 443                                         PCF85063_REG_CLKO_F_MASK, buf);
 444 }
 445
 446 static int pcf85063_clkout_prepare(struct clk_hw *hw)
 447 {
 448         return pcf85063_clkout_control(hw, 1);
 449 }
 450
 451 static void pcf85063_clkout_unprepare(struct clk_hw *hw)
 452 {
 453         pcf85063_clkout_control(hw, 0);
 454 }
 455
 456 static int pcf85063_clkout_is_prepared(struct clk_hw *hw)
 457 {
 458         struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
 459         unsigned int buf;
 460         int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
 461
 462         if (ret < 0)
 463                 return 0;
 464
 465         return (buf & PCF85063_REG_CLKO_F_MASK) != PCF85063_REG_CLKO_F_OFF;
 466 }
 467
 468 static const struct clk_ops pcf85063_clkout_ops = {
 469         .prepare = pcf85063_clkout_prepare,
 470         .unprepare = pcf85063_clkout_unprepare,
 471         .is_prepared = pcf85063_clkout_is_prepared,
 472         .recalc_rate = pcf85063_clkout_recalc_rate,
 473         .round_rate = pcf85063_clkout_round_rate,
 474         .set_rate = pcf85063_clkout_set_rate,
 475 };
 476
 477 static struct clk *pcf85063_clkout_register_clk(struct pcf85063 *pcf85063)
 478 {
 479         struct clk *clk;
 480         struct clk_init_data init;
 481         struct device_node *node = pcf85063->rtc->dev.parent->of_node;
 482
 483         init.name = "pcf85063-clkout";
 484         init.ops = &pcf85063_clkout_ops;
 485         init.flags = 0;
 486         init.parent_names = NULL;
 487         init.num_parents = 0;
 488         pcf85063->clkout_hw.init = &init;
 489
 490         /* optional override of the clockname */
 491         of_property_read_string(node, "clock-output-names", &init.name);
 492
 493         /* register the clock */
 494         clk = devm_clk_register(&pcf85063->rtc->dev, &pcf85063->clkout_hw);
 495
 496         if (!IS_ERR(clk))
 497                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 498
 499         return clk;
 500 }
 501 #endif
 502
 503 static const struct pcf85063_config pcf85063tp_config = {
 504         .regmap = {
 505                 .reg_bits = 8,
 506                 .val_bits = 8,
 507                 .max_register = 0x0a,
 508         },
 509 };
 510
 511 static int pcf85063_probe(struct i2c_client *client)
 512 {
 513         struct pcf85063 *pcf85063;
 514         unsigned int tmp;
 515         int err;
 516         const struct pcf85063_config *config = &pcf85063tp_config;
 517         const void *data = of_device_get_match_data(&client->dev);
 518         struct nvmem_config nvmem_cfg = {
 519                 .name = "pcf85063_nvram",
 520                 .reg_read = pcf85063_nvmem_read,
 521                 .reg_write = pcf85063_nvmem_write,
 522                 .type = NVMEM_TYPE_BATTERY_BACKED,
 523                 .size = 1,
 524         };
 525
 526         dev_dbg(&client->dev, "%s\n", __func__);
 527
 528         pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063),
 529                                 GFP_KERNEL);
 530         if (!pcf85063)
 531                 return -ENOMEM;
 532
 533         if (data)
 534                 config = data;
 535
 536         pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
 537         if (IS_ERR(pcf85063->regmap))
 538                 return PTR_ERR(pcf85063->regmap);
 539
 540         i2c_set_clientdata(client, pcf85063);
 541
 542         err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp);
 543         if (err) {
 544                 dev_err(&client->dev, "RTC chip is not present\n");
 545                 return err;
 546         }
 547
 548         pcf85063->rtc = devm_rtc_allocate_device(&client->dev);
 549         if (IS_ERR(pcf85063->rtc))
 550                 return PTR_ERR(pcf85063->rtc);
 551
 552         err = pcf85063_load_capacitance(pcf85063, client->dev.of_node,
 553                                         config->force_cap_7000 ? 7000 : 0);
 554         if (err < 0)
 555                 dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
 556                          err);
 557
 558         pcf85063->rtc->ops = &pcf85063_rtc_ops;
 559         pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
 560         pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
 561         pcf85063->rtc->uie_unsupported = 1;
 562         clear_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
 563
 564         if (config->has_alarms && client->irq > 0) {
 565                 err = devm_request_threaded_irq(&client->dev, client->irq,
 566                                                 NULL, pcf85063_rtc_handle_irq,
 567                                                 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
 568                                                 "pcf85063", pcf85063);
 569                 if (err) {
 570                         dev_warn(&pcf85063->rtc->dev,
 571                                  "unable to request IRQ, alarms disabled\n");
 572                 } else {
 573                         set_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
 574                         device_init_wakeup(&client->dev, true);
 575                         err = dev_pm_set_wake_irq(&client->dev, client->irq);
 576                         if (err)
 577                                 dev_err(&pcf85063->rtc->dev,
 578                                         "failed to enable irq wake\n");
 579                 }
 580         }
 581
 582         nvmem_cfg.priv = pcf85063->regmap;
 583         devm_rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);
 584
 585 #ifdef CONFIG_COMMON_CLK
 586         /* register clk in common clk framework */
 587         pcf85063_clkout_register_clk(pcf85063);
 588 #endif
 589
 590         return devm_rtc_register_device(pcf85063->rtc);
 591 }
 592
 593 #ifdef CONFIG_OF
 594 static const struct pcf85063_config pcf85063a_config = {
 595         .regmap = {
 596                 .reg_bits = 8,
 597                 .val_bits = 8,
 598                 .max_register = 0x11,
 599         },
 600         .has_alarms = 1,
 601 };
 602
 603 static const struct pcf85063_config rv8263_config = {
 604         .regmap = {
 605                 .reg_bits = 8,
 606                 .val_bits = 8,
 607                 .max_register = 0x11,
 608         },
 609         .has_alarms = 1,
 610         .force_cap_7000 = 1,
 611 };
 612
 613 static const struct of_device_id pcf85063_of_match[] = {
 614         { .compatible = "nxp,pcf85063", .data = &pcf85063tp_config },
 615         { .compatible = "nxp,pcf85063tp", .data = &pcf85063tp_config },
 616         { .compatible = "nxp,pcf85063a", .data = &pcf85063a_config },
 617         { .compatible = "microcrystal,rv8263", .data = &rv8263_config },
 618         {}
 619 };
 620 MODULE_DEVICE_TABLE(of, pcf85063_of_match);
 621 #endif
 622
 623 static struct i2c_driver pcf85063_driver = {
 624         .driver         = {
 625                 .name   = "rtc-pcf85063",
 626                 .of_match_table = of_match_ptr(pcf85063_of_match),
 627         },
 628         .probe_new      = pcf85063_probe,
 629 };
 630
 631 module_i2c_driver(pcf85063_driver);
 632
 633 MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
 634 MODULE_DESCRIPTION("PCF85063 RTC driver");
 635 MODULE_LICENSE("GPL");