1 // SPDX-License-Identifier: GPL-2.0
3 * An I2C driver for the PCF85063 RTC
4 * Copyright 2014 Rose Technology
6 * Author: Søren Andersen <san@rosetechnology.dk>
7 * Maintainers: http://www.nslu2-linux.org/
9 * Copyright (C) 2019 Micro Crystal AG
10 * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
12 #include <linux/clk-provider.h>
13 #include <linux/i2c.h>
14 #include <linux/bcd.h>
15 #include <linux/rtc.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/pm_wakeirq.h>
19 #include <linux/regmap.h>
22 * Information for this driver was pulled from the following datasheets.
24 * https://www.nxp.com/docs/en/data-sheet/PCF85063A.pdf
25 * https://www.nxp.com/docs/en/data-sheet/PCF85063TP.pdf
27 * PCF85063A -- Rev. 7 — 30 March 2018
28 * PCF85063TP -- Rev. 4 — 6 May 2015
30 * https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
31 * RV8263 -- Rev. 1.0 — January 2019
34 #define PCF85063_REG_CTRL1 0x00 /* status */
35 #define PCF85063_REG_CTRL1_CAP_SEL BIT(0)
36 #define PCF85063_REG_CTRL1_STOP BIT(5)
38 #define PCF85063_REG_CTRL2 0x01
39 #define PCF85063_CTRL2_AF BIT(6)
40 #define PCF85063_CTRL2_AIE BIT(7)
42 #define PCF85063_REG_OFFSET 0x02
43 #define PCF85063_OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
44 #define PCF85063_OFFSET_MODE BIT(7)
45 #define PCF85063_OFFSET_STEP0 4340
46 #define PCF85063_OFFSET_STEP1 4069
48 #define PCF85063_REG_CLKO_F_MASK 0x07 /* frequency mask */
49 #define PCF85063_REG_CLKO_F_32768HZ 0x00
50 #define PCF85063_REG_CLKO_F_OFF 0x07
52 #define PCF85063_REG_RAM 0x03
54 #define PCF85063_REG_SC 0x04 /* datetime */
55 #define PCF85063_REG_SC_OS 0x80
57 #define PCF85063_REG_ALM_S 0x0b
58 #define PCF85063_AEN BIT(7)
60 struct pcf85063_config
{
61 struct regmap_config regmap
;
62 unsigned has_alarms
:1;
63 unsigned force_cap_7000
:1;
67 struct rtc_device
*rtc
;
68 struct regmap
*regmap
;
69 #ifdef CONFIG_COMMON_CLK
70 struct clk_hw clkout_hw
;
74 static int pcf85063_rtc_read_time(struct device
*dev
, struct rtc_time
*tm
)
76 struct pcf85063
*pcf85063
= dev_get_drvdata(dev
);
81 * while reading, the time/date registers are blocked and not updated
82 * anymore until the access is finished. To not lose a second
83 * event, the access must be finished within one second. So, read all
84 * time/date registers in one turn.
86 rc
= regmap_bulk_read(pcf85063
->regmap
, PCF85063_REG_SC
, regs
,
91 /* if the clock has lost its power it makes no sense to use its time */
92 if (regs
[0] & PCF85063_REG_SC_OS
) {
93 dev_warn(&pcf85063
->rtc
->dev
, "Power loss detected, invalid time\n");
97 tm
->tm_sec
= bcd2bin(regs
[0] & 0x7F);
98 tm
->tm_min
= bcd2bin(regs
[1] & 0x7F);
99 tm
->tm_hour
= bcd2bin(regs
[2] & 0x3F); /* rtc hr 0-23 */
100 tm
->tm_mday
= bcd2bin(regs
[3] & 0x3F);
101 tm
->tm_wday
= regs
[4] & 0x07;
102 tm
->tm_mon
= bcd2bin(regs
[5] & 0x1F) - 1; /* rtc mn 1-12 */
103 tm
->tm_year
= bcd2bin(regs
[6]);
109 static int pcf85063_rtc_set_time(struct device
*dev
, struct rtc_time
*tm
)
111 struct pcf85063
*pcf85063
= dev_get_drvdata(dev
);
116 * to accurately set the time, reset the divider chain and keep it in
117 * reset state until all time/date registers are written
119 rc
= regmap_update_bits(pcf85063
->regmap
, PCF85063_REG_CTRL1
,
120 PCF85063_REG_CTRL1_STOP
,
121 PCF85063_REG_CTRL1_STOP
);
125 /* hours, minutes and seconds */
126 regs
[0] = bin2bcd(tm
->tm_sec
) & 0x7F; /* clear OS flag */
128 regs
[1] = bin2bcd(tm
->tm_min
);
129 regs
[2] = bin2bcd(tm
->tm_hour
);
131 /* Day of month, 1 - 31 */
132 regs
[3] = bin2bcd(tm
->tm_mday
);
135 regs
[4] = tm
->tm_wday
& 0x07;
138 regs
[5] = bin2bcd(tm
->tm_mon
+ 1);
140 /* year and century */
141 regs
[6] = bin2bcd(tm
->tm_year
- 100);
143 /* write all registers at once */
144 rc
= regmap_bulk_write(pcf85063
->regmap
, PCF85063_REG_SC
,
150 * Write the control register as a separate action since the size of
151 * the register space is different between the PCF85063TP and
152 * PCF85063A devices. The rollover point can not be used.
154 return regmap_update_bits(pcf85063
->regmap
, PCF85063_REG_CTRL1
,
155 PCF85063_REG_CTRL1_STOP
, 0);
158 static int pcf85063_rtc_read_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
160 struct pcf85063
*pcf85063
= dev_get_drvdata(dev
);
165 ret
= regmap_bulk_read(pcf85063
->regmap
, PCF85063_REG_ALM_S
,
170 alrm
->time
.tm_sec
= bcd2bin(buf
[0]);
171 alrm
->time
.tm_min
= bcd2bin(buf
[1]);
172 alrm
->time
.tm_hour
= bcd2bin(buf
[2]);
173 alrm
->time
.tm_mday
= bcd2bin(buf
[3]);
175 ret
= regmap_read(pcf85063
->regmap
, PCF85063_REG_CTRL2
, &val
);
179 alrm
->enabled
= !!(val
& PCF85063_CTRL2_AIE
);
184 static int pcf85063_rtc_set_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
186 struct pcf85063
*pcf85063
= dev_get_drvdata(dev
);
190 buf
[0] = bin2bcd(alrm
->time
.tm_sec
);
191 buf
[1] = bin2bcd(alrm
->time
.tm_min
);
192 buf
[2] = bin2bcd(alrm
->time
.tm_hour
);
193 buf
[3] = bin2bcd(alrm
->time
.tm_mday
);
194 buf
[4] = PCF85063_AEN
; /* Do not match on week day */
196 ret
= regmap_update_bits(pcf85063
->regmap
, PCF85063_REG_CTRL2
,
197 PCF85063_CTRL2_AIE
| PCF85063_CTRL2_AF
, 0);
201 ret
= regmap_bulk_write(pcf85063
->regmap
, PCF85063_REG_ALM_S
,
206 return regmap_update_bits(pcf85063
->regmap
, PCF85063_REG_CTRL2
,
207 PCF85063_CTRL2_AIE
| PCF85063_CTRL2_AF
,
208 alrm
->enabled
? PCF85063_CTRL2_AIE
| PCF85063_CTRL2_AF
: PCF85063_CTRL2_AF
);
211 static int pcf85063_rtc_alarm_irq_enable(struct device
*dev
,
212 unsigned int enabled
)
214 struct pcf85063
*pcf85063
= dev_get_drvdata(dev
);
216 return regmap_update_bits(pcf85063
->regmap
, PCF85063_REG_CTRL2
,
218 enabled
? PCF85063_CTRL2_AIE
: 0);
221 static irqreturn_t
pcf85063_rtc_handle_irq(int irq
, void *dev_id
)
223 struct pcf85063
*pcf85063
= dev_id
;
227 err
= regmap_read(pcf85063
->regmap
, PCF85063_REG_CTRL2
, &val
);
231 if (val
& PCF85063_CTRL2_AF
) {
232 rtc_update_irq(pcf85063
->rtc
, 1, RTC_IRQF
| RTC_AF
);
233 regmap_update_bits(pcf85063
->regmap
, PCF85063_REG_CTRL2
,
234 PCF85063_CTRL2_AIE
| PCF85063_CTRL2_AF
,
242 static int pcf85063_read_offset(struct device
*dev
, long *offset
)
244 struct pcf85063
*pcf85063
= dev_get_drvdata(dev
);
249 ret
= regmap_read(pcf85063
->regmap
, PCF85063_REG_OFFSET
, ®
);
253 val
= sign_extend32(reg
& ~PCF85063_OFFSET_MODE
,
254 PCF85063_OFFSET_SIGN_BIT
);
256 if (reg
& PCF85063_OFFSET_MODE
)
257 *offset
= val
* PCF85063_OFFSET_STEP1
;
259 *offset
= val
* PCF85063_OFFSET_STEP0
;
264 static int pcf85063_set_offset(struct device
*dev
, long offset
)
266 struct pcf85063
*pcf85063
= dev_get_drvdata(dev
);
267 s8 mode0
, mode1
, reg
;
268 unsigned int error0
, error1
;
270 if (offset
> PCF85063_OFFSET_STEP0
* 63)
272 if (offset
< PCF85063_OFFSET_STEP0
* -64)
275 mode0
= DIV_ROUND_CLOSEST(offset
, PCF85063_OFFSET_STEP0
);
276 mode1
= DIV_ROUND_CLOSEST(offset
, PCF85063_OFFSET_STEP1
);
278 error0
= abs(offset
- (mode0
* PCF85063_OFFSET_STEP0
));
279 error1
= abs(offset
- (mode1
* PCF85063_OFFSET_STEP1
));
280 if (mode1
> 63 || mode1
< -64 || error0
< error1
)
281 reg
= mode0
& ~PCF85063_OFFSET_MODE
;
283 reg
= mode1
| PCF85063_OFFSET_MODE
;
285 return regmap_write(pcf85063
->regmap
, PCF85063_REG_OFFSET
, reg
);
288 static int pcf85063_ioctl(struct device
*dev
, unsigned int cmd
,
291 struct pcf85063
*pcf85063
= dev_get_drvdata(dev
);
296 ret
= regmap_read(pcf85063
->regmap
, PCF85063_REG_SC
, &status
);
300 status
= status
& PCF85063_REG_SC_OS
? RTC_VL_DATA_INVALID
: 0;
302 return put_user(status
, (unsigned int __user
*)arg
);
309 static const struct rtc_class_ops pcf85063_rtc_ops
= {
310 .read_time
= pcf85063_rtc_read_time
,
311 .set_time
= pcf85063_rtc_set_time
,
312 .read_offset
= pcf85063_read_offset
,
313 .set_offset
= pcf85063_set_offset
,
314 .read_alarm
= pcf85063_rtc_read_alarm
,
315 .set_alarm
= pcf85063_rtc_set_alarm
,
316 .alarm_irq_enable
= pcf85063_rtc_alarm_irq_enable
,
317 .ioctl
= pcf85063_ioctl
,
320 static int pcf85063_nvmem_read(void *priv
, unsigned int offset
,
321 void *val
, size_t bytes
)
323 return regmap_read(priv
, PCF85063_REG_RAM
, val
);
326 static int pcf85063_nvmem_write(void *priv
, unsigned int offset
,
327 void *val
, size_t bytes
)
329 return regmap_write(priv
, PCF85063_REG_RAM
, *(u8
*)val
);
332 static int pcf85063_load_capacitance(struct pcf85063
*pcf85063
,
333 const struct device_node
*np
,
334 unsigned int force_cap
)
342 of_property_read_u32(np
, "quartz-load-femtofarads", &load
);
346 dev_warn(&pcf85063
->rtc
->dev
, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
352 reg
= PCF85063_REG_CTRL1_CAP_SEL
;
356 return regmap_update_bits(pcf85063
->regmap
, PCF85063_REG_CTRL1
,
357 PCF85063_REG_CTRL1_CAP_SEL
, reg
);
360 #ifdef CONFIG_COMMON_CLK
362 * Handling of the clkout
365 #define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)
367 static int clkout_rates
[] = {
378 static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw
*hw
,
379 unsigned long parent_rate
)
381 struct pcf85063
*pcf85063
= clkout_hw_to_pcf85063(hw
);
383 int ret
= regmap_read(pcf85063
->regmap
, PCF85063_REG_CTRL2
, &buf
);
388 buf
&= PCF85063_REG_CLKO_F_MASK
;
389 return clkout_rates
[buf
];
392 static long pcf85063_clkout_round_rate(struct clk_hw
*hw
, unsigned long rate
,
393 unsigned long *prate
)
397 for (i
= 0; i
< ARRAY_SIZE(clkout_rates
); i
++)
398 if (clkout_rates
[i
] <= rate
)
399 return clkout_rates
[i
];
404 static int pcf85063_clkout_set_rate(struct clk_hw
*hw
, unsigned long rate
,
405 unsigned long parent_rate
)
407 struct pcf85063
*pcf85063
= clkout_hw_to_pcf85063(hw
);
410 for (i
= 0; i
< ARRAY_SIZE(clkout_rates
); i
++)
411 if (clkout_rates
[i
] == rate
)
412 return regmap_update_bits(pcf85063
->regmap
,
414 PCF85063_REG_CLKO_F_MASK
, i
);
419 static int pcf85063_clkout_control(struct clk_hw
*hw
, bool enable
)
421 struct pcf85063
*pcf85063
= clkout_hw_to_pcf85063(hw
);
425 ret
= regmap_read(pcf85063
->regmap
, PCF85063_REG_OFFSET
, &buf
);
428 buf
&= PCF85063_REG_CLKO_F_MASK
;
431 if (buf
== PCF85063_REG_CLKO_F_OFF
)
432 buf
= PCF85063_REG_CLKO_F_32768HZ
;
436 if (buf
!= PCF85063_REG_CLKO_F_OFF
)
437 buf
= PCF85063_REG_CLKO_F_OFF
;
442 return regmap_update_bits(pcf85063
->regmap
, PCF85063_REG_CTRL2
,
443 PCF85063_REG_CLKO_F_MASK
, buf
);
446 static int pcf85063_clkout_prepare(struct clk_hw
*hw
)
448 return pcf85063_clkout_control(hw
, 1);
451 static void pcf85063_clkout_unprepare(struct clk_hw
*hw
)
453 pcf85063_clkout_control(hw
, 0);
456 static int pcf85063_clkout_is_prepared(struct clk_hw
*hw
)
458 struct pcf85063
*pcf85063
= clkout_hw_to_pcf85063(hw
);
460 int ret
= regmap_read(pcf85063
->regmap
, PCF85063_REG_CTRL2
, &buf
);
465 return (buf
& PCF85063_REG_CLKO_F_MASK
) != PCF85063_REG_CLKO_F_OFF
;
468 static const struct clk_ops pcf85063_clkout_ops
= {
469 .prepare
= pcf85063_clkout_prepare
,
470 .unprepare
= pcf85063_clkout_unprepare
,
471 .is_prepared
= pcf85063_clkout_is_prepared
,
472 .recalc_rate
= pcf85063_clkout_recalc_rate
,
473 .round_rate
= pcf85063_clkout_round_rate
,
474 .set_rate
= pcf85063_clkout_set_rate
,
477 static struct clk
*pcf85063_clkout_register_clk(struct pcf85063
*pcf85063
)
480 struct clk_init_data init
;
481 struct device_node
*node
= pcf85063
->rtc
->dev
.parent
->of_node
;
483 init
.name
= "pcf85063-clkout";
484 init
.ops
= &pcf85063_clkout_ops
;
486 init
.parent_names
= NULL
;
487 init
.num_parents
= 0;
488 pcf85063
->clkout_hw
.init
= &init
;
490 /* optional override of the clockname */
491 of_property_read_string(node
, "clock-output-names", &init
.name
);
493 /* register the clock */
494 clk
= devm_clk_register(&pcf85063
->rtc
->dev
, &pcf85063
->clkout_hw
);
497 of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
503 static const struct pcf85063_config pcf85063tp_config
= {
507 .max_register
= 0x0a,
511 static int pcf85063_probe(struct i2c_client
*client
)
513 struct pcf85063
*pcf85063
;
516 const struct pcf85063_config
*config
= &pcf85063tp_config
;
517 const void *data
= of_device_get_match_data(&client
->dev
);
518 struct nvmem_config nvmem_cfg
= {
519 .name
= "pcf85063_nvram",
520 .reg_read
= pcf85063_nvmem_read
,
521 .reg_write
= pcf85063_nvmem_write
,
522 .type
= NVMEM_TYPE_BATTERY_BACKED
,
526 dev_dbg(&client
->dev
, "%s\n", __func__
);
528 pcf85063
= devm_kzalloc(&client
->dev
, sizeof(struct pcf85063
),
536 pcf85063
->regmap
= devm_regmap_init_i2c(client
, &config
->regmap
);
537 if (IS_ERR(pcf85063
->regmap
))
538 return PTR_ERR(pcf85063
->regmap
);
540 i2c_set_clientdata(client
, pcf85063
);
542 err
= regmap_read(pcf85063
->regmap
, PCF85063_REG_CTRL1
, &tmp
);
544 dev_err(&client
->dev
, "RTC chip is not present\n");
548 pcf85063
->rtc
= devm_rtc_allocate_device(&client
->dev
);
549 if (IS_ERR(pcf85063
->rtc
))
550 return PTR_ERR(pcf85063
->rtc
);
552 err
= pcf85063_load_capacitance(pcf85063
, client
->dev
.of_node
,
553 config
->force_cap_7000
? 7000 : 0);
555 dev_warn(&client
->dev
, "failed to set xtal load capacitance: %d",
558 pcf85063
->rtc
->ops
= &pcf85063_rtc_ops
;
559 pcf85063
->rtc
->range_min
= RTC_TIMESTAMP_BEGIN_2000
;
560 pcf85063
->rtc
->range_max
= RTC_TIMESTAMP_END_2099
;
561 pcf85063
->rtc
->uie_unsupported
= 1;
562 clear_bit(RTC_FEATURE_ALARM
, pcf85063
->rtc
->features
);
564 if (config
->has_alarms
&& client
->irq
> 0) {
565 err
= devm_request_threaded_irq(&client
->dev
, client
->irq
,
566 NULL
, pcf85063_rtc_handle_irq
,
567 IRQF_TRIGGER_LOW
| IRQF_ONESHOT
,
568 "pcf85063", pcf85063
);
570 dev_warn(&pcf85063
->rtc
->dev
,
571 "unable to request IRQ, alarms disabled\n");
573 set_bit(RTC_FEATURE_ALARM
, pcf85063
->rtc
->features
);
574 device_init_wakeup(&client
->dev
, true);
575 err
= dev_pm_set_wake_irq(&client
->dev
, client
->irq
);
577 dev_err(&pcf85063
->rtc
->dev
,
578 "failed to enable irq wake\n");
582 nvmem_cfg
.priv
= pcf85063
->regmap
;
583 devm_rtc_nvmem_register(pcf85063
->rtc
, &nvmem_cfg
);
585 #ifdef CONFIG_COMMON_CLK
586 /* register clk in common clk framework */
587 pcf85063_clkout_register_clk(pcf85063
);
590 return devm_rtc_register_device(pcf85063
->rtc
);
594 static const struct pcf85063_config pcf85063a_config
= {
598 .max_register
= 0x11,
603 static const struct pcf85063_config rv8263_config
= {
607 .max_register
= 0x11,
613 static const struct of_device_id pcf85063_of_match
[] = {
614 { .compatible
= "nxp,pcf85063", .data
= &pcf85063tp_config
},
615 { .compatible
= "nxp,pcf85063tp", .data
= &pcf85063tp_config
},
616 { .compatible
= "nxp,pcf85063a", .data
= &pcf85063a_config
},
617 { .compatible
= "microcrystal,rv8263", .data
= &rv8263_config
},
620 MODULE_DEVICE_TABLE(of
, pcf85063_of_match
);
623 static struct i2c_driver pcf85063_driver
= {
625 .name
= "rtc-pcf85063",
626 .of_match_table
= of_match_ptr(pcf85063_of_match
),
628 .probe_new
= pcf85063_probe
,
631 module_i2c_driver(pcf85063_driver
);
633 MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
634 MODULE_DESCRIPTION("PCF85063 RTC driver");
635 MODULE_LICENSE("GPL");