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[mirror_ubuntu-artful-kernel.git] / drivers / rtc / rtc-stm32.c
1 /*
2 * Copyright (C) Amelie Delaunay 2016
3 * Author: Amelie Delaunay <amelie.delaunay@st.com>
4 * License terms: GNU General Public License (GPL), version 2
5 */
6
7 #include <linux/bcd.h>
8 #include <linux/clk.h>
9 #include <linux/iopoll.h>
10 #include <linux/ioport.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/regmap.h>
15 #include <linux/rtc.h>
16
17 #define DRIVER_NAME "stm32_rtc"
18
19 /* STM32 RTC registers */
20 #define STM32_RTC_TR 0x00
21 #define STM32_RTC_DR 0x04
22 #define STM32_RTC_CR 0x08
23 #define STM32_RTC_ISR 0x0C
24 #define STM32_RTC_PRER 0x10
25 #define STM32_RTC_ALRMAR 0x1C
26 #define STM32_RTC_WPR 0x24
27
28 /* STM32_RTC_TR bit fields */
29 #define STM32_RTC_TR_SEC_SHIFT 0
30 #define STM32_RTC_TR_SEC GENMASK(6, 0)
31 #define STM32_RTC_TR_MIN_SHIFT 8
32 #define STM32_RTC_TR_MIN GENMASK(14, 8)
33 #define STM32_RTC_TR_HOUR_SHIFT 16
34 #define STM32_RTC_TR_HOUR GENMASK(21, 16)
35
36 /* STM32_RTC_DR bit fields */
37 #define STM32_RTC_DR_DATE_SHIFT 0
38 #define STM32_RTC_DR_DATE GENMASK(5, 0)
39 #define STM32_RTC_DR_MONTH_SHIFT 8
40 #define STM32_RTC_DR_MONTH GENMASK(12, 8)
41 #define STM32_RTC_DR_WDAY_SHIFT 13
42 #define STM32_RTC_DR_WDAY GENMASK(15, 13)
43 #define STM32_RTC_DR_YEAR_SHIFT 16
44 #define STM32_RTC_DR_YEAR GENMASK(23, 16)
45
46 /* STM32_RTC_CR bit fields */
47 #define STM32_RTC_CR_FMT BIT(6)
48 #define STM32_RTC_CR_ALRAE BIT(8)
49 #define STM32_RTC_CR_ALRAIE BIT(12)
50
51 /* STM32_RTC_ISR bit fields */
52 #define STM32_RTC_ISR_ALRAWF BIT(0)
53 #define STM32_RTC_ISR_INITS BIT(4)
54 #define STM32_RTC_ISR_RSF BIT(5)
55 #define STM32_RTC_ISR_INITF BIT(6)
56 #define STM32_RTC_ISR_INIT BIT(7)
57 #define STM32_RTC_ISR_ALRAF BIT(8)
58
59 /* STM32_RTC_PRER bit fields */
60 #define STM32_RTC_PRER_PRED_S_SHIFT 0
61 #define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
62 #define STM32_RTC_PRER_PRED_A_SHIFT 16
63 #define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
64
65 /* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */
66 #define STM32_RTC_ALRMXR_SEC_SHIFT 0
67 #define STM32_RTC_ALRMXR_SEC GENMASK(6, 0)
68 #define STM32_RTC_ALRMXR_SEC_MASK BIT(7)
69 #define STM32_RTC_ALRMXR_MIN_SHIFT 8
70 #define STM32_RTC_ALRMXR_MIN GENMASK(14, 8)
71 #define STM32_RTC_ALRMXR_MIN_MASK BIT(15)
72 #define STM32_RTC_ALRMXR_HOUR_SHIFT 16
73 #define STM32_RTC_ALRMXR_HOUR GENMASK(21, 16)
74 #define STM32_RTC_ALRMXR_PM BIT(22)
75 #define STM32_RTC_ALRMXR_HOUR_MASK BIT(23)
76 #define STM32_RTC_ALRMXR_DATE_SHIFT 24
77 #define STM32_RTC_ALRMXR_DATE GENMASK(29, 24)
78 #define STM32_RTC_ALRMXR_WDSEL BIT(30)
79 #define STM32_RTC_ALRMXR_WDAY_SHIFT 24
80 #define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24)
81 #define STM32_RTC_ALRMXR_DATE_MASK BIT(31)
82
83 /* STM32_RTC_WPR key constants */
84 #define RTC_WPR_1ST_KEY 0xCA
85 #define RTC_WPR_2ND_KEY 0x53
86 #define RTC_WPR_WRONG_KEY 0xFF
87
88 /*
89 * RTC registers are protected against parasitic write access.
90 * PWR_CR_DBP bit must be set to enable write access to RTC registers.
91 */
92 /* STM32_PWR_CR */
93 #define PWR_CR 0x00
94 /* STM32_PWR_CR bit field */
95 #define PWR_CR_DBP BIT(8)
96
97 struct stm32_rtc {
98 struct rtc_device *rtc_dev;
99 void __iomem *base;
100 struct regmap *dbp;
101 struct clk *ck_rtc;
102 int irq_alarm;
103 };
104
105 static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
106 {
107 writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + STM32_RTC_WPR);
108 writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + STM32_RTC_WPR);
109 }
110
111 static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc)
112 {
113 writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + STM32_RTC_WPR);
114 }
115
116 static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
117 {
118 unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
119
120 if (!(isr & STM32_RTC_ISR_INITF)) {
121 isr |= STM32_RTC_ISR_INIT;
122 writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
123
124 /*
125 * It takes around 2 ck_rtc clock cycles to enter in
126 * initialization phase mode (and have INITF flag set). As
127 * slowest ck_rtc frequency may be 32kHz and highest should be
128 * 1MHz, we poll every 10 us with a timeout of 100ms.
129 */
130 return readl_relaxed_poll_timeout_atomic(
131 rtc->base + STM32_RTC_ISR,
132 isr, (isr & STM32_RTC_ISR_INITF),
133 10, 100000);
134 }
135
136 return 0;
137 }
138
139 static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc)
140 {
141 unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
142
143 isr &= ~STM32_RTC_ISR_INIT;
144 writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
145 }
146
147 static int stm32_rtc_wait_sync(struct stm32_rtc *rtc)
148 {
149 unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
150
151 isr &= ~STM32_RTC_ISR_RSF;
152 writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
153
154 /*
155 * Wait for RSF to be set to ensure the calendar registers are
156 * synchronised, it takes around 2 ck_rtc clock cycles
157 */
158 return readl_relaxed_poll_timeout_atomic(rtc->base + STM32_RTC_ISR,
159 isr,
160 (isr & STM32_RTC_ISR_RSF),
161 10, 100000);
162 }
163
164 static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
165 {
166 struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id;
167 unsigned int isr, cr;
168
169 mutex_lock(&rtc->rtc_dev->ops_lock);
170
171 isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
172 cr = readl_relaxed(rtc->base + STM32_RTC_CR);
173
174 if ((isr & STM32_RTC_ISR_ALRAF) &&
175 (cr & STM32_RTC_CR_ALRAIE)) {
176 /* Alarm A flag - Alarm interrupt */
177 dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n");
178
179 /* Pass event to the kernel */
180 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
181
182 /* Clear event flag, otherwise new events won't be received */
183 writel_relaxed(isr & ~STM32_RTC_ISR_ALRAF,
184 rtc->base + STM32_RTC_ISR);
185 }
186
187 mutex_unlock(&rtc->rtc_dev->ops_lock);
188
189 return IRQ_HANDLED;
190 }
191
192 /* Convert rtc_time structure from bin to bcd format */
193 static void tm2bcd(struct rtc_time *tm)
194 {
195 tm->tm_sec = bin2bcd(tm->tm_sec);
196 tm->tm_min = bin2bcd(tm->tm_min);
197 tm->tm_hour = bin2bcd(tm->tm_hour);
198
199 tm->tm_mday = bin2bcd(tm->tm_mday);
200 tm->tm_mon = bin2bcd(tm->tm_mon + 1);
201 tm->tm_year = bin2bcd(tm->tm_year - 100);
202 /*
203 * Number of days since Sunday
204 * - on kernel side, 0=Sunday...6=Saturday
205 * - on rtc side, 0=invalid,1=Monday...7=Sunday
206 */
207 tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday;
208 }
209
210 /* Convert rtc_time structure from bcd to bin format */
211 static void bcd2tm(struct rtc_time *tm)
212 {
213 tm->tm_sec = bcd2bin(tm->tm_sec);
214 tm->tm_min = bcd2bin(tm->tm_min);
215 tm->tm_hour = bcd2bin(tm->tm_hour);
216
217 tm->tm_mday = bcd2bin(tm->tm_mday);
218 tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
219 tm->tm_year = bcd2bin(tm->tm_year) + 100;
220 /*
221 * Number of days since Sunday
222 * - on kernel side, 0=Sunday...6=Saturday
223 * - on rtc side, 0=invalid,1=Monday...7=Sunday
224 */
225 tm->tm_wday %= 7;
226 }
227
228 static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm)
229 {
230 struct stm32_rtc *rtc = dev_get_drvdata(dev);
231 unsigned int tr, dr;
232
233 /* Time and Date in BCD format */
234 tr = readl_relaxed(rtc->base + STM32_RTC_TR);
235 dr = readl_relaxed(rtc->base + STM32_RTC_DR);
236
237 tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
238 tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
239 tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
240
241 tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
242 tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
243 tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
244 tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT;
245
246 /* We don't report tm_yday and tm_isdst */
247
248 bcd2tm(tm);
249
250 return 0;
251 }
252
253 static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
254 {
255 struct stm32_rtc *rtc = dev_get_drvdata(dev);
256 unsigned int tr, dr;
257 int ret = 0;
258
259 tm2bcd(tm);
260
261 /* Time in BCD format */
262 tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) |
263 ((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) |
264 ((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR);
265
266 /* Date in BCD format */
267 dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) |
268 ((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) |
269 ((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) |
270 ((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY);
271
272 stm32_rtc_wpr_unlock(rtc);
273
274 ret = stm32_rtc_enter_init_mode(rtc);
275 if (ret) {
276 dev_err(dev, "Can't enter in init mode. Set time aborted.\n");
277 goto end;
278 }
279
280 writel_relaxed(tr, rtc->base + STM32_RTC_TR);
281 writel_relaxed(dr, rtc->base + STM32_RTC_DR);
282
283 stm32_rtc_exit_init_mode(rtc);
284
285 ret = stm32_rtc_wait_sync(rtc);
286 end:
287 stm32_rtc_wpr_lock(rtc);
288
289 return ret;
290 }
291
292 static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
293 {
294 struct stm32_rtc *rtc = dev_get_drvdata(dev);
295 struct rtc_time *tm = &alrm->time;
296 unsigned int alrmar, cr, isr;
297
298 alrmar = readl_relaxed(rtc->base + STM32_RTC_ALRMAR);
299 cr = readl_relaxed(rtc->base + STM32_RTC_CR);
300 isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
301
302 if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) {
303 /*
304 * Date/day doesn't matter in Alarm comparison so alarm
305 * triggers every day
306 */
307 tm->tm_mday = -1;
308 tm->tm_wday = -1;
309 } else {
310 if (alrmar & STM32_RTC_ALRMXR_WDSEL) {
311 /* Alarm is set to a day of week */
312 tm->tm_mday = -1;
313 tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >>
314 STM32_RTC_ALRMXR_WDAY_SHIFT;
315 tm->tm_wday %= 7;
316 } else {
317 /* Alarm is set to a day of month */
318 tm->tm_wday = -1;
319 tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >>
320 STM32_RTC_ALRMXR_DATE_SHIFT;
321 }
322 }
323
324 if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) {
325 /* Hours don't matter in Alarm comparison */
326 tm->tm_hour = -1;
327 } else {
328 tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >>
329 STM32_RTC_ALRMXR_HOUR_SHIFT;
330 if (alrmar & STM32_RTC_ALRMXR_PM)
331 tm->tm_hour += 12;
332 }
333
334 if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) {
335 /* Minutes don't matter in Alarm comparison */
336 tm->tm_min = -1;
337 } else {
338 tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >>
339 STM32_RTC_ALRMXR_MIN_SHIFT;
340 }
341
342 if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) {
343 /* Seconds don't matter in Alarm comparison */
344 tm->tm_sec = -1;
345 } else {
346 tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >>
347 STM32_RTC_ALRMXR_SEC_SHIFT;
348 }
349
350 bcd2tm(tm);
351
352 alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0;
353 alrm->pending = (isr & STM32_RTC_ISR_ALRAF) ? 1 : 0;
354
355 return 0;
356 }
357
358 static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
359 {
360 struct stm32_rtc *rtc = dev_get_drvdata(dev);
361 unsigned int isr, cr;
362
363 cr = readl_relaxed(rtc->base + STM32_RTC_CR);
364
365 stm32_rtc_wpr_unlock(rtc);
366
367 /* We expose Alarm A to the kernel */
368 if (enabled)
369 cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
370 else
371 cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
372 writel_relaxed(cr, rtc->base + STM32_RTC_CR);
373
374 /* Clear event flag, otherwise new events won't be received */
375 isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
376 isr &= ~STM32_RTC_ISR_ALRAF;
377 writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
378
379 stm32_rtc_wpr_lock(rtc);
380
381 return 0;
382 }
383
384 static int stm32_rtc_valid_alrm(struct stm32_rtc *rtc, struct rtc_time *tm)
385 {
386 int cur_day, cur_mon, cur_year, cur_hour, cur_min, cur_sec;
387 unsigned int dr = readl_relaxed(rtc->base + STM32_RTC_DR);
388 unsigned int tr = readl_relaxed(rtc->base + STM32_RTC_TR);
389
390 cur_day = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
391 cur_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
392 cur_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
393 cur_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
394 cur_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
395 cur_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
396
397 /*
398 * Assuming current date is M-D-Y H:M:S.
399 * RTC alarm can't be set on a specific month and year.
400 * So the valid alarm range is:
401 * M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S
402 * with a specific case for December...
403 */
404 if ((((tm->tm_year > cur_year) &&
405 (tm->tm_mon == 0x1) && (cur_mon == 0x12)) ||
406 ((tm->tm_year == cur_year) &&
407 (tm->tm_mon <= cur_mon + 1))) &&
408 ((tm->tm_mday > cur_day) ||
409 ((tm->tm_mday == cur_day) &&
410 ((tm->tm_hour > cur_hour) ||
411 ((tm->tm_hour == cur_hour) && (tm->tm_min > cur_min)) ||
412 ((tm->tm_hour == cur_hour) && (tm->tm_min == cur_min) &&
413 (tm->tm_sec >= cur_sec))))))
414 return 0;
415
416 return -EINVAL;
417 }
418
419 static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
420 {
421 struct stm32_rtc *rtc = dev_get_drvdata(dev);
422 struct rtc_time *tm = &alrm->time;
423 unsigned int cr, isr, alrmar;
424 int ret = 0;
425
426 tm2bcd(tm);
427
428 /*
429 * RTC alarm can't be set on a specific date, unless this date is
430 * up to the same day of month next month.
431 */
432 if (stm32_rtc_valid_alrm(rtc, tm) < 0) {
433 dev_err(dev, "Alarm can be set only on upcoming month.\n");
434 return -EINVAL;
435 }
436
437 alrmar = 0;
438 /* tm_year and tm_mon are not used because not supported by RTC */
439 alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) &
440 STM32_RTC_ALRMXR_DATE;
441 /* 24-hour format */
442 alrmar &= ~STM32_RTC_ALRMXR_PM;
443 alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) &
444 STM32_RTC_ALRMXR_HOUR;
445 alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) &
446 STM32_RTC_ALRMXR_MIN;
447 alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) &
448 STM32_RTC_ALRMXR_SEC;
449
450 stm32_rtc_wpr_unlock(rtc);
451
452 /* Disable Alarm */
453 cr = readl_relaxed(rtc->base + STM32_RTC_CR);
454 cr &= ~STM32_RTC_CR_ALRAE;
455 writel_relaxed(cr, rtc->base + STM32_RTC_CR);
456
457 /*
458 * Poll Alarm write flag to be sure that Alarm update is allowed: it
459 * takes around 2 ck_rtc clock cycles
460 */
461 ret = readl_relaxed_poll_timeout_atomic(rtc->base + STM32_RTC_ISR,
462 isr,
463 (isr & STM32_RTC_ISR_ALRAWF),
464 10, 100000);
465
466 if (ret) {
467 dev_err(dev, "Alarm update not allowed\n");
468 goto end;
469 }
470
471 /* Write to Alarm register */
472 writel_relaxed(alrmar, rtc->base + STM32_RTC_ALRMAR);
473
474 if (alrm->enabled)
475 stm32_rtc_alarm_irq_enable(dev, 1);
476 else
477 stm32_rtc_alarm_irq_enable(dev, 0);
478
479 end:
480 stm32_rtc_wpr_lock(rtc);
481
482 return ret;
483 }
484
485 static const struct rtc_class_ops stm32_rtc_ops = {
486 .read_time = stm32_rtc_read_time,
487 .set_time = stm32_rtc_set_time,
488 .read_alarm = stm32_rtc_read_alarm,
489 .set_alarm = stm32_rtc_set_alarm,
490 .alarm_irq_enable = stm32_rtc_alarm_irq_enable,
491 };
492
493 static const struct of_device_id stm32_rtc_of_match[] = {
494 { .compatible = "st,stm32-rtc" },
495 {}
496 };
497 MODULE_DEVICE_TABLE(of, stm32_rtc_of_match);
498
499 static int stm32_rtc_init(struct platform_device *pdev,
500 struct stm32_rtc *rtc)
501 {
502 unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
503 unsigned int rate;
504 int ret = 0;
505
506 rate = clk_get_rate(rtc->ck_rtc);
507
508 /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
509 pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
510 pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
511
512 for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
513 pred_s = (rate / (pred_a + 1)) - 1;
514
515 if (((pred_s + 1) * (pred_a + 1)) == rate)
516 break;
517 }
518
519 /*
520 * Can't find a 1Hz, so give priority to RTC power consumption
521 * by choosing the higher possible value for prediv_a
522 */
523 if ((pred_s > pred_s_max) || (pred_a > pred_a_max)) {
524 pred_a = pred_a_max;
525 pred_s = (rate / (pred_a + 1)) - 1;
526
527 dev_warn(&pdev->dev, "ck_rtc is %s\n",
528 (rate < ((pred_a + 1) * (pred_s + 1))) ?
529 "fast" : "slow");
530 }
531
532 stm32_rtc_wpr_unlock(rtc);
533
534 ret = stm32_rtc_enter_init_mode(rtc);
535 if (ret) {
536 dev_err(&pdev->dev,
537 "Can't enter in init mode. Prescaler config failed.\n");
538 goto end;
539 }
540
541 prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
542 writel_relaxed(prer, rtc->base + STM32_RTC_PRER);
543 prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
544 writel_relaxed(prer, rtc->base + STM32_RTC_PRER);
545
546 /* Force 24h time format */
547 cr = readl_relaxed(rtc->base + STM32_RTC_CR);
548 cr &= ~STM32_RTC_CR_FMT;
549 writel_relaxed(cr, rtc->base + STM32_RTC_CR);
550
551 stm32_rtc_exit_init_mode(rtc);
552
553 ret = stm32_rtc_wait_sync(rtc);
554 end:
555 stm32_rtc_wpr_lock(rtc);
556
557 return ret;
558 }
559
560 static int stm32_rtc_probe(struct platform_device *pdev)
561 {
562 struct stm32_rtc *rtc;
563 struct resource *res;
564 int ret;
565
566 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
567 if (!rtc)
568 return -ENOMEM;
569
570 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
571 rtc->base = devm_ioremap_resource(&pdev->dev, res);
572 if (IS_ERR(rtc->base))
573 return PTR_ERR(rtc->base);
574
575 rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
576 "st,syscfg");
577 if (IS_ERR(rtc->dbp)) {
578 dev_err(&pdev->dev, "no st,syscfg\n");
579 return PTR_ERR(rtc->dbp);
580 }
581
582 rtc->ck_rtc = devm_clk_get(&pdev->dev, NULL);
583 if (IS_ERR(rtc->ck_rtc)) {
584 dev_err(&pdev->dev, "no ck_rtc clock");
585 return PTR_ERR(rtc->ck_rtc);
586 }
587
588 ret = clk_prepare_enable(rtc->ck_rtc);
589 if (ret)
590 return ret;
591
592 regmap_update_bits(rtc->dbp, PWR_CR, PWR_CR_DBP, PWR_CR_DBP);
593
594 /*
595 * After a system reset, RTC_ISR.INITS flag can be read to check if
596 * the calendar has been initalized or not. INITS flag is reset by a
597 * power-on reset (no vbat, no power-supply). It is not reset if
598 * ck_rtc parent clock has changed (so RTC prescalers need to be
599 * changed). That's why we cannot rely on this flag to know if RTC
600 * init has to be done.
601 */
602 ret = stm32_rtc_init(pdev, rtc);
603 if (ret)
604 goto err;
605
606 rtc->irq_alarm = platform_get_irq(pdev, 0);
607 if (rtc->irq_alarm <= 0) {
608 dev_err(&pdev->dev, "no alarm irq\n");
609 ret = rtc->irq_alarm;
610 goto err;
611 }
612
613 platform_set_drvdata(pdev, rtc);
614
615 ret = device_init_wakeup(&pdev->dev, true);
616 if (ret)
617 dev_warn(&pdev->dev,
618 "alarm won't be able to wake up the system");
619
620 rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
621 &stm32_rtc_ops, THIS_MODULE);
622 if (IS_ERR(rtc->rtc_dev)) {
623 ret = PTR_ERR(rtc->rtc_dev);
624 dev_err(&pdev->dev, "rtc device registration failed, err=%d\n",
625 ret);
626 goto err;
627 }
628
629 /* Handle RTC alarm interrupts */
630 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL,
631 stm32_rtc_alarm_irq,
632 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
633 pdev->name, rtc);
634 if (ret) {
635 dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n",
636 rtc->irq_alarm);
637 goto err;
638 }
639
640 /*
641 * If INITS flag is reset (calendar year field set to 0x00), calendar
642 * must be initialized
643 */
644 if (!(readl_relaxed(rtc->base + STM32_RTC_ISR) & STM32_RTC_ISR_INITS))
645 dev_warn(&pdev->dev, "Date/Time must be initialized\n");
646
647 return 0;
648 err:
649 clk_disable_unprepare(rtc->ck_rtc);
650
651 regmap_update_bits(rtc->dbp, PWR_CR, PWR_CR_DBP, 0);
652
653 device_init_wakeup(&pdev->dev, false);
654
655 return ret;
656 }
657
658 static int stm32_rtc_remove(struct platform_device *pdev)
659 {
660 struct stm32_rtc *rtc = platform_get_drvdata(pdev);
661 unsigned int cr;
662
663 /* Disable interrupts */
664 stm32_rtc_wpr_unlock(rtc);
665 cr = readl_relaxed(rtc->base + STM32_RTC_CR);
666 cr &= ~STM32_RTC_CR_ALRAIE;
667 writel_relaxed(cr, rtc->base + STM32_RTC_CR);
668 stm32_rtc_wpr_lock(rtc);
669
670 clk_disable_unprepare(rtc->ck_rtc);
671
672 /* Enable backup domain write protection */
673 regmap_update_bits(rtc->dbp, PWR_CR, PWR_CR_DBP, 0);
674
675 device_init_wakeup(&pdev->dev, false);
676
677 return 0;
678 }
679
680 #ifdef CONFIG_PM_SLEEP
681 static int stm32_rtc_suspend(struct device *dev)
682 {
683 struct stm32_rtc *rtc = dev_get_drvdata(dev);
684
685 if (device_may_wakeup(dev))
686 return enable_irq_wake(rtc->irq_alarm);
687
688 return 0;
689 }
690
691 static int stm32_rtc_resume(struct device *dev)
692 {
693 struct stm32_rtc *rtc = dev_get_drvdata(dev);
694 int ret = 0;
695
696 ret = stm32_rtc_wait_sync(rtc);
697 if (ret < 0)
698 return ret;
699
700 if (device_may_wakeup(dev))
701 return disable_irq_wake(rtc->irq_alarm);
702
703 return ret;
704 }
705 #endif
706
707 static SIMPLE_DEV_PM_OPS(stm32_rtc_pm_ops,
708 stm32_rtc_suspend, stm32_rtc_resume);
709
710 static struct platform_driver stm32_rtc_driver = {
711 .probe = stm32_rtc_probe,
712 .remove = stm32_rtc_remove,
713 .driver = {
714 .name = DRIVER_NAME,
715 .pm = &stm32_rtc_pm_ops,
716 .of_match_table = stm32_rtc_of_match,
717 },
718 };
719
720 module_platform_driver(stm32_rtc_driver);
721
722 MODULE_ALIAS("platform:" DRIVER_NAME);
723 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
724 MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver");
725 MODULE_LICENSE("GPL v2");
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