drivers/sbus/char/cd180.h

   1
   2 /* Definitions for Cirrus Logic CL-CD180 8-port async mux chip */
   3 #define CD180_NCH       8       /* Total number of channels                */
   4 #define CD180_TPC       16      /* Ticks per character                     */
   5 #define CD180_NFIFO     8       /* TX FIFO size                            */
   6
   7 /* Global registers */
   8 #define CD180_GFRCR     0x6b    /* Global Firmware Revision Code Register  */
   9 #define CD180_SRCR      0x66    /* Service Request Configuration Register  */
  10 #define CD180_PPRH      0x70    /* Prescaler Period Register High          */
  11 #define CD180_PPRL      0x71    /* Prescaler Period Register Low           */
  12 #define CD180_MSMR      0x61    /* Modem Service Match Register            */
  13 #define CD180_TSMR      0x62    /* Transmit Service Match Register         */
  14 #define CD180_RSMR      0x63    /* Receive Service Match Register          */
  15 #define CD180_GSVR      0x40    /* Global Service Vector Register          */
  16 #define CD180_SRSR      0x65    /* Service Request Status Register         */
  17 #define CD180_GSCR      0x41    /* Global Service Channel Register         */
  18 #define CD180_CAR       0x64    /* Channel Access Register                 */
  19
  20 /* Indexed registers */
  21 #define CD180_RDCR      0x07    /* Receive Data Count Register             */
  22 #define CD180_RDR       0x78    /* Receiver Data Register                  */
  23 #define CD180_RCSR      0x7a    /* Receiver Character Status Register      */
  24 #define CD180_TDR       0x7b    /* Transmit Data Register                  */
  25 #define CD180_EOSRR     0x7f    /* End of Service Request Register         */
  26
  27 /* Channel Registers */
  28 #define CD180_SRER      0x02    /* Service Request Enable Register         */
  29 #define CD180_CCR       0x01    /* Channel Command Register                */
  30 #define CD180_COR1      0x03    /* Channel Option Register 1               */
  31 #define CD180_COR2      0x04    /* Channel Option Register 2               */
  32 #define CD180_COR3      0x05    /* Channel Option Register 3               */
  33 #define CD180_CCSR      0x06    /* Channel Control Status Register         */
  34 #define CD180_RTPR      0x18    /* Receive Timeout Period Register         */
  35 #define CD180_RBPRH     0x31    /* Receive Bit Rate Period Register High  */
  36 #define CD180_RBPRL     0x32    /* Receive Bit Rate Period Register Low   */
  37 #define CD180_TBPRH     0x39    /* Transmit Bit Rate Period Register High */
  38 #define CD180_TBPRL     0x3a    /* Transmit Bit Rate Period Register Low  */
  39 #define CD180_SCHR1     0x09    /* Special Character Register 1            */
  40 #define CD180_SCHR2     0x0a    /* Special Character Register 2            */
  41 #define CD180_SCHR3     0x0b    /* Special Character Register 3            */
  42 #define CD180_SCHR4     0x0c    /* Special Character Register 4            */
  43 #define CD180_MCR       0x12    /* Modem Change Register                   */
  44 #define CD180_MCOR1     0x10    /* Modem Change Option 1 Register          */
  45 #define CD180_MCOR2     0x11    /* Modem Change Option 2 Register          */
  46 #define CD180_MSVR      0x28    /* Modem Signal Value Register             */
  47 #define CD180_MSVRTS    0x29    /* Modem Signal Value RTS                  */
  48 #define CD180_MSVDTR    0x2a    /* Modem Signal Value DTR                  */
  49
  50 /* Global Interrupt Vector Register (R/W) */
  51
  52 #define GSVR_ITMASK     0x07     /* Interrupt type mask                     */
  53 #define  GSVR_IT_MDM     0x01    /* Modem Signal Change Interrupt           */
  54 #define  GSVR_IT_TX      0x02    /* Transmit Data Interrupt                 */
  55 #define  GSVR_IT_RGD     0x03    /* Receive Good Data Interrupt             */
  56 #define  GSVR_IT_REXC    0x07    /* Receive Exception Interrupt             */
  57
  58
  59 /* Global Interrupt Channel Register (R/W) */
  60
  61 #define GSCR_CHAN       0x1c    /* Channel Number Mask                     */
  62 #define GSCR_CHAN_OFF   2       /* Channel Number Offset                   */
  63
  64
  65 /* Channel Address Register (R/W) */
  66
  67 #define CAR_CHAN        0x07    /* Channel Number Mask                     */
  68
  69
  70 /* Receive Character Status Register (R/O) */
  71
  72 #define RCSR_TOUT       0x80    /* Rx Timeout                              */
  73 #define RCSR_SCDET      0x70    /* Special Character Detected Mask         */
  74 #define  RCSR_NO_SC      0x00   /* No Special Characters Detected          */
  75 #define  RCSR_SC_1       0x10   /* Special Char 1 (or 1 & 3) Detected      */
  76 #define  RCSR_SC_2       0x20   /* Special Char 2 (or 2 & 4) Detected      */
  77 #define  RCSR_SC_3       0x30   /* Special Char 3 Detected                 */
  78 #define  RCSR_SC_4       0x40   /* Special Char 4 Detected                 */
  79 #define RCSR_BREAK      0x08    /* Break has been detected                 */
  80 #define RCSR_PE         0x04    /* Parity Error                            */
  81 #define RCSR_FE         0x02    /* Frame Error                             */
  82 #define RCSR_OE         0x01    /* Overrun Error                           */
  83
  84
  85 /* Channel Command Register (R/W) (commands in groups can be OR-ed) */
  86
  87 #define CCR_HARDRESET   0x81    /* Reset the chip                          */
  88
  89 #define CCR_SOFTRESET   0x80    /* Soft Channel Reset                      */
  90
  91 #define CCR_CORCHG1     0x42    /* Channel Option Register 1 Changed       */
  92 #define CCR_CORCHG2     0x44    /* Channel Option Register 2 Changed       */
  93 #define CCR_CORCHG3     0x48    /* Channel Option Register 3 Changed       */
  94
  95 #define CCR_SSCH1       0x21    /* Send Special Character 1                */
  96
  97 #define CCR_SSCH2       0x22    /* Send Special Character 2                */
  98
  99 #define CCR_SSCH3       0x23    /* Send Special Character 3                */
 100
 101 #define CCR_SSCH4       0x24    /* Send Special Character 4                */
 102
 103 #define CCR_TXEN        0x18    /* Enable Transmitter                      */
 104 #define CCR_RXEN        0x12    /* Enable Receiver                         */
 105
 106 #define CCR_TXDIS       0x14    /* Disable Transmitter                     */
 107 #define CCR_RXDIS       0x11    /* Disable Receiver                        */
 108
 109
 110 /* Service Request Enable Register (R/W) */
 111
 112 #define SRER_DSR         0x80    /* Enable interrupt on DSR change          */
 113 #define SRER_CD          0x40    /* Enable interrupt on CD change           */
 114 #define SRER_CTS         0x20    /* Enable interrupt on CTS change          */
 115 #define SRER_RXD         0x10    /* Enable interrupt on Receive Data        */
 116 #define SRER_RXSC        0x08    /* Enable interrupt on Receive Spec. Char  */
 117 #define SRER_TXRDY       0x04    /* Enable interrupt on TX FIFO empty       */
 118 #define SRER_TXEMPTY     0x02    /* Enable interrupt on TX completely empty */
 119 #define SRER_RET         0x01    /* Enable interrupt on RX Exc. Timeout     */
 120
 121
 122 /* Channel Option Register 1 (R/W) */
 123
 124 #define COR1_ODDP       0x80    /* Odd Parity                              */
 125 #define COR1_PARMODE    0x60    /* Parity Mode mask                        */
 126 #define  COR1_NOPAR      0x00   /* No Parity                               */
 127 #define  COR1_FORCEPAR   0x20   /* Force Parity                            */
 128 #define  COR1_NORMPAR    0x40   /* Normal Parity                           */
 129 #define COR1_IGNORE     0x10    /* Ignore Parity on RX                     */
 130 #define COR1_STOPBITS   0x0c    /* Number of Stop Bits                     */
 131 #define  COR1_1SB        0x00   /* 1 Stop Bit                              */
 132 #define  COR1_15SB       0x04   /* 1.5 Stop Bits                           */
 133 #define  COR1_2SB        0x08   /* 2 Stop Bits                             */
 134 #define COR1_CHARLEN    0x03    /* Character Length                        */
 135 #define  COR1_5BITS      0x00   /* 5 bits                                  */
 136 #define  COR1_6BITS      0x01   /* 6 bits                                  */
 137 #define  COR1_7BITS      0x02   /* 7 bits                                  */
 138 #define  COR1_8BITS      0x03   /* 8 bits                                  */
 139
 140
 141 /* Channel Option Register 2 (R/W) */
 142
 143 #define COR2_IXM        0x80    /* Implied XON mode                        */
 144 #define COR2_TXIBE      0x40    /* Enable In-Band (XON/XOFF) Flow Control  */
 145 #define COR2_ETC        0x20    /* Embedded Tx Commands Enable             */
 146 #define COR2_LLM        0x10    /* Local Loopback Mode                     */
 147 #define COR2_RLM        0x08    /* Remote Loopback Mode                    */
 148 #define COR2_RTSAO      0x04    /* RTS Automatic Output Enable             */
 149 #define COR2_CTSAE      0x02    /* CTS Automatic Enable                    */
 150 #define COR2_DSRAE      0x01    /* DSR Automatic Enable                    */
 151
 152
 153 /* Channel Option Register 3 (R/W) */
 154
 155 #define COR3_XONCH      0x80    /* XON is a pair of characters (1 & 3)     */
 156 #define COR3_XOFFCH     0x40    /* XOFF is a pair of characters (2 & 4)    */
 157 #define COR3_FCT        0x20    /* Flow-Control Transparency Mode          */
 158 #define COR3_SCDE       0x10    /* Special Character Detection Enable      */
 159 #define COR3_RXTH       0x0f    /* RX FIFO Threshold value (1-8)           */
 160
 161
 162 /* Channel Control Status Register (R/O) */
 163
 164 #define CCSR_RXEN       0x80    /* Receiver Enabled                        */
 165 #define CCSR_RXFLOFF    0x40    /* Receive Flow Off (XOFF was sent)        */
 166 #define CCSR_RXFLON     0x20    /* Receive Flow On (XON was sent)          */
 167 #define CCSR_TXEN       0x08    /* Transmitter Enabled                     */
 168 #define CCSR_TXFLOFF    0x04    /* Transmit Flow Off (got XOFF)            */
 169 #define CCSR_TXFLON     0x02    /* Transmit Flow On (got XON)              */
 170
 171
 172 /* Modem Change Option Register 1 (R/W) */
 173
 174 #define MCOR1_DSRZD     0x80    /* Detect 0->1 transition of DSR           */
 175 #define MCOR1_CDZD      0x40    /* Detect 0->1 transition of CD            */
 176 #define MCOR1_CTSZD     0x20    /* Detect 0->1 transition of CTS           */
 177 #define MCOR1_DTRTH     0x0f    /* Auto DTR flow control Threshold (1-8)   */
 178 #define  MCOR1_NODTRFC   0x0     /* Automatic DTR flow control disabled     */
 179
 180
 181 /* Modem Change Option Register 2 (R/W) */
 182
 183 #define MCOR2_DSROD     0x80    /* Detect 1->0 transition of DSR           */
 184 #define MCOR2_CDOD      0x40    /* Detect 1->0 transition of CD            */
 185 #define MCOR2_CTSOD     0x20    /* Detect 1->0 transition of CTS           */
 186
 187
 188 /* Modem Change Register (R/W) */
 189
 190 #define MCR_DSRCHG      0x80    /* DSR Changed                             */
 191 #define MCR_CDCHG       0x40    /* CD Changed                              */
 192 #define MCR_CTSCHG      0x20    /* CTS Changed                             */
 193
 194
 195 /* Modem Signal Value Register (R/W) */
 196
 197 #define MSVR_DSR        0x80    /* Current state of DSR input              */
 198 #define MSVR_CD         0x40    /* Current state of CD input               */
 199 #define MSVR_CTS        0x20    /* Current state of CTS input              */
 200 #define MSVR_DTR        0x02    /* Current state of DTR output             */
 201 #define MSVR_RTS        0x01    /* Current state of RTS output             */
 202
 203
 204 /* Service Request Status Register */
 205
 206 #define SRSR_CMASK      0xC0    /* Current Service Context Mask            */
 207 #define  SRSR_CNONE     0x00    /* Not in a service context                */
 208 #define  SRSR_CRX       0x40    /* Rx Context                              */
 209 #define  SRSR_CTX       0x80    /* Tx Context                              */
 210 #define  SRSR_CMDM      0xC0    /* Modem Context                           */
 211 #define SRSR_ANYINT     0x6F    /* Any interrupt flag                      */
 212 #define SRSR_RINT       0x10    /* Receive Interrupt                       */
 213 #define SRSR_TINT       0x04    /* Transmit Interrupt                      */
 214 #define SRSR_MINT       0x01    /* Modem Interrupt                         */
 215 #define SRSR_REXT       0x20    /* Receive External Interrupt              */
 216 #define SRSR_TEXT       0x08    /* Transmit External Interrupt             */
 217 #define SRSR_MEXT       0x02    /* Modem External Interrupt                */
 218
 219
 220 /* Service Request Configuration Register */
 221
 222 #define SRCR_PKGTYPE    0x80
 223 #define SRCR_REGACKEN   0x40
 224 #define SRCR_DAISYEN    0x20
 225 #define SRCR_GLOBPRI    0x10
 226 #define SRCR_UNFAIR     0x08
 227 #define SRCR_AUTOPRI    0x02
 228 #define SRCR_PRISEL     0x01
 229
 230 /* Values for register-based Interrupt ACKs */
 231 #define CD180_ACK_MINT  0x75    /* goes to MSMR                            */
 232 #define CD180_ACK_TINT  0x76    /* goes to TSMR                            */
 233 #define CD180_ACK_RINT  0x77    /* goes to RSMR                            */
 234
 235 /* Escape characters */
 236
 237 #define CD180_C_ESC     0x00    /* Escape character                        */
 238 #define CD180_C_SBRK    0x81    /* Start sending BREAK                     */
 239 #define CD180_C_DELAY   0x82    /* Delay output                            */
 240 #define CD180_C_EBRK    0x83    /* Stop sending BREAK                      */