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scsi: aacraid: Log count info of scsi cmds before reset
[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / aacraid / aacraid.h
1 /*
2 * Adaptec AAC series RAID controller driver
3 * (c) Copyright 2001 Red Hat Inc. <alan@redhat.com>
4 *
5 * based on the old aacraid driver that is..
6 * Adaptec aacraid device driver for Linux.
7 *
8 * Copyright (c) 2000-2010 Adaptec, Inc.
9 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
10 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Module Name:
27 * aacraid.h
28 *
29 * Abstract: Contains all routines for control of the aacraid driver
30 *
31 */
32
33 #ifndef _AACRAID_H_
34 #define _AACRAID_H_
35 #ifndef dprintk
36 # define dprintk(x)
37 #endif
38 /* eg: if (nblank(dprintk(x))) */
39 #define _nblank(x) #x
40 #define nblank(x) _nblank(x)[0]
41
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44
45 /*------------------------------------------------------------------------------
46 * D E F I N E S
47 *----------------------------------------------------------------------------*/
48
49 #define AAC_MAX_MSIX 32 /* vectors */
50 #define AAC_PCI_MSI_ENABLE 0x8000
51
52 enum {
53 AAC_ENABLE_INTERRUPT = 0x0,
54 AAC_DISABLE_INTERRUPT,
55 AAC_ENABLE_MSIX,
56 AAC_DISABLE_MSIX,
57 AAC_CLEAR_AIF_BIT,
58 AAC_CLEAR_SYNC_BIT,
59 AAC_ENABLE_INTX
60 };
61
62 #define AAC_INT_MODE_INTX (1<<0)
63 #define AAC_INT_MODE_MSI (1<<1)
64 #define AAC_INT_MODE_AIF (1<<2)
65 #define AAC_INT_MODE_SYNC (1<<3)
66 #define AAC_INT_MODE_MSIX (1<<16)
67
68 #define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb
69 #define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa
70 #define AAC_INT_DISABLE_ALL 0xffffffff
71
72 /* Bit definitions in IOA->Host Interrupt Register */
73 #define PMC_TRANSITION_TO_OPERATIONAL (1<<31)
74 #define PMC_IOARCB_TRANSFER_FAILED (1<<28)
75 #define PMC_IOA_UNIT_CHECK (1<<27)
76 #define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26)
77 #define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25)
78 #define PMC_IOARRIN_LOST (1<<4)
79 #define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3)
80 #define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2)
81 #define PMC_HOST_RRQ_VALID (1<<1)
82 #define PMC_OPERATIONAL_STATUS (1<<31)
83 #define PMC_ALLOW_MSIX_VECTOR0 (1<<0)
84
85 #define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \
86 PMC_IOA_UNIT_CHECK | \
87 PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \
88 PMC_IOARRIN_LOST | \
89 PMC_SYSTEM_BUS_MMIO_ERROR | \
90 PMC_IOA_PROCESSOR_IN_ERROR_STATE)
91
92 #define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \
93 PMC_HOST_RRQ_VALID | \
94 PMC_TRANSITION_TO_OPERATIONAL | \
95 PMC_ALLOW_MSIX_VECTOR0)
96 #define PMC_GLOBAL_INT_BIT2 0x00000004
97 #define PMC_GLOBAL_INT_BIT0 0x00000001
98
99 #ifndef AAC_DRIVER_BUILD
100 # define AAC_DRIVER_BUILD 50792
101 # define AAC_DRIVER_BRANCH "-custom"
102 #endif
103 #define MAXIMUM_NUM_CONTAINERS 32
104
105 #define AAC_NUM_MGT_FIB 8
106 #define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB)
107 #define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB)
108
109 #define AAC_MAX_LUN 256
110
111 #define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff)
112 #define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256)
113
114 #define AAC_DEBUG_INSTRUMENT_AIF_DELETE
115
116 #define AAC_MAX_NATIVE_TARGETS 1024
117 /* Thor: 5 phys. buses: #0: empty, 1-4: 256 targets each */
118 #define AAC_MAX_BUSES 5
119 #define AAC_MAX_TARGETS 256
120 #define AAC_MAX_NATIVE_SIZE 2048
121 #define FW_ERROR_BUFFER_SIZE 512
122
123 /* Thor AIF events */
124 #define SA_AIF_HOTPLUG (1<<1)
125 #define SA_AIF_HARDWARE (1<<2)
126 #define SA_AIF_PDEV_CHANGE (1<<4)
127 #define SA_AIF_LDEV_CHANGE (1<<5)
128 #define SA_AIF_BPSTAT_CHANGE (1<<30)
129 #define SA_AIF_BPCFG_CHANGE (1<<31)
130
131 #define HBA_MAX_SG_EMBEDDED 28
132 #define HBA_MAX_SG_SEPARATE 90
133 #define HBA_SENSE_DATA_LEN_MAX 32
134 #define HBA_REQUEST_TAG_ERROR_FLAG 0x00000002
135 #define HBA_SGL_FLAGS_EXT 0x80000000UL
136
137 struct aac_hba_sgl {
138 u32 addr_lo; /* Lower 32-bits of SGL element address */
139 u32 addr_hi; /* Upper 32-bits of SGL element address */
140 u32 len; /* Length of SGL element in bytes */
141 u32 flags; /* SGL element flags */
142 };
143
144 enum {
145 HBA_IU_TYPE_SCSI_CMD_REQ = 0x40,
146 HBA_IU_TYPE_SCSI_TM_REQ = 0x41,
147 HBA_IU_TYPE_SATA_REQ = 0x42,
148 HBA_IU_TYPE_RESP = 0x60,
149 HBA_IU_TYPE_COALESCED_RESP = 0x61,
150 HBA_IU_TYPE_INT_COALESCING_CFG_REQ = 0x70
151 };
152
153 enum {
154 HBA_CMD_BYTE1_DATA_DIR_IN = 0x1,
155 HBA_CMD_BYTE1_DATA_DIR_OUT = 0x2,
156 HBA_CMD_BYTE1_DATA_TYPE_DDR = 0x4,
157 HBA_CMD_BYTE1_CRYPTO_ENABLE = 0x8
158 };
159
160 enum {
161 HBA_CMD_BYTE1_BITOFF_DATA_DIR_IN = 0x0,
162 HBA_CMD_BYTE1_BITOFF_DATA_DIR_OUT,
163 HBA_CMD_BYTE1_BITOFF_DATA_TYPE_DDR,
164 HBA_CMD_BYTE1_BITOFF_CRYPTO_ENABLE
165 };
166
167 enum {
168 HBA_RESP_DATAPRES_NO_DATA = 0x0,
169 HBA_RESP_DATAPRES_RESPONSE_DATA,
170 HBA_RESP_DATAPRES_SENSE_DATA
171 };
172
173 enum {
174 HBA_RESP_SVCRES_TASK_COMPLETE = 0x0,
175 HBA_RESP_SVCRES_FAILURE,
176 HBA_RESP_SVCRES_TMF_COMPLETE,
177 HBA_RESP_SVCRES_TMF_SUCCEEDED,
178 HBA_RESP_SVCRES_TMF_REJECTED,
179 HBA_RESP_SVCRES_TMF_LUN_INVALID
180 };
181
182 enum {
183 HBA_RESP_STAT_IO_ERROR = 0x1,
184 HBA_RESP_STAT_IO_ABORTED,
185 HBA_RESP_STAT_NO_PATH_TO_DEVICE,
186 HBA_RESP_STAT_INVALID_DEVICE,
187 HBA_RESP_STAT_HBAMODE_DISABLED = 0xE,
188 HBA_RESP_STAT_UNDERRUN = 0x51,
189 HBA_RESP_STAT_OVERRUN = 0x75
190 };
191
192 struct aac_hba_cmd_req {
193 u8 iu_type; /* HBA information unit type */
194 /*
195 * byte1:
196 * [1:0] DIR - 0=No data, 0x1 = IN, 0x2 = OUT
197 * [2] TYPE - 0=PCI, 1=DDR
198 * [3] CRYPTO_ENABLE - 0=Crypto disabled, 1=Crypto enabled
199 */
200 u8 byte1;
201 u8 reply_qid; /* Host reply queue to post response to */
202 u8 reserved1;
203 __le32 it_nexus; /* Device handle for the request */
204 __le32 request_id; /* Sender context */
205 /* Lower 32-bits of tweak value for crypto enabled IOs */
206 __le32 tweak_value_lo;
207 u8 cdb[16]; /* SCSI CDB of the command */
208 u8 lun[8]; /* SCSI LUN of the command */
209
210 /* Total data length in bytes to be read/written (if any) */
211 __le32 data_length;
212
213 /* [2:0] Task Attribute, [6:3] Command Priority */
214 u8 attr_prio;
215
216 /* Number of SGL elements embedded in the HBA req */
217 u8 emb_data_desc_count;
218
219 __le16 dek_index; /* DEK index for crypto enabled IOs */
220
221 /* Lower 32-bits of reserved error data target location on the host */
222 __le32 error_ptr_lo;
223
224 /* Upper 32-bits of reserved error data target location on the host */
225 __le32 error_ptr_hi;
226
227 /* Length of reserved error data area on the host in bytes */
228 __le32 error_length;
229
230 /* Upper 32-bits of tweak value for crypto enabled IOs */
231 __le32 tweak_value_hi;
232
233 struct aac_hba_sgl sge[HBA_MAX_SG_SEPARATE+2]; /* SG list space */
234
235 /*
236 * structure must not exceed
237 * AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE
238 */
239 };
240
241 /* Task Management Functions (TMF) */
242 #define HBA_TMF_ABORT_TASK 0x01
243 #define HBA_TMF_LUN_RESET 0x08
244
245 struct aac_hba_tm_req {
246 u8 iu_type; /* HBA information unit type */
247 u8 reply_qid; /* Host reply queue to post response to */
248 u8 tmf; /* Task management function */
249 u8 reserved1;
250
251 __le32 it_nexus; /* Device handle for the command */
252
253 u8 lun[8]; /* SCSI LUN */
254
255 /* Used to hold sender context. */
256 __le32 request_id; /* Sender context */
257 __le32 reserved2;
258
259 /* Request identifier of managed task */
260 __le32 managed_request_id; /* Sender context being managed */
261 __le32 reserved3;
262
263 /* Lower 32-bits of reserved error data target location on the host */
264 __le32 error_ptr_lo;
265 /* Upper 32-bits of reserved error data target location on the host */
266 __le32 error_ptr_hi;
267 /* Length of reserved error data area on the host in bytes */
268 __le32 error_length;
269 };
270
271 struct aac_hba_reset_req {
272 u8 iu_type; /* HBA information unit type */
273 /* 0 - reset specified device, 1 - reset all devices */
274 u8 reset_type;
275 u8 reply_qid; /* Host reply queue to post response to */
276 u8 reserved1;
277
278 __le32 it_nexus; /* Device handle for the command */
279 __le32 request_id; /* Sender context */
280 /* Lower 32-bits of reserved error data target location on the host */
281 __le32 error_ptr_lo;
282 /* Upper 32-bits of reserved error data target location on the host */
283 __le32 error_ptr_hi;
284 /* Length of reserved error data area on the host in bytes */
285 __le32 error_length;
286 };
287
288 struct aac_hba_resp {
289 u8 iu_type; /* HBA information unit type */
290 u8 reserved1[3];
291 __le32 request_identifier; /* sender context */
292 __le32 reserved2;
293 u8 service_response; /* SCSI service response */
294 u8 status; /* SCSI status */
295 u8 datapres; /* [1:0] - data present, [7:2] - reserved */
296 u8 sense_response_data_len; /* Sense/response data length */
297 __le32 residual_count; /* Residual data length in bytes */
298 /* Sense/response data */
299 u8 sense_response_buf[HBA_SENSE_DATA_LEN_MAX];
300 };
301
302 struct aac_native_hba {
303 union {
304 struct aac_hba_cmd_req cmd;
305 struct aac_hba_tm_req tmr;
306 u8 cmd_bytes[AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE];
307 } cmd;
308 union {
309 struct aac_hba_resp err;
310 u8 resp_bytes[FW_ERROR_BUFFER_SIZE];
311 } resp;
312 };
313
314 #define CISS_REPORT_PHYSICAL_LUNS 0xc3
315 #define WRITE_HOST_WELLNESS 0xa5
316 #define CISS_IDENTIFY_PHYSICAL_DEVICE 0x15
317 #define BMIC_IN 0x26
318 #define BMIC_OUT 0x27
319
320 struct aac_ciss_phys_luns_resp {
321 u8 list_length[4]; /* LUN list length (N-7, big endian) */
322 u8 resp_flag; /* extended response_flag */
323 u8 reserved[3];
324 struct _ciss_lun {
325 u8 tid[3]; /* Target ID */
326 u8 bus; /* Bus, flag (bits 6,7) */
327 u8 level3[2];
328 u8 level2[2];
329 u8 node_ident[16]; /* phys. node identifier */
330 } lun[1]; /* List of phys. devices */
331 };
332
333 /*
334 * Interrupts
335 */
336 #define AAC_MAX_HRRQ 64
337
338 struct aac_ciss_identify_pd {
339 u8 scsi_bus; /* SCSI Bus number on controller */
340 u8 scsi_id; /* SCSI ID on this bus */
341 u16 block_size; /* sector size in bytes */
342 u32 total_blocks; /* number for sectors on drive */
343 u32 reserved_blocks; /* controller reserved (RIS) */
344 u8 model[40]; /* Physical Drive Model */
345 u8 serial_number[40]; /* Drive Serial Number */
346 u8 firmware_revision[8]; /* drive firmware revision */
347 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */
348 u8 compaq_drive_stamp; /* 0 means drive not stamped */
349 u8 last_failure_reason;
350
351 u8 flags;
352 u8 more_flags;
353 u8 scsi_lun; /* SCSI LUN for phys drive */
354 u8 yet_more_flags;
355 u8 even_more_flags;
356 u32 spi_speed_rules; /* SPI Speed :Ultra disable diagnose */
357 u8 phys_connector[2]; /* connector number on controller */
358 u8 phys_box_on_bus; /* phys enclosure this drive resides */
359 u8 phys_bay_in_box; /* phys drv bay this drive resides */
360 u32 rpm; /* Drive rotational speed in rpm */
361 u8 device_type; /* type of drive */
362 u8 sata_version; /* only valid when drive_type is SATA */
363 u64 big_total_block_count;
364 u64 ris_starting_lba;
365 u32 ris_size;
366 u8 wwid[20];
367 u8 controller_phy_map[32];
368 u16 phy_count;
369 u8 phy_connected_dev_type[256];
370 u8 phy_to_drive_bay_num[256];
371 u16 phy_to_attached_dev_index[256];
372 u8 box_index;
373 u8 spitfire_support;
374 u16 extra_physical_drive_flags;
375 u8 negotiated_link_rate[256];
376 u8 phy_to_phy_map[256];
377 u8 redundant_path_present_map;
378 u8 redundant_path_failure_map;
379 u8 active_path_number;
380 u16 alternate_paths_phys_connector[8];
381 u8 alternate_paths_phys_box_on_port[8];
382 u8 multi_lun_device_lun_count;
383 u8 minimum_good_fw_revision[8];
384 u8 unique_inquiry_bytes[20];
385 u8 current_temperature_degreesC;
386 u8 temperature_threshold_degreesC;
387 u8 max_temperature_degreesC;
388 u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512 * 2^exp */
389 u16 current_queue_depth_limit;
390 u8 switch_name[10];
391 u16 switch_port;
392 u8 alternate_paths_switch_name[40];
393 u8 alternate_paths_switch_port[8];
394 u16 power_on_hours; /* valid only if gas gauge supported */
395 u16 percent_endurance_used; /* valid only if gas gauge supported. */
396 u8 drive_authentication;
397 u8 smart_carrier_authentication;
398 u8 smart_carrier_app_fw_version;
399 u8 smart_carrier_bootloader_fw_version;
400 u8 SanitizeSecureEraseSupport;
401 u8 DriveKeyFlags;
402 u8 encryption_key_name[64];
403 u32 misc_drive_flags;
404 u16 dek_index;
405 u16 drive_encryption_flags;
406 u8 sanitize_maximum_time[6];
407 u8 connector_info_mode;
408 u8 connector_info_number[4];
409 u8 long_connector_name[64];
410 u8 device_unique_identifier[16];
411 u8 padto_2K[17];
412 } __packed;
413
414 /*
415 * These macros convert from physical channels to virtual channels
416 */
417 #define CONTAINER_CHANNEL (0)
418 #define NATIVE_CHANNEL (1)
419 #define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL)
420 #define CONTAINER_TO_ID(cont) (cont)
421 #define CONTAINER_TO_LUN(cont) (0)
422 #define ENCLOSURE_CHANNEL (3)
423
424 #define PMC_DEVICE_S6 0x28b
425 #define PMC_DEVICE_S7 0x28c
426 #define PMC_DEVICE_S8 0x28d
427 #define PMC_DEVICE_S9 0x28f
428
429 #define aac_phys_to_logical(x) ((x)+1)
430 #define aac_logical_to_phys(x) ((x)?(x)-1:0)
431
432 /*
433 * These macros are for keeping track of
434 * character device state.
435 */
436 #define AAC_CHARDEV_UNREGISTERED (-1)
437 #define AAC_CHARDEV_NEEDS_REINIT (-2)
438
439 /* #define AAC_DETAILED_STATUS_INFO */
440
441 struct diskparm
442 {
443 int heads;
444 int sectors;
445 int cylinders;
446 };
447
448
449 /*
450 * Firmware constants
451 */
452
453 #define CT_NONE 0
454 #define CT_OK 218
455 #define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */
456 #define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */
457
458 /*
459 * Host side memory scatter gather list
460 * Used by the adapter for read, write, and readdirplus operations
461 * We have separate 32 and 64 bit version because even
462 * on 64 bit systems not all cards support the 64 bit version
463 */
464 struct sgentry {
465 __le32 addr; /* 32-bit address. */
466 __le32 count; /* Length. */
467 };
468
469 struct user_sgentry {
470 u32 addr; /* 32-bit address. */
471 u32 count; /* Length. */
472 };
473
474 struct sgentry64 {
475 __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
476 __le32 count; /* Length. */
477 };
478
479 struct user_sgentry64 {
480 u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
481 u32 count; /* Length. */
482 };
483
484 struct sgentryraw {
485 __le32 next; /* reserved for F/W use */
486 __le32 prev; /* reserved for F/W use */
487 __le32 addr[2];
488 __le32 count;
489 __le32 flags; /* reserved for F/W use */
490 };
491
492 struct user_sgentryraw {
493 u32 next; /* reserved for F/W use */
494 u32 prev; /* reserved for F/W use */
495 u32 addr[2];
496 u32 count;
497 u32 flags; /* reserved for F/W use */
498 };
499
500 struct sge_ieee1212 {
501 u32 addrLow;
502 u32 addrHigh;
503 u32 length;
504 u32 flags;
505 };
506
507 /*
508 * SGMAP
509 *
510 * This is the SGMAP structure for all commands that use
511 * 32-bit addressing.
512 */
513
514 struct sgmap {
515 __le32 count;
516 struct sgentry sg[1];
517 };
518
519 struct user_sgmap {
520 u32 count;
521 struct user_sgentry sg[1];
522 };
523
524 struct sgmap64 {
525 __le32 count;
526 struct sgentry64 sg[1];
527 };
528
529 struct user_sgmap64 {
530 u32 count;
531 struct user_sgentry64 sg[1];
532 };
533
534 struct sgmapraw {
535 __le32 count;
536 struct sgentryraw sg[1];
537 };
538
539 struct user_sgmapraw {
540 u32 count;
541 struct user_sgentryraw sg[1];
542 };
543
544 struct creation_info
545 {
546 u8 buildnum; /* e.g., 588 */
547 u8 usec; /* e.g., 588 */
548 u8 via; /* e.g., 1 = FSU,
549 * 2 = API
550 */
551 u8 year; /* e.g., 1997 = 97 */
552 __le32 date; /*
553 * unsigned Month :4; // 1 - 12
554 * unsigned Day :6; // 1 - 32
555 * unsigned Hour :6; // 0 - 23
556 * unsigned Minute :6; // 0 - 60
557 * unsigned Second :6; // 0 - 60
558 */
559 __le32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */
560 };
561
562
563 /*
564 * Define all the constants needed for the communication interface
565 */
566
567 /*
568 * Define how many queue entries each queue will have and the total
569 * number of entries for the entire communication interface. Also define
570 * how many queues we support.
571 *
572 * This has to match the controller
573 */
574
575 #define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response
576 #define HOST_HIGH_CMD_ENTRIES 4
577 #define HOST_NORM_CMD_ENTRIES 8
578 #define ADAP_HIGH_CMD_ENTRIES 4
579 #define ADAP_NORM_CMD_ENTRIES 512
580 #define HOST_HIGH_RESP_ENTRIES 4
581 #define HOST_NORM_RESP_ENTRIES 512
582 #define ADAP_HIGH_RESP_ENTRIES 4
583 #define ADAP_NORM_RESP_ENTRIES 8
584
585 #define TOTAL_QUEUE_ENTRIES \
586 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \
587 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES)
588
589
590 /*
591 * Set the queues on a 16 byte alignment
592 */
593
594 #define QUEUE_ALIGNMENT 16
595
596 /*
597 * The queue headers define the Communication Region queues. These
598 * are physically contiguous and accessible by both the adapter and the
599 * host. Even though all queue headers are in the same contiguous block
600 * they will be represented as individual units in the data structures.
601 */
602
603 struct aac_entry {
604 __le32 size; /* Size in bytes of Fib which this QE points to */
605 __le32 addr; /* Receiver address of the FIB */
606 };
607
608 /*
609 * The adapter assumes the ProducerIndex and ConsumerIndex are grouped
610 * adjacently and in that order.
611 */
612
613 struct aac_qhdr {
614 __le64 header_addr;/* Address to hand the adapter to access
615 to this queue head */
616 __le32 *producer; /* The producer index for this queue (host address) */
617 __le32 *consumer; /* The consumer index for this queue (host address) */
618 };
619
620 /*
621 * Define all the events which the adapter would like to notify
622 * the host of.
623 */
624
625 #define HostNormCmdQue 1 /* Change in host normal priority command queue */
626 #define HostHighCmdQue 2 /* Change in host high priority command queue */
627 #define HostNormRespQue 3 /* Change in host normal priority response queue */
628 #define HostHighRespQue 4 /* Change in host high priority response queue */
629 #define AdapNormRespNotFull 5
630 #define AdapHighRespNotFull 6
631 #define AdapNormCmdNotFull 7
632 #define AdapHighCmdNotFull 8
633 #define SynchCommandComplete 9
634 #define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */
635
636 /*
637 * Define all the events the host wishes to notify the
638 * adapter of. The first four values much match the Qid the
639 * corresponding queue.
640 */
641
642 #define AdapNormCmdQue 2
643 #define AdapHighCmdQue 3
644 #define AdapNormRespQue 6
645 #define AdapHighRespQue 7
646 #define HostShutdown 8
647 #define HostPowerFail 9
648 #define FatalCommError 10
649 #define HostNormRespNotFull 11
650 #define HostHighRespNotFull 12
651 #define HostNormCmdNotFull 13
652 #define HostHighCmdNotFull 14
653 #define FastIo 15
654 #define AdapPrintfDone 16
655
656 /*
657 * Define all the queues that the adapter and host use to communicate
658 * Number them to match the physical queue layout.
659 */
660
661 enum aac_queue_types {
662 HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */
663 HostHighCmdQueue, /* Adapter to host high priority command traffic */
664 AdapNormCmdQueue, /* Host to adapter normal priority command traffic */
665 AdapHighCmdQueue, /* Host to adapter high priority command traffic */
666 HostNormRespQueue, /* Adapter to host normal priority response traffic */
667 HostHighRespQueue, /* Adapter to host high priority response traffic */
668 AdapNormRespQueue, /* Host to adapter normal priority response traffic */
669 AdapHighRespQueue /* Host to adapter high priority response traffic */
670 };
671
672 /*
673 * Assign type values to the FSA communication data structures
674 */
675
676 #define FIB_MAGIC 0x0001
677 #define FIB_MAGIC2 0x0004
678 #define FIB_MAGIC2_64 0x0005
679
680 /*
681 * Define the priority levels the FSA communication routines support.
682 */
683
684 #define FsaNormal 1
685
686 /* transport FIB header (PMC) */
687 struct aac_fib_xporthdr {
688 __le64 HostAddress; /* FIB host address w/o xport header */
689 __le32 Size; /* FIB size excluding xport header */
690 __le32 Handle; /* driver handle to reference the FIB */
691 __le64 Reserved[2];
692 };
693
694 #define ALIGN32 32
695
696 /*
697 * Define the FIB. The FIB is the where all the requested data and
698 * command information are put to the application on the FSA adapter.
699 */
700
701 struct aac_fibhdr {
702 __le32 XferState; /* Current transfer state for this CCB */
703 __le16 Command; /* Routing information for the destination */
704 u8 StructType; /* Type FIB */
705 u8 Unused; /* Unused */
706 __le16 Size; /* Size of this FIB in bytes */
707 __le16 SenderSize; /* Size of the FIB in the sender
708 (for response sizing) */
709 __le32 SenderFibAddress; /* Host defined data in the FIB */
710 union {
711 __le32 ReceiverFibAddress;/* Logical address of this FIB for
712 the adapter (old) */
713 __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */
714 __le32 TimeStamp; /* otherwise timestamp for FW internal use */
715 } u;
716 __le32 Handle; /* FIB handle used for MSGU commnunication */
717 u32 Previous; /* FW internal use */
718 u32 Next; /* FW internal use */
719 };
720
721 struct hw_fib {
722 struct aac_fibhdr header;
723 u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data
724 };
725
726 /*
727 * FIB commands
728 */
729
730 #define TestCommandResponse 1
731 #define TestAdapterCommand 2
732 /*
733 * Lowlevel and comm commands
734 */
735 #define LastTestCommand 100
736 #define ReinitHostNormCommandQueue 101
737 #define ReinitHostHighCommandQueue 102
738 #define ReinitHostHighRespQueue 103
739 #define ReinitHostNormRespQueue 104
740 #define ReinitAdapNormCommandQueue 105
741 #define ReinitAdapHighCommandQueue 107
742 #define ReinitAdapHighRespQueue 108
743 #define ReinitAdapNormRespQueue 109
744 #define InterfaceShutdown 110
745 #define DmaCommandFib 120
746 #define StartProfile 121
747 #define TermProfile 122
748 #define SpeedTest 123
749 #define TakeABreakPt 124
750 #define RequestPerfData 125
751 #define SetInterruptDefTimer 126
752 #define SetInterruptDefCount 127
753 #define GetInterruptDefStatus 128
754 #define LastCommCommand 129
755 /*
756 * Filesystem commands
757 */
758 #define NuFileSystem 300
759 #define UFS 301
760 #define HostFileSystem 302
761 #define LastFileSystemCommand 303
762 /*
763 * Container Commands
764 */
765 #define ContainerCommand 500
766 #define ContainerCommand64 501
767 #define ContainerRawIo 502
768 #define ContainerRawIo2 503
769 /*
770 * Scsi Port commands (scsi passthrough)
771 */
772 #define ScsiPortCommand 600
773 #define ScsiPortCommand64 601
774 /*
775 * Misc house keeping and generic adapter initiated commands
776 */
777 #define AifRequest 700
778 #define CheckRevision 701
779 #define FsaHostShutdown 702
780 #define RequestAdapterInfo 703
781 #define IsAdapterPaused 704
782 #define SendHostTime 705
783 #define RequestSupplementAdapterInfo 706
784 #define LastMiscCommand 707
785
786 /*
787 * Commands that will target the failover level on the FSA adapter
788 */
789
790 enum fib_xfer_state {
791 HostOwned = (1<<0),
792 AdapterOwned = (1<<1),
793 FibInitialized = (1<<2),
794 FibEmpty = (1<<3),
795 AllocatedFromPool = (1<<4),
796 SentFromHost = (1<<5),
797 SentFromAdapter = (1<<6),
798 ResponseExpected = (1<<7),
799 NoResponseExpected = (1<<8),
800 AdapterProcessed = (1<<9),
801 HostProcessed = (1<<10),
802 HighPriority = (1<<11),
803 NormalPriority = (1<<12),
804 Async = (1<<13),
805 AsyncIo = (1<<13), // rpbfix: remove with new regime
806 PageFileIo = (1<<14), // rpbfix: remove with new regime
807 ShutdownRequest = (1<<15),
808 LazyWrite = (1<<16), // rpbfix: remove with new regime
809 AdapterMicroFib = (1<<17),
810 BIOSFibPath = (1<<18),
811 FastResponseCapable = (1<<19),
812 ApiFib = (1<<20), /* Its an API Fib */
813 /* PMC NEW COMM: There is no more AIF data pending */
814 NoMoreAifDataAvailable = (1<<21)
815 };
816
817 /*
818 * The following defines needs to be updated any time there is an
819 * incompatible change made to the aac_init structure.
820 */
821
822 #define ADAPTER_INIT_STRUCT_REVISION 3
823 #define ADAPTER_INIT_STRUCT_REVISION_4 4 // rocket science
824 #define ADAPTER_INIT_STRUCT_REVISION_6 6 /* PMC src */
825 #define ADAPTER_INIT_STRUCT_REVISION_7 7 /* Denali */
826 #define ADAPTER_INIT_STRUCT_REVISION_8 8 // Thor
827
828 union aac_init
829 {
830 struct _r7 {
831 __le32 init_struct_revision;
832 __le32 no_of_msix_vectors;
833 __le32 fsrev;
834 __le32 comm_header_address;
835 __le32 fast_io_comm_area_address;
836 __le32 adapter_fibs_physical_address;
837 __le32 adapter_fibs_virtual_address;
838 __le32 adapter_fibs_size;
839 __le32 adapter_fib_align;
840 __le32 printfbuf;
841 __le32 printfbufsiz;
842 /* number of 4k pages of host phys. mem. */
843 __le32 host_phys_mem_pages;
844 /* number of seconds since 1970. */
845 __le32 host_elapsed_seconds;
846 /* ADAPTER_INIT_STRUCT_REVISION_4 begins here */
847 __le32 init_flags; /* flags for supported features */
848 #define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001
849 #define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010
850 #define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020
851 #define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040
852 #define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080
853 #define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100
854 #define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE 0x00000400
855 __le32 max_io_commands; /* max outstanding commands */
856 __le32 max_io_size; /* largest I/O command */
857 __le32 max_fib_size; /* largest FIB to adapter */
858 /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */
859 __le32 max_num_aif; /* max number of aif */
860 /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */
861 /* Host RRQ (response queue) for SRC */
862 __le32 host_rrq_addr_low;
863 __le32 host_rrq_addr_high;
864 } r7;
865 struct _r8 {
866 /* ADAPTER_INIT_STRUCT_REVISION_8 */
867 __le32 init_struct_revision;
868 __le32 rr_queue_count;
869 __le32 host_elapsed_seconds; /* number of secs since 1970. */
870 __le32 init_flags;
871 __le32 max_io_size; /* largest I/O command */
872 __le32 max_num_aif; /* max number of aif */
873 __le32 reserved1;
874 __le32 reserved2;
875 struct _rrq {
876 __le32 host_addr_low;
877 __le32 host_addr_high;
878 __le16 msix_id;
879 __le16 element_count;
880 __le16 comp_thresh;
881 __le16 unused;
882 } rrq[1]; /* up to 64 RRQ addresses */
883 } r8;
884 };
885
886 enum aac_log_level {
887 LOG_AAC_INIT = 10,
888 LOG_AAC_INFORMATIONAL = 20,
889 LOG_AAC_WARNING = 30,
890 LOG_AAC_LOW_ERROR = 40,
891 LOG_AAC_MEDIUM_ERROR = 50,
892 LOG_AAC_HIGH_ERROR = 60,
893 LOG_AAC_PANIC = 70,
894 LOG_AAC_DEBUG = 80,
895 LOG_AAC_WINDBG_PRINT = 90
896 };
897
898 #define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b
899 #define FSAFS_NTC_FIB_CONTEXT 0x030c
900
901 struct aac_dev;
902 struct fib;
903 struct scsi_cmnd;
904
905 struct adapter_ops
906 {
907 /* Low level operations */
908 void (*adapter_interrupt)(struct aac_dev *dev);
909 void (*adapter_notify)(struct aac_dev *dev, u32 event);
910 void (*adapter_disable_int)(struct aac_dev *dev);
911 void (*adapter_enable_int)(struct aac_dev *dev);
912 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4);
913 int (*adapter_check_health)(struct aac_dev *dev);
914 int (*adapter_restart)(struct aac_dev *dev, int bled, u8 reset_type);
915 void (*adapter_start)(struct aac_dev *dev);
916 /* Transport operations */
917 int (*adapter_ioremap)(struct aac_dev * dev, u32 size);
918 irq_handler_t adapter_intr;
919 /* Packet operations */
920 int (*adapter_deliver)(struct fib * fib);
921 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba);
922 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count);
923 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua);
924 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd);
925 /* Administrative operations */
926 int (*adapter_comm)(struct aac_dev * dev, int comm);
927 };
928
929 /*
930 * Define which interrupt handler needs to be installed
931 */
932
933 struct aac_driver_ident
934 {
935 int (*init)(struct aac_dev *dev);
936 char * name;
937 char * vname;
938 char * model;
939 u16 channels;
940 int quirks;
941 };
942 /*
943 * Some adapter firmware needs communication memory
944 * below 2gig. This tells the init function to set the
945 * dma mask such that fib memory will be allocated where the
946 * adapter firmware can get to it.
947 */
948 #define AAC_QUIRK_31BIT 0x0001
949
950 /*
951 * Some adapter firmware, when the raid card's cache is turned off, can not
952 * split up scatter gathers in order to deal with the limits of the
953 * underlying CHIM. This limit is 34 scatter gather elements.
954 */
955 #define AAC_QUIRK_34SG 0x0002
956
957 /*
958 * This adapter is a slave (no Firmware)
959 */
960 #define AAC_QUIRK_SLAVE 0x0004
961
962 /*
963 * This adapter is a master.
964 */
965 #define AAC_QUIRK_MASTER 0x0008
966
967 /*
968 * Some adapter firmware perform poorly when it must split up scatter gathers
969 * in order to deal with the limits of the underlying CHIM. This limit in this
970 * class of adapters is 17 scatter gather elements.
971 */
972 #define AAC_QUIRK_17SG 0x0010
973
974 /*
975 * Some adapter firmware does not support 64 bit scsi passthrough
976 * commands.
977 */
978 #define AAC_QUIRK_SCSI_32 0x0020
979
980 /*
981 * SRC based adapters support the AifReqEvent functions
982 */
983 #define AAC_QUIRK_SRC 0x0040
984
985 /*
986 * The adapter interface specs all queues to be located in the same
987 * physically contiguous block. The host structure that defines the
988 * commuication queues will assume they are each a separate physically
989 * contiguous memory region that will support them all being one big
990 * contiguous block.
991 * There is a command and response queue for each level and direction of
992 * commuication. These regions are accessed by both the host and adapter.
993 */
994
995 struct aac_queue {
996 u64 logical; /*address we give the adapter */
997 struct aac_entry *base; /*system virtual address */
998 struct aac_qhdr headers; /*producer,consumer q headers*/
999 u32 entries; /*Number of queue entries */
1000 wait_queue_head_t qfull; /*Event to wait on if q full */
1001 wait_queue_head_t cmdready; /*Cmd ready from the adapter */
1002 /* This is only valid for adapter to host command queues. */
1003 spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */
1004 spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */
1005 struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */
1006 /* only valid for command queues which receive entries from the adapter. */
1007 /* Number of entries on outstanding queue. */
1008 atomic_t numpending;
1009 struct aac_dev * dev; /* Back pointer to adapter structure */
1010 };
1011
1012 /*
1013 * Message queues. The order here is important, see also the
1014 * queue type ordering
1015 */
1016
1017 struct aac_queue_block
1018 {
1019 struct aac_queue queue[8];
1020 };
1021
1022 /*
1023 * SaP1 Message Unit Registers
1024 */
1025
1026 struct sa_drawbridge_CSR {
1027 /* Offset | Name */
1028 __le32 reserved[10]; /* 00h-27h | Reserved */
1029 u8 LUT_Offset; /* 28h | Lookup Table Offset */
1030 u8 reserved1[3]; /* 29h-2bh | Reserved */
1031 __le32 LUT_Data; /* 2ch | Looup Table Data */
1032 __le32 reserved2[26]; /* 30h-97h | Reserved */
1033 __le16 PRICLEARIRQ; /* 98h | Primary Clear Irq */
1034 __le16 SECCLEARIRQ; /* 9ah | Secondary Clear Irq */
1035 __le16 PRISETIRQ; /* 9ch | Primary Set Irq */
1036 __le16 SECSETIRQ; /* 9eh | Secondary Set Irq */
1037 __le16 PRICLEARIRQMASK;/* a0h | Primary Clear Irq Mask */
1038 __le16 SECCLEARIRQMASK;/* a2h | Secondary Clear Irq Mask */
1039 __le16 PRISETIRQMASK; /* a4h | Primary Set Irq Mask */
1040 __le16 SECSETIRQMASK; /* a6h | Secondary Set Irq Mask */
1041 __le32 MAILBOX0; /* a8h | Scratchpad 0 */
1042 __le32 MAILBOX1; /* ach | Scratchpad 1 */
1043 __le32 MAILBOX2; /* b0h | Scratchpad 2 */
1044 __le32 MAILBOX3; /* b4h | Scratchpad 3 */
1045 __le32 MAILBOX4; /* b8h | Scratchpad 4 */
1046 __le32 MAILBOX5; /* bch | Scratchpad 5 */
1047 __le32 MAILBOX6; /* c0h | Scratchpad 6 */
1048 __le32 MAILBOX7; /* c4h | Scratchpad 7 */
1049 __le32 ROM_Setup_Data; /* c8h | Rom Setup and Data */
1050 __le32 ROM_Control_Addr;/* cch | Rom Control and Address */
1051 __le32 reserved3[12]; /* d0h-ffh | reserved */
1052 __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */
1053 };
1054
1055 #define Mailbox0 SaDbCSR.MAILBOX0
1056 #define Mailbox1 SaDbCSR.MAILBOX1
1057 #define Mailbox2 SaDbCSR.MAILBOX2
1058 #define Mailbox3 SaDbCSR.MAILBOX3
1059 #define Mailbox4 SaDbCSR.MAILBOX4
1060 #define Mailbox5 SaDbCSR.MAILBOX5
1061 #define Mailbox6 SaDbCSR.MAILBOX6
1062 #define Mailbox7 SaDbCSR.MAILBOX7
1063
1064 #define DoorbellReg_p SaDbCSR.PRISETIRQ
1065 #define DoorbellReg_s SaDbCSR.SECSETIRQ
1066 #define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ
1067
1068
1069 #define DOORBELL_0 0x0001
1070 #define DOORBELL_1 0x0002
1071 #define DOORBELL_2 0x0004
1072 #define DOORBELL_3 0x0008
1073 #define DOORBELL_4 0x0010
1074 #define DOORBELL_5 0x0020
1075 #define DOORBELL_6 0x0040
1076
1077
1078 #define PrintfReady DOORBELL_5
1079 #define PrintfDone DOORBELL_5
1080
1081 struct sa_registers {
1082 struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */
1083 };
1084
1085
1086 #define SA_INIT_NUM_MSIXVECTORS 1
1087 #define SA_MINIPORT_REVISION SA_INIT_NUM_MSIXVECTORS
1088
1089 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
1090 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
1091 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
1092 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
1093
1094 /*
1095 * Rx Message Unit Registers
1096 */
1097
1098 struct rx_mu_registers {
1099 /* Local | PCI*| Name */
1100 __le32 ARSR; /* 1300h | 00h | APIC Register Select Register */
1101 __le32 reserved0; /* 1304h | 04h | Reserved */
1102 __le32 AWR; /* 1308h | 08h | APIC Window Register */
1103 __le32 reserved1; /* 130Ch | 0Ch | Reserved */
1104 __le32 IMRx[2]; /* 1310h | 10h | Inbound Message Registers */
1105 __le32 OMRx[2]; /* 1318h | 18h | Outbound Message Registers */
1106 __le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */
1107 __le32 IISR; /* 1324h | 24h | Inbound Interrupt
1108 Status Register */
1109 __le32 IIMR; /* 1328h | 28h | Inbound Interrupt
1110 Mask Register */
1111 __le32 ODR; /* 132Ch | 2Ch | Outbound Doorbell Register */
1112 __le32 OISR; /* 1330h | 30h | Outbound Interrupt
1113 Status Register */
1114 __le32 OIMR; /* 1334h | 34h | Outbound Interrupt
1115 Mask Register */
1116 __le32 reserved2; /* 1338h | 38h | Reserved */
1117 __le32 reserved3; /* 133Ch | 3Ch | Reserved */
1118 __le32 InboundQueue;/* 1340h | 40h | Inbound Queue Port relative to firmware */
1119 __le32 OutboundQueue;/*1344h | 44h | Outbound Queue Port relative to firmware */
1120 /* * Must access through ATU Inbound
1121 Translation Window */
1122 };
1123
1124 struct rx_inbound {
1125 __le32 Mailbox[8];
1126 };
1127
1128 #define INBOUNDDOORBELL_0 0x00000001
1129 #define INBOUNDDOORBELL_1 0x00000002
1130 #define INBOUNDDOORBELL_2 0x00000004
1131 #define INBOUNDDOORBELL_3 0x00000008
1132 #define INBOUNDDOORBELL_4 0x00000010
1133 #define INBOUNDDOORBELL_5 0x00000020
1134 #define INBOUNDDOORBELL_6 0x00000040
1135
1136 #define OUTBOUNDDOORBELL_0 0x00000001
1137 #define OUTBOUNDDOORBELL_1 0x00000002
1138 #define OUTBOUNDDOORBELL_2 0x00000004
1139 #define OUTBOUNDDOORBELL_3 0x00000008
1140 #define OUTBOUNDDOORBELL_4 0x00000010
1141
1142 #define InboundDoorbellReg MUnit.IDR
1143 #define OutboundDoorbellReg MUnit.ODR
1144
1145 struct rx_registers {
1146 struct rx_mu_registers MUnit; /* 1300h - 1347h */
1147 __le32 reserved1[2]; /* 1348h - 134ch */
1148 struct rx_inbound IndexRegs;
1149 };
1150
1151 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
1152 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
1153 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
1154 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
1155
1156 /*
1157 * Rkt Message Unit Registers (same as Rx, except a larger reserve region)
1158 */
1159
1160 #define rkt_mu_registers rx_mu_registers
1161 #define rkt_inbound rx_inbound
1162
1163 struct rkt_registers {
1164 struct rkt_mu_registers MUnit; /* 1300h - 1347h */
1165 __le32 reserved1[1006]; /* 1348h - 22fch */
1166 struct rkt_inbound IndexRegs; /* 2300h - */
1167 };
1168
1169 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR))
1170 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR))
1171 #define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR))
1172 #define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
1173
1174 /*
1175 * PMC SRC message unit registers
1176 */
1177
1178 #define src_inbound rx_inbound
1179
1180 struct src_mu_registers {
1181 /* PCI*| Name */
1182 __le32 reserved0[6]; /* 00h | Reserved */
1183 __le32 IOAR[2]; /* 18h | IOA->host interrupt register */
1184 __le32 IDR; /* 20h | Inbound Doorbell Register */
1185 __le32 IISR; /* 24h | Inbound Int. Status Register */
1186 __le32 reserved1[3]; /* 28h | Reserved */
1187 __le32 OIMR; /* 34h | Outbound Int. Mask Register */
1188 __le32 reserved2[25]; /* 38h | Reserved */
1189 __le32 ODR_R; /* 9ch | Outbound Doorbell Read */
1190 __le32 ODR_C; /* a0h | Outbound Doorbell Clear */
1191 __le32 reserved3[3]; /* a4h | Reserved */
1192 __le32 SCR0; /* b0h | Scratchpad 0 */
1193 __le32 reserved4[2]; /* b4h | Reserved */
1194 __le32 OMR; /* bch | Outbound Message Register */
1195 __le32 IQ_L; /* c0h | Inbound Queue (Low address) */
1196 __le32 IQ_H; /* c4h | Inbound Queue (High address) */
1197 __le32 ODR_MSI; /* c8h | MSI register for sync./AIF */
1198 __le32 reserved5; /* cch | Reserved */
1199 __le32 IQN_L; /* d0h | Inbound (native cmd) low */
1200 __le32 IQN_H; /* d4h | Inbound (native cmd) high */
1201 };
1202
1203 struct src_registers {
1204 struct src_mu_registers MUnit; /* 00h - cbh */
1205 union {
1206 struct {
1207 __le32 reserved1[130786]; /* d8h - 7fc5fh */
1208 struct src_inbound IndexRegs; /* 7fc60h */
1209 } tupelo;
1210 struct {
1211 __le32 reserved1[970]; /* d8h - fffh */
1212 struct src_inbound IndexRegs; /* 1000h */
1213 } denali;
1214 } u;
1215 };
1216
1217 #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR))
1218 #define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR))
1219 #define src_writeb(AEP, CSR, value) writeb(value, \
1220 &((AEP)->regs.src.bar0->CSR))
1221 #define src_writel(AEP, CSR, value) writel(value, \
1222 &((AEP)->regs.src.bar0->CSR))
1223 #if defined(writeq)
1224 #define src_writeq(AEP, CSR, value) writeq(value, \
1225 &((AEP)->regs.src.bar0->CSR))
1226 #endif
1227
1228 #define SRC_ODR_SHIFT 12
1229 #define SRC_IDR_SHIFT 9
1230
1231 typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);
1232
1233 struct aac_fib_context {
1234 s16 type; // used for verification of structure
1235 s16 size;
1236 u32 unique; // unique value representing this context
1237 ulong jiffies; // used for cleanup - dmb changed to ulong
1238 struct list_head next; // used to link context's into a linked list
1239 struct semaphore wait_sem; // this is used to wait for the next fib to arrive.
1240 int wait; // Set to true when thread is in WaitForSingleObject
1241 unsigned long count; // total number of FIBs on FibList
1242 struct list_head fib_list; // this holds fibs and their attachd hw_fibs
1243 };
1244
1245 struct sense_data {
1246 u8 error_code; /* 70h (current errors), 71h(deferred errors) */
1247 u8 valid:1; /* A valid bit of one indicates that the information */
1248 /* field contains valid information as defined in the
1249 * SCSI-2 Standard.
1250 */
1251 u8 segment_number; /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */
1252 u8 sense_key:4; /* Sense Key */
1253 u8 reserved:1;
1254 u8 ILI:1; /* Incorrect Length Indicator */
1255 u8 EOM:1; /* End Of Medium - reserved for random access devices */
1256 u8 filemark:1; /* Filemark - reserved for random access devices */
1257
1258 u8 information[4]; /* for direct-access devices, contains the unsigned
1259 * logical block address or residue associated with
1260 * the sense key
1261 */
1262 u8 add_sense_len; /* number of additional sense bytes to follow this field */
1263 u8 cmnd_info[4]; /* not used */
1264 u8 ASC; /* Additional Sense Code */
1265 u8 ASCQ; /* Additional Sense Code Qualifier */
1266 u8 FRUC; /* Field Replaceable Unit Code - not used */
1267 u8 bit_ptr:3; /* indicates which byte of the CDB or parameter data
1268 * was in error
1269 */
1270 u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that
1271 * the bit_ptr field has valid value
1272 */
1273 u8 reserved2:2;
1274 u8 CD:1; /* command data bit: 1- illegal parameter in CDB.
1275 * 0- illegal parameter in data.
1276 */
1277 u8 SKSV:1;
1278 u8 field_ptr[2]; /* byte of the CDB or parameter data in error */
1279 };
1280
1281 struct fsa_dev_info {
1282 u64 last;
1283 u64 size;
1284 u32 type;
1285 u32 config_waiting_on;
1286 unsigned long config_waiting_stamp;
1287 u16 queue_depth;
1288 u8 config_needed;
1289 u8 valid;
1290 u8 ro;
1291 u8 locked;
1292 u8 deleted;
1293 char devname[8];
1294 struct sense_data sense_data;
1295 u32 block_size;
1296 u8 identifier[16];
1297 };
1298
1299 struct fib {
1300 void *next; /* this is used by the allocator */
1301 s16 type;
1302 s16 size;
1303 /*
1304 * The Adapter that this I/O is destined for.
1305 */
1306 struct aac_dev *dev;
1307 /*
1308 * This is the event the sendfib routine will wait on if the
1309 * caller did not pass one and this is synch io.
1310 */
1311 struct semaphore event_wait;
1312 spinlock_t event_lock;
1313
1314 u32 done; /* gets set to 1 when fib is complete */
1315 fib_callback callback;
1316 void *callback_data;
1317 u32 flags; // u32 dmb was ulong
1318 /*
1319 * And for the internal issue/reply queues (we may be able
1320 * to merge these two)
1321 */
1322 struct list_head fiblink;
1323 void *data;
1324 u32 vector_no;
1325 struct hw_fib *hw_fib_va; /* also used for native */
1326 dma_addr_t hw_fib_pa; /* physical address of hw_fib*/
1327 dma_addr_t hw_sgl_pa; /* extra sgl for native */
1328 dma_addr_t hw_error_pa; /* error buffer for native */
1329 u32 hbacmd_size; /* cmd size for native */
1330 };
1331
1332 #define AAC_INIT 0
1333 #define AAC_RESCAN 1
1334
1335 #define AAC_DEVTYPE_RAID_MEMBER 1
1336 #define AAC_DEVTYPE_ARC_RAW 2
1337 #define AAC_DEVTYPE_NATIVE_RAW 3
1338 #define AAC_EXPOSE_DISK 0
1339 #define AAC_HIDE_DISK 3
1340
1341 struct aac_hba_map_info {
1342 __le32 rmw_nexus; /* nexus for native HBA devices */
1343 u8 devtype; /* device type */
1344 u8 new_devtype;
1345 u8 reset_state; /* 0 - no reset, 1..x - */
1346 /* after xth TM LUN reset */
1347 u16 qd_limit;
1348 u8 expose; /*checks if to expose or not*/
1349 };
1350
1351 /*
1352 * Adapter Information Block
1353 *
1354 * This is returned by the RequestAdapterInfo block
1355 */
1356
1357 struct aac_adapter_info
1358 {
1359 __le32 platform;
1360 __le32 cpu;
1361 __le32 subcpu;
1362 __le32 clock;
1363 __le32 execmem;
1364 __le32 buffermem;
1365 __le32 totalmem;
1366 __le32 kernelrev;
1367 __le32 kernelbuild;
1368 __le32 monitorrev;
1369 __le32 monitorbuild;
1370 __le32 hwrev;
1371 __le32 hwbuild;
1372 __le32 biosrev;
1373 __le32 biosbuild;
1374 __le32 cluster;
1375 __le32 clusterchannelmask;
1376 __le32 serial[2];
1377 __le32 battery;
1378 __le32 options;
1379 __le32 OEM;
1380 };
1381
1382 struct aac_supplement_adapter_info
1383 {
1384 u8 adapter_type_text[17+1];
1385 u8 pad[2];
1386 __le32 flash_memory_byte_size;
1387 __le32 flash_image_id;
1388 __le32 max_number_ports;
1389 __le32 version;
1390 __le32 feature_bits;
1391 u8 slot_number;
1392 u8 reserved_pad0[3];
1393 u8 build_date[12];
1394 __le32 current_number_ports;
1395 struct {
1396 u8 assembly_pn[8];
1397 u8 fru_pn[8];
1398 u8 battery_fru_pn[8];
1399 u8 ec_version_string[8];
1400 u8 tsid[12];
1401 } vpd_info;
1402 __le32 flash_firmware_revision;
1403 __le32 flash_firmware_build;
1404 __le32 raid_type_morph_options;
1405 __le32 flash_firmware_boot_revision;
1406 __le32 flash_firmware_boot_build;
1407 u8 mfg_pcba_serial_no[12];
1408 u8 mfg_wwn_name[8];
1409 __le32 supported_options2;
1410 __le32 struct_expansion;
1411 /* StructExpansion == 1 */
1412 __le32 feature_bits3;
1413 __le32 supported_performance_modes;
1414 u8 host_bus_type; /* uses HOST_BUS_TYPE_xxx defines */
1415 u8 host_bus_width; /* actual width in bits or links */
1416 u16 host_bus_speed; /* actual bus speed/link rate in MHz */
1417 u8 max_rrc_drives; /* max. number of ITP-RRC drives/pool */
1418 u8 max_disk_xtasks; /* max. possible num of DiskX Tasks */
1419
1420 u8 cpld_ver_loaded;
1421 u8 cpld_ver_in_flash;
1422
1423 __le64 max_rrc_capacity;
1424 __le32 compiled_max_hist_log_level;
1425 u8 custom_board_name[12];
1426 u16 supported_cntlr_mode; /* identify supported controller mode */
1427 u16 reserved_for_future16;
1428 __le32 supported_options3; /* reserved for future options */
1429
1430 __le16 virt_device_bus; /* virt. SCSI device for Thor */
1431 __le16 virt_device_target;
1432 __le16 virt_device_lun;
1433 __le16 unused;
1434 __le32 reserved_for_future_growth[68];
1435
1436 };
1437 #define AAC_FEATURE_FALCON cpu_to_le32(0x00000010)
1438 #define AAC_FEATURE_JBOD cpu_to_le32(0x08000000)
1439 /* SupportedOptions2 */
1440 #define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001)
1441 #define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002)
1442 #define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004)
1443 #define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000)
1444 /* 4KB sector size */
1445 #define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000)
1446 /* 240 simple volume support */
1447 #define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000)
1448 /*
1449 * Supports FIB dump sync command send prior to IOP_RESET
1450 */
1451 #define AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP cpu_to_le32(0x00004000)
1452 #define AAC_SIS_VERSION_V3 3
1453 #define AAC_SIS_SLOT_UNKNOWN 0xFF
1454
1455 #define GetBusInfo 0x00000009
1456 struct aac_bus_info {
1457 __le32 Command; /* VM_Ioctl */
1458 __le32 ObjType; /* FT_DRIVE */
1459 __le32 MethodId; /* 1 = SCSI Layer */
1460 __le32 ObjectId; /* Handle */
1461 __le32 CtlCmd; /* GetBusInfo */
1462 };
1463
1464 struct aac_bus_info_response {
1465 __le32 Status; /* ST_OK */
1466 __le32 ObjType;
1467 __le32 MethodId; /* unused */
1468 __le32 ObjectId; /* unused */
1469 __le32 CtlCmd; /* unused */
1470 __le32 ProbeComplete;
1471 __le32 BusCount;
1472 __le32 TargetsPerBus;
1473 u8 InitiatorBusId[10];
1474 u8 BusValid[10];
1475 };
1476
1477 /*
1478 * Battery platforms
1479 */
1480 #define AAC_BAT_REQ_PRESENT (1)
1481 #define AAC_BAT_REQ_NOTPRESENT (2)
1482 #define AAC_BAT_OPT_PRESENT (3)
1483 #define AAC_BAT_OPT_NOTPRESENT (4)
1484 #define AAC_BAT_NOT_SUPPORTED (5)
1485 /*
1486 * cpu types
1487 */
1488 #define AAC_CPU_SIMULATOR (1)
1489 #define AAC_CPU_I960 (2)
1490 #define AAC_CPU_STRONGARM (3)
1491
1492 /*
1493 * Supported Options
1494 */
1495 #define AAC_OPT_SNAPSHOT cpu_to_le32(1)
1496 #define AAC_OPT_CLUSTERS cpu_to_le32(1<<1)
1497 #define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2)
1498 #define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3)
1499 #define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4)
1500 #define AAC_OPT_RAID50 cpu_to_le32(1<<5)
1501 #define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6)
1502 #define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7)
1503 #define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8)
1504 #define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9)
1505 #define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10)
1506 #define AAC_OPT_ALARM cpu_to_le32(1<<11)
1507 #define AAC_OPT_NONDASD cpu_to_le32(1<<12)
1508 #define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13)
1509 #define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14)
1510 #define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16)
1511 #define AAC_OPT_NEW_COMM cpu_to_le32(1<<17)
1512 #define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18)
1513 #define AAC_OPT_EXTENDED cpu_to_le32(1<<23)
1514 #define AAC_OPT_NATIVE_HBA cpu_to_le32(1<<25)
1515 #define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28)
1516 #define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29)
1517 #define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30)
1518 #define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31)
1519
1520 #define AAC_COMM_PRODUCER 0
1521 #define AAC_COMM_MESSAGE 1
1522 #define AAC_COMM_MESSAGE_TYPE1 3
1523 #define AAC_COMM_MESSAGE_TYPE2 4
1524 #define AAC_COMM_MESSAGE_TYPE3 5
1525
1526 #define AAC_EXTOPT_SA_FIRMWARE cpu_to_le32(1<<1)
1527
1528 /* MSIX context */
1529 struct aac_msix_ctx {
1530 int vector_no;
1531 struct aac_dev *dev;
1532 };
1533
1534 struct aac_dev
1535 {
1536 struct list_head entry;
1537 const char *name;
1538 int id;
1539
1540 /*
1541 * negotiated FIB settings
1542 */
1543 unsigned int max_fib_size;
1544 unsigned int sg_tablesize;
1545 unsigned int max_num_aif;
1546
1547 unsigned int max_cmd_size; /* max_fib_size or MAX_NATIVE */
1548
1549 /*
1550 * Map for 128 fib objects (64k)
1551 */
1552 dma_addr_t hw_fib_pa; /* also used for native cmd */
1553 struct hw_fib *hw_fib_va; /* also used for native cmd */
1554 struct hw_fib *aif_base_va;
1555 /*
1556 * Fib Headers
1557 */
1558 struct fib *fibs;
1559
1560 struct fib *free_fib;
1561 spinlock_t fib_lock;
1562
1563 struct mutex ioctl_mutex;
1564 struct aac_queue_block *queues;
1565 /*
1566 * The user API will use an IOCTL to register itself to receive
1567 * FIBs from the adapter. The following list is used to keep
1568 * track of all the threads that have requested these FIBs. The
1569 * mutex is used to synchronize access to all data associated
1570 * with the adapter fibs.
1571 */
1572 struct list_head fib_list;
1573
1574 struct adapter_ops a_ops;
1575 unsigned long fsrev; /* Main driver's revision number */
1576
1577 resource_size_t base_start; /* main IO base */
1578 resource_size_t dbg_base; /* address of UART
1579 * debug buffer */
1580
1581 resource_size_t base_size, dbg_size; /* Size of
1582 * mapped in region */
1583 /*
1584 * Holds initialization info
1585 * to communicate with adapter
1586 */
1587 union aac_init *init;
1588 dma_addr_t init_pa; /* Holds physical address of the init struct */
1589 /* response queue (if AAC_COMM_MESSAGE_TYPE1) */
1590 __le32 *host_rrq;
1591 dma_addr_t host_rrq_pa; /* phys. address */
1592 /* index into rrq buffer */
1593 u32 host_rrq_idx[AAC_MAX_MSIX];
1594 atomic_t rrq_outstanding[AAC_MAX_MSIX];
1595 u32 fibs_pushed_no;
1596 struct pci_dev *pdev; /* Our PCI interface */
1597 /* pointer to buffer used for printf's from the adapter */
1598 void *printfbuf;
1599 void *comm_addr; /* Base address of Comm area */
1600 dma_addr_t comm_phys; /* Physical Address of Comm area */
1601 size_t comm_size;
1602
1603 struct Scsi_Host *scsi_host_ptr;
1604 int maximum_num_containers;
1605 int maximum_num_physicals;
1606 int maximum_num_channels;
1607 struct fsa_dev_info *fsa_dev;
1608 struct task_struct *thread;
1609 int cardtype;
1610 /*
1611 *This lock will protect the two 32-bit
1612 *writes to the Inbound Queue
1613 */
1614 spinlock_t iq_lock;
1615
1616 /*
1617 * The following is the device specific extension.
1618 */
1619 #ifndef AAC_MIN_FOOTPRINT_SIZE
1620 # define AAC_MIN_FOOTPRINT_SIZE 8192
1621 # define AAC_MIN_SRC_BAR0_SIZE 0x400000
1622 # define AAC_MIN_SRC_BAR1_SIZE 0x800
1623 # define AAC_MIN_SRCV_BAR0_SIZE 0x100000
1624 # define AAC_MIN_SRCV_BAR1_SIZE 0x400
1625 #endif
1626 union
1627 {
1628 struct sa_registers __iomem *sa;
1629 struct rx_registers __iomem *rx;
1630 struct rkt_registers __iomem *rkt;
1631 struct {
1632 struct src_registers __iomem *bar0;
1633 char __iomem *bar1;
1634 } src;
1635 } regs;
1636 volatile void __iomem *base, *dbg_base_mapped;
1637 volatile struct rx_inbound __iomem *IndexRegs;
1638 u32 OIMR; /* Mask Register Cache */
1639 /*
1640 * AIF thread states
1641 */
1642 u32 aif_thread;
1643 struct aac_adapter_info adapter_info;
1644 struct aac_supplement_adapter_info supplement_adapter_info;
1645 /* These are in adapter info but they are in the io flow so
1646 * lets break them out so we don't have to do an AND to check them
1647 */
1648 u8 nondasd_support;
1649 u8 jbod;
1650 u8 cache_protected;
1651 u8 dac_support;
1652 u8 needs_dac;
1653 u8 raid_scsi_mode;
1654 u8 comm_interface;
1655 u8 raw_io_interface;
1656 u8 raw_io_64;
1657 u8 printf_enabled;
1658 u8 in_reset;
1659 u8 msi;
1660 u8 sa_firmware;
1661 int management_fib_count;
1662 spinlock_t manage_lock;
1663 spinlock_t sync_lock;
1664 int sync_mode;
1665 struct fib *sync_fib;
1666 struct list_head sync_fib_list;
1667 u32 doorbell_mask;
1668 u32 max_msix; /* max. MSI-X vectors */
1669 u32 vector_cap; /* MSI-X vector capab.*/
1670 int msi_enabled; /* MSI/MSI-X enabled */
1671 atomic_t msix_counter;
1672 struct msix_entry msixentry[AAC_MAX_MSIX];
1673 struct aac_msix_ctx aac_msix[AAC_MAX_MSIX]; /* context */
1674 struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS];
1675 u8 adapter_shutdown;
1676 u32 handle_pci_error;
1677 };
1678
1679 #define aac_adapter_interrupt(dev) \
1680 (dev)->a_ops.adapter_interrupt(dev)
1681
1682 #define aac_adapter_notify(dev, event) \
1683 (dev)->a_ops.adapter_notify(dev, event)
1684
1685 #define aac_adapter_disable_int(dev) \
1686 (dev)->a_ops.adapter_disable_int(dev)
1687
1688 #define aac_adapter_enable_int(dev) \
1689 (dev)->a_ops.adapter_enable_int(dev)
1690
1691 #define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \
1692 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4)
1693
1694 #define aac_adapter_restart(dev, bled, reset_type) \
1695 ((dev)->a_ops.adapter_restart(dev, bled, reset_type))
1696
1697 #define aac_adapter_start(dev) \
1698 ((dev)->a_ops.adapter_start(dev))
1699
1700 #define aac_adapter_ioremap(dev, size) \
1701 (dev)->a_ops.adapter_ioremap(dev, size)
1702
1703 #define aac_adapter_deliver(fib) \
1704 ((fib)->dev)->a_ops.adapter_deliver(fib)
1705
1706 #define aac_adapter_bounds(dev,cmd,lba) \
1707 dev->a_ops.adapter_bounds(dev,cmd,lba)
1708
1709 #define aac_adapter_read(fib,cmd,lba,count) \
1710 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count)
1711
1712 #define aac_adapter_write(fib,cmd,lba,count,fua) \
1713 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua)
1714
1715 #define aac_adapter_scsi(fib,cmd) \
1716 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd)
1717
1718 #define aac_adapter_comm(dev,comm) \
1719 (dev)->a_ops.adapter_comm(dev, comm)
1720
1721 #define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001)
1722 #define FIB_CONTEXT_FLAG (0x00000002)
1723 #define FIB_CONTEXT_FLAG_WAIT (0x00000004)
1724 #define FIB_CONTEXT_FLAG_FASTRESP (0x00000008)
1725 #define FIB_CONTEXT_FLAG_NATIVE_HBA (0x00000010)
1726 #define FIB_CONTEXT_FLAG_NATIVE_HBA_TMF (0x00000020)
1727
1728 /*
1729 * Define the command values
1730 */
1731
1732 #define Null 0
1733 #define GetAttributes 1
1734 #define SetAttributes 2
1735 #define Lookup 3
1736 #define ReadLink 4
1737 #define Read 5
1738 #define Write 6
1739 #define Create 7
1740 #define MakeDirectory 8
1741 #define SymbolicLink 9
1742 #define MakeNode 10
1743 #define Removex 11
1744 #define RemoveDirectoryx 12
1745 #define Rename 13
1746 #define Link 14
1747 #define ReadDirectory 15
1748 #define ReadDirectoryPlus 16
1749 #define FileSystemStatus 17
1750 #define FileSystemInfo 18
1751 #define PathConfigure 19
1752 #define Commit 20
1753 #define Mount 21
1754 #define UnMount 22
1755 #define Newfs 23
1756 #define FsCheck 24
1757 #define FsSync 25
1758 #define SimReadWrite 26
1759 #define SetFileSystemStatus 27
1760 #define BlockRead 28
1761 #define BlockWrite 29
1762 #define NvramIoctl 30
1763 #define FsSyncWait 31
1764 #define ClearArchiveBit 32
1765 #define SetAcl 33
1766 #define GetAcl 34
1767 #define AssignAcl 35
1768 #define FaultInsertion 36 /* Fault Insertion Command */
1769 #define CrazyCache 37 /* Crazycache */
1770
1771 #define MAX_FSACOMMAND_NUM 38
1772
1773
1774 /*
1775 * Define the status returns. These are very unixlike although
1776 * most are not in fact used
1777 */
1778
1779 #define ST_OK 0
1780 #define ST_PERM 1
1781 #define ST_NOENT 2
1782 #define ST_IO 5
1783 #define ST_NXIO 6
1784 #define ST_E2BIG 7
1785 #define ST_MEDERR 8
1786 #define ST_ACCES 13
1787 #define ST_EXIST 17
1788 #define ST_XDEV 18
1789 #define ST_NODEV 19
1790 #define ST_NOTDIR 20
1791 #define ST_ISDIR 21
1792 #define ST_INVAL 22
1793 #define ST_FBIG 27
1794 #define ST_NOSPC 28
1795 #define ST_ROFS 30
1796 #define ST_MLINK 31
1797 #define ST_WOULDBLOCK 35
1798 #define ST_NAMETOOLONG 63
1799 #define ST_NOTEMPTY 66
1800 #define ST_DQUOT 69
1801 #define ST_STALE 70
1802 #define ST_REMOTE 71
1803 #define ST_NOT_READY 72
1804 #define ST_BADHANDLE 10001
1805 #define ST_NOT_SYNC 10002
1806 #define ST_BAD_COOKIE 10003
1807 #define ST_NOTSUPP 10004
1808 #define ST_TOOSMALL 10005
1809 #define ST_SERVERFAULT 10006
1810 #define ST_BADTYPE 10007
1811 #define ST_JUKEBOX 10008
1812 #define ST_NOTMOUNTED 10009
1813 #define ST_MAINTMODE 10010
1814 #define ST_STALEACL 10011
1815
1816 /*
1817 * On writes how does the client want the data written.
1818 */
1819
1820 #define CACHE_CSTABLE 1
1821 #define CACHE_UNSTABLE 2
1822
1823 /*
1824 * Lets the client know at which level the data was committed on
1825 * a write request
1826 */
1827
1828 #define CMFILE_SYNCH_NVRAM 1
1829 #define CMDATA_SYNCH_NVRAM 2
1830 #define CMFILE_SYNCH 3
1831 #define CMDATA_SYNCH 4
1832 #define CMUNSTABLE 5
1833
1834 #define RIO_TYPE_WRITE 0x0000
1835 #define RIO_TYPE_READ 0x0001
1836 #define RIO_SUREWRITE 0x0008
1837
1838 #define RIO2_IO_TYPE 0x0003
1839 #define RIO2_IO_TYPE_WRITE 0x0000
1840 #define RIO2_IO_TYPE_READ 0x0001
1841 #define RIO2_IO_TYPE_VERIFY 0x0002
1842 #define RIO2_IO_ERROR 0x0004
1843 #define RIO2_IO_SUREWRITE 0x0008
1844 #define RIO2_SGL_CONFORMANT 0x0010
1845 #define RIO2_SG_FORMAT 0xF000
1846 #define RIO2_SG_FORMAT_ARC 0x0000
1847 #define RIO2_SG_FORMAT_SRL 0x1000
1848 #define RIO2_SG_FORMAT_IEEE1212 0x2000
1849
1850 struct aac_read
1851 {
1852 __le32 command;
1853 __le32 cid;
1854 __le32 block;
1855 __le32 count;
1856 struct sgmap sg; // Must be last in struct because it is variable
1857 };
1858
1859 struct aac_read64
1860 {
1861 __le32 command;
1862 __le16 cid;
1863 __le16 sector_count;
1864 __le32 block;
1865 __le16 pad;
1866 __le16 flags;
1867 struct sgmap64 sg; // Must be last in struct because it is variable
1868 };
1869
1870 struct aac_read_reply
1871 {
1872 __le32 status;
1873 __le32 count;
1874 };
1875
1876 struct aac_write
1877 {
1878 __le32 command;
1879 __le32 cid;
1880 __le32 block;
1881 __le32 count;
1882 __le32 stable; // Not used
1883 struct sgmap sg; // Must be last in struct because it is variable
1884 };
1885
1886 struct aac_write64
1887 {
1888 __le32 command;
1889 __le16 cid;
1890 __le16 sector_count;
1891 __le32 block;
1892 __le16 pad;
1893 __le16 flags;
1894 struct sgmap64 sg; // Must be last in struct because it is variable
1895 };
1896 struct aac_write_reply
1897 {
1898 __le32 status;
1899 __le32 count;
1900 __le32 committed;
1901 };
1902
1903 struct aac_raw_io
1904 {
1905 __le32 block[2];
1906 __le32 count;
1907 __le16 cid;
1908 __le16 flags; /* 00 W, 01 R */
1909 __le16 bpTotal; /* reserved for F/W use */
1910 __le16 bpComplete; /* reserved for F/W use */
1911 struct sgmapraw sg;
1912 };
1913
1914 struct aac_raw_io2 {
1915 __le32 blockLow;
1916 __le32 blockHigh;
1917 __le32 byteCount;
1918 __le16 cid;
1919 __le16 flags; /* RIO2 flags */
1920 __le32 sgeFirstSize; /* size of first sge el. */
1921 __le32 sgeNominalSize; /* size of 2nd sge el. (if conformant) */
1922 u8 sgeCnt; /* only 8 bits required */
1923 u8 bpTotal; /* reserved for F/W use */
1924 u8 bpComplete; /* reserved for F/W use */
1925 u8 sgeFirstIndex; /* reserved for F/W use */
1926 u8 unused[4];
1927 struct sge_ieee1212 sge[1];
1928 };
1929
1930 #define CT_FLUSH_CACHE 129
1931 struct aac_synchronize {
1932 __le32 command; /* VM_ContainerConfig */
1933 __le32 type; /* CT_FLUSH_CACHE */
1934 __le32 cid;
1935 __le32 parm1;
1936 __le32 parm2;
1937 __le32 parm3;
1938 __le32 parm4;
1939 __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */
1940 };
1941
1942 struct aac_synchronize_reply {
1943 __le32 dummy0;
1944 __le32 dummy1;
1945 __le32 status; /* CT_OK */
1946 __le32 parm1;
1947 __le32 parm2;
1948 __le32 parm3;
1949 __le32 parm4;
1950 __le32 parm5;
1951 u8 data[16];
1952 };
1953
1954 #define CT_POWER_MANAGEMENT 245
1955 #define CT_PM_START_UNIT 2
1956 #define CT_PM_STOP_UNIT 3
1957 #define CT_PM_UNIT_IMMEDIATE 1
1958 struct aac_power_management {
1959 __le32 command; /* VM_ContainerConfig */
1960 __le32 type; /* CT_POWER_MANAGEMENT */
1961 __le32 sub; /* CT_PM_* */
1962 __le32 cid;
1963 __le32 parm; /* CT_PM_sub_* */
1964 };
1965
1966 #define CT_PAUSE_IO 65
1967 #define CT_RELEASE_IO 66
1968 struct aac_pause {
1969 __le32 command; /* VM_ContainerConfig */
1970 __le32 type; /* CT_PAUSE_IO */
1971 __le32 timeout; /* 10ms ticks */
1972 __le32 min;
1973 __le32 noRescan;
1974 __le32 parm3;
1975 __le32 parm4;
1976 __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */
1977 };
1978
1979 struct aac_srb
1980 {
1981 __le32 function;
1982 __le32 channel;
1983 __le32 id;
1984 __le32 lun;
1985 __le32 timeout;
1986 __le32 flags;
1987 __le32 count; // Data xfer size
1988 __le32 retry_limit;
1989 __le32 cdb_size;
1990 u8 cdb[16];
1991 struct sgmap sg;
1992 };
1993
1994 /*
1995 * This and associated data structs are used by the
1996 * ioctl caller and are in cpu order.
1997 */
1998 struct user_aac_srb
1999 {
2000 u32 function;
2001 u32 channel;
2002 u32 id;
2003 u32 lun;
2004 u32 timeout;
2005 u32 flags;
2006 u32 count; // Data xfer size
2007 u32 retry_limit;
2008 u32 cdb_size;
2009 u8 cdb[16];
2010 struct user_sgmap sg;
2011 };
2012
2013 #define AAC_SENSE_BUFFERSIZE 30
2014
2015 struct aac_srb_reply
2016 {
2017 __le32 status;
2018 __le32 srb_status;
2019 __le32 scsi_status;
2020 __le32 data_xfer_length;
2021 __le32 sense_data_size;
2022 u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE
2023 };
2024 /*
2025 * SRB Flags
2026 */
2027 #define SRB_NoDataXfer 0x0000
2028 #define SRB_DisableDisconnect 0x0004
2029 #define SRB_DisableSynchTransfer 0x0008
2030 #define SRB_BypassFrozenQueue 0x0010
2031 #define SRB_DisableAutosense 0x0020
2032 #define SRB_DataIn 0x0040
2033 #define SRB_DataOut 0x0080
2034
2035 /*
2036 * SRB Functions - set in aac_srb->function
2037 */
2038 #define SRBF_ExecuteScsi 0x0000
2039 #define SRBF_ClaimDevice 0x0001
2040 #define SRBF_IO_Control 0x0002
2041 #define SRBF_ReceiveEvent 0x0003
2042 #define SRBF_ReleaseQueue 0x0004
2043 #define SRBF_AttachDevice 0x0005
2044 #define SRBF_ReleaseDevice 0x0006
2045 #define SRBF_Shutdown 0x0007
2046 #define SRBF_Flush 0x0008
2047 #define SRBF_AbortCommand 0x0010
2048 #define SRBF_ReleaseRecovery 0x0011
2049 #define SRBF_ResetBus 0x0012
2050 #define SRBF_ResetDevice 0x0013
2051 #define SRBF_TerminateIO 0x0014
2052 #define SRBF_FlushQueue 0x0015
2053 #define SRBF_RemoveDevice 0x0016
2054 #define SRBF_DomainValidation 0x0017
2055
2056 /*
2057 * SRB SCSI Status - set in aac_srb->scsi_status
2058 */
2059 #define SRB_STATUS_PENDING 0x00
2060 #define SRB_STATUS_SUCCESS 0x01
2061 #define SRB_STATUS_ABORTED 0x02
2062 #define SRB_STATUS_ABORT_FAILED 0x03
2063 #define SRB_STATUS_ERROR 0x04
2064 #define SRB_STATUS_BUSY 0x05
2065 #define SRB_STATUS_INVALID_REQUEST 0x06
2066 #define SRB_STATUS_INVALID_PATH_ID 0x07
2067 #define SRB_STATUS_NO_DEVICE 0x08
2068 #define SRB_STATUS_TIMEOUT 0x09
2069 #define SRB_STATUS_SELECTION_TIMEOUT 0x0A
2070 #define SRB_STATUS_COMMAND_TIMEOUT 0x0B
2071 #define SRB_STATUS_MESSAGE_REJECTED 0x0D
2072 #define SRB_STATUS_BUS_RESET 0x0E
2073 #define SRB_STATUS_PARITY_ERROR 0x0F
2074 #define SRB_STATUS_REQUEST_SENSE_FAILED 0x10
2075 #define SRB_STATUS_NO_HBA 0x11
2076 #define SRB_STATUS_DATA_OVERRUN 0x12
2077 #define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13
2078 #define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14
2079 #define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15
2080 #define SRB_STATUS_REQUEST_FLUSHED 0x16
2081 #define SRB_STATUS_DELAYED_RETRY 0x17
2082 #define SRB_STATUS_INVALID_LUN 0x20
2083 #define SRB_STATUS_INVALID_TARGET_ID 0x21
2084 #define SRB_STATUS_BAD_FUNCTION 0x22
2085 #define SRB_STATUS_ERROR_RECOVERY 0x23
2086 #define SRB_STATUS_NOT_STARTED 0x24
2087 #define SRB_STATUS_NOT_IN_USE 0x30
2088 #define SRB_STATUS_FORCE_ABORT 0x31
2089 #define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32
2090
2091 /*
2092 * Object-Server / Volume-Manager Dispatch Classes
2093 */
2094
2095 #define VM_Null 0
2096 #define VM_NameServe 1
2097 #define VM_ContainerConfig 2
2098 #define VM_Ioctl 3
2099 #define VM_FilesystemIoctl 4
2100 #define VM_CloseAll 5
2101 #define VM_CtBlockRead 6
2102 #define VM_CtBlockWrite 7
2103 #define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */
2104 #define VM_SliceBlockWrite 9
2105 #define VM_DriveBlockRead 10 /* raw access to physical devices */
2106 #define VM_DriveBlockWrite 11
2107 #define VM_EnclosureMgt 12 /* enclosure management */
2108 #define VM_Unused 13 /* used to be diskset management */
2109 #define VM_CtBlockVerify 14
2110 #define VM_CtPerf 15 /* performance test */
2111 #define VM_CtBlockRead64 16
2112 #define VM_CtBlockWrite64 17
2113 #define VM_CtBlockVerify64 18
2114 #define VM_CtHostRead64 19
2115 #define VM_CtHostWrite64 20
2116 #define VM_DrvErrTblLog 21
2117 #define VM_NameServe64 22
2118 #define VM_NameServeAllBlk 30
2119
2120 #define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */
2121
2122 /*
2123 * Descriptive information (eg, vital stats)
2124 * that a content manager might report. The
2125 * FileArray filesystem component is one example
2126 * of a content manager. Raw mode might be
2127 * another.
2128 */
2129
2130 struct aac_fsinfo {
2131 __le32 fsTotalSize; /* Consumed by fs, incl. metadata */
2132 __le32 fsBlockSize;
2133 __le32 fsFragSize;
2134 __le32 fsMaxExtendSize;
2135 __le32 fsSpaceUnits;
2136 __le32 fsMaxNumFiles;
2137 __le32 fsNumFreeFiles;
2138 __le32 fsInodeDensity;
2139 }; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */
2140
2141 struct aac_blockdevinfo {
2142 __le32 block_size;
2143 __le32 logical_phys_map;
2144 u8 identifier[16];
2145 };
2146
2147 union aac_contentinfo {
2148 struct aac_fsinfo filesys;
2149 struct aac_blockdevinfo bdevinfo;
2150 };
2151
2152 /*
2153 * Query for Container Configuration Status
2154 */
2155
2156 #define CT_GET_CONFIG_STATUS 147
2157 struct aac_get_config_status {
2158 __le32 command; /* VM_ContainerConfig */
2159 __le32 type; /* CT_GET_CONFIG_STATUS */
2160 __le32 parm1;
2161 __le32 parm2;
2162 __le32 parm3;
2163 __le32 parm4;
2164 __le32 parm5;
2165 __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */
2166 };
2167
2168 #define CFACT_CONTINUE 0
2169 #define CFACT_PAUSE 1
2170 #define CFACT_ABORT 2
2171 struct aac_get_config_status_resp {
2172 __le32 response; /* ST_OK */
2173 __le32 dummy0;
2174 __le32 status; /* CT_OK */
2175 __le32 parm1;
2176 __le32 parm2;
2177 __le32 parm3;
2178 __le32 parm4;
2179 __le32 parm5;
2180 struct {
2181 __le32 action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */
2182 __le16 flags;
2183 __le16 count;
2184 } data;
2185 };
2186
2187 /*
2188 * Accept the configuration as-is
2189 */
2190
2191 #define CT_COMMIT_CONFIG 152
2192
2193 struct aac_commit_config {
2194 __le32 command; /* VM_ContainerConfig */
2195 __le32 type; /* CT_COMMIT_CONFIG */
2196 };
2197
2198 /*
2199 * Query for Container Configuration Status
2200 */
2201
2202 #define CT_GET_CONTAINER_COUNT 4
2203 struct aac_get_container_count {
2204 __le32 command; /* VM_ContainerConfig */
2205 __le32 type; /* CT_GET_CONTAINER_COUNT */
2206 };
2207
2208 struct aac_get_container_count_resp {
2209 __le32 response; /* ST_OK */
2210 __le32 dummy0;
2211 __le32 MaxContainers;
2212 __le32 ContainerSwitchEntries;
2213 __le32 MaxPartitions;
2214 __le32 MaxSimpleVolumes;
2215 };
2216
2217
2218 /*
2219 * Query for "mountable" objects, ie, objects that are typically
2220 * associated with a drive letter on the client (host) side.
2221 */
2222
2223 struct aac_mntent {
2224 __le32 oid;
2225 u8 name[16]; /* if applicable */
2226 struct creation_info create_info; /* if applicable */
2227 __le32 capacity;
2228 __le32 vol; /* substrate structure */
2229 __le32 obj; /* FT_FILESYS, etc. */
2230 __le32 state; /* unready for mounting,
2231 readonly, etc. */
2232 union aac_contentinfo fileinfo; /* Info specific to content
2233 manager (eg, filesystem) */
2234 __le32 altoid; /* != oid <==> snapshot or
2235 broken mirror exists */
2236 __le32 capacityhigh;
2237 };
2238
2239 #define FSCS_NOTCLEAN 0x0001 /* fsck is necessary before mounting */
2240 #define FSCS_READONLY 0x0002 /* possible result of broken mirror */
2241 #define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */
2242 #define FSCS_NOT_READY 0x0008 /* Array spinning up to fulfil request */
2243
2244 struct aac_query_mount {
2245 __le32 command;
2246 __le32 type;
2247 __le32 count;
2248 };
2249
2250 struct aac_mount {
2251 __le32 status;
2252 __le32 type; /* should be same as that requested */
2253 __le32 count;
2254 struct aac_mntent mnt[1];
2255 };
2256
2257 #define CT_READ_NAME 130
2258 struct aac_get_name {
2259 __le32 command; /* VM_ContainerConfig */
2260 __le32 type; /* CT_READ_NAME */
2261 __le32 cid;
2262 __le32 parm1;
2263 __le32 parm2;
2264 __le32 parm3;
2265 __le32 parm4;
2266 __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */
2267 };
2268
2269 struct aac_get_name_resp {
2270 __le32 dummy0;
2271 __le32 dummy1;
2272 __le32 status; /* CT_OK */
2273 __le32 parm1;
2274 __le32 parm2;
2275 __le32 parm3;
2276 __le32 parm4;
2277 __le32 parm5;
2278 u8 data[16];
2279 };
2280
2281 #define CT_CID_TO_32BITS_UID 165
2282 struct aac_get_serial {
2283 __le32 command; /* VM_ContainerConfig */
2284 __le32 type; /* CT_CID_TO_32BITS_UID */
2285 __le32 cid;
2286 };
2287
2288 struct aac_get_serial_resp {
2289 __le32 dummy0;
2290 __le32 dummy1;
2291 __le32 status; /* CT_OK */
2292 __le32 uid;
2293 };
2294
2295 /*
2296 * The following command is sent to shut down each container.
2297 */
2298
2299 struct aac_close {
2300 __le32 command;
2301 __le32 cid;
2302 };
2303
2304 struct aac_query_disk
2305 {
2306 s32 cnum;
2307 s32 bus;
2308 s32 id;
2309 s32 lun;
2310 u32 valid;
2311 u32 locked;
2312 u32 deleted;
2313 s32 instance;
2314 s8 name[10];
2315 u32 unmapped;
2316 };
2317
2318 struct aac_delete_disk {
2319 u32 disknum;
2320 u32 cnum;
2321 };
2322
2323 struct fib_ioctl
2324 {
2325 u32 fibctx;
2326 s32 wait;
2327 char __user *fib;
2328 };
2329
2330 struct revision
2331 {
2332 u32 compat;
2333 __le32 version;
2334 __le32 build;
2335 };
2336
2337
2338 /*
2339 * Ugly - non Linux like ioctl coding for back compat.
2340 */
2341
2342 #define CTL_CODE(function, method) ( \
2343 (4<< 16) | ((function) << 2) | (method) \
2344 )
2345
2346 /*
2347 * Define the method codes for how buffers are passed for I/O and FS
2348 * controls
2349 */
2350
2351 #define METHOD_BUFFERED 0
2352 #define METHOD_NEITHER 3
2353
2354 /*
2355 * Filesystem ioctls
2356 */
2357
2358 #define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED)
2359 #define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED)
2360 #define FSACTL_DELETE_DISK 0x163
2361 #define FSACTL_QUERY_DISK 0x173
2362 #define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED)
2363 #define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED)
2364 #define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED)
2365 #define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED)
2366 #define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED)
2367 #define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER)
2368 #define FSACTL_GET_CONTAINERS 2131
2369 #define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED)
2370 #define FSACTL_RESET_IOP CTL_CODE(2140, METHOD_BUFFERED)
2371 #define FSACTL_GET_HBA_INFO CTL_CODE(2150, METHOD_BUFFERED)
2372 /* flags defined for IOP & HW SOFT RESET */
2373 #define HW_IOP_RESET 0x01
2374 #define HW_SOFT_RESET 0x02
2375 #define IOP_HWSOFT_RESET (HW_IOP_RESET | HW_SOFT_RESET)
2376 /* HW Soft Reset register offset */
2377 #define IBW_SWR_OFFSET 0x4000
2378 #define SOFT_RESET_TIME 60
2379
2380
2381 struct aac_common
2382 {
2383 /*
2384 * If this value is set to 1 then interrupt moderation will occur
2385 * in the base commuication support.
2386 */
2387 u32 irq_mod;
2388 u32 peak_fibs;
2389 u32 zero_fibs;
2390 u32 fib_timeouts;
2391 /*
2392 * Statistical counters in debug mode
2393 */
2394 #ifdef DBG
2395 u32 FibsSent;
2396 u32 FibRecved;
2397 u32 NativeSent;
2398 u32 NativeRecved;
2399 u32 NoResponseSent;
2400 u32 NoResponseRecved;
2401 u32 AsyncSent;
2402 u32 AsyncRecved;
2403 u32 NormalSent;
2404 u32 NormalRecved;
2405 #endif
2406 };
2407
2408 extern struct aac_common aac_config;
2409
2410 /*
2411 * This is for management ioctl purpose only.
2412 */
2413 struct aac_hba_info {
2414
2415 u8 driver_name[50];
2416 u8 adapter_number;
2417 u8 system_io_bus_number;
2418 u8 device_number;
2419 u32 function_number;
2420 u32 vendor_id;
2421 u32 device_id;
2422 u32 sub_vendor_id;
2423 u32 sub_system_id;
2424 u32 mapped_base_address_size;
2425 u32 base_physical_address_high_part;
2426 u32 base_physical_address_low_part;
2427
2428 u32 max_command_size;
2429 u32 max_fib_size;
2430 u32 max_scatter_gather_from_os;
2431 u32 max_scatter_gather_to_fw;
2432 u32 max_outstanding_fibs;
2433
2434 u32 queue_start_threshold;
2435 u32 queue_dump_threshold;
2436 u32 max_io_size_queued;
2437 u32 outstanding_io;
2438
2439 u32 firmware_build_number;
2440 u32 bios_build_number;
2441 u32 driver_build_number;
2442 u32 serial_number_high_part;
2443 u32 serial_number_low_part;
2444 u32 supported_options;
2445 u32 feature_bits;
2446 u32 currentnumber_ports;
2447
2448 u8 new_comm_interface:1;
2449 u8 new_commands_supported:1;
2450 u8 disable_passthrough:1;
2451 u8 expose_non_dasd:1;
2452 u8 queue_allowed:1;
2453 u8 bled_check_enabled:1;
2454 u8 reserved1:1;
2455 u8 reserted2:1;
2456
2457 u32 reserved3[10];
2458
2459 };
2460
2461 /*
2462 * The following macro is used when sending and receiving FIBs. It is
2463 * only used for debugging.
2464 */
2465
2466 #ifdef DBG
2467 #define FIB_COUNTER_INCREMENT(counter) (counter)++
2468 #else
2469 #define FIB_COUNTER_INCREMENT(counter)
2470 #endif
2471
2472 /*
2473 * Adapter direct commands
2474 * Monitor/Kernel API
2475 */
2476
2477 #define BREAKPOINT_REQUEST 0x00000004
2478 #define INIT_STRUCT_BASE_ADDRESS 0x00000005
2479 #define READ_PERMANENT_PARAMETERS 0x0000000a
2480 #define WRITE_PERMANENT_PARAMETERS 0x0000000b
2481 #define HOST_CRASHING 0x0000000d
2482 #define SEND_SYNCHRONOUS_FIB 0x0000000c
2483 #define COMMAND_POST_RESULTS 0x00000014
2484 #define GET_ADAPTER_PROPERTIES 0x00000019
2485 #define GET_DRIVER_BUFFER_PROPERTIES 0x00000023
2486 #define RCV_TEMP_READINGS 0x00000025
2487 #define GET_COMM_PREFERRED_SETTINGS 0x00000026
2488 #define IOP_RESET_FW_FIB_DUMP 0x00000034
2489 #define IOP_RESET 0x00001000
2490 #define IOP_RESET_ALWAYS 0x00001001
2491 #define RE_INIT_ADAPTER 0x000000ee
2492
2493 /*
2494 * Adapter Status Register
2495 *
2496 * Phase Staus mailbox is 32bits:
2497 * <31:16> = Phase Status
2498 * <15:0> = Phase
2499 *
2500 * The adapter reports is present state through the phase. Only
2501 * a single phase should be ever be set. Each phase can have multiple
2502 * phase status bits to provide more detailed information about the
2503 * state of the board. Care should be taken to ensure that any phase
2504 * status bits that are set when changing the phase are also valid
2505 * for the new phase or be cleared out. Adapter software (monitor,
2506 * iflash, kernel) is responsible for properly maintining the phase
2507 * status mailbox when it is running.
2508 *
2509 * MONKER_API Phases
2510 *
2511 * Phases are bit oriented. It is NOT valid to have multiple bits set
2512 */
2513
2514 #define SELF_TEST_FAILED 0x00000004
2515 #define MONITOR_PANIC 0x00000020
2516 #define KERNEL_UP_AND_RUNNING 0x00000080
2517 #define KERNEL_PANIC 0x00000100
2518 #define FLASH_UPD_PENDING 0x00002000
2519 #define FLASH_UPD_SUCCESS 0x00004000
2520 #define FLASH_UPD_FAILED 0x00008000
2521 #define FWUPD_TIMEOUT (5 * 60)
2522
2523 /*
2524 * Doorbell bit defines
2525 */
2526
2527 #define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */
2528 #define DoorBellPrintfDone (1<<5) /* Host -> Adapter */
2529 #define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */
2530 #define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */
2531 #define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */
2532 #define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */
2533 #define DoorBellPrintfReady (1<<5) /* Adapter -> Host */
2534 #define DoorBellAifPending (1<<6) /* Adapter -> Host */
2535
2536 /* PMC specific outbound doorbell bits */
2537 #define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */
2538
2539 /*
2540 * For FIB communication, we need all of the following things
2541 * to send back to the user.
2542 */
2543
2544 #define AifCmdEventNotify 1 /* Notify of event */
2545 #define AifEnConfigChange 3 /* Adapter configuration change */
2546 #define AifEnContainerChange 4 /* Container configuration change */
2547 #define AifEnDeviceFailure 5 /* SCSI device failed */
2548 #define AifEnEnclosureManagement 13 /* EM_DRIVE_* */
2549 #define EM_DRIVE_INSERTION 31
2550 #define EM_DRIVE_REMOVAL 32
2551 #define EM_SES_DRIVE_INSERTION 33
2552 #define EM_SES_DRIVE_REMOVAL 26
2553 #define AifEnBatteryEvent 14 /* Change in Battery State */
2554 #define AifEnAddContainer 15 /* A new array was created */
2555 #define AifEnDeleteContainer 16 /* A container was deleted */
2556 #define AifEnExpEvent 23 /* Firmware Event Log */
2557 #define AifExeFirmwarePanic 3 /* Firmware Event Panic */
2558 #define AifHighPriority 3 /* Highest Priority Event */
2559 #define AifEnAddJBOD 30 /* JBOD created */
2560 #define AifEnDeleteJBOD 31 /* JBOD deleted */
2561
2562 #define AifBuManagerEvent 42 /* Bu management*/
2563 #define AifBuCacheDataLoss 10
2564 #define AifBuCacheDataRecover 11
2565
2566 #define AifCmdJobProgress 2 /* Progress report */
2567 #define AifJobCtrZero 101 /* Array Zero progress */
2568 #define AifJobStsSuccess 1 /* Job completes */
2569 #define AifJobStsRunning 102 /* Job running */
2570 #define AifCmdAPIReport 3 /* Report from other user of API */
2571 #define AifCmdDriverNotify 4 /* Notify host driver of event */
2572 #define AifDenMorphComplete 200 /* A morph operation completed */
2573 #define AifDenVolumeExtendComplete 201 /* A volume extend completed */
2574 #define AifReqJobList 100 /* Gets back complete job list */
2575 #define AifReqJobsForCtr 101 /* Gets back jobs for specific container */
2576 #define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */
2577 #define AifReqJobReport 103 /* Gets back a specific job report or list of them */
2578 #define AifReqTerminateJob 104 /* Terminates job */
2579 #define AifReqSuspendJob 105 /* Suspends a job */
2580 #define AifReqResumeJob 106 /* Resumes a job */
2581 #define AifReqSendAPIReport 107 /* API generic report requests */
2582 #define AifReqAPIJobStart 108 /* Start a job from the API */
2583 #define AifReqAPIJobUpdate 109 /* Update a job report from the API */
2584 #define AifReqAPIJobFinish 110 /* Finish a job from the API */
2585
2586 /* PMC NEW COMM: Request the event data */
2587 #define AifReqEvent 200
2588 #define AifRawDeviceRemove 203 /* RAW device deleted */
2589 #define AifNativeDeviceAdd 204 /* native HBA device added */
2590 #define AifNativeDeviceRemove 205 /* native HBA device removed */
2591
2592
2593 /*
2594 * Adapter Initiated FIB command structures. Start with the adapter
2595 * initiated FIBs that really come from the adapter, and get responded
2596 * to by the host.
2597 */
2598
2599 struct aac_aifcmd {
2600 __le32 command; /* Tell host what type of notify this is */
2601 __le32 seqnum; /* To allow ordering of reports (if necessary) */
2602 u8 data[1]; /* Undefined length (from kernel viewpoint) */
2603 };
2604
2605 /**
2606 * Convert capacity to cylinders
2607 * accounting for the fact capacity could be a 64 bit value
2608 *
2609 */
2610 static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor)
2611 {
2612 sector_div(capacity, divisor);
2613 return capacity;
2614 }
2615
2616 static inline int aac_adapter_check_health(struct aac_dev *dev)
2617 {
2618 if (unlikely(pci_channel_offline(dev->pdev)))
2619 return -1;
2620
2621 return (dev)->a_ops.adapter_check_health(dev);
2622 }
2623
2624 /* SCp.phase values */
2625 #define AAC_OWNER_MIDLEVEL 0x101
2626 #define AAC_OWNER_LOWLEVEL 0x102
2627 #define AAC_OWNER_ERROR_HANDLER 0x103
2628 #define AAC_OWNER_FIRMWARE 0x106
2629
2630 int aac_acquire_irq(struct aac_dev *dev);
2631 void aac_free_irq(struct aac_dev *dev);
2632 int aac_report_phys_luns(struct aac_dev *dev, struct fib *fibptr, int rescan);
2633 int aac_issue_bmic_identify(struct aac_dev *dev, u32 bus, u32 target);
2634 const char *aac_driverinfo(struct Scsi_Host *);
2635 void aac_fib_vector_assign(struct aac_dev *dev);
2636 struct fib *aac_fib_alloc(struct aac_dev *dev);
2637 struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd);
2638 int aac_fib_setup(struct aac_dev *dev);
2639 void aac_fib_map_free(struct aac_dev *dev);
2640 void aac_fib_free(struct fib * context);
2641 void aac_fib_init(struct fib * context);
2642 void aac_printf(struct aac_dev *dev, u32 val);
2643 int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt);
2644 int aac_hba_send(u8 command, struct fib *context,
2645 fib_callback callback, void *ctxt);
2646 int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry);
2647 void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum);
2648 int aac_fib_complete(struct fib * context);
2649 void aac_hba_callback(void *context, struct fib *fibptr);
2650 #define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data)
2651 struct aac_dev *aac_init_adapter(struct aac_dev *dev);
2652 void aac_src_access_devreg(struct aac_dev *dev, int mode);
2653 void aac_set_intx_mode(struct aac_dev *dev);
2654 int aac_get_config_status(struct aac_dev *dev, int commit_flag);
2655 int aac_get_containers(struct aac_dev *dev);
2656 int aac_scsi_cmd(struct scsi_cmnd *cmd);
2657 int aac_dev_ioctl(struct aac_dev *dev, int cmd, void __user *arg);
2658 #ifndef shost_to_class
2659 #define shost_to_class(shost) &shost->shost_dev
2660 #endif
2661 ssize_t aac_get_serial_number(struct device *dev, char *buf);
2662 int aac_do_ioctl(struct aac_dev * dev, int cmd, void __user *arg);
2663 int aac_rx_init(struct aac_dev *dev);
2664 int aac_rkt_init(struct aac_dev *dev);
2665 int aac_nark_init(struct aac_dev *dev);
2666 int aac_sa_init(struct aac_dev *dev);
2667 int aac_src_init(struct aac_dev *dev);
2668 int aac_srcv_init(struct aac_dev *dev);
2669 int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify);
2670 void aac_define_int_mode(struct aac_dev *dev);
2671 unsigned int aac_response_normal(struct aac_queue * q);
2672 unsigned int aac_command_normal(struct aac_queue * q);
2673 unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index,
2674 int isAif, int isFastResponse,
2675 struct hw_fib *aif_fib);
2676 int aac_reset_adapter(struct aac_dev *dev, int forced, u8 reset_type);
2677 int aac_check_health(struct aac_dev * dev);
2678 int aac_command_thread(void *data);
2679 int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx);
2680 int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size);
2681 struct aac_driver_ident* aac_get_driver_ident(int devtype);
2682 int aac_get_adapter_info(struct aac_dev* dev);
2683 int aac_send_shutdown(struct aac_dev *dev);
2684 int aac_probe_container(struct aac_dev *dev, int cid);
2685 int _aac_rx_init(struct aac_dev *dev);
2686 int aac_rx_select_comm(struct aac_dev *dev, int comm);
2687 int aac_rx_deliver_producer(struct fib * fib);
2688 char * get_container_type(unsigned type);
2689 extern int numacb;
2690 extern char aac_driver_version[];
2691 extern int startup_timeout;
2692 extern int aif_timeout;
2693 extern int expose_physicals;
2694 extern int aac_reset_devices;
2695 extern int aac_msi;
2696 extern int aac_commit;
2697 extern int update_interval;
2698 extern int check_interval;
2699 extern int aac_check_reset;
2700 extern int aac_fib_dump;
2701 #endif
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