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HID: usbhid: Add HID_QUIRK_NOGET for Aten CS-1758 KVM switch
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / aacraid / aacraid.h
1 #ifndef dprintk
2 # define dprintk(x)
3 #endif
4 /* eg: if (nblank(dprintk(x))) */
5 #define _nblank(x) #x
6 #define nblank(x) _nblank(x)[0]
7
8 #include <linux/interrupt.h>
9 #include <linux/pci.h>
10
11 /*------------------------------------------------------------------------------
12 * D E F I N E S
13 *----------------------------------------------------------------------------*/
14
15 #define AAC_MAX_MSIX 32 /* vectors */
16 #define AAC_PCI_MSI_ENABLE 0x8000
17
18 enum {
19 AAC_ENABLE_INTERRUPT = 0x0,
20 AAC_DISABLE_INTERRUPT,
21 AAC_ENABLE_MSIX,
22 AAC_DISABLE_MSIX,
23 AAC_CLEAR_AIF_BIT,
24 AAC_CLEAR_SYNC_BIT,
25 AAC_ENABLE_INTX
26 };
27
28 #define AAC_INT_MODE_INTX (1<<0)
29 #define AAC_INT_MODE_MSI (1<<1)
30 #define AAC_INT_MODE_AIF (1<<2)
31 #define AAC_INT_MODE_SYNC (1<<3)
32 #define AAC_INT_MODE_MSIX (1<<16)
33
34 #define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb
35 #define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa
36 #define AAC_INT_DISABLE_ALL 0xffffffff
37
38 /* Bit definitions in IOA->Host Interrupt Register */
39 #define PMC_TRANSITION_TO_OPERATIONAL (1<<31)
40 #define PMC_IOARCB_TRANSFER_FAILED (1<<28)
41 #define PMC_IOA_UNIT_CHECK (1<<27)
42 #define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26)
43 #define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25)
44 #define PMC_IOARRIN_LOST (1<<4)
45 #define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3)
46 #define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2)
47 #define PMC_HOST_RRQ_VALID (1<<1)
48 #define PMC_OPERATIONAL_STATUS (1<<31)
49 #define PMC_ALLOW_MSIX_VECTOR0 (1<<0)
50
51 #define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \
52 PMC_IOA_UNIT_CHECK | \
53 PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \
54 PMC_IOARRIN_LOST | \
55 PMC_SYSTEM_BUS_MMIO_ERROR | \
56 PMC_IOA_PROCESSOR_IN_ERROR_STATE)
57
58 #define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \
59 PMC_HOST_RRQ_VALID | \
60 PMC_TRANSITION_TO_OPERATIONAL | \
61 PMC_ALLOW_MSIX_VECTOR0)
62 #define PMC_GLOBAL_INT_BIT2 0x00000004
63 #define PMC_GLOBAL_INT_BIT0 0x00000001
64
65 #ifndef AAC_DRIVER_BUILD
66 # define AAC_DRIVER_BUILD 41066
67 # define AAC_DRIVER_BRANCH "-ms"
68 #endif
69 #define MAXIMUM_NUM_CONTAINERS 32
70
71 #define AAC_NUM_MGT_FIB 8
72 #define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB)
73 #define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB)
74
75 #define AAC_MAX_LUN (8)
76
77 #define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff)
78 #define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256)
79
80 #define AAC_DEBUG_INSTRUMENT_AIF_DELETE
81
82 /*
83 * These macros convert from physical channels to virtual channels
84 */
85 #define CONTAINER_CHANNEL (0)
86 #define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL)
87 #define CONTAINER_TO_ID(cont) (cont)
88 #define CONTAINER_TO_LUN(cont) (0)
89
90 #define PMC_DEVICE_S6 0x28b
91 #define PMC_DEVICE_S7 0x28c
92 #define PMC_DEVICE_S8 0x28d
93 #define PMC_DEVICE_S9 0x28f
94
95 #define aac_phys_to_logical(x) ((x)+1)
96 #define aac_logical_to_phys(x) ((x)?(x)-1:0)
97
98 /*
99 * These macros are for keeping track of
100 * character device state.
101 */
102 #define AAC_CHARDEV_UNREGISTERED (-1)
103 #define AAC_CHARDEV_NEEDS_REINIT (-2)
104
105 /* #define AAC_DETAILED_STATUS_INFO */
106
107 struct diskparm
108 {
109 int heads;
110 int sectors;
111 int cylinders;
112 };
113
114
115 /*
116 * Firmware constants
117 */
118
119 #define CT_NONE 0
120 #define CT_OK 218
121 #define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */
122 #define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */
123
124 /*
125 * Host side memory scatter gather list
126 * Used by the adapter for read, write, and readdirplus operations
127 * We have separate 32 and 64 bit version because even
128 * on 64 bit systems not all cards support the 64 bit version
129 */
130 struct sgentry {
131 __le32 addr; /* 32-bit address. */
132 __le32 count; /* Length. */
133 };
134
135 struct user_sgentry {
136 u32 addr; /* 32-bit address. */
137 u32 count; /* Length. */
138 };
139
140 struct sgentry64 {
141 __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
142 __le32 count; /* Length. */
143 };
144
145 struct user_sgentry64 {
146 u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
147 u32 count; /* Length. */
148 };
149
150 struct sgentryraw {
151 __le32 next; /* reserved for F/W use */
152 __le32 prev; /* reserved for F/W use */
153 __le32 addr[2];
154 __le32 count;
155 __le32 flags; /* reserved for F/W use */
156 };
157
158 struct user_sgentryraw {
159 u32 next; /* reserved for F/W use */
160 u32 prev; /* reserved for F/W use */
161 u32 addr[2];
162 u32 count;
163 u32 flags; /* reserved for F/W use */
164 };
165
166 struct sge_ieee1212 {
167 u32 addrLow;
168 u32 addrHigh;
169 u32 length;
170 u32 flags;
171 };
172
173 /*
174 * SGMAP
175 *
176 * This is the SGMAP structure for all commands that use
177 * 32-bit addressing.
178 */
179
180 struct sgmap {
181 __le32 count;
182 struct sgentry sg[1];
183 };
184
185 struct user_sgmap {
186 u32 count;
187 struct user_sgentry sg[1];
188 };
189
190 struct sgmap64 {
191 __le32 count;
192 struct sgentry64 sg[1];
193 };
194
195 struct user_sgmap64 {
196 u32 count;
197 struct user_sgentry64 sg[1];
198 };
199
200 struct sgmapraw {
201 __le32 count;
202 struct sgentryraw sg[1];
203 };
204
205 struct user_sgmapraw {
206 u32 count;
207 struct user_sgentryraw sg[1];
208 };
209
210 struct creation_info
211 {
212 u8 buildnum; /* e.g., 588 */
213 u8 usec; /* e.g., 588 */
214 u8 via; /* e.g., 1 = FSU,
215 * 2 = API
216 */
217 u8 year; /* e.g., 1997 = 97 */
218 __le32 date; /*
219 * unsigned Month :4; // 1 - 12
220 * unsigned Day :6; // 1 - 32
221 * unsigned Hour :6; // 0 - 23
222 * unsigned Minute :6; // 0 - 60
223 * unsigned Second :6; // 0 - 60
224 */
225 __le32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */
226 };
227
228
229 /*
230 * Define all the constants needed for the communication interface
231 */
232
233 /*
234 * Define how many queue entries each queue will have and the total
235 * number of entries for the entire communication interface. Also define
236 * how many queues we support.
237 *
238 * This has to match the controller
239 */
240
241 #define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response
242 #define HOST_HIGH_CMD_ENTRIES 4
243 #define HOST_NORM_CMD_ENTRIES 8
244 #define ADAP_HIGH_CMD_ENTRIES 4
245 #define ADAP_NORM_CMD_ENTRIES 512
246 #define HOST_HIGH_RESP_ENTRIES 4
247 #define HOST_NORM_RESP_ENTRIES 512
248 #define ADAP_HIGH_RESP_ENTRIES 4
249 #define ADAP_NORM_RESP_ENTRIES 8
250
251 #define TOTAL_QUEUE_ENTRIES \
252 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \
253 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES)
254
255
256 /*
257 * Set the queues on a 16 byte alignment
258 */
259
260 #define QUEUE_ALIGNMENT 16
261
262 /*
263 * The queue headers define the Communication Region queues. These
264 * are physically contiguous and accessible by both the adapter and the
265 * host. Even though all queue headers are in the same contiguous block
266 * they will be represented as individual units in the data structures.
267 */
268
269 struct aac_entry {
270 __le32 size; /* Size in bytes of Fib which this QE points to */
271 __le32 addr; /* Receiver address of the FIB */
272 };
273
274 /*
275 * The adapter assumes the ProducerIndex and ConsumerIndex are grouped
276 * adjacently and in that order.
277 */
278
279 struct aac_qhdr {
280 __le64 header_addr;/* Address to hand the adapter to access
281 to this queue head */
282 __le32 *producer; /* The producer index for this queue (host address) */
283 __le32 *consumer; /* The consumer index for this queue (host address) */
284 };
285
286 /*
287 * Define all the events which the adapter would like to notify
288 * the host of.
289 */
290
291 #define HostNormCmdQue 1 /* Change in host normal priority command queue */
292 #define HostHighCmdQue 2 /* Change in host high priority command queue */
293 #define HostNormRespQue 3 /* Change in host normal priority response queue */
294 #define HostHighRespQue 4 /* Change in host high priority response queue */
295 #define AdapNormRespNotFull 5
296 #define AdapHighRespNotFull 6
297 #define AdapNormCmdNotFull 7
298 #define AdapHighCmdNotFull 8
299 #define SynchCommandComplete 9
300 #define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */
301
302 /*
303 * Define all the events the host wishes to notify the
304 * adapter of. The first four values much match the Qid the
305 * corresponding queue.
306 */
307
308 #define AdapNormCmdQue 2
309 #define AdapHighCmdQue 3
310 #define AdapNormRespQue 6
311 #define AdapHighRespQue 7
312 #define HostShutdown 8
313 #define HostPowerFail 9
314 #define FatalCommError 10
315 #define HostNormRespNotFull 11
316 #define HostHighRespNotFull 12
317 #define HostNormCmdNotFull 13
318 #define HostHighCmdNotFull 14
319 #define FastIo 15
320 #define AdapPrintfDone 16
321
322 /*
323 * Define all the queues that the adapter and host use to communicate
324 * Number them to match the physical queue layout.
325 */
326
327 enum aac_queue_types {
328 HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */
329 HostHighCmdQueue, /* Adapter to host high priority command traffic */
330 AdapNormCmdQueue, /* Host to adapter normal priority command traffic */
331 AdapHighCmdQueue, /* Host to adapter high priority command traffic */
332 HostNormRespQueue, /* Adapter to host normal priority response traffic */
333 HostHighRespQueue, /* Adapter to host high priority response traffic */
334 AdapNormRespQueue, /* Host to adapter normal priority response traffic */
335 AdapHighRespQueue /* Host to adapter high priority response traffic */
336 };
337
338 /*
339 * Assign type values to the FSA communication data structures
340 */
341
342 #define FIB_MAGIC 0x0001
343 #define FIB_MAGIC2 0x0004
344 #define FIB_MAGIC2_64 0x0005
345
346 /*
347 * Define the priority levels the FSA communication routines support.
348 */
349
350 #define FsaNormal 1
351
352 /* transport FIB header (PMC) */
353 struct aac_fib_xporthdr {
354 u64 HostAddress; /* FIB host address w/o xport header */
355 u32 Size; /* FIB size excluding xport header */
356 u32 Handle; /* driver handle to reference the FIB */
357 u64 Reserved[2];
358 };
359
360 #define ALIGN32 32
361
362 /*
363 * Define the FIB. The FIB is the where all the requested data and
364 * command information are put to the application on the FSA adapter.
365 */
366
367 struct aac_fibhdr {
368 __le32 XferState; /* Current transfer state for this CCB */
369 __le16 Command; /* Routing information for the destination */
370 u8 StructType; /* Type FIB */
371 u8 Unused; /* Unused */
372 __le16 Size; /* Size of this FIB in bytes */
373 __le16 SenderSize; /* Size of the FIB in the sender
374 (for response sizing) */
375 __le32 SenderFibAddress; /* Host defined data in the FIB */
376 union {
377 __le32 ReceiverFibAddress;/* Logical address of this FIB for
378 the adapter (old) */
379 __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */
380 __le32 TimeStamp; /* otherwise timestamp for FW internal use */
381 } u;
382 u32 Handle; /* FIB handle used for MSGU commnunication */
383 u32 Previous; /* FW internal use */
384 u32 Next; /* FW internal use */
385 };
386
387 struct hw_fib {
388 struct aac_fibhdr header;
389 u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data
390 };
391
392 /*
393 * FIB commands
394 */
395
396 #define TestCommandResponse 1
397 #define TestAdapterCommand 2
398 /*
399 * Lowlevel and comm commands
400 */
401 #define LastTestCommand 100
402 #define ReinitHostNormCommandQueue 101
403 #define ReinitHostHighCommandQueue 102
404 #define ReinitHostHighRespQueue 103
405 #define ReinitHostNormRespQueue 104
406 #define ReinitAdapNormCommandQueue 105
407 #define ReinitAdapHighCommandQueue 107
408 #define ReinitAdapHighRespQueue 108
409 #define ReinitAdapNormRespQueue 109
410 #define InterfaceShutdown 110
411 #define DmaCommandFib 120
412 #define StartProfile 121
413 #define TermProfile 122
414 #define SpeedTest 123
415 #define TakeABreakPt 124
416 #define RequestPerfData 125
417 #define SetInterruptDefTimer 126
418 #define SetInterruptDefCount 127
419 #define GetInterruptDefStatus 128
420 #define LastCommCommand 129
421 /*
422 * Filesystem commands
423 */
424 #define NuFileSystem 300
425 #define UFS 301
426 #define HostFileSystem 302
427 #define LastFileSystemCommand 303
428 /*
429 * Container Commands
430 */
431 #define ContainerCommand 500
432 #define ContainerCommand64 501
433 #define ContainerRawIo 502
434 #define ContainerRawIo2 503
435 /*
436 * Scsi Port commands (scsi passthrough)
437 */
438 #define ScsiPortCommand 600
439 #define ScsiPortCommand64 601
440 /*
441 * Misc house keeping and generic adapter initiated commands
442 */
443 #define AifRequest 700
444 #define CheckRevision 701
445 #define FsaHostShutdown 702
446 #define RequestAdapterInfo 703
447 #define IsAdapterPaused 704
448 #define SendHostTime 705
449 #define RequestSupplementAdapterInfo 706
450 #define LastMiscCommand 707
451
452 /*
453 * Commands that will target the failover level on the FSA adapter
454 */
455
456 enum fib_xfer_state {
457 HostOwned = (1<<0),
458 AdapterOwned = (1<<1),
459 FibInitialized = (1<<2),
460 FibEmpty = (1<<3),
461 AllocatedFromPool = (1<<4),
462 SentFromHost = (1<<5),
463 SentFromAdapter = (1<<6),
464 ResponseExpected = (1<<7),
465 NoResponseExpected = (1<<8),
466 AdapterProcessed = (1<<9),
467 HostProcessed = (1<<10),
468 HighPriority = (1<<11),
469 NormalPriority = (1<<12),
470 Async = (1<<13),
471 AsyncIo = (1<<13), // rpbfix: remove with new regime
472 PageFileIo = (1<<14), // rpbfix: remove with new regime
473 ShutdownRequest = (1<<15),
474 LazyWrite = (1<<16), // rpbfix: remove with new regime
475 AdapterMicroFib = (1<<17),
476 BIOSFibPath = (1<<18),
477 FastResponseCapable = (1<<19),
478 ApiFib = (1<<20), /* Its an API Fib */
479 /* PMC NEW COMM: There is no more AIF data pending */
480 NoMoreAifDataAvailable = (1<<21)
481 };
482
483 /*
484 * The following defines needs to be updated any time there is an
485 * incompatible change made to the aac_init structure.
486 */
487
488 #define ADAPTER_INIT_STRUCT_REVISION 3
489 #define ADAPTER_INIT_STRUCT_REVISION_4 4 // rocket science
490 #define ADAPTER_INIT_STRUCT_REVISION_6 6 /* PMC src */
491 #define ADAPTER_INIT_STRUCT_REVISION_7 7 /* Denali */
492
493 struct aac_init
494 {
495 __le32 InitStructRevision;
496 __le32 Sa_MSIXVectors;
497 __le32 fsrev;
498 __le32 CommHeaderAddress;
499 __le32 FastIoCommAreaAddress;
500 __le32 AdapterFibsPhysicalAddress;
501 __le32 AdapterFibsVirtualAddress;
502 __le32 AdapterFibsSize;
503 __le32 AdapterFibAlign;
504 __le32 printfbuf;
505 __le32 printfbufsiz;
506 __le32 HostPhysMemPages; /* number of 4k pages of host
507 physical memory */
508 __le32 HostElapsedSeconds; /* number of seconds since 1970. */
509 /*
510 * ADAPTER_INIT_STRUCT_REVISION_4 begins here
511 */
512 __le32 InitFlags; /* flags for supported features */
513 #define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001
514 #define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010
515 #define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020
516 #define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040
517 #define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080
518 #define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100
519 __le32 MaxIoCommands; /* max outstanding commands */
520 __le32 MaxIoSize; /* largest I/O command */
521 __le32 MaxFibSize; /* largest FIB to adapter */
522 /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */
523 __le32 MaxNumAif; /* max number of aif */
524 /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */
525 __le32 HostRRQ_AddrLow;
526 __le32 HostRRQ_AddrHigh; /* Host RRQ (response queue) for SRC */
527 };
528
529 enum aac_log_level {
530 LOG_AAC_INIT = 10,
531 LOG_AAC_INFORMATIONAL = 20,
532 LOG_AAC_WARNING = 30,
533 LOG_AAC_LOW_ERROR = 40,
534 LOG_AAC_MEDIUM_ERROR = 50,
535 LOG_AAC_HIGH_ERROR = 60,
536 LOG_AAC_PANIC = 70,
537 LOG_AAC_DEBUG = 80,
538 LOG_AAC_WINDBG_PRINT = 90
539 };
540
541 #define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b
542 #define FSAFS_NTC_FIB_CONTEXT 0x030c
543
544 struct aac_dev;
545 struct fib;
546 struct scsi_cmnd;
547
548 struct adapter_ops
549 {
550 /* Low level operations */
551 void (*adapter_interrupt)(struct aac_dev *dev);
552 void (*adapter_notify)(struct aac_dev *dev, u32 event);
553 void (*adapter_disable_int)(struct aac_dev *dev);
554 void (*adapter_enable_int)(struct aac_dev *dev);
555 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4);
556 int (*adapter_check_health)(struct aac_dev *dev);
557 int (*adapter_restart)(struct aac_dev *dev, int bled);
558 void (*adapter_start)(struct aac_dev *dev);
559 /* Transport operations */
560 int (*adapter_ioremap)(struct aac_dev * dev, u32 size);
561 irq_handler_t adapter_intr;
562 /* Packet operations */
563 int (*adapter_deliver)(struct fib * fib);
564 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba);
565 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count);
566 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua);
567 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd);
568 /* Administrative operations */
569 int (*adapter_comm)(struct aac_dev * dev, int comm);
570 };
571
572 /*
573 * Define which interrupt handler needs to be installed
574 */
575
576 struct aac_driver_ident
577 {
578 int (*init)(struct aac_dev *dev);
579 char * name;
580 char * vname;
581 char * model;
582 u16 channels;
583 int quirks;
584 };
585 /*
586 * Some adapter firmware needs communication memory
587 * below 2gig. This tells the init function to set the
588 * dma mask such that fib memory will be allocated where the
589 * adapter firmware can get to it.
590 */
591 #define AAC_QUIRK_31BIT 0x0001
592
593 /*
594 * Some adapter firmware, when the raid card's cache is turned off, can not
595 * split up scatter gathers in order to deal with the limits of the
596 * underlying CHIM. This limit is 34 scatter gather elements.
597 */
598 #define AAC_QUIRK_34SG 0x0002
599
600 /*
601 * This adapter is a slave (no Firmware)
602 */
603 #define AAC_QUIRK_SLAVE 0x0004
604
605 /*
606 * This adapter is a master.
607 */
608 #define AAC_QUIRK_MASTER 0x0008
609
610 /*
611 * Some adapter firmware perform poorly when it must split up scatter gathers
612 * in order to deal with the limits of the underlying CHIM. This limit in this
613 * class of adapters is 17 scatter gather elements.
614 */
615 #define AAC_QUIRK_17SG 0x0010
616
617 /*
618 * Some adapter firmware does not support 64 bit scsi passthrough
619 * commands.
620 */
621 #define AAC_QUIRK_SCSI_32 0x0020
622
623 /*
624 * SRC based adapters support the AifReqEvent functions
625 */
626 #define AAC_QUIRK_SRC 0x0040
627
628 /*
629 * The adapter interface specs all queues to be located in the same
630 * physically contiguous block. The host structure that defines the
631 * commuication queues will assume they are each a separate physically
632 * contiguous memory region that will support them all being one big
633 * contiguous block.
634 * There is a command and response queue for each level and direction of
635 * commuication. These regions are accessed by both the host and adapter.
636 */
637
638 struct aac_queue {
639 u64 logical; /*address we give the adapter */
640 struct aac_entry *base; /*system virtual address */
641 struct aac_qhdr headers; /*producer,consumer q headers*/
642 u32 entries; /*Number of queue entries */
643 wait_queue_head_t qfull; /*Event to wait on if q full */
644 wait_queue_head_t cmdready; /*Cmd ready from the adapter */
645 /* This is only valid for adapter to host command queues. */
646 spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */
647 spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */
648 struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */
649 /* only valid for command queues which receive entries from the adapter. */
650 /* Number of entries on outstanding queue. */
651 atomic_t numpending;
652 struct aac_dev * dev; /* Back pointer to adapter structure */
653 };
654
655 /*
656 * Message queues. The order here is important, see also the
657 * queue type ordering
658 */
659
660 struct aac_queue_block
661 {
662 struct aac_queue queue[8];
663 };
664
665 /*
666 * SaP1 Message Unit Registers
667 */
668
669 struct sa_drawbridge_CSR {
670 /* Offset | Name */
671 __le32 reserved[10]; /* 00h-27h | Reserved */
672 u8 LUT_Offset; /* 28h | Lookup Table Offset */
673 u8 reserved1[3]; /* 29h-2bh | Reserved */
674 __le32 LUT_Data; /* 2ch | Looup Table Data */
675 __le32 reserved2[26]; /* 30h-97h | Reserved */
676 __le16 PRICLEARIRQ; /* 98h | Primary Clear Irq */
677 __le16 SECCLEARIRQ; /* 9ah | Secondary Clear Irq */
678 __le16 PRISETIRQ; /* 9ch | Primary Set Irq */
679 __le16 SECSETIRQ; /* 9eh | Secondary Set Irq */
680 __le16 PRICLEARIRQMASK;/* a0h | Primary Clear Irq Mask */
681 __le16 SECCLEARIRQMASK;/* a2h | Secondary Clear Irq Mask */
682 __le16 PRISETIRQMASK; /* a4h | Primary Set Irq Mask */
683 __le16 SECSETIRQMASK; /* a6h | Secondary Set Irq Mask */
684 __le32 MAILBOX0; /* a8h | Scratchpad 0 */
685 __le32 MAILBOX1; /* ach | Scratchpad 1 */
686 __le32 MAILBOX2; /* b0h | Scratchpad 2 */
687 __le32 MAILBOX3; /* b4h | Scratchpad 3 */
688 __le32 MAILBOX4; /* b8h | Scratchpad 4 */
689 __le32 MAILBOX5; /* bch | Scratchpad 5 */
690 __le32 MAILBOX6; /* c0h | Scratchpad 6 */
691 __le32 MAILBOX7; /* c4h | Scratchpad 7 */
692 __le32 ROM_Setup_Data; /* c8h | Rom Setup and Data */
693 __le32 ROM_Control_Addr;/* cch | Rom Control and Address */
694 __le32 reserved3[12]; /* d0h-ffh | reserved */
695 __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */
696 };
697
698 #define Mailbox0 SaDbCSR.MAILBOX0
699 #define Mailbox1 SaDbCSR.MAILBOX1
700 #define Mailbox2 SaDbCSR.MAILBOX2
701 #define Mailbox3 SaDbCSR.MAILBOX3
702 #define Mailbox4 SaDbCSR.MAILBOX4
703 #define Mailbox5 SaDbCSR.MAILBOX5
704 #define Mailbox6 SaDbCSR.MAILBOX6
705 #define Mailbox7 SaDbCSR.MAILBOX7
706
707 #define DoorbellReg_p SaDbCSR.PRISETIRQ
708 #define DoorbellReg_s SaDbCSR.SECSETIRQ
709 #define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ
710
711
712 #define DOORBELL_0 0x0001
713 #define DOORBELL_1 0x0002
714 #define DOORBELL_2 0x0004
715 #define DOORBELL_3 0x0008
716 #define DOORBELL_4 0x0010
717 #define DOORBELL_5 0x0020
718 #define DOORBELL_6 0x0040
719
720
721 #define PrintfReady DOORBELL_5
722 #define PrintfDone DOORBELL_5
723
724 struct sa_registers {
725 struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */
726 };
727
728
729 #define SA_INIT_NUM_MSIXVECTORS 1
730
731 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
732 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
733 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
734 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
735
736 /*
737 * Rx Message Unit Registers
738 */
739
740 struct rx_mu_registers {
741 /* Local | PCI*| Name */
742 __le32 ARSR; /* 1300h | 00h | APIC Register Select Register */
743 __le32 reserved0; /* 1304h | 04h | Reserved */
744 __le32 AWR; /* 1308h | 08h | APIC Window Register */
745 __le32 reserved1; /* 130Ch | 0Ch | Reserved */
746 __le32 IMRx[2]; /* 1310h | 10h | Inbound Message Registers */
747 __le32 OMRx[2]; /* 1318h | 18h | Outbound Message Registers */
748 __le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */
749 __le32 IISR; /* 1324h | 24h | Inbound Interrupt
750 Status Register */
751 __le32 IIMR; /* 1328h | 28h | Inbound Interrupt
752 Mask Register */
753 __le32 ODR; /* 132Ch | 2Ch | Outbound Doorbell Register */
754 __le32 OISR; /* 1330h | 30h | Outbound Interrupt
755 Status Register */
756 __le32 OIMR; /* 1334h | 34h | Outbound Interrupt
757 Mask Register */
758 __le32 reserved2; /* 1338h | 38h | Reserved */
759 __le32 reserved3; /* 133Ch | 3Ch | Reserved */
760 __le32 InboundQueue;/* 1340h | 40h | Inbound Queue Port relative to firmware */
761 __le32 OutboundQueue;/*1344h | 44h | Outbound Queue Port relative to firmware */
762 /* * Must access through ATU Inbound
763 Translation Window */
764 };
765
766 struct rx_inbound {
767 __le32 Mailbox[8];
768 };
769
770 #define INBOUNDDOORBELL_0 0x00000001
771 #define INBOUNDDOORBELL_1 0x00000002
772 #define INBOUNDDOORBELL_2 0x00000004
773 #define INBOUNDDOORBELL_3 0x00000008
774 #define INBOUNDDOORBELL_4 0x00000010
775 #define INBOUNDDOORBELL_5 0x00000020
776 #define INBOUNDDOORBELL_6 0x00000040
777
778 #define OUTBOUNDDOORBELL_0 0x00000001
779 #define OUTBOUNDDOORBELL_1 0x00000002
780 #define OUTBOUNDDOORBELL_2 0x00000004
781 #define OUTBOUNDDOORBELL_3 0x00000008
782 #define OUTBOUNDDOORBELL_4 0x00000010
783
784 #define InboundDoorbellReg MUnit.IDR
785 #define OutboundDoorbellReg MUnit.ODR
786
787 struct rx_registers {
788 struct rx_mu_registers MUnit; /* 1300h - 1347h */
789 __le32 reserved1[2]; /* 1348h - 134ch */
790 struct rx_inbound IndexRegs;
791 };
792
793 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
794 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
795 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
796 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
797
798 /*
799 * Rkt Message Unit Registers (same as Rx, except a larger reserve region)
800 */
801
802 #define rkt_mu_registers rx_mu_registers
803 #define rkt_inbound rx_inbound
804
805 struct rkt_registers {
806 struct rkt_mu_registers MUnit; /* 1300h - 1347h */
807 __le32 reserved1[1006]; /* 1348h - 22fch */
808 struct rkt_inbound IndexRegs; /* 2300h - */
809 };
810
811 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR))
812 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR))
813 #define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR))
814 #define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
815
816 /*
817 * PMC SRC message unit registers
818 */
819
820 #define src_inbound rx_inbound
821
822 struct src_mu_registers {
823 /* PCI*| Name */
824 __le32 reserved0[6]; /* 00h | Reserved */
825 __le32 IOAR[2]; /* 18h | IOA->host interrupt register */
826 __le32 IDR; /* 20h | Inbound Doorbell Register */
827 __le32 IISR; /* 24h | Inbound Int. Status Register */
828 __le32 reserved1[3]; /* 28h | Reserved */
829 __le32 OIMR; /* 34h | Outbound Int. Mask Register */
830 __le32 reserved2[25]; /* 38h | Reserved */
831 __le32 ODR_R; /* 9ch | Outbound Doorbell Read */
832 __le32 ODR_C; /* a0h | Outbound Doorbell Clear */
833 __le32 reserved3[6]; /* a4h | Reserved */
834 __le32 OMR; /* bch | Outbound Message Register */
835 __le32 IQ_L; /* c0h | Inbound Queue (Low address) */
836 __le32 IQ_H; /* c4h | Inbound Queue (High address) */
837 __le32 ODR_MSI; /* c8h | MSI register for sync./AIF */
838 };
839
840 struct src_registers {
841 struct src_mu_registers MUnit; /* 00h - cbh */
842 union {
843 struct {
844 __le32 reserved1[130789]; /* cch - 7fc5fh */
845 struct src_inbound IndexRegs; /* 7fc60h */
846 } tupelo;
847 struct {
848 __le32 reserved1[973]; /* cch - fffh */
849 struct src_inbound IndexRegs; /* 1000h */
850 } denali;
851 } u;
852 };
853
854 #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR))
855 #define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR))
856 #define src_writeb(AEP, CSR, value) writeb(value, \
857 &((AEP)->regs.src.bar0->CSR))
858 #define src_writel(AEP, CSR, value) writel(value, \
859 &((AEP)->regs.src.bar0->CSR))
860 #if defined(writeq)
861 #define src_writeq(AEP, CSR, value) writeq(value, \
862 &((AEP)->regs.src.bar0->CSR))
863 #endif
864
865 #define SRC_ODR_SHIFT 12
866 #define SRC_IDR_SHIFT 9
867
868 typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);
869
870 struct aac_fib_context {
871 s16 type; // used for verification of structure
872 s16 size;
873 u32 unique; // unique value representing this context
874 ulong jiffies; // used for cleanup - dmb changed to ulong
875 struct list_head next; // used to link context's into a linked list
876 struct semaphore wait_sem; // this is used to wait for the next fib to arrive.
877 int wait; // Set to true when thread is in WaitForSingleObject
878 unsigned long count; // total number of FIBs on FibList
879 struct list_head fib_list; // this holds fibs and their attachd hw_fibs
880 };
881
882 struct sense_data {
883 u8 error_code; /* 70h (current errors), 71h(deferred errors) */
884 u8 valid:1; /* A valid bit of one indicates that the information */
885 /* field contains valid information as defined in the
886 * SCSI-2 Standard.
887 */
888 u8 segment_number; /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */
889 u8 sense_key:4; /* Sense Key */
890 u8 reserved:1;
891 u8 ILI:1; /* Incorrect Length Indicator */
892 u8 EOM:1; /* End Of Medium - reserved for random access devices */
893 u8 filemark:1; /* Filemark - reserved for random access devices */
894
895 u8 information[4]; /* for direct-access devices, contains the unsigned
896 * logical block address or residue associated with
897 * the sense key
898 */
899 u8 add_sense_len; /* number of additional sense bytes to follow this field */
900 u8 cmnd_info[4]; /* not used */
901 u8 ASC; /* Additional Sense Code */
902 u8 ASCQ; /* Additional Sense Code Qualifier */
903 u8 FRUC; /* Field Replaceable Unit Code - not used */
904 u8 bit_ptr:3; /* indicates which byte of the CDB or parameter data
905 * was in error
906 */
907 u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that
908 * the bit_ptr field has valid value
909 */
910 u8 reserved2:2;
911 u8 CD:1; /* command data bit: 1- illegal parameter in CDB.
912 * 0- illegal parameter in data.
913 */
914 u8 SKSV:1;
915 u8 field_ptr[2]; /* byte of the CDB or parameter data in error */
916 };
917
918 struct fsa_dev_info {
919 u64 last;
920 u64 size;
921 u32 type;
922 u32 config_waiting_on;
923 unsigned long config_waiting_stamp;
924 u16 queue_depth;
925 u8 config_needed;
926 u8 valid;
927 u8 ro;
928 u8 locked;
929 u8 deleted;
930 char devname[8];
931 struct sense_data sense_data;
932 u32 block_size;
933 };
934
935 struct fib {
936 void *next; /* this is used by the allocator */
937 s16 type;
938 s16 size;
939 /*
940 * The Adapter that this I/O is destined for.
941 */
942 struct aac_dev *dev;
943 /*
944 * This is the event the sendfib routine will wait on if the
945 * caller did not pass one and this is synch io.
946 */
947 struct semaphore event_wait;
948 spinlock_t event_lock;
949
950 u32 done; /* gets set to 1 when fib is complete */
951 fib_callback callback;
952 void *callback_data;
953 u32 flags; // u32 dmb was ulong
954 /*
955 * And for the internal issue/reply queues (we may be able
956 * to merge these two)
957 */
958 struct list_head fiblink;
959 void *data;
960 u32 vector_no;
961 struct hw_fib *hw_fib_va; /* Actual shared object */
962 dma_addr_t hw_fib_pa; /* physical address of hw_fib*/
963 };
964
965 /*
966 * Adapter Information Block
967 *
968 * This is returned by the RequestAdapterInfo block
969 */
970
971 struct aac_adapter_info
972 {
973 __le32 platform;
974 __le32 cpu;
975 __le32 subcpu;
976 __le32 clock;
977 __le32 execmem;
978 __le32 buffermem;
979 __le32 totalmem;
980 __le32 kernelrev;
981 __le32 kernelbuild;
982 __le32 monitorrev;
983 __le32 monitorbuild;
984 __le32 hwrev;
985 __le32 hwbuild;
986 __le32 biosrev;
987 __le32 biosbuild;
988 __le32 cluster;
989 __le32 clusterchannelmask;
990 __le32 serial[2];
991 __le32 battery;
992 __le32 options;
993 __le32 OEM;
994 };
995
996 struct aac_supplement_adapter_info
997 {
998 u8 AdapterTypeText[17+1];
999 u8 Pad[2];
1000 __le32 FlashMemoryByteSize;
1001 __le32 FlashImageId;
1002 __le32 MaxNumberPorts;
1003 __le32 Version;
1004 __le32 FeatureBits;
1005 u8 SlotNumber;
1006 u8 ReservedPad0[3];
1007 u8 BuildDate[12];
1008 __le32 CurrentNumberPorts;
1009 struct {
1010 u8 AssemblyPn[8];
1011 u8 FruPn[8];
1012 u8 BatteryFruPn[8];
1013 u8 EcVersionString[8];
1014 u8 Tsid[12];
1015 } VpdInfo;
1016 __le32 FlashFirmwareRevision;
1017 __le32 FlashFirmwareBuild;
1018 __le32 RaidTypeMorphOptions;
1019 __le32 FlashFirmwareBootRevision;
1020 __le32 FlashFirmwareBootBuild;
1021 u8 MfgPcbaSerialNo[12];
1022 u8 MfgWWNName[8];
1023 __le32 SupportedOptions2;
1024 __le32 StructExpansion;
1025 /* StructExpansion == 1 */
1026 __le32 FeatureBits3;
1027 __le32 SupportedPerformanceModes;
1028 __le32 ReservedForFutureGrowth[80];
1029 };
1030 #define AAC_FEATURE_FALCON cpu_to_le32(0x00000010)
1031 #define AAC_FEATURE_JBOD cpu_to_le32(0x08000000)
1032 /* SupportedOptions2 */
1033 #define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001)
1034 #define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002)
1035 #define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004)
1036 #define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000)
1037 /* 4KB sector size */
1038 #define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000)
1039 /* 240 simple volume support */
1040 #define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000)
1041 #define AAC_SIS_VERSION_V3 3
1042 #define AAC_SIS_SLOT_UNKNOWN 0xFF
1043
1044 #define GetBusInfo 0x00000009
1045 struct aac_bus_info {
1046 __le32 Command; /* VM_Ioctl */
1047 __le32 ObjType; /* FT_DRIVE */
1048 __le32 MethodId; /* 1 = SCSI Layer */
1049 __le32 ObjectId; /* Handle */
1050 __le32 CtlCmd; /* GetBusInfo */
1051 };
1052
1053 struct aac_bus_info_response {
1054 __le32 Status; /* ST_OK */
1055 __le32 ObjType;
1056 __le32 MethodId; /* unused */
1057 __le32 ObjectId; /* unused */
1058 __le32 CtlCmd; /* unused */
1059 __le32 ProbeComplete;
1060 __le32 BusCount;
1061 __le32 TargetsPerBus;
1062 u8 InitiatorBusId[10];
1063 u8 BusValid[10];
1064 };
1065
1066 /*
1067 * Battery platforms
1068 */
1069 #define AAC_BAT_REQ_PRESENT (1)
1070 #define AAC_BAT_REQ_NOTPRESENT (2)
1071 #define AAC_BAT_OPT_PRESENT (3)
1072 #define AAC_BAT_OPT_NOTPRESENT (4)
1073 #define AAC_BAT_NOT_SUPPORTED (5)
1074 /*
1075 * cpu types
1076 */
1077 #define AAC_CPU_SIMULATOR (1)
1078 #define AAC_CPU_I960 (2)
1079 #define AAC_CPU_STRONGARM (3)
1080
1081 /*
1082 * Supported Options
1083 */
1084 #define AAC_OPT_SNAPSHOT cpu_to_le32(1)
1085 #define AAC_OPT_CLUSTERS cpu_to_le32(1<<1)
1086 #define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2)
1087 #define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3)
1088 #define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4)
1089 #define AAC_OPT_RAID50 cpu_to_le32(1<<5)
1090 #define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6)
1091 #define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7)
1092 #define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8)
1093 #define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9)
1094 #define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10)
1095 #define AAC_OPT_ALARM cpu_to_le32(1<<11)
1096 #define AAC_OPT_NONDASD cpu_to_le32(1<<12)
1097 #define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13)
1098 #define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14)
1099 #define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16)
1100 #define AAC_OPT_NEW_COMM cpu_to_le32(1<<17)
1101 #define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18)
1102 #define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28)
1103 #define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29)
1104 #define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30)
1105 #define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31)
1106
1107 /* MSIX context */
1108 struct aac_msix_ctx {
1109 int vector_no;
1110 struct aac_dev *dev;
1111 };
1112
1113 struct aac_dev
1114 {
1115 struct list_head entry;
1116 const char *name;
1117 int id;
1118
1119 /*
1120 * negotiated FIB settings
1121 */
1122 unsigned max_fib_size;
1123 unsigned sg_tablesize;
1124 unsigned max_num_aif;
1125
1126 /*
1127 * Map for 128 fib objects (64k)
1128 */
1129 dma_addr_t hw_fib_pa;
1130 struct hw_fib *hw_fib_va;
1131 struct hw_fib *aif_base_va;
1132 /*
1133 * Fib Headers
1134 */
1135 struct fib *fibs;
1136
1137 struct fib *free_fib;
1138 spinlock_t fib_lock;
1139
1140 struct mutex ioctl_mutex;
1141 struct aac_queue_block *queues;
1142 /*
1143 * The user API will use an IOCTL to register itself to receive
1144 * FIBs from the adapter. The following list is used to keep
1145 * track of all the threads that have requested these FIBs. The
1146 * mutex is used to synchronize access to all data associated
1147 * with the adapter fibs.
1148 */
1149 struct list_head fib_list;
1150
1151 struct adapter_ops a_ops;
1152 unsigned long fsrev; /* Main driver's revision number */
1153
1154 resource_size_t base_start; /* main IO base */
1155 resource_size_t dbg_base; /* address of UART
1156 * debug buffer */
1157
1158 resource_size_t base_size, dbg_size; /* Size of
1159 * mapped in region */
1160
1161 struct aac_init *init; /* Holds initialization info to communicate with adapter */
1162 dma_addr_t init_pa; /* Holds physical address of the init struct */
1163
1164 u32 *host_rrq; /* response queue
1165 * if AAC_COMM_MESSAGE_TYPE1 */
1166
1167 dma_addr_t host_rrq_pa; /* phys. address */
1168 /* index into rrq buffer */
1169 u32 host_rrq_idx[AAC_MAX_MSIX];
1170 atomic_t rrq_outstanding[AAC_MAX_MSIX];
1171 u32 fibs_pushed_no;
1172 struct pci_dev *pdev; /* Our PCI interface */
1173 void * printfbuf; /* pointer to buffer used for printf's from the adapter */
1174 void * comm_addr; /* Base address of Comm area */
1175 dma_addr_t comm_phys; /* Physical Address of Comm area */
1176 size_t comm_size;
1177
1178 struct Scsi_Host *scsi_host_ptr;
1179 int maximum_num_containers;
1180 int maximum_num_physicals;
1181 int maximum_num_channels;
1182 struct fsa_dev_info *fsa_dev;
1183 struct task_struct *thread;
1184 int cardtype;
1185 /*
1186 *This lock will protect the two 32-bit
1187 *writes to the Inbound Queue
1188 */
1189 spinlock_t iq_lock;
1190
1191 /*
1192 * The following is the device specific extension.
1193 */
1194 #ifndef AAC_MIN_FOOTPRINT_SIZE
1195 # define AAC_MIN_FOOTPRINT_SIZE 8192
1196 # define AAC_MIN_SRC_BAR0_SIZE 0x400000
1197 # define AAC_MIN_SRC_BAR1_SIZE 0x800
1198 # define AAC_MIN_SRCV_BAR0_SIZE 0x100000
1199 # define AAC_MIN_SRCV_BAR1_SIZE 0x400
1200 #endif
1201 union
1202 {
1203 struct sa_registers __iomem *sa;
1204 struct rx_registers __iomem *rx;
1205 struct rkt_registers __iomem *rkt;
1206 struct {
1207 struct src_registers __iomem *bar0;
1208 char __iomem *bar1;
1209 } src;
1210 } regs;
1211 volatile void __iomem *base, *dbg_base_mapped;
1212 volatile struct rx_inbound __iomem *IndexRegs;
1213 u32 OIMR; /* Mask Register Cache */
1214 /*
1215 * AIF thread states
1216 */
1217 u32 aif_thread;
1218 struct aac_adapter_info adapter_info;
1219 struct aac_supplement_adapter_info supplement_adapter_info;
1220 /* These are in adapter info but they are in the io flow so
1221 * lets break them out so we don't have to do an AND to check them
1222 */
1223 u8 nondasd_support;
1224 u8 jbod;
1225 u8 cache_protected;
1226 u8 dac_support;
1227 u8 needs_dac;
1228 u8 raid_scsi_mode;
1229 u8 comm_interface;
1230 # define AAC_COMM_PRODUCER 0
1231 # define AAC_COMM_MESSAGE 1
1232 # define AAC_COMM_MESSAGE_TYPE1 3
1233 # define AAC_COMM_MESSAGE_TYPE2 4
1234 u8 raw_io_interface;
1235 u8 raw_io_64;
1236 u8 printf_enabled;
1237 u8 in_reset;
1238 u8 msi;
1239 int management_fib_count;
1240 spinlock_t manage_lock;
1241 spinlock_t sync_lock;
1242 int sync_mode;
1243 struct fib *sync_fib;
1244 struct list_head sync_fib_list;
1245 u32 doorbell_mask;
1246 u32 max_msix; /* max. MSI-X vectors */
1247 u32 vector_cap; /* MSI-X vector capab.*/
1248 int msi_enabled; /* MSI/MSI-X enabled */
1249 struct aac_msix_ctx aac_msix[AAC_MAX_MSIX]; /* context */
1250 u8 adapter_shutdown;
1251 u32 handle_pci_error;
1252 };
1253
1254 #define aac_adapter_interrupt(dev) \
1255 (dev)->a_ops.adapter_interrupt(dev)
1256
1257 #define aac_adapter_notify(dev, event) \
1258 (dev)->a_ops.adapter_notify(dev, event)
1259
1260 #define aac_adapter_disable_int(dev) \
1261 (dev)->a_ops.adapter_disable_int(dev)
1262
1263 #define aac_adapter_enable_int(dev) \
1264 (dev)->a_ops.adapter_enable_int(dev)
1265
1266 #define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \
1267 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4)
1268
1269 #define aac_adapter_check_health(dev) \
1270 (dev)->a_ops.adapter_check_health(dev)
1271
1272 #define aac_adapter_restart(dev,bled) \
1273 (dev)->a_ops.adapter_restart(dev,bled)
1274
1275 #define aac_adapter_start(dev) \
1276 ((dev)->a_ops.adapter_start(dev))
1277
1278 #define aac_adapter_ioremap(dev, size) \
1279 (dev)->a_ops.adapter_ioremap(dev, size)
1280
1281 #define aac_adapter_deliver(fib) \
1282 ((fib)->dev)->a_ops.adapter_deliver(fib)
1283
1284 #define aac_adapter_bounds(dev,cmd,lba) \
1285 dev->a_ops.adapter_bounds(dev,cmd,lba)
1286
1287 #define aac_adapter_read(fib,cmd,lba,count) \
1288 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count)
1289
1290 #define aac_adapter_write(fib,cmd,lba,count,fua) \
1291 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua)
1292
1293 #define aac_adapter_scsi(fib,cmd) \
1294 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd)
1295
1296 #define aac_adapter_comm(dev,comm) \
1297 (dev)->a_ops.adapter_comm(dev, comm)
1298
1299 #define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001)
1300 #define FIB_CONTEXT_FLAG (0x00000002)
1301 #define FIB_CONTEXT_FLAG_WAIT (0x00000004)
1302 #define FIB_CONTEXT_FLAG_FASTRESP (0x00000008)
1303
1304 /*
1305 * Define the command values
1306 */
1307
1308 #define Null 0
1309 #define GetAttributes 1
1310 #define SetAttributes 2
1311 #define Lookup 3
1312 #define ReadLink 4
1313 #define Read 5
1314 #define Write 6
1315 #define Create 7
1316 #define MakeDirectory 8
1317 #define SymbolicLink 9
1318 #define MakeNode 10
1319 #define Removex 11
1320 #define RemoveDirectoryx 12
1321 #define Rename 13
1322 #define Link 14
1323 #define ReadDirectory 15
1324 #define ReadDirectoryPlus 16
1325 #define FileSystemStatus 17
1326 #define FileSystemInfo 18
1327 #define PathConfigure 19
1328 #define Commit 20
1329 #define Mount 21
1330 #define UnMount 22
1331 #define Newfs 23
1332 #define FsCheck 24
1333 #define FsSync 25
1334 #define SimReadWrite 26
1335 #define SetFileSystemStatus 27
1336 #define BlockRead 28
1337 #define BlockWrite 29
1338 #define NvramIoctl 30
1339 #define FsSyncWait 31
1340 #define ClearArchiveBit 32
1341 #define SetAcl 33
1342 #define GetAcl 34
1343 #define AssignAcl 35
1344 #define FaultInsertion 36 /* Fault Insertion Command */
1345 #define CrazyCache 37 /* Crazycache */
1346
1347 #define MAX_FSACOMMAND_NUM 38
1348
1349
1350 /*
1351 * Define the status returns. These are very unixlike although
1352 * most are not in fact used
1353 */
1354
1355 #define ST_OK 0
1356 #define ST_PERM 1
1357 #define ST_NOENT 2
1358 #define ST_IO 5
1359 #define ST_NXIO 6
1360 #define ST_E2BIG 7
1361 #define ST_ACCES 13
1362 #define ST_EXIST 17
1363 #define ST_XDEV 18
1364 #define ST_NODEV 19
1365 #define ST_NOTDIR 20
1366 #define ST_ISDIR 21
1367 #define ST_INVAL 22
1368 #define ST_FBIG 27
1369 #define ST_NOSPC 28
1370 #define ST_ROFS 30
1371 #define ST_MLINK 31
1372 #define ST_WOULDBLOCK 35
1373 #define ST_NAMETOOLONG 63
1374 #define ST_NOTEMPTY 66
1375 #define ST_DQUOT 69
1376 #define ST_STALE 70
1377 #define ST_REMOTE 71
1378 #define ST_NOT_READY 72
1379 #define ST_BADHANDLE 10001
1380 #define ST_NOT_SYNC 10002
1381 #define ST_BAD_COOKIE 10003
1382 #define ST_NOTSUPP 10004
1383 #define ST_TOOSMALL 10005
1384 #define ST_SERVERFAULT 10006
1385 #define ST_BADTYPE 10007
1386 #define ST_JUKEBOX 10008
1387 #define ST_NOTMOUNTED 10009
1388 #define ST_MAINTMODE 10010
1389 #define ST_STALEACL 10011
1390
1391 /*
1392 * On writes how does the client want the data written.
1393 */
1394
1395 #define CACHE_CSTABLE 1
1396 #define CACHE_UNSTABLE 2
1397
1398 /*
1399 * Lets the client know at which level the data was committed on
1400 * a write request
1401 */
1402
1403 #define CMFILE_SYNCH_NVRAM 1
1404 #define CMDATA_SYNCH_NVRAM 2
1405 #define CMFILE_SYNCH 3
1406 #define CMDATA_SYNCH 4
1407 #define CMUNSTABLE 5
1408
1409 #define RIO_TYPE_WRITE 0x0000
1410 #define RIO_TYPE_READ 0x0001
1411 #define RIO_SUREWRITE 0x0008
1412
1413 #define RIO2_IO_TYPE 0x0003
1414 #define RIO2_IO_TYPE_WRITE 0x0000
1415 #define RIO2_IO_TYPE_READ 0x0001
1416 #define RIO2_IO_TYPE_VERIFY 0x0002
1417 #define RIO2_IO_ERROR 0x0004
1418 #define RIO2_IO_SUREWRITE 0x0008
1419 #define RIO2_SGL_CONFORMANT 0x0010
1420 #define RIO2_SG_FORMAT 0xF000
1421 #define RIO2_SG_FORMAT_ARC 0x0000
1422 #define RIO2_SG_FORMAT_SRL 0x1000
1423 #define RIO2_SG_FORMAT_IEEE1212 0x2000
1424
1425 struct aac_read
1426 {
1427 __le32 command;
1428 __le32 cid;
1429 __le32 block;
1430 __le32 count;
1431 struct sgmap sg; // Must be last in struct because it is variable
1432 };
1433
1434 struct aac_read64
1435 {
1436 __le32 command;
1437 __le16 cid;
1438 __le16 sector_count;
1439 __le32 block;
1440 __le16 pad;
1441 __le16 flags;
1442 struct sgmap64 sg; // Must be last in struct because it is variable
1443 };
1444
1445 struct aac_read_reply
1446 {
1447 __le32 status;
1448 __le32 count;
1449 };
1450
1451 struct aac_write
1452 {
1453 __le32 command;
1454 __le32 cid;
1455 __le32 block;
1456 __le32 count;
1457 __le32 stable; // Not used
1458 struct sgmap sg; // Must be last in struct because it is variable
1459 };
1460
1461 struct aac_write64
1462 {
1463 __le32 command;
1464 __le16 cid;
1465 __le16 sector_count;
1466 __le32 block;
1467 __le16 pad;
1468 __le16 flags;
1469 struct sgmap64 sg; // Must be last in struct because it is variable
1470 };
1471 struct aac_write_reply
1472 {
1473 __le32 status;
1474 __le32 count;
1475 __le32 committed;
1476 };
1477
1478 struct aac_raw_io
1479 {
1480 __le32 block[2];
1481 __le32 count;
1482 __le16 cid;
1483 __le16 flags; /* 00 W, 01 R */
1484 __le16 bpTotal; /* reserved for F/W use */
1485 __le16 bpComplete; /* reserved for F/W use */
1486 struct sgmapraw sg;
1487 };
1488
1489 struct aac_raw_io2 {
1490 __le32 blockLow;
1491 __le32 blockHigh;
1492 __le32 byteCount;
1493 __le16 cid;
1494 __le16 flags; /* RIO2 flags */
1495 __le32 sgeFirstSize; /* size of first sge el. */
1496 __le32 sgeNominalSize; /* size of 2nd sge el. (if conformant) */
1497 u8 sgeCnt; /* only 8 bits required */
1498 u8 bpTotal; /* reserved for F/W use */
1499 u8 bpComplete; /* reserved for F/W use */
1500 u8 sgeFirstIndex; /* reserved for F/W use */
1501 u8 unused[4];
1502 struct sge_ieee1212 sge[1];
1503 };
1504
1505 #define CT_FLUSH_CACHE 129
1506 struct aac_synchronize {
1507 __le32 command; /* VM_ContainerConfig */
1508 __le32 type; /* CT_FLUSH_CACHE */
1509 __le32 cid;
1510 __le32 parm1;
1511 __le32 parm2;
1512 __le32 parm3;
1513 __le32 parm4;
1514 __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */
1515 };
1516
1517 struct aac_synchronize_reply {
1518 __le32 dummy0;
1519 __le32 dummy1;
1520 __le32 status; /* CT_OK */
1521 __le32 parm1;
1522 __le32 parm2;
1523 __le32 parm3;
1524 __le32 parm4;
1525 __le32 parm5;
1526 u8 data[16];
1527 };
1528
1529 #define CT_POWER_MANAGEMENT 245
1530 #define CT_PM_START_UNIT 2
1531 #define CT_PM_STOP_UNIT 3
1532 #define CT_PM_UNIT_IMMEDIATE 1
1533 struct aac_power_management {
1534 __le32 command; /* VM_ContainerConfig */
1535 __le32 type; /* CT_POWER_MANAGEMENT */
1536 __le32 sub; /* CT_PM_* */
1537 __le32 cid;
1538 __le32 parm; /* CT_PM_sub_* */
1539 };
1540
1541 #define CT_PAUSE_IO 65
1542 #define CT_RELEASE_IO 66
1543 struct aac_pause {
1544 __le32 command; /* VM_ContainerConfig */
1545 __le32 type; /* CT_PAUSE_IO */
1546 __le32 timeout; /* 10ms ticks */
1547 __le32 min;
1548 __le32 noRescan;
1549 __le32 parm3;
1550 __le32 parm4;
1551 __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */
1552 };
1553
1554 struct aac_srb
1555 {
1556 __le32 function;
1557 __le32 channel;
1558 __le32 id;
1559 __le32 lun;
1560 __le32 timeout;
1561 __le32 flags;
1562 __le32 count; // Data xfer size
1563 __le32 retry_limit;
1564 __le32 cdb_size;
1565 u8 cdb[16];
1566 struct sgmap sg;
1567 };
1568
1569 /*
1570 * This and associated data structs are used by the
1571 * ioctl caller and are in cpu order.
1572 */
1573 struct user_aac_srb
1574 {
1575 u32 function;
1576 u32 channel;
1577 u32 id;
1578 u32 lun;
1579 u32 timeout;
1580 u32 flags;
1581 u32 count; // Data xfer size
1582 u32 retry_limit;
1583 u32 cdb_size;
1584 u8 cdb[16];
1585 struct user_sgmap sg;
1586 };
1587
1588 #define AAC_SENSE_BUFFERSIZE 30
1589
1590 struct aac_srb_reply
1591 {
1592 __le32 status;
1593 __le32 srb_status;
1594 __le32 scsi_status;
1595 __le32 data_xfer_length;
1596 __le32 sense_data_size;
1597 u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE
1598 };
1599 /*
1600 * SRB Flags
1601 */
1602 #define SRB_NoDataXfer 0x0000
1603 #define SRB_DisableDisconnect 0x0004
1604 #define SRB_DisableSynchTransfer 0x0008
1605 #define SRB_BypassFrozenQueue 0x0010
1606 #define SRB_DisableAutosense 0x0020
1607 #define SRB_DataIn 0x0040
1608 #define SRB_DataOut 0x0080
1609
1610 /*
1611 * SRB Functions - set in aac_srb->function
1612 */
1613 #define SRBF_ExecuteScsi 0x0000
1614 #define SRBF_ClaimDevice 0x0001
1615 #define SRBF_IO_Control 0x0002
1616 #define SRBF_ReceiveEvent 0x0003
1617 #define SRBF_ReleaseQueue 0x0004
1618 #define SRBF_AttachDevice 0x0005
1619 #define SRBF_ReleaseDevice 0x0006
1620 #define SRBF_Shutdown 0x0007
1621 #define SRBF_Flush 0x0008
1622 #define SRBF_AbortCommand 0x0010
1623 #define SRBF_ReleaseRecovery 0x0011
1624 #define SRBF_ResetBus 0x0012
1625 #define SRBF_ResetDevice 0x0013
1626 #define SRBF_TerminateIO 0x0014
1627 #define SRBF_FlushQueue 0x0015
1628 #define SRBF_RemoveDevice 0x0016
1629 #define SRBF_DomainValidation 0x0017
1630
1631 /*
1632 * SRB SCSI Status - set in aac_srb->scsi_status
1633 */
1634 #define SRB_STATUS_PENDING 0x00
1635 #define SRB_STATUS_SUCCESS 0x01
1636 #define SRB_STATUS_ABORTED 0x02
1637 #define SRB_STATUS_ABORT_FAILED 0x03
1638 #define SRB_STATUS_ERROR 0x04
1639 #define SRB_STATUS_BUSY 0x05
1640 #define SRB_STATUS_INVALID_REQUEST 0x06
1641 #define SRB_STATUS_INVALID_PATH_ID 0x07
1642 #define SRB_STATUS_NO_DEVICE 0x08
1643 #define SRB_STATUS_TIMEOUT 0x09
1644 #define SRB_STATUS_SELECTION_TIMEOUT 0x0A
1645 #define SRB_STATUS_COMMAND_TIMEOUT 0x0B
1646 #define SRB_STATUS_MESSAGE_REJECTED 0x0D
1647 #define SRB_STATUS_BUS_RESET 0x0E
1648 #define SRB_STATUS_PARITY_ERROR 0x0F
1649 #define SRB_STATUS_REQUEST_SENSE_FAILED 0x10
1650 #define SRB_STATUS_NO_HBA 0x11
1651 #define SRB_STATUS_DATA_OVERRUN 0x12
1652 #define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13
1653 #define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14
1654 #define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15
1655 #define SRB_STATUS_REQUEST_FLUSHED 0x16
1656 #define SRB_STATUS_DELAYED_RETRY 0x17
1657 #define SRB_STATUS_INVALID_LUN 0x20
1658 #define SRB_STATUS_INVALID_TARGET_ID 0x21
1659 #define SRB_STATUS_BAD_FUNCTION 0x22
1660 #define SRB_STATUS_ERROR_RECOVERY 0x23
1661 #define SRB_STATUS_NOT_STARTED 0x24
1662 #define SRB_STATUS_NOT_IN_USE 0x30
1663 #define SRB_STATUS_FORCE_ABORT 0x31
1664 #define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32
1665
1666 /*
1667 * Object-Server / Volume-Manager Dispatch Classes
1668 */
1669
1670 #define VM_Null 0
1671 #define VM_NameServe 1
1672 #define VM_ContainerConfig 2
1673 #define VM_Ioctl 3
1674 #define VM_FilesystemIoctl 4
1675 #define VM_CloseAll 5
1676 #define VM_CtBlockRead 6
1677 #define VM_CtBlockWrite 7
1678 #define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */
1679 #define VM_SliceBlockWrite 9
1680 #define VM_DriveBlockRead 10 /* raw access to physical devices */
1681 #define VM_DriveBlockWrite 11
1682 #define VM_EnclosureMgt 12 /* enclosure management */
1683 #define VM_Unused 13 /* used to be diskset management */
1684 #define VM_CtBlockVerify 14
1685 #define VM_CtPerf 15 /* performance test */
1686 #define VM_CtBlockRead64 16
1687 #define VM_CtBlockWrite64 17
1688 #define VM_CtBlockVerify64 18
1689 #define VM_CtHostRead64 19
1690 #define VM_CtHostWrite64 20
1691 #define VM_DrvErrTblLog 21
1692 #define VM_NameServe64 22
1693 #define VM_NameServeAllBlk 30
1694
1695 #define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */
1696
1697 /*
1698 * Descriptive information (eg, vital stats)
1699 * that a content manager might report. The
1700 * FileArray filesystem component is one example
1701 * of a content manager. Raw mode might be
1702 * another.
1703 */
1704
1705 struct aac_fsinfo {
1706 __le32 fsTotalSize; /* Consumed by fs, incl. metadata */
1707 __le32 fsBlockSize;
1708 __le32 fsFragSize;
1709 __le32 fsMaxExtendSize;
1710 __le32 fsSpaceUnits;
1711 __le32 fsMaxNumFiles;
1712 __le32 fsNumFreeFiles;
1713 __le32 fsInodeDensity;
1714 }; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */
1715
1716 struct aac_blockdevinfo {
1717 __le32 block_size;
1718 };
1719
1720 union aac_contentinfo {
1721 struct aac_fsinfo filesys;
1722 struct aac_blockdevinfo bdevinfo;
1723 };
1724
1725 /*
1726 * Query for Container Configuration Status
1727 */
1728
1729 #define CT_GET_CONFIG_STATUS 147
1730 struct aac_get_config_status {
1731 __le32 command; /* VM_ContainerConfig */
1732 __le32 type; /* CT_GET_CONFIG_STATUS */
1733 __le32 parm1;
1734 __le32 parm2;
1735 __le32 parm3;
1736 __le32 parm4;
1737 __le32 parm5;
1738 __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */
1739 };
1740
1741 #define CFACT_CONTINUE 0
1742 #define CFACT_PAUSE 1
1743 #define CFACT_ABORT 2
1744 struct aac_get_config_status_resp {
1745 __le32 response; /* ST_OK */
1746 __le32 dummy0;
1747 __le32 status; /* CT_OK */
1748 __le32 parm1;
1749 __le32 parm2;
1750 __le32 parm3;
1751 __le32 parm4;
1752 __le32 parm5;
1753 struct {
1754 __le32 action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */
1755 __le16 flags;
1756 __le16 count;
1757 } data;
1758 };
1759
1760 /*
1761 * Accept the configuration as-is
1762 */
1763
1764 #define CT_COMMIT_CONFIG 152
1765
1766 struct aac_commit_config {
1767 __le32 command; /* VM_ContainerConfig */
1768 __le32 type; /* CT_COMMIT_CONFIG */
1769 };
1770
1771 /*
1772 * Query for Container Configuration Status
1773 */
1774
1775 #define CT_GET_CONTAINER_COUNT 4
1776 struct aac_get_container_count {
1777 __le32 command; /* VM_ContainerConfig */
1778 __le32 type; /* CT_GET_CONTAINER_COUNT */
1779 };
1780
1781 struct aac_get_container_count_resp {
1782 __le32 response; /* ST_OK */
1783 __le32 dummy0;
1784 __le32 MaxContainers;
1785 __le32 ContainerSwitchEntries;
1786 __le32 MaxPartitions;
1787 __le32 MaxSimpleVolumes;
1788 };
1789
1790
1791 /*
1792 * Query for "mountable" objects, ie, objects that are typically
1793 * associated with a drive letter on the client (host) side.
1794 */
1795
1796 struct aac_mntent {
1797 __le32 oid;
1798 u8 name[16]; /* if applicable */
1799 struct creation_info create_info; /* if applicable */
1800 __le32 capacity;
1801 __le32 vol; /* substrate structure */
1802 __le32 obj; /* FT_FILESYS, etc. */
1803 __le32 state; /* unready for mounting,
1804 readonly, etc. */
1805 union aac_contentinfo fileinfo; /* Info specific to content
1806 manager (eg, filesystem) */
1807 __le32 altoid; /* != oid <==> snapshot or
1808 broken mirror exists */
1809 __le32 capacityhigh;
1810 };
1811
1812 #define FSCS_NOTCLEAN 0x0001 /* fsck is necessary before mounting */
1813 #define FSCS_READONLY 0x0002 /* possible result of broken mirror */
1814 #define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */
1815 #define FSCS_NOT_READY 0x0008 /* Array spinning up to fulfil request */
1816
1817 struct aac_query_mount {
1818 __le32 command;
1819 __le32 type;
1820 __le32 count;
1821 };
1822
1823 struct aac_mount {
1824 __le32 status;
1825 __le32 type; /* should be same as that requested */
1826 __le32 count;
1827 struct aac_mntent mnt[1];
1828 };
1829
1830 #define CT_READ_NAME 130
1831 struct aac_get_name {
1832 __le32 command; /* VM_ContainerConfig */
1833 __le32 type; /* CT_READ_NAME */
1834 __le32 cid;
1835 __le32 parm1;
1836 __le32 parm2;
1837 __le32 parm3;
1838 __le32 parm4;
1839 __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */
1840 };
1841
1842 struct aac_get_name_resp {
1843 __le32 dummy0;
1844 __le32 dummy1;
1845 __le32 status; /* CT_OK */
1846 __le32 parm1;
1847 __le32 parm2;
1848 __le32 parm3;
1849 __le32 parm4;
1850 __le32 parm5;
1851 u8 data[16];
1852 };
1853
1854 #define CT_CID_TO_32BITS_UID 165
1855 struct aac_get_serial {
1856 __le32 command; /* VM_ContainerConfig */
1857 __le32 type; /* CT_CID_TO_32BITS_UID */
1858 __le32 cid;
1859 };
1860
1861 struct aac_get_serial_resp {
1862 __le32 dummy0;
1863 __le32 dummy1;
1864 __le32 status; /* CT_OK */
1865 __le32 uid;
1866 };
1867
1868 /*
1869 * The following command is sent to shut down each container.
1870 */
1871
1872 struct aac_close {
1873 __le32 command;
1874 __le32 cid;
1875 };
1876
1877 struct aac_query_disk
1878 {
1879 s32 cnum;
1880 s32 bus;
1881 s32 id;
1882 s32 lun;
1883 u32 valid;
1884 u32 locked;
1885 u32 deleted;
1886 s32 instance;
1887 s8 name[10];
1888 u32 unmapped;
1889 };
1890
1891 struct aac_delete_disk {
1892 u32 disknum;
1893 u32 cnum;
1894 };
1895
1896 struct fib_ioctl
1897 {
1898 u32 fibctx;
1899 s32 wait;
1900 char __user *fib;
1901 };
1902
1903 struct revision
1904 {
1905 u32 compat;
1906 __le32 version;
1907 __le32 build;
1908 };
1909
1910
1911 /*
1912 * Ugly - non Linux like ioctl coding for back compat.
1913 */
1914
1915 #define CTL_CODE(function, method) ( \
1916 (4<< 16) | ((function) << 2) | (method) \
1917 )
1918
1919 /*
1920 * Define the method codes for how buffers are passed for I/O and FS
1921 * controls
1922 */
1923
1924 #define METHOD_BUFFERED 0
1925 #define METHOD_NEITHER 3
1926
1927 /*
1928 * Filesystem ioctls
1929 */
1930
1931 #define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED)
1932 #define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED)
1933 #define FSACTL_DELETE_DISK 0x163
1934 #define FSACTL_QUERY_DISK 0x173
1935 #define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED)
1936 #define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED)
1937 #define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED)
1938 #define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED)
1939 #define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED)
1940 #define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER)
1941 #define FSACTL_GET_CONTAINERS 2131
1942 #define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED)
1943
1944
1945 struct aac_common
1946 {
1947 /*
1948 * If this value is set to 1 then interrupt moderation will occur
1949 * in the base commuication support.
1950 */
1951 u32 irq_mod;
1952 u32 peak_fibs;
1953 u32 zero_fibs;
1954 u32 fib_timeouts;
1955 /*
1956 * Statistical counters in debug mode
1957 */
1958 #ifdef DBG
1959 u32 FibsSent;
1960 u32 FibRecved;
1961 u32 NoResponseSent;
1962 u32 NoResponseRecved;
1963 u32 AsyncSent;
1964 u32 AsyncRecved;
1965 u32 NormalSent;
1966 u32 NormalRecved;
1967 #endif
1968 };
1969
1970 extern struct aac_common aac_config;
1971
1972
1973 /*
1974 * The following macro is used when sending and receiving FIBs. It is
1975 * only used for debugging.
1976 */
1977
1978 #ifdef DBG
1979 #define FIB_COUNTER_INCREMENT(counter) (counter)++
1980 #else
1981 #define FIB_COUNTER_INCREMENT(counter)
1982 #endif
1983
1984 /*
1985 * Adapter direct commands
1986 * Monitor/Kernel API
1987 */
1988
1989 #define BREAKPOINT_REQUEST 0x00000004
1990 #define INIT_STRUCT_BASE_ADDRESS 0x00000005
1991 #define READ_PERMANENT_PARAMETERS 0x0000000a
1992 #define WRITE_PERMANENT_PARAMETERS 0x0000000b
1993 #define HOST_CRASHING 0x0000000d
1994 #define SEND_SYNCHRONOUS_FIB 0x0000000c
1995 #define COMMAND_POST_RESULTS 0x00000014
1996 #define GET_ADAPTER_PROPERTIES 0x00000019
1997 #define GET_DRIVER_BUFFER_PROPERTIES 0x00000023
1998 #define RCV_TEMP_READINGS 0x00000025
1999 #define GET_COMM_PREFERRED_SETTINGS 0x00000026
2000 #define IOP_RESET 0x00001000
2001 #define IOP_RESET_ALWAYS 0x00001001
2002 #define RE_INIT_ADAPTER 0x000000ee
2003
2004 /*
2005 * Adapter Status Register
2006 *
2007 * Phase Staus mailbox is 32bits:
2008 * <31:16> = Phase Status
2009 * <15:0> = Phase
2010 *
2011 * The adapter reports is present state through the phase. Only
2012 * a single phase should be ever be set. Each phase can have multiple
2013 * phase status bits to provide more detailed information about the
2014 * state of the board. Care should be taken to ensure that any phase
2015 * status bits that are set when changing the phase are also valid
2016 * for the new phase or be cleared out. Adapter software (monitor,
2017 * iflash, kernel) is responsible for properly maintining the phase
2018 * status mailbox when it is running.
2019 *
2020 * MONKER_API Phases
2021 *
2022 * Phases are bit oriented. It is NOT valid to have multiple bits set
2023 */
2024
2025 #define SELF_TEST_FAILED 0x00000004
2026 #define MONITOR_PANIC 0x00000020
2027 #define KERNEL_UP_AND_RUNNING 0x00000080
2028 #define KERNEL_PANIC 0x00000100
2029 #define FLASH_UPD_PENDING 0x00002000
2030 #define FLASH_UPD_SUCCESS 0x00004000
2031 #define FLASH_UPD_FAILED 0x00008000
2032 #define FWUPD_TIMEOUT (5 * 60)
2033
2034 /*
2035 * Doorbell bit defines
2036 */
2037
2038 #define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */
2039 #define DoorBellPrintfDone (1<<5) /* Host -> Adapter */
2040 #define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */
2041 #define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */
2042 #define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */
2043 #define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */
2044 #define DoorBellPrintfReady (1<<5) /* Adapter -> Host */
2045 #define DoorBellAifPending (1<<6) /* Adapter -> Host */
2046
2047 /* PMC specific outbound doorbell bits */
2048 #define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */
2049
2050 /*
2051 * For FIB communication, we need all of the following things
2052 * to send back to the user.
2053 */
2054
2055 #define AifCmdEventNotify 1 /* Notify of event */
2056 #define AifEnConfigChange 3 /* Adapter configuration change */
2057 #define AifEnContainerChange 4 /* Container configuration change */
2058 #define AifEnDeviceFailure 5 /* SCSI device failed */
2059 #define AifEnEnclosureManagement 13 /* EM_DRIVE_* */
2060 #define EM_DRIVE_INSERTION 31
2061 #define EM_DRIVE_REMOVAL 32
2062 #define EM_SES_DRIVE_INSERTION 33
2063 #define EM_SES_DRIVE_REMOVAL 26
2064 #define AifEnBatteryEvent 14 /* Change in Battery State */
2065 #define AifEnAddContainer 15 /* A new array was created */
2066 #define AifEnDeleteContainer 16 /* A container was deleted */
2067 #define AifEnExpEvent 23 /* Firmware Event Log */
2068 #define AifExeFirmwarePanic 3 /* Firmware Event Panic */
2069 #define AifHighPriority 3 /* Highest Priority Event */
2070 #define AifEnAddJBOD 30 /* JBOD created */
2071 #define AifEnDeleteJBOD 31 /* JBOD deleted */
2072
2073 #define AifBuManagerEvent 42 /* Bu management*/
2074 #define AifBuCacheDataLoss 10
2075 #define AifBuCacheDataRecover 11
2076
2077 #define AifCmdJobProgress 2 /* Progress report */
2078 #define AifJobCtrZero 101 /* Array Zero progress */
2079 #define AifJobStsSuccess 1 /* Job completes */
2080 #define AifJobStsRunning 102 /* Job running */
2081 #define AifCmdAPIReport 3 /* Report from other user of API */
2082 #define AifCmdDriverNotify 4 /* Notify host driver of event */
2083 #define AifDenMorphComplete 200 /* A morph operation completed */
2084 #define AifDenVolumeExtendComplete 201 /* A volume extend completed */
2085 #define AifReqJobList 100 /* Gets back complete job list */
2086 #define AifReqJobsForCtr 101 /* Gets back jobs for specific container */
2087 #define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */
2088 #define AifReqJobReport 103 /* Gets back a specific job report or list of them */
2089 #define AifReqTerminateJob 104 /* Terminates job */
2090 #define AifReqSuspendJob 105 /* Suspends a job */
2091 #define AifReqResumeJob 106 /* Resumes a job */
2092 #define AifReqSendAPIReport 107 /* API generic report requests */
2093 #define AifReqAPIJobStart 108 /* Start a job from the API */
2094 #define AifReqAPIJobUpdate 109 /* Update a job report from the API */
2095 #define AifReqAPIJobFinish 110 /* Finish a job from the API */
2096
2097 /* PMC NEW COMM: Request the event data */
2098 #define AifReqEvent 200
2099
2100 /* RAW device deleted */
2101 #define AifRawDeviceRemove 203
2102
2103 /*
2104 * Adapter Initiated FIB command structures. Start with the adapter
2105 * initiated FIBs that really come from the adapter, and get responded
2106 * to by the host.
2107 */
2108
2109 struct aac_aifcmd {
2110 __le32 command; /* Tell host what type of notify this is */
2111 __le32 seqnum; /* To allow ordering of reports (if necessary) */
2112 u8 data[1]; /* Undefined length (from kernel viewpoint) */
2113 };
2114
2115 /**
2116 * Convert capacity to cylinders
2117 * accounting for the fact capacity could be a 64 bit value
2118 *
2119 */
2120 static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor)
2121 {
2122 sector_div(capacity, divisor);
2123 return capacity;
2124 }
2125
2126 /* SCp.phase values */
2127 #define AAC_OWNER_MIDLEVEL 0x101
2128 #define AAC_OWNER_LOWLEVEL 0x102
2129 #define AAC_OWNER_ERROR_HANDLER 0x103
2130 #define AAC_OWNER_FIRMWARE 0x106
2131
2132 int aac_acquire_irq(struct aac_dev *dev);
2133 void aac_free_irq(struct aac_dev *dev);
2134 const char *aac_driverinfo(struct Scsi_Host *);
2135 void aac_fib_vector_assign(struct aac_dev *dev);
2136 struct fib *aac_fib_alloc(struct aac_dev *dev);
2137 struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd);
2138 int aac_fib_setup(struct aac_dev *dev);
2139 void aac_fib_map_free(struct aac_dev *dev);
2140 void aac_fib_free(struct fib * context);
2141 void aac_fib_init(struct fib * context);
2142 void aac_printf(struct aac_dev *dev, u32 val);
2143 int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt);
2144 int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry);
2145 void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum);
2146 int aac_fib_complete(struct fib * context);
2147 #define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data)
2148 struct aac_dev *aac_init_adapter(struct aac_dev *dev);
2149 void aac_src_access_devreg(struct aac_dev *dev, int mode);
2150 int aac_get_config_status(struct aac_dev *dev, int commit_flag);
2151 int aac_get_containers(struct aac_dev *dev);
2152 int aac_scsi_cmd(struct scsi_cmnd *cmd);
2153 int aac_dev_ioctl(struct aac_dev *dev, int cmd, void __user *arg);
2154 #ifndef shost_to_class
2155 #define shost_to_class(shost) &shost->shost_dev
2156 #endif
2157 ssize_t aac_get_serial_number(struct device *dev, char *buf);
2158 int aac_do_ioctl(struct aac_dev * dev, int cmd, void __user *arg);
2159 int aac_rx_init(struct aac_dev *dev);
2160 int aac_rkt_init(struct aac_dev *dev);
2161 int aac_nark_init(struct aac_dev *dev);
2162 int aac_sa_init(struct aac_dev *dev);
2163 int aac_src_init(struct aac_dev *dev);
2164 int aac_srcv_init(struct aac_dev *dev);
2165 int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify);
2166 void aac_define_int_mode(struct aac_dev *dev);
2167 unsigned int aac_response_normal(struct aac_queue * q);
2168 unsigned int aac_command_normal(struct aac_queue * q);
2169 unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index,
2170 int isAif, int isFastResponse,
2171 struct hw_fib *aif_fib);
2172 int aac_reset_adapter(struct aac_dev * dev, int forced);
2173 int aac_check_health(struct aac_dev * dev);
2174 int aac_command_thread(void *data);
2175 int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx);
2176 int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size);
2177 struct aac_driver_ident* aac_get_driver_ident(int devtype);
2178 int aac_get_adapter_info(struct aac_dev* dev);
2179 int aac_send_shutdown(struct aac_dev *dev);
2180 int aac_probe_container(struct aac_dev *dev, int cid);
2181 int _aac_rx_init(struct aac_dev *dev);
2182 int aac_rx_select_comm(struct aac_dev *dev, int comm);
2183 int aac_rx_deliver_producer(struct fib * fib);
2184 char * get_container_type(unsigned type);
2185 extern int numacb;
2186 extern int acbsize;
2187 extern char aac_driver_version[];
2188 extern int startup_timeout;
2189 extern int aif_timeout;
2190 extern int expose_physicals;
2191 extern int aac_reset_devices;
2192 extern int aac_msi;
2193 extern int aac_commit;
2194 extern int update_interval;
2195 extern int check_interval;
2196 extern int aac_check_reset;
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