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scsi: aacraid: Retrieve Queue Depth from Adapter FW
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / aacraid / aacraid.h
1 #ifndef _AACRAID_H_
2 #define _AACRAID_H_
3 #ifndef dprintk
4 # define dprintk(x)
5 #endif
6 /* eg: if (nblank(dprintk(x))) */
7 #define _nblank(x) #x
8 #define nblank(x) _nblank(x)[0]
9
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12
13 /*------------------------------------------------------------------------------
14 * D E F I N E S
15 *----------------------------------------------------------------------------*/
16
17 #define AAC_MAX_MSIX 32 /* vectors */
18 #define AAC_PCI_MSI_ENABLE 0x8000
19
20 enum {
21 AAC_ENABLE_INTERRUPT = 0x0,
22 AAC_DISABLE_INTERRUPT,
23 AAC_ENABLE_MSIX,
24 AAC_DISABLE_MSIX,
25 AAC_CLEAR_AIF_BIT,
26 AAC_CLEAR_SYNC_BIT,
27 AAC_ENABLE_INTX
28 };
29
30 #define AAC_INT_MODE_INTX (1<<0)
31 #define AAC_INT_MODE_MSI (1<<1)
32 #define AAC_INT_MODE_AIF (1<<2)
33 #define AAC_INT_MODE_SYNC (1<<3)
34 #define AAC_INT_MODE_MSIX (1<<16)
35
36 #define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb
37 #define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa
38 #define AAC_INT_DISABLE_ALL 0xffffffff
39
40 /* Bit definitions in IOA->Host Interrupt Register */
41 #define PMC_TRANSITION_TO_OPERATIONAL (1<<31)
42 #define PMC_IOARCB_TRANSFER_FAILED (1<<28)
43 #define PMC_IOA_UNIT_CHECK (1<<27)
44 #define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26)
45 #define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25)
46 #define PMC_IOARRIN_LOST (1<<4)
47 #define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3)
48 #define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2)
49 #define PMC_HOST_RRQ_VALID (1<<1)
50 #define PMC_OPERATIONAL_STATUS (1<<31)
51 #define PMC_ALLOW_MSIX_VECTOR0 (1<<0)
52
53 #define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \
54 PMC_IOA_UNIT_CHECK | \
55 PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \
56 PMC_IOARRIN_LOST | \
57 PMC_SYSTEM_BUS_MMIO_ERROR | \
58 PMC_IOA_PROCESSOR_IN_ERROR_STATE)
59
60 #define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \
61 PMC_HOST_RRQ_VALID | \
62 PMC_TRANSITION_TO_OPERATIONAL | \
63 PMC_ALLOW_MSIX_VECTOR0)
64 #define PMC_GLOBAL_INT_BIT2 0x00000004
65 #define PMC_GLOBAL_INT_BIT0 0x00000001
66
67 #ifndef AAC_DRIVER_BUILD
68 # define AAC_DRIVER_BUILD 41066
69 # define AAC_DRIVER_BRANCH "-ms"
70 #endif
71 #define MAXIMUM_NUM_CONTAINERS 32
72
73 #define AAC_NUM_MGT_FIB 8
74 #define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB)
75 #define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB)
76
77 #define AAC_MAX_LUN (256)
78
79 #define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff)
80 #define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256)
81
82 #define AAC_DEBUG_INSTRUMENT_AIF_DELETE
83
84 #define AAC_MAX_NATIVE_TARGETS 1024
85 /* Thor: 5 phys. buses: #0: empty, 1-4: 256 targets each */
86 #define AAC_MAX_BUSES 5
87 #define AAC_MAX_TARGETS 256
88 #define AAC_MAX_NATIVE_SIZE 2048
89
90 #define CISS_REPORT_PHYSICAL_LUNS 0xc3
91 #define WRITE_HOST_WELLNESS 0xa5
92 #define CISS_IDENTIFY_PHYSICAL_DEVICE 0x15
93 #define BMIC_IN 0x26
94 #define BMIC_OUT 0x27
95
96 struct aac_ciss_phys_luns_resp {
97 u8 list_length[4]; /* LUN list length (N-7, big endian) */
98 u8 resp_flag; /* extended response_flag */
99 u8 reserved[3];
100 struct _ciss_lun {
101 u8 tid[3]; /* Target ID */
102 u8 bus; /* Bus, flag (bits 6,7) */
103 u8 level3[2];
104 u8 level2[2];
105 u8 node_ident[16]; /* phys. node identifier */
106 } lun[1]; /* List of phys. devices */
107 };
108
109 /*
110 * Interrupts
111 */
112 #define AAC_MAX_HRRQ 64
113
114 struct aac_ciss_identify_pd {
115 u8 scsi_bus; /* SCSI Bus number on controller */
116 u8 scsi_id; /* SCSI ID on this bus */
117 u16 block_size; /* sector size in bytes */
118 u32 total_blocks; /* number for sectors on drive */
119 u32 reserved_blocks; /* controller reserved (RIS) */
120 u8 model[40]; /* Physical Drive Model */
121 u8 serial_number[40]; /* Drive Serial Number */
122 u8 firmware_revision[8]; /* drive firmware revision */
123 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */
124 u8 compaq_drive_stamp; /* 0 means drive not stamped */
125 u8 last_failure_reason;
126
127 u8 flags;
128 u8 more_flags;
129 u8 scsi_lun; /* SCSI LUN for phys drive */
130 u8 yet_more_flags;
131 u8 even_more_flags;
132 u32 spi_speed_rules; /* SPI Speed :Ultra disable diagnose */
133 u8 phys_connector[2]; /* connector number on controller */
134 u8 phys_box_on_bus; /* phys enclosure this drive resides */
135 u8 phys_bay_in_box; /* phys drv bay this drive resides */
136 u32 rpm; /* Drive rotational speed in rpm */
137 u8 device_type; /* type of drive */
138 u8 sata_version; /* only valid when drive_type is SATA */
139 u64 big_total_block_count;
140 u64 ris_starting_lba;
141 u32 ris_size;
142 u8 wwid[20];
143 u8 controller_phy_map[32];
144 u16 phy_count;
145 u8 phy_connected_dev_type[256];
146 u8 phy_to_drive_bay_num[256];
147 u16 phy_to_attached_dev_index[256];
148 u8 box_index;
149 u8 spitfire_support;
150 u16 extra_physical_drive_flags;
151 u8 negotiated_link_rate[256];
152 u8 phy_to_phy_map[256];
153 u8 redundant_path_present_map;
154 u8 redundant_path_failure_map;
155 u8 active_path_number;
156 u16 alternate_paths_phys_connector[8];
157 u8 alternate_paths_phys_box_on_port[8];
158 u8 multi_lun_device_lun_count;
159 u8 minimum_good_fw_revision[8];
160 u8 unique_inquiry_bytes[20];
161 u8 current_temperature_degreesC;
162 u8 temperature_threshold_degreesC;
163 u8 max_temperature_degreesC;
164 u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512 * 2^exp */
165 u16 current_queue_depth_limit;
166 u8 switch_name[10];
167 u16 switch_port;
168 u8 alternate_paths_switch_name[40];
169 u8 alternate_paths_switch_port[8];
170 u16 power_on_hours; /* valid only if gas gauge supported */
171 u16 percent_endurance_used; /* valid only if gas gauge supported. */
172 u8 drive_authentication;
173 u8 smart_carrier_authentication;
174 u8 smart_carrier_app_fw_version;
175 u8 smart_carrier_bootloader_fw_version;
176 u8 SanitizeSecureEraseSupport;
177 u8 DriveKeyFlags;
178 u8 encryption_key_name[64];
179 u32 misc_drive_flags;
180 u16 dek_index;
181 u16 drive_encryption_flags;
182 u8 sanitize_maximum_time[6];
183 u8 connector_info_mode;
184 u8 connector_info_number[4];
185 u8 long_connector_name[64];
186 u8 device_unique_identifier[16];
187 u8 padto_2K[17];
188 } __packed;
189
190 /*
191 * These macros convert from physical channels to virtual channels
192 */
193 #define CONTAINER_CHANNEL (0)
194 #define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL)
195 #define CONTAINER_TO_ID(cont) (cont)
196 #define CONTAINER_TO_LUN(cont) (0)
197
198 #define PMC_DEVICE_S6 0x28b
199 #define PMC_DEVICE_S7 0x28c
200 #define PMC_DEVICE_S8 0x28d
201 #define PMC_DEVICE_S9 0x28f
202
203 #define aac_phys_to_logical(x) ((x)+1)
204 #define aac_logical_to_phys(x) ((x)?(x)-1:0)
205
206 /*
207 * These macros are for keeping track of
208 * character device state.
209 */
210 #define AAC_CHARDEV_UNREGISTERED (-1)
211 #define AAC_CHARDEV_NEEDS_REINIT (-2)
212
213 /* #define AAC_DETAILED_STATUS_INFO */
214
215 struct diskparm
216 {
217 int heads;
218 int sectors;
219 int cylinders;
220 };
221
222
223 /*
224 * Firmware constants
225 */
226
227 #define CT_NONE 0
228 #define CT_OK 218
229 #define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */
230 #define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */
231
232 /*
233 * Host side memory scatter gather list
234 * Used by the adapter for read, write, and readdirplus operations
235 * We have separate 32 and 64 bit version because even
236 * on 64 bit systems not all cards support the 64 bit version
237 */
238 struct sgentry {
239 __le32 addr; /* 32-bit address. */
240 __le32 count; /* Length. */
241 };
242
243 struct user_sgentry {
244 u32 addr; /* 32-bit address. */
245 u32 count; /* Length. */
246 };
247
248 struct sgentry64 {
249 __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
250 __le32 count; /* Length. */
251 };
252
253 struct user_sgentry64 {
254 u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
255 u32 count; /* Length. */
256 };
257
258 struct sgentryraw {
259 __le32 next; /* reserved for F/W use */
260 __le32 prev; /* reserved for F/W use */
261 __le32 addr[2];
262 __le32 count;
263 __le32 flags; /* reserved for F/W use */
264 };
265
266 struct user_sgentryraw {
267 u32 next; /* reserved for F/W use */
268 u32 prev; /* reserved for F/W use */
269 u32 addr[2];
270 u32 count;
271 u32 flags; /* reserved for F/W use */
272 };
273
274 struct sge_ieee1212 {
275 u32 addrLow;
276 u32 addrHigh;
277 u32 length;
278 u32 flags;
279 };
280
281 /*
282 * SGMAP
283 *
284 * This is the SGMAP structure for all commands that use
285 * 32-bit addressing.
286 */
287
288 struct sgmap {
289 __le32 count;
290 struct sgentry sg[1];
291 };
292
293 struct user_sgmap {
294 u32 count;
295 struct user_sgentry sg[1];
296 };
297
298 struct sgmap64 {
299 __le32 count;
300 struct sgentry64 sg[1];
301 };
302
303 struct user_sgmap64 {
304 u32 count;
305 struct user_sgentry64 sg[1];
306 };
307
308 struct sgmapraw {
309 __le32 count;
310 struct sgentryraw sg[1];
311 };
312
313 struct user_sgmapraw {
314 u32 count;
315 struct user_sgentryraw sg[1];
316 };
317
318 struct creation_info
319 {
320 u8 buildnum; /* e.g., 588 */
321 u8 usec; /* e.g., 588 */
322 u8 via; /* e.g., 1 = FSU,
323 * 2 = API
324 */
325 u8 year; /* e.g., 1997 = 97 */
326 __le32 date; /*
327 * unsigned Month :4; // 1 - 12
328 * unsigned Day :6; // 1 - 32
329 * unsigned Hour :6; // 0 - 23
330 * unsigned Minute :6; // 0 - 60
331 * unsigned Second :6; // 0 - 60
332 */
333 __le32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */
334 };
335
336
337 /*
338 * Define all the constants needed for the communication interface
339 */
340
341 /*
342 * Define how many queue entries each queue will have and the total
343 * number of entries for the entire communication interface. Also define
344 * how many queues we support.
345 *
346 * This has to match the controller
347 */
348
349 #define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response
350 #define HOST_HIGH_CMD_ENTRIES 4
351 #define HOST_NORM_CMD_ENTRIES 8
352 #define ADAP_HIGH_CMD_ENTRIES 4
353 #define ADAP_NORM_CMD_ENTRIES 512
354 #define HOST_HIGH_RESP_ENTRIES 4
355 #define HOST_NORM_RESP_ENTRIES 512
356 #define ADAP_HIGH_RESP_ENTRIES 4
357 #define ADAP_NORM_RESP_ENTRIES 8
358
359 #define TOTAL_QUEUE_ENTRIES \
360 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \
361 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES)
362
363
364 /*
365 * Set the queues on a 16 byte alignment
366 */
367
368 #define QUEUE_ALIGNMENT 16
369
370 /*
371 * The queue headers define the Communication Region queues. These
372 * are physically contiguous and accessible by both the adapter and the
373 * host. Even though all queue headers are in the same contiguous block
374 * they will be represented as individual units in the data structures.
375 */
376
377 struct aac_entry {
378 __le32 size; /* Size in bytes of Fib which this QE points to */
379 __le32 addr; /* Receiver address of the FIB */
380 };
381
382 /*
383 * The adapter assumes the ProducerIndex and ConsumerIndex are grouped
384 * adjacently and in that order.
385 */
386
387 struct aac_qhdr {
388 __le64 header_addr;/* Address to hand the adapter to access
389 to this queue head */
390 __le32 *producer; /* The producer index for this queue (host address) */
391 __le32 *consumer; /* The consumer index for this queue (host address) */
392 };
393
394 /*
395 * Define all the events which the adapter would like to notify
396 * the host of.
397 */
398
399 #define HostNormCmdQue 1 /* Change in host normal priority command queue */
400 #define HostHighCmdQue 2 /* Change in host high priority command queue */
401 #define HostNormRespQue 3 /* Change in host normal priority response queue */
402 #define HostHighRespQue 4 /* Change in host high priority response queue */
403 #define AdapNormRespNotFull 5
404 #define AdapHighRespNotFull 6
405 #define AdapNormCmdNotFull 7
406 #define AdapHighCmdNotFull 8
407 #define SynchCommandComplete 9
408 #define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */
409
410 /*
411 * Define all the events the host wishes to notify the
412 * adapter of. The first four values much match the Qid the
413 * corresponding queue.
414 */
415
416 #define AdapNormCmdQue 2
417 #define AdapHighCmdQue 3
418 #define AdapNormRespQue 6
419 #define AdapHighRespQue 7
420 #define HostShutdown 8
421 #define HostPowerFail 9
422 #define FatalCommError 10
423 #define HostNormRespNotFull 11
424 #define HostHighRespNotFull 12
425 #define HostNormCmdNotFull 13
426 #define HostHighCmdNotFull 14
427 #define FastIo 15
428 #define AdapPrintfDone 16
429
430 /*
431 * Define all the queues that the adapter and host use to communicate
432 * Number them to match the physical queue layout.
433 */
434
435 enum aac_queue_types {
436 HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */
437 HostHighCmdQueue, /* Adapter to host high priority command traffic */
438 AdapNormCmdQueue, /* Host to adapter normal priority command traffic */
439 AdapHighCmdQueue, /* Host to adapter high priority command traffic */
440 HostNormRespQueue, /* Adapter to host normal priority response traffic */
441 HostHighRespQueue, /* Adapter to host high priority response traffic */
442 AdapNormRespQueue, /* Host to adapter normal priority response traffic */
443 AdapHighRespQueue /* Host to adapter high priority response traffic */
444 };
445
446 /*
447 * Assign type values to the FSA communication data structures
448 */
449
450 #define FIB_MAGIC 0x0001
451 #define FIB_MAGIC2 0x0004
452 #define FIB_MAGIC2_64 0x0005
453
454 /*
455 * Define the priority levels the FSA communication routines support.
456 */
457
458 #define FsaNormal 1
459
460 /* transport FIB header (PMC) */
461 struct aac_fib_xporthdr {
462 u64 HostAddress; /* FIB host address w/o xport header */
463 u32 Size; /* FIB size excluding xport header */
464 u32 Handle; /* driver handle to reference the FIB */
465 u64 Reserved[2];
466 };
467
468 #define ALIGN32 32
469
470 /*
471 * Define the FIB. The FIB is the where all the requested data and
472 * command information are put to the application on the FSA adapter.
473 */
474
475 struct aac_fibhdr {
476 __le32 XferState; /* Current transfer state for this CCB */
477 __le16 Command; /* Routing information for the destination */
478 u8 StructType; /* Type FIB */
479 u8 Unused; /* Unused */
480 __le16 Size; /* Size of this FIB in bytes */
481 __le16 SenderSize; /* Size of the FIB in the sender
482 (for response sizing) */
483 __le32 SenderFibAddress; /* Host defined data in the FIB */
484 union {
485 __le32 ReceiverFibAddress;/* Logical address of this FIB for
486 the adapter (old) */
487 __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */
488 __le32 TimeStamp; /* otherwise timestamp for FW internal use */
489 } u;
490 __le32 Handle; /* FIB handle used for MSGU commnunication */
491 u32 Previous; /* FW internal use */
492 u32 Next; /* FW internal use */
493 };
494
495 struct hw_fib {
496 struct aac_fibhdr header;
497 u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data
498 };
499
500 /*
501 * FIB commands
502 */
503
504 #define TestCommandResponse 1
505 #define TestAdapterCommand 2
506 /*
507 * Lowlevel and comm commands
508 */
509 #define LastTestCommand 100
510 #define ReinitHostNormCommandQueue 101
511 #define ReinitHostHighCommandQueue 102
512 #define ReinitHostHighRespQueue 103
513 #define ReinitHostNormRespQueue 104
514 #define ReinitAdapNormCommandQueue 105
515 #define ReinitAdapHighCommandQueue 107
516 #define ReinitAdapHighRespQueue 108
517 #define ReinitAdapNormRespQueue 109
518 #define InterfaceShutdown 110
519 #define DmaCommandFib 120
520 #define StartProfile 121
521 #define TermProfile 122
522 #define SpeedTest 123
523 #define TakeABreakPt 124
524 #define RequestPerfData 125
525 #define SetInterruptDefTimer 126
526 #define SetInterruptDefCount 127
527 #define GetInterruptDefStatus 128
528 #define LastCommCommand 129
529 /*
530 * Filesystem commands
531 */
532 #define NuFileSystem 300
533 #define UFS 301
534 #define HostFileSystem 302
535 #define LastFileSystemCommand 303
536 /*
537 * Container Commands
538 */
539 #define ContainerCommand 500
540 #define ContainerCommand64 501
541 #define ContainerRawIo 502
542 #define ContainerRawIo2 503
543 /*
544 * Scsi Port commands (scsi passthrough)
545 */
546 #define ScsiPortCommand 600
547 #define ScsiPortCommand64 601
548 /*
549 * Misc house keeping and generic adapter initiated commands
550 */
551 #define AifRequest 700
552 #define CheckRevision 701
553 #define FsaHostShutdown 702
554 #define RequestAdapterInfo 703
555 #define IsAdapterPaused 704
556 #define SendHostTime 705
557 #define RequestSupplementAdapterInfo 706
558 #define LastMiscCommand 707
559
560 /*
561 * Commands that will target the failover level on the FSA adapter
562 */
563
564 enum fib_xfer_state {
565 HostOwned = (1<<0),
566 AdapterOwned = (1<<1),
567 FibInitialized = (1<<2),
568 FibEmpty = (1<<3),
569 AllocatedFromPool = (1<<4),
570 SentFromHost = (1<<5),
571 SentFromAdapter = (1<<6),
572 ResponseExpected = (1<<7),
573 NoResponseExpected = (1<<8),
574 AdapterProcessed = (1<<9),
575 HostProcessed = (1<<10),
576 HighPriority = (1<<11),
577 NormalPriority = (1<<12),
578 Async = (1<<13),
579 AsyncIo = (1<<13), // rpbfix: remove with new regime
580 PageFileIo = (1<<14), // rpbfix: remove with new regime
581 ShutdownRequest = (1<<15),
582 LazyWrite = (1<<16), // rpbfix: remove with new regime
583 AdapterMicroFib = (1<<17),
584 BIOSFibPath = (1<<18),
585 FastResponseCapable = (1<<19),
586 ApiFib = (1<<20), /* Its an API Fib */
587 /* PMC NEW COMM: There is no more AIF data pending */
588 NoMoreAifDataAvailable = (1<<21)
589 };
590
591 /*
592 * The following defines needs to be updated any time there is an
593 * incompatible change made to the aac_init structure.
594 */
595
596 #define ADAPTER_INIT_STRUCT_REVISION 3
597 #define ADAPTER_INIT_STRUCT_REVISION_4 4 // rocket science
598 #define ADAPTER_INIT_STRUCT_REVISION_6 6 /* PMC src */
599 #define ADAPTER_INIT_STRUCT_REVISION_7 7 /* Denali */
600 #define ADAPTER_INIT_STRUCT_REVISION_8 8 // Thor
601
602 union aac_init
603 {
604 struct _r7 {
605 __le32 init_struct_revision;
606 __le32 no_of_msix_vectors;
607 __le32 fsrev;
608 __le32 comm_header_address;
609 __le32 fast_io_comm_area_address;
610 __le32 adapter_fibs_physical_address;
611 __le32 adapter_fibs_virtual_address;
612 __le32 adapter_fibs_size;
613 __le32 adapter_fib_align;
614 __le32 printfbuf;
615 __le32 printfbufsiz;
616 /* number of 4k pages of host phys. mem. */
617 __le32 host_phys_mem_pages;
618 /* number of seconds since 1970. */
619 __le32 host_elapsed_seconds;
620 /* ADAPTER_INIT_STRUCT_REVISION_4 begins here */
621 __le32 init_flags; /* flags for supported features */
622 #define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001
623 #define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010
624 #define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020
625 #define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040
626 #define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080
627 #define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100
628 #define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE 0x00000400
629 __le32 max_io_commands; /* max outstanding commands */
630 __le32 max_io_size; /* largest I/O command */
631 __le32 max_fib_size; /* largest FIB to adapter */
632 /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */
633 __le32 max_num_aif; /* max number of aif */
634 /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */
635 /* Host RRQ (response queue) for SRC */
636 __le32 host_rrq_addr_low;
637 __le32 host_rrq_addr_high;
638 } r7;
639 struct _r8 {
640 /* ADAPTER_INIT_STRUCT_REVISION_8 */
641 __le32 init_struct_revision;
642 __le32 rr_queue_count;
643 __le32 host_elapsed_seconds; /* number of secs since 1970. */
644 __le32 init_flags;
645 __le32 max_io_size; /* largest I/O command */
646 __le32 max_num_aif; /* max number of aif */
647 __le32 reserved1;
648 __le32 reserved2;
649 struct _rrq {
650 __le32 host_addr_low;
651 __le32 host_addr_high;
652 __le16 msix_id;
653 __le16 element_count;
654 __le16 comp_thresh;
655 __le16 unused;
656 } rrq[1]; /* up to 64 RRQ addresses */
657 } r8;
658 };
659
660 enum aac_log_level {
661 LOG_AAC_INIT = 10,
662 LOG_AAC_INFORMATIONAL = 20,
663 LOG_AAC_WARNING = 30,
664 LOG_AAC_LOW_ERROR = 40,
665 LOG_AAC_MEDIUM_ERROR = 50,
666 LOG_AAC_HIGH_ERROR = 60,
667 LOG_AAC_PANIC = 70,
668 LOG_AAC_DEBUG = 80,
669 LOG_AAC_WINDBG_PRINT = 90
670 };
671
672 #define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b
673 #define FSAFS_NTC_FIB_CONTEXT 0x030c
674
675 struct aac_dev;
676 struct fib;
677 struct scsi_cmnd;
678
679 struct adapter_ops
680 {
681 /* Low level operations */
682 void (*adapter_interrupt)(struct aac_dev *dev);
683 void (*adapter_notify)(struct aac_dev *dev, u32 event);
684 void (*adapter_disable_int)(struct aac_dev *dev);
685 void (*adapter_enable_int)(struct aac_dev *dev);
686 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4);
687 int (*adapter_check_health)(struct aac_dev *dev);
688 int (*adapter_restart)(struct aac_dev *dev, int bled);
689 void (*adapter_start)(struct aac_dev *dev);
690 /* Transport operations */
691 int (*adapter_ioremap)(struct aac_dev * dev, u32 size);
692 irq_handler_t adapter_intr;
693 /* Packet operations */
694 int (*adapter_deliver)(struct fib * fib);
695 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba);
696 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count);
697 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua);
698 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd);
699 /* Administrative operations */
700 int (*adapter_comm)(struct aac_dev * dev, int comm);
701 };
702
703 /*
704 * Define which interrupt handler needs to be installed
705 */
706
707 struct aac_driver_ident
708 {
709 int (*init)(struct aac_dev *dev);
710 char * name;
711 char * vname;
712 char * model;
713 u16 channels;
714 int quirks;
715 };
716 /*
717 * Some adapter firmware needs communication memory
718 * below 2gig. This tells the init function to set the
719 * dma mask such that fib memory will be allocated where the
720 * adapter firmware can get to it.
721 */
722 #define AAC_QUIRK_31BIT 0x0001
723
724 /*
725 * Some adapter firmware, when the raid card's cache is turned off, can not
726 * split up scatter gathers in order to deal with the limits of the
727 * underlying CHIM. This limit is 34 scatter gather elements.
728 */
729 #define AAC_QUIRK_34SG 0x0002
730
731 /*
732 * This adapter is a slave (no Firmware)
733 */
734 #define AAC_QUIRK_SLAVE 0x0004
735
736 /*
737 * This adapter is a master.
738 */
739 #define AAC_QUIRK_MASTER 0x0008
740
741 /*
742 * Some adapter firmware perform poorly when it must split up scatter gathers
743 * in order to deal with the limits of the underlying CHIM. This limit in this
744 * class of adapters is 17 scatter gather elements.
745 */
746 #define AAC_QUIRK_17SG 0x0010
747
748 /*
749 * Some adapter firmware does not support 64 bit scsi passthrough
750 * commands.
751 */
752 #define AAC_QUIRK_SCSI_32 0x0020
753
754 /*
755 * SRC based adapters support the AifReqEvent functions
756 */
757 #define AAC_QUIRK_SRC 0x0040
758
759 /*
760 * The adapter interface specs all queues to be located in the same
761 * physically contiguous block. The host structure that defines the
762 * commuication queues will assume they are each a separate physically
763 * contiguous memory region that will support them all being one big
764 * contiguous block.
765 * There is a command and response queue for each level and direction of
766 * commuication. These regions are accessed by both the host and adapter.
767 */
768
769 struct aac_queue {
770 u64 logical; /*address we give the adapter */
771 struct aac_entry *base; /*system virtual address */
772 struct aac_qhdr headers; /*producer,consumer q headers*/
773 u32 entries; /*Number of queue entries */
774 wait_queue_head_t qfull; /*Event to wait on if q full */
775 wait_queue_head_t cmdready; /*Cmd ready from the adapter */
776 /* This is only valid for adapter to host command queues. */
777 spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */
778 spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */
779 struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */
780 /* only valid for command queues which receive entries from the adapter. */
781 /* Number of entries on outstanding queue. */
782 atomic_t numpending;
783 struct aac_dev * dev; /* Back pointer to adapter structure */
784 };
785
786 /*
787 * Message queues. The order here is important, see also the
788 * queue type ordering
789 */
790
791 struct aac_queue_block
792 {
793 struct aac_queue queue[8];
794 };
795
796 /*
797 * SaP1 Message Unit Registers
798 */
799
800 struct sa_drawbridge_CSR {
801 /* Offset | Name */
802 __le32 reserved[10]; /* 00h-27h | Reserved */
803 u8 LUT_Offset; /* 28h | Lookup Table Offset */
804 u8 reserved1[3]; /* 29h-2bh | Reserved */
805 __le32 LUT_Data; /* 2ch | Looup Table Data */
806 __le32 reserved2[26]; /* 30h-97h | Reserved */
807 __le16 PRICLEARIRQ; /* 98h | Primary Clear Irq */
808 __le16 SECCLEARIRQ; /* 9ah | Secondary Clear Irq */
809 __le16 PRISETIRQ; /* 9ch | Primary Set Irq */
810 __le16 SECSETIRQ; /* 9eh | Secondary Set Irq */
811 __le16 PRICLEARIRQMASK;/* a0h | Primary Clear Irq Mask */
812 __le16 SECCLEARIRQMASK;/* a2h | Secondary Clear Irq Mask */
813 __le16 PRISETIRQMASK; /* a4h | Primary Set Irq Mask */
814 __le16 SECSETIRQMASK; /* a6h | Secondary Set Irq Mask */
815 __le32 MAILBOX0; /* a8h | Scratchpad 0 */
816 __le32 MAILBOX1; /* ach | Scratchpad 1 */
817 __le32 MAILBOX2; /* b0h | Scratchpad 2 */
818 __le32 MAILBOX3; /* b4h | Scratchpad 3 */
819 __le32 MAILBOX4; /* b8h | Scratchpad 4 */
820 __le32 MAILBOX5; /* bch | Scratchpad 5 */
821 __le32 MAILBOX6; /* c0h | Scratchpad 6 */
822 __le32 MAILBOX7; /* c4h | Scratchpad 7 */
823 __le32 ROM_Setup_Data; /* c8h | Rom Setup and Data */
824 __le32 ROM_Control_Addr;/* cch | Rom Control and Address */
825 __le32 reserved3[12]; /* d0h-ffh | reserved */
826 __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */
827 };
828
829 #define Mailbox0 SaDbCSR.MAILBOX0
830 #define Mailbox1 SaDbCSR.MAILBOX1
831 #define Mailbox2 SaDbCSR.MAILBOX2
832 #define Mailbox3 SaDbCSR.MAILBOX3
833 #define Mailbox4 SaDbCSR.MAILBOX4
834 #define Mailbox5 SaDbCSR.MAILBOX5
835 #define Mailbox6 SaDbCSR.MAILBOX6
836 #define Mailbox7 SaDbCSR.MAILBOX7
837
838 #define DoorbellReg_p SaDbCSR.PRISETIRQ
839 #define DoorbellReg_s SaDbCSR.SECSETIRQ
840 #define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ
841
842
843 #define DOORBELL_0 0x0001
844 #define DOORBELL_1 0x0002
845 #define DOORBELL_2 0x0004
846 #define DOORBELL_3 0x0008
847 #define DOORBELL_4 0x0010
848 #define DOORBELL_5 0x0020
849 #define DOORBELL_6 0x0040
850
851
852 #define PrintfReady DOORBELL_5
853 #define PrintfDone DOORBELL_5
854
855 struct sa_registers {
856 struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */
857 };
858
859
860 #define SA_INIT_NUM_MSIXVECTORS 1
861 #define SA_MINIPORT_REVISION SA_INIT_NUM_MSIXVECTORS
862
863 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
864 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
865 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
866 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
867
868 /*
869 * Rx Message Unit Registers
870 */
871
872 struct rx_mu_registers {
873 /* Local | PCI*| Name */
874 __le32 ARSR; /* 1300h | 00h | APIC Register Select Register */
875 __le32 reserved0; /* 1304h | 04h | Reserved */
876 __le32 AWR; /* 1308h | 08h | APIC Window Register */
877 __le32 reserved1; /* 130Ch | 0Ch | Reserved */
878 __le32 IMRx[2]; /* 1310h | 10h | Inbound Message Registers */
879 __le32 OMRx[2]; /* 1318h | 18h | Outbound Message Registers */
880 __le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */
881 __le32 IISR; /* 1324h | 24h | Inbound Interrupt
882 Status Register */
883 __le32 IIMR; /* 1328h | 28h | Inbound Interrupt
884 Mask Register */
885 __le32 ODR; /* 132Ch | 2Ch | Outbound Doorbell Register */
886 __le32 OISR; /* 1330h | 30h | Outbound Interrupt
887 Status Register */
888 __le32 OIMR; /* 1334h | 34h | Outbound Interrupt
889 Mask Register */
890 __le32 reserved2; /* 1338h | 38h | Reserved */
891 __le32 reserved3; /* 133Ch | 3Ch | Reserved */
892 __le32 InboundQueue;/* 1340h | 40h | Inbound Queue Port relative to firmware */
893 __le32 OutboundQueue;/*1344h | 44h | Outbound Queue Port relative to firmware */
894 /* * Must access through ATU Inbound
895 Translation Window */
896 };
897
898 struct rx_inbound {
899 __le32 Mailbox[8];
900 };
901
902 #define INBOUNDDOORBELL_0 0x00000001
903 #define INBOUNDDOORBELL_1 0x00000002
904 #define INBOUNDDOORBELL_2 0x00000004
905 #define INBOUNDDOORBELL_3 0x00000008
906 #define INBOUNDDOORBELL_4 0x00000010
907 #define INBOUNDDOORBELL_5 0x00000020
908 #define INBOUNDDOORBELL_6 0x00000040
909
910 #define OUTBOUNDDOORBELL_0 0x00000001
911 #define OUTBOUNDDOORBELL_1 0x00000002
912 #define OUTBOUNDDOORBELL_2 0x00000004
913 #define OUTBOUNDDOORBELL_3 0x00000008
914 #define OUTBOUNDDOORBELL_4 0x00000010
915
916 #define InboundDoorbellReg MUnit.IDR
917 #define OutboundDoorbellReg MUnit.ODR
918
919 struct rx_registers {
920 struct rx_mu_registers MUnit; /* 1300h - 1347h */
921 __le32 reserved1[2]; /* 1348h - 134ch */
922 struct rx_inbound IndexRegs;
923 };
924
925 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
926 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
927 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
928 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
929
930 /*
931 * Rkt Message Unit Registers (same as Rx, except a larger reserve region)
932 */
933
934 #define rkt_mu_registers rx_mu_registers
935 #define rkt_inbound rx_inbound
936
937 struct rkt_registers {
938 struct rkt_mu_registers MUnit; /* 1300h - 1347h */
939 __le32 reserved1[1006]; /* 1348h - 22fch */
940 struct rkt_inbound IndexRegs; /* 2300h - */
941 };
942
943 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR))
944 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR))
945 #define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR))
946 #define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
947
948 /*
949 * PMC SRC message unit registers
950 */
951
952 #define src_inbound rx_inbound
953
954 struct src_mu_registers {
955 /* PCI*| Name */
956 __le32 reserved0[6]; /* 00h | Reserved */
957 __le32 IOAR[2]; /* 18h | IOA->host interrupt register */
958 __le32 IDR; /* 20h | Inbound Doorbell Register */
959 __le32 IISR; /* 24h | Inbound Int. Status Register */
960 __le32 reserved1[3]; /* 28h | Reserved */
961 __le32 OIMR; /* 34h | Outbound Int. Mask Register */
962 __le32 reserved2[25]; /* 38h | Reserved */
963 __le32 ODR_R; /* 9ch | Outbound Doorbell Read */
964 __le32 ODR_C; /* a0h | Outbound Doorbell Clear */
965 __le32 reserved3[3]; /* a4h | Reserved */
966 __le32 SCR0; /* b0h | Scratchpad 0 */
967 __le32 reserved4[2]; /* b4h | Reserved */
968 __le32 OMR; /* bch | Outbound Message Register */
969 __le32 IQ_L; /* c0h | Inbound Queue (Low address) */
970 __le32 IQ_H; /* c4h | Inbound Queue (High address) */
971 __le32 ODR_MSI; /* c8h | MSI register for sync./AIF */
972 };
973
974 struct src_registers {
975 struct src_mu_registers MUnit; /* 00h - cbh */
976 union {
977 struct {
978 __le32 reserved1[130789]; /* cch - 7fc5fh */
979 struct src_inbound IndexRegs; /* 7fc60h */
980 } tupelo;
981 struct {
982 __le32 reserved1[973]; /* cch - fffh */
983 struct src_inbound IndexRegs; /* 1000h */
984 } denali;
985 } u;
986 };
987
988 #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR))
989 #define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR))
990 #define src_writeb(AEP, CSR, value) writeb(value, \
991 &((AEP)->regs.src.bar0->CSR))
992 #define src_writel(AEP, CSR, value) writel(value, \
993 &((AEP)->regs.src.bar0->CSR))
994 #if defined(writeq)
995 #define src_writeq(AEP, CSR, value) writeq(value, \
996 &((AEP)->regs.src.bar0->CSR))
997 #endif
998
999 #define SRC_ODR_SHIFT 12
1000 #define SRC_IDR_SHIFT 9
1001
1002 typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);
1003
1004 struct aac_fib_context {
1005 s16 type; // used for verification of structure
1006 s16 size;
1007 u32 unique; // unique value representing this context
1008 ulong jiffies; // used for cleanup - dmb changed to ulong
1009 struct list_head next; // used to link context's into a linked list
1010 struct semaphore wait_sem; // this is used to wait for the next fib to arrive.
1011 int wait; // Set to true when thread is in WaitForSingleObject
1012 unsigned long count; // total number of FIBs on FibList
1013 struct list_head fib_list; // this holds fibs and their attachd hw_fibs
1014 };
1015
1016 struct sense_data {
1017 u8 error_code; /* 70h (current errors), 71h(deferred errors) */
1018 u8 valid:1; /* A valid bit of one indicates that the information */
1019 /* field contains valid information as defined in the
1020 * SCSI-2 Standard.
1021 */
1022 u8 segment_number; /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */
1023 u8 sense_key:4; /* Sense Key */
1024 u8 reserved:1;
1025 u8 ILI:1; /* Incorrect Length Indicator */
1026 u8 EOM:1; /* End Of Medium - reserved for random access devices */
1027 u8 filemark:1; /* Filemark - reserved for random access devices */
1028
1029 u8 information[4]; /* for direct-access devices, contains the unsigned
1030 * logical block address or residue associated with
1031 * the sense key
1032 */
1033 u8 add_sense_len; /* number of additional sense bytes to follow this field */
1034 u8 cmnd_info[4]; /* not used */
1035 u8 ASC; /* Additional Sense Code */
1036 u8 ASCQ; /* Additional Sense Code Qualifier */
1037 u8 FRUC; /* Field Replaceable Unit Code - not used */
1038 u8 bit_ptr:3; /* indicates which byte of the CDB or parameter data
1039 * was in error
1040 */
1041 u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that
1042 * the bit_ptr field has valid value
1043 */
1044 u8 reserved2:2;
1045 u8 CD:1; /* command data bit: 1- illegal parameter in CDB.
1046 * 0- illegal parameter in data.
1047 */
1048 u8 SKSV:1;
1049 u8 field_ptr[2]; /* byte of the CDB or parameter data in error */
1050 };
1051
1052 struct fsa_dev_info {
1053 u64 last;
1054 u64 size;
1055 u32 type;
1056 u32 config_waiting_on;
1057 unsigned long config_waiting_stamp;
1058 u16 queue_depth;
1059 u8 config_needed;
1060 u8 valid;
1061 u8 ro;
1062 u8 locked;
1063 u8 deleted;
1064 char devname[8];
1065 struct sense_data sense_data;
1066 u32 block_size;
1067 u8 identifier[16];
1068 };
1069
1070 struct fib {
1071 void *next; /* this is used by the allocator */
1072 s16 type;
1073 s16 size;
1074 /*
1075 * The Adapter that this I/O is destined for.
1076 */
1077 struct aac_dev *dev;
1078 /*
1079 * This is the event the sendfib routine will wait on if the
1080 * caller did not pass one and this is synch io.
1081 */
1082 struct semaphore event_wait;
1083 spinlock_t event_lock;
1084
1085 u32 done; /* gets set to 1 when fib is complete */
1086 fib_callback callback;
1087 void *callback_data;
1088 u32 flags; // u32 dmb was ulong
1089 /*
1090 * And for the internal issue/reply queues (we may be able
1091 * to merge these two)
1092 */
1093 struct list_head fiblink;
1094 void *data;
1095 u32 vector_no;
1096 struct hw_fib *hw_fib_va; /* Actual shared object */
1097 dma_addr_t hw_fib_pa; /* physical address of hw_fib*/
1098 u32 hbacmd_size; /* cmd size for native */
1099 };
1100
1101 #define AAC_DEVTYPE_RAID_MEMBER 1
1102 #define AAC_DEVTYPE_ARC_RAW 2
1103 #define AAC_DEVTYPE_NATIVE_RAW 3
1104 #define AAC_EXPOSE_DISK 0
1105 #define AAC_HIDE_DISK 3
1106
1107 struct aac_hba_map_info {
1108 __le32 rmw_nexus; /* nexus for native HBA devices */
1109 u8 devtype; /* device type */
1110 u8 reset_state; /* 0 - no reset, 1..x - */
1111 /* after xth TM LUN reset */
1112 u16 qd_limit;
1113 u8 expose; /*checks if to expose or not*/
1114 };
1115
1116 /*
1117 * Adapter Information Block
1118 *
1119 * This is returned by the RequestAdapterInfo block
1120 */
1121
1122 struct aac_adapter_info
1123 {
1124 __le32 platform;
1125 __le32 cpu;
1126 __le32 subcpu;
1127 __le32 clock;
1128 __le32 execmem;
1129 __le32 buffermem;
1130 __le32 totalmem;
1131 __le32 kernelrev;
1132 __le32 kernelbuild;
1133 __le32 monitorrev;
1134 __le32 monitorbuild;
1135 __le32 hwrev;
1136 __le32 hwbuild;
1137 __le32 biosrev;
1138 __le32 biosbuild;
1139 __le32 cluster;
1140 __le32 clusterchannelmask;
1141 __le32 serial[2];
1142 __le32 battery;
1143 __le32 options;
1144 __le32 OEM;
1145 };
1146
1147 struct aac_supplement_adapter_info
1148 {
1149 u8 AdapterTypeText[17+1];
1150 u8 Pad[2];
1151 __le32 FlashMemoryByteSize;
1152 __le32 FlashImageId;
1153 __le32 MaxNumberPorts;
1154 __le32 Version;
1155 __le32 FeatureBits;
1156 u8 SlotNumber;
1157 u8 ReservedPad0[3];
1158 u8 BuildDate[12];
1159 __le32 CurrentNumberPorts;
1160 struct {
1161 u8 AssemblyPn[8];
1162 u8 FruPn[8];
1163 u8 BatteryFruPn[8];
1164 u8 EcVersionString[8];
1165 u8 Tsid[12];
1166 } VpdInfo;
1167 __le32 FlashFirmwareRevision;
1168 __le32 FlashFirmwareBuild;
1169 __le32 RaidTypeMorphOptions;
1170 __le32 FlashFirmwareBootRevision;
1171 __le32 FlashFirmwareBootBuild;
1172 u8 MfgPcbaSerialNo[12];
1173 u8 MfgWWNName[8];
1174 __le32 SupportedOptions2;
1175 __le32 StructExpansion;
1176 /* StructExpansion == 1 */
1177 __le32 FeatureBits3;
1178 __le32 SupportedPerformanceModes;
1179 u8 HostBusType; /* uses HOST_BUS_TYPE_xxx defines */
1180 u8 HostBusWidth; /* actual width in bits or links */
1181 u16 HostBusSpeed; /* actual bus speed/link rate in MHz */
1182 u8 MaxRRCDrives; /* max. number of ITP-RRC drives/pool */
1183 u8 MaxDiskXtasks; /* max. possible num of DiskX Tasks */
1184
1185 u8 CpldVerLoaded;
1186 u8 CpldVerInFlash;
1187
1188 __le64 MaxRRCCapacity;
1189 __le32 CompiledMaxHistLogLevel;
1190 u8 CustomBoardName[12];
1191 u16 SupportedCntlrMode; /* identify supported controller mode */
1192 u16 ReservedForFuture16;
1193 __le32 SupportedOptions3; /* reserved for future options */
1194
1195 __le16 VirtDeviceBus; /* virt. SCSI device for Thor */
1196 __le16 VirtDeviceTarget;
1197 __le16 VirtDeviceLUN;
1198 __le16 Unused;
1199 __le32 ReservedForFutureGrowth[68];
1200
1201 };
1202 #define AAC_FEATURE_FALCON cpu_to_le32(0x00000010)
1203 #define AAC_FEATURE_JBOD cpu_to_le32(0x08000000)
1204 /* SupportedOptions2 */
1205 #define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001)
1206 #define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002)
1207 #define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004)
1208 #define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000)
1209 /* 4KB sector size */
1210 #define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000)
1211 /* 240 simple volume support */
1212 #define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000)
1213 #define AAC_SIS_VERSION_V3 3
1214 #define AAC_SIS_SLOT_UNKNOWN 0xFF
1215
1216 #define GetBusInfo 0x00000009
1217 struct aac_bus_info {
1218 __le32 Command; /* VM_Ioctl */
1219 __le32 ObjType; /* FT_DRIVE */
1220 __le32 MethodId; /* 1 = SCSI Layer */
1221 __le32 ObjectId; /* Handle */
1222 __le32 CtlCmd; /* GetBusInfo */
1223 };
1224
1225 struct aac_bus_info_response {
1226 __le32 Status; /* ST_OK */
1227 __le32 ObjType;
1228 __le32 MethodId; /* unused */
1229 __le32 ObjectId; /* unused */
1230 __le32 CtlCmd; /* unused */
1231 __le32 ProbeComplete;
1232 __le32 BusCount;
1233 __le32 TargetsPerBus;
1234 u8 InitiatorBusId[10];
1235 u8 BusValid[10];
1236 };
1237
1238 /*
1239 * Battery platforms
1240 */
1241 #define AAC_BAT_REQ_PRESENT (1)
1242 #define AAC_BAT_REQ_NOTPRESENT (2)
1243 #define AAC_BAT_OPT_PRESENT (3)
1244 #define AAC_BAT_OPT_NOTPRESENT (4)
1245 #define AAC_BAT_NOT_SUPPORTED (5)
1246 /*
1247 * cpu types
1248 */
1249 #define AAC_CPU_SIMULATOR (1)
1250 #define AAC_CPU_I960 (2)
1251 #define AAC_CPU_STRONGARM (3)
1252
1253 /*
1254 * Supported Options
1255 */
1256 #define AAC_OPT_SNAPSHOT cpu_to_le32(1)
1257 #define AAC_OPT_CLUSTERS cpu_to_le32(1<<1)
1258 #define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2)
1259 #define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3)
1260 #define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4)
1261 #define AAC_OPT_RAID50 cpu_to_le32(1<<5)
1262 #define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6)
1263 #define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7)
1264 #define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8)
1265 #define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9)
1266 #define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10)
1267 #define AAC_OPT_ALARM cpu_to_le32(1<<11)
1268 #define AAC_OPT_NONDASD cpu_to_le32(1<<12)
1269 #define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13)
1270 #define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14)
1271 #define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16)
1272 #define AAC_OPT_NEW_COMM cpu_to_le32(1<<17)
1273 #define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18)
1274 #define AAC_OPT_EXTENDED cpu_to_le32(1<<23)
1275 #define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28)
1276 #define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29)
1277 #define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30)
1278 #define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31)
1279
1280 #define AAC_COMM_PRODUCER 0
1281 #define AAC_COMM_MESSAGE 1
1282 #define AAC_COMM_MESSAGE_TYPE1 3
1283 #define AAC_COMM_MESSAGE_TYPE2 4
1284 #define AAC_COMM_MESSAGE_TYPE3 5
1285
1286 #define AAC_EXTOPT_SA_FIRMWARE cpu_to_le32(1<<1)
1287
1288 /* MSIX context */
1289 struct aac_msix_ctx {
1290 int vector_no;
1291 struct aac_dev *dev;
1292 };
1293
1294 struct aac_dev
1295 {
1296 struct list_head entry;
1297 const char *name;
1298 int id;
1299
1300 /*
1301 * negotiated FIB settings
1302 */
1303 unsigned int max_fib_size;
1304 unsigned int sg_tablesize;
1305 unsigned int max_num_aif;
1306
1307 unsigned int max_cmd_size; /* max_fib_size or MAX_NATIVE */
1308
1309 /*
1310 * Map for 128 fib objects (64k)
1311 */
1312 dma_addr_t hw_fib_pa;
1313 struct hw_fib *hw_fib_va;
1314 struct hw_fib *aif_base_va;
1315 /*
1316 * Fib Headers
1317 */
1318 struct fib *fibs;
1319
1320 struct fib *free_fib;
1321 spinlock_t fib_lock;
1322
1323 struct mutex ioctl_mutex;
1324 struct aac_queue_block *queues;
1325 /*
1326 * The user API will use an IOCTL to register itself to receive
1327 * FIBs from the adapter. The following list is used to keep
1328 * track of all the threads that have requested these FIBs. The
1329 * mutex is used to synchronize access to all data associated
1330 * with the adapter fibs.
1331 */
1332 struct list_head fib_list;
1333
1334 struct adapter_ops a_ops;
1335 unsigned long fsrev; /* Main driver's revision number */
1336
1337 resource_size_t base_start; /* main IO base */
1338 resource_size_t dbg_base; /* address of UART
1339 * debug buffer */
1340
1341 resource_size_t base_size, dbg_size; /* Size of
1342 * mapped in region */
1343 /*
1344 * Holds initialization info
1345 * to communicate with adapter
1346 */
1347 union aac_init *init;
1348 dma_addr_t init_pa; /* Holds physical address of the init struct */
1349 /* response queue (if AAC_COMM_MESSAGE_TYPE1) */
1350 __le32 *host_rrq;
1351 dma_addr_t host_rrq_pa; /* phys. address */
1352 /* index into rrq buffer */
1353 u32 host_rrq_idx[AAC_MAX_MSIX];
1354 atomic_t rrq_outstanding[AAC_MAX_MSIX];
1355 u32 fibs_pushed_no;
1356 struct pci_dev *pdev; /* Our PCI interface */
1357 /* pointer to buffer used for printf's from the adapter */
1358 void *printfbuf;
1359 void *comm_addr; /* Base address of Comm area */
1360 dma_addr_t comm_phys; /* Physical Address of Comm area */
1361 size_t comm_size;
1362
1363 struct Scsi_Host *scsi_host_ptr;
1364 int maximum_num_containers;
1365 int maximum_num_physicals;
1366 int maximum_num_channels;
1367 struct fsa_dev_info *fsa_dev;
1368 struct task_struct *thread;
1369 int cardtype;
1370 /*
1371 *This lock will protect the two 32-bit
1372 *writes to the Inbound Queue
1373 */
1374 spinlock_t iq_lock;
1375
1376 /*
1377 * The following is the device specific extension.
1378 */
1379 #ifndef AAC_MIN_FOOTPRINT_SIZE
1380 # define AAC_MIN_FOOTPRINT_SIZE 8192
1381 # define AAC_MIN_SRC_BAR0_SIZE 0x400000
1382 # define AAC_MIN_SRC_BAR1_SIZE 0x800
1383 # define AAC_MIN_SRCV_BAR0_SIZE 0x100000
1384 # define AAC_MIN_SRCV_BAR1_SIZE 0x400
1385 #endif
1386 union
1387 {
1388 struct sa_registers __iomem *sa;
1389 struct rx_registers __iomem *rx;
1390 struct rkt_registers __iomem *rkt;
1391 struct {
1392 struct src_registers __iomem *bar0;
1393 char __iomem *bar1;
1394 } src;
1395 } regs;
1396 volatile void __iomem *base, *dbg_base_mapped;
1397 volatile struct rx_inbound __iomem *IndexRegs;
1398 u32 OIMR; /* Mask Register Cache */
1399 /*
1400 * AIF thread states
1401 */
1402 u32 aif_thread;
1403 struct aac_adapter_info adapter_info;
1404 struct aac_supplement_adapter_info supplement_adapter_info;
1405 /* These are in adapter info but they are in the io flow so
1406 * lets break them out so we don't have to do an AND to check them
1407 */
1408 u8 nondasd_support;
1409 u8 jbod;
1410 u8 cache_protected;
1411 u8 dac_support;
1412 u8 needs_dac;
1413 u8 raid_scsi_mode;
1414 u8 comm_interface;
1415 u8 raw_io_interface;
1416 u8 raw_io_64;
1417 u8 printf_enabled;
1418 u8 in_reset;
1419 u8 msi;
1420 u8 sa_firmware;
1421 int management_fib_count;
1422 spinlock_t manage_lock;
1423 spinlock_t sync_lock;
1424 int sync_mode;
1425 struct fib *sync_fib;
1426 struct list_head sync_fib_list;
1427 u32 doorbell_mask;
1428 u32 max_msix; /* max. MSI-X vectors */
1429 u32 vector_cap; /* MSI-X vector capab.*/
1430 int msi_enabled; /* MSI/MSI-X enabled */
1431 atomic_t msix_counter;
1432 struct msix_entry msixentry[AAC_MAX_MSIX];
1433 struct aac_msix_ctx aac_msix[AAC_MAX_MSIX]; /* context */
1434 struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS];
1435 u8 adapter_shutdown;
1436 u32 handle_pci_error;
1437 };
1438
1439 #define aac_adapter_interrupt(dev) \
1440 (dev)->a_ops.adapter_interrupt(dev)
1441
1442 #define aac_adapter_notify(dev, event) \
1443 (dev)->a_ops.adapter_notify(dev, event)
1444
1445 #define aac_adapter_disable_int(dev) \
1446 (dev)->a_ops.adapter_disable_int(dev)
1447
1448 #define aac_adapter_enable_int(dev) \
1449 (dev)->a_ops.adapter_enable_int(dev)
1450
1451 #define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \
1452 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4)
1453
1454 #define aac_adapter_check_health(dev) \
1455 (dev)->a_ops.adapter_check_health(dev)
1456
1457 #define aac_adapter_restart(dev,bled) \
1458 (dev)->a_ops.adapter_restart(dev,bled)
1459
1460 #define aac_adapter_start(dev) \
1461 ((dev)->a_ops.adapter_start(dev))
1462
1463 #define aac_adapter_ioremap(dev, size) \
1464 (dev)->a_ops.adapter_ioremap(dev, size)
1465
1466 #define aac_adapter_deliver(fib) \
1467 ((fib)->dev)->a_ops.adapter_deliver(fib)
1468
1469 #define aac_adapter_bounds(dev,cmd,lba) \
1470 dev->a_ops.adapter_bounds(dev,cmd,lba)
1471
1472 #define aac_adapter_read(fib,cmd,lba,count) \
1473 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count)
1474
1475 #define aac_adapter_write(fib,cmd,lba,count,fua) \
1476 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua)
1477
1478 #define aac_adapter_scsi(fib,cmd) \
1479 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd)
1480
1481 #define aac_adapter_comm(dev,comm) \
1482 (dev)->a_ops.adapter_comm(dev, comm)
1483
1484 #define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001)
1485 #define FIB_CONTEXT_FLAG (0x00000002)
1486 #define FIB_CONTEXT_FLAG_WAIT (0x00000004)
1487 #define FIB_CONTEXT_FLAG_FASTRESP (0x00000008)
1488
1489 /*
1490 * Define the command values
1491 */
1492
1493 #define Null 0
1494 #define GetAttributes 1
1495 #define SetAttributes 2
1496 #define Lookup 3
1497 #define ReadLink 4
1498 #define Read 5
1499 #define Write 6
1500 #define Create 7
1501 #define MakeDirectory 8
1502 #define SymbolicLink 9
1503 #define MakeNode 10
1504 #define Removex 11
1505 #define RemoveDirectoryx 12
1506 #define Rename 13
1507 #define Link 14
1508 #define ReadDirectory 15
1509 #define ReadDirectoryPlus 16
1510 #define FileSystemStatus 17
1511 #define FileSystemInfo 18
1512 #define PathConfigure 19
1513 #define Commit 20
1514 #define Mount 21
1515 #define UnMount 22
1516 #define Newfs 23
1517 #define FsCheck 24
1518 #define FsSync 25
1519 #define SimReadWrite 26
1520 #define SetFileSystemStatus 27
1521 #define BlockRead 28
1522 #define BlockWrite 29
1523 #define NvramIoctl 30
1524 #define FsSyncWait 31
1525 #define ClearArchiveBit 32
1526 #define SetAcl 33
1527 #define GetAcl 34
1528 #define AssignAcl 35
1529 #define FaultInsertion 36 /* Fault Insertion Command */
1530 #define CrazyCache 37 /* Crazycache */
1531
1532 #define MAX_FSACOMMAND_NUM 38
1533
1534
1535 /*
1536 * Define the status returns. These are very unixlike although
1537 * most are not in fact used
1538 */
1539
1540 #define ST_OK 0
1541 #define ST_PERM 1
1542 #define ST_NOENT 2
1543 #define ST_IO 5
1544 #define ST_NXIO 6
1545 #define ST_E2BIG 7
1546 #define ST_MEDERR 8
1547 #define ST_ACCES 13
1548 #define ST_EXIST 17
1549 #define ST_XDEV 18
1550 #define ST_NODEV 19
1551 #define ST_NOTDIR 20
1552 #define ST_ISDIR 21
1553 #define ST_INVAL 22
1554 #define ST_FBIG 27
1555 #define ST_NOSPC 28
1556 #define ST_ROFS 30
1557 #define ST_MLINK 31
1558 #define ST_WOULDBLOCK 35
1559 #define ST_NAMETOOLONG 63
1560 #define ST_NOTEMPTY 66
1561 #define ST_DQUOT 69
1562 #define ST_STALE 70
1563 #define ST_REMOTE 71
1564 #define ST_NOT_READY 72
1565 #define ST_BADHANDLE 10001
1566 #define ST_NOT_SYNC 10002
1567 #define ST_BAD_COOKIE 10003
1568 #define ST_NOTSUPP 10004
1569 #define ST_TOOSMALL 10005
1570 #define ST_SERVERFAULT 10006
1571 #define ST_BADTYPE 10007
1572 #define ST_JUKEBOX 10008
1573 #define ST_NOTMOUNTED 10009
1574 #define ST_MAINTMODE 10010
1575 #define ST_STALEACL 10011
1576
1577 /*
1578 * On writes how does the client want the data written.
1579 */
1580
1581 #define CACHE_CSTABLE 1
1582 #define CACHE_UNSTABLE 2
1583
1584 /*
1585 * Lets the client know at which level the data was committed on
1586 * a write request
1587 */
1588
1589 #define CMFILE_SYNCH_NVRAM 1
1590 #define CMDATA_SYNCH_NVRAM 2
1591 #define CMFILE_SYNCH 3
1592 #define CMDATA_SYNCH 4
1593 #define CMUNSTABLE 5
1594
1595 #define RIO_TYPE_WRITE 0x0000
1596 #define RIO_TYPE_READ 0x0001
1597 #define RIO_SUREWRITE 0x0008
1598
1599 #define RIO2_IO_TYPE 0x0003
1600 #define RIO2_IO_TYPE_WRITE 0x0000
1601 #define RIO2_IO_TYPE_READ 0x0001
1602 #define RIO2_IO_TYPE_VERIFY 0x0002
1603 #define RIO2_IO_ERROR 0x0004
1604 #define RIO2_IO_SUREWRITE 0x0008
1605 #define RIO2_SGL_CONFORMANT 0x0010
1606 #define RIO2_SG_FORMAT 0xF000
1607 #define RIO2_SG_FORMAT_ARC 0x0000
1608 #define RIO2_SG_FORMAT_SRL 0x1000
1609 #define RIO2_SG_FORMAT_IEEE1212 0x2000
1610
1611 struct aac_read
1612 {
1613 __le32 command;
1614 __le32 cid;
1615 __le32 block;
1616 __le32 count;
1617 struct sgmap sg; // Must be last in struct because it is variable
1618 };
1619
1620 struct aac_read64
1621 {
1622 __le32 command;
1623 __le16 cid;
1624 __le16 sector_count;
1625 __le32 block;
1626 __le16 pad;
1627 __le16 flags;
1628 struct sgmap64 sg; // Must be last in struct because it is variable
1629 };
1630
1631 struct aac_read_reply
1632 {
1633 __le32 status;
1634 __le32 count;
1635 };
1636
1637 struct aac_write
1638 {
1639 __le32 command;
1640 __le32 cid;
1641 __le32 block;
1642 __le32 count;
1643 __le32 stable; // Not used
1644 struct sgmap sg; // Must be last in struct because it is variable
1645 };
1646
1647 struct aac_write64
1648 {
1649 __le32 command;
1650 __le16 cid;
1651 __le16 sector_count;
1652 __le32 block;
1653 __le16 pad;
1654 __le16 flags;
1655 struct sgmap64 sg; // Must be last in struct because it is variable
1656 };
1657 struct aac_write_reply
1658 {
1659 __le32 status;
1660 __le32 count;
1661 __le32 committed;
1662 };
1663
1664 struct aac_raw_io
1665 {
1666 __le32 block[2];
1667 __le32 count;
1668 __le16 cid;
1669 __le16 flags; /* 00 W, 01 R */
1670 __le16 bpTotal; /* reserved for F/W use */
1671 __le16 bpComplete; /* reserved for F/W use */
1672 struct sgmapraw sg;
1673 };
1674
1675 struct aac_raw_io2 {
1676 __le32 blockLow;
1677 __le32 blockHigh;
1678 __le32 byteCount;
1679 __le16 cid;
1680 __le16 flags; /* RIO2 flags */
1681 __le32 sgeFirstSize; /* size of first sge el. */
1682 __le32 sgeNominalSize; /* size of 2nd sge el. (if conformant) */
1683 u8 sgeCnt; /* only 8 bits required */
1684 u8 bpTotal; /* reserved for F/W use */
1685 u8 bpComplete; /* reserved for F/W use */
1686 u8 sgeFirstIndex; /* reserved for F/W use */
1687 u8 unused[4];
1688 struct sge_ieee1212 sge[1];
1689 };
1690
1691 #define CT_FLUSH_CACHE 129
1692 struct aac_synchronize {
1693 __le32 command; /* VM_ContainerConfig */
1694 __le32 type; /* CT_FLUSH_CACHE */
1695 __le32 cid;
1696 __le32 parm1;
1697 __le32 parm2;
1698 __le32 parm3;
1699 __le32 parm4;
1700 __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */
1701 };
1702
1703 struct aac_synchronize_reply {
1704 __le32 dummy0;
1705 __le32 dummy1;
1706 __le32 status; /* CT_OK */
1707 __le32 parm1;
1708 __le32 parm2;
1709 __le32 parm3;
1710 __le32 parm4;
1711 __le32 parm5;
1712 u8 data[16];
1713 };
1714
1715 #define CT_POWER_MANAGEMENT 245
1716 #define CT_PM_START_UNIT 2
1717 #define CT_PM_STOP_UNIT 3
1718 #define CT_PM_UNIT_IMMEDIATE 1
1719 struct aac_power_management {
1720 __le32 command; /* VM_ContainerConfig */
1721 __le32 type; /* CT_POWER_MANAGEMENT */
1722 __le32 sub; /* CT_PM_* */
1723 __le32 cid;
1724 __le32 parm; /* CT_PM_sub_* */
1725 };
1726
1727 #define CT_PAUSE_IO 65
1728 #define CT_RELEASE_IO 66
1729 struct aac_pause {
1730 __le32 command; /* VM_ContainerConfig */
1731 __le32 type; /* CT_PAUSE_IO */
1732 __le32 timeout; /* 10ms ticks */
1733 __le32 min;
1734 __le32 noRescan;
1735 __le32 parm3;
1736 __le32 parm4;
1737 __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */
1738 };
1739
1740 struct aac_srb
1741 {
1742 __le32 function;
1743 __le32 channel;
1744 __le32 id;
1745 __le32 lun;
1746 __le32 timeout;
1747 __le32 flags;
1748 __le32 count; // Data xfer size
1749 __le32 retry_limit;
1750 __le32 cdb_size;
1751 u8 cdb[16];
1752 struct sgmap sg;
1753 };
1754
1755 /*
1756 * This and associated data structs are used by the
1757 * ioctl caller and are in cpu order.
1758 */
1759 struct user_aac_srb
1760 {
1761 u32 function;
1762 u32 channel;
1763 u32 id;
1764 u32 lun;
1765 u32 timeout;
1766 u32 flags;
1767 u32 count; // Data xfer size
1768 u32 retry_limit;
1769 u32 cdb_size;
1770 u8 cdb[16];
1771 struct user_sgmap sg;
1772 };
1773
1774 #define AAC_SENSE_BUFFERSIZE 30
1775
1776 struct aac_srb_reply
1777 {
1778 __le32 status;
1779 __le32 srb_status;
1780 __le32 scsi_status;
1781 __le32 data_xfer_length;
1782 __le32 sense_data_size;
1783 u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE
1784 };
1785 /*
1786 * SRB Flags
1787 */
1788 #define SRB_NoDataXfer 0x0000
1789 #define SRB_DisableDisconnect 0x0004
1790 #define SRB_DisableSynchTransfer 0x0008
1791 #define SRB_BypassFrozenQueue 0x0010
1792 #define SRB_DisableAutosense 0x0020
1793 #define SRB_DataIn 0x0040
1794 #define SRB_DataOut 0x0080
1795
1796 /*
1797 * SRB Functions - set in aac_srb->function
1798 */
1799 #define SRBF_ExecuteScsi 0x0000
1800 #define SRBF_ClaimDevice 0x0001
1801 #define SRBF_IO_Control 0x0002
1802 #define SRBF_ReceiveEvent 0x0003
1803 #define SRBF_ReleaseQueue 0x0004
1804 #define SRBF_AttachDevice 0x0005
1805 #define SRBF_ReleaseDevice 0x0006
1806 #define SRBF_Shutdown 0x0007
1807 #define SRBF_Flush 0x0008
1808 #define SRBF_AbortCommand 0x0010
1809 #define SRBF_ReleaseRecovery 0x0011
1810 #define SRBF_ResetBus 0x0012
1811 #define SRBF_ResetDevice 0x0013
1812 #define SRBF_TerminateIO 0x0014
1813 #define SRBF_FlushQueue 0x0015
1814 #define SRBF_RemoveDevice 0x0016
1815 #define SRBF_DomainValidation 0x0017
1816
1817 /*
1818 * SRB SCSI Status - set in aac_srb->scsi_status
1819 */
1820 #define SRB_STATUS_PENDING 0x00
1821 #define SRB_STATUS_SUCCESS 0x01
1822 #define SRB_STATUS_ABORTED 0x02
1823 #define SRB_STATUS_ABORT_FAILED 0x03
1824 #define SRB_STATUS_ERROR 0x04
1825 #define SRB_STATUS_BUSY 0x05
1826 #define SRB_STATUS_INVALID_REQUEST 0x06
1827 #define SRB_STATUS_INVALID_PATH_ID 0x07
1828 #define SRB_STATUS_NO_DEVICE 0x08
1829 #define SRB_STATUS_TIMEOUT 0x09
1830 #define SRB_STATUS_SELECTION_TIMEOUT 0x0A
1831 #define SRB_STATUS_COMMAND_TIMEOUT 0x0B
1832 #define SRB_STATUS_MESSAGE_REJECTED 0x0D
1833 #define SRB_STATUS_BUS_RESET 0x0E
1834 #define SRB_STATUS_PARITY_ERROR 0x0F
1835 #define SRB_STATUS_REQUEST_SENSE_FAILED 0x10
1836 #define SRB_STATUS_NO_HBA 0x11
1837 #define SRB_STATUS_DATA_OVERRUN 0x12
1838 #define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13
1839 #define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14
1840 #define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15
1841 #define SRB_STATUS_REQUEST_FLUSHED 0x16
1842 #define SRB_STATUS_DELAYED_RETRY 0x17
1843 #define SRB_STATUS_INVALID_LUN 0x20
1844 #define SRB_STATUS_INVALID_TARGET_ID 0x21
1845 #define SRB_STATUS_BAD_FUNCTION 0x22
1846 #define SRB_STATUS_ERROR_RECOVERY 0x23
1847 #define SRB_STATUS_NOT_STARTED 0x24
1848 #define SRB_STATUS_NOT_IN_USE 0x30
1849 #define SRB_STATUS_FORCE_ABORT 0x31
1850 #define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32
1851
1852 /*
1853 * Object-Server / Volume-Manager Dispatch Classes
1854 */
1855
1856 #define VM_Null 0
1857 #define VM_NameServe 1
1858 #define VM_ContainerConfig 2
1859 #define VM_Ioctl 3
1860 #define VM_FilesystemIoctl 4
1861 #define VM_CloseAll 5
1862 #define VM_CtBlockRead 6
1863 #define VM_CtBlockWrite 7
1864 #define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */
1865 #define VM_SliceBlockWrite 9
1866 #define VM_DriveBlockRead 10 /* raw access to physical devices */
1867 #define VM_DriveBlockWrite 11
1868 #define VM_EnclosureMgt 12 /* enclosure management */
1869 #define VM_Unused 13 /* used to be diskset management */
1870 #define VM_CtBlockVerify 14
1871 #define VM_CtPerf 15 /* performance test */
1872 #define VM_CtBlockRead64 16
1873 #define VM_CtBlockWrite64 17
1874 #define VM_CtBlockVerify64 18
1875 #define VM_CtHostRead64 19
1876 #define VM_CtHostWrite64 20
1877 #define VM_DrvErrTblLog 21
1878 #define VM_NameServe64 22
1879 #define VM_NameServeAllBlk 30
1880
1881 #define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */
1882
1883 /*
1884 * Descriptive information (eg, vital stats)
1885 * that a content manager might report. The
1886 * FileArray filesystem component is one example
1887 * of a content manager. Raw mode might be
1888 * another.
1889 */
1890
1891 struct aac_fsinfo {
1892 __le32 fsTotalSize; /* Consumed by fs, incl. metadata */
1893 __le32 fsBlockSize;
1894 __le32 fsFragSize;
1895 __le32 fsMaxExtendSize;
1896 __le32 fsSpaceUnits;
1897 __le32 fsMaxNumFiles;
1898 __le32 fsNumFreeFiles;
1899 __le32 fsInodeDensity;
1900 }; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */
1901
1902 struct aac_blockdevinfo {
1903 __le32 block_size;
1904 };
1905
1906 union aac_contentinfo {
1907 struct aac_fsinfo filesys;
1908 struct aac_blockdevinfo bdevinfo;
1909 };
1910
1911 /*
1912 * Query for Container Configuration Status
1913 */
1914
1915 #define CT_GET_CONFIG_STATUS 147
1916 struct aac_get_config_status {
1917 __le32 command; /* VM_ContainerConfig */
1918 __le32 type; /* CT_GET_CONFIG_STATUS */
1919 __le32 parm1;
1920 __le32 parm2;
1921 __le32 parm3;
1922 __le32 parm4;
1923 __le32 parm5;
1924 __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */
1925 };
1926
1927 #define CFACT_CONTINUE 0
1928 #define CFACT_PAUSE 1
1929 #define CFACT_ABORT 2
1930 struct aac_get_config_status_resp {
1931 __le32 response; /* ST_OK */
1932 __le32 dummy0;
1933 __le32 status; /* CT_OK */
1934 __le32 parm1;
1935 __le32 parm2;
1936 __le32 parm3;
1937 __le32 parm4;
1938 __le32 parm5;
1939 struct {
1940 __le32 action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */
1941 __le16 flags;
1942 __le16 count;
1943 } data;
1944 };
1945
1946 /*
1947 * Accept the configuration as-is
1948 */
1949
1950 #define CT_COMMIT_CONFIG 152
1951
1952 struct aac_commit_config {
1953 __le32 command; /* VM_ContainerConfig */
1954 __le32 type; /* CT_COMMIT_CONFIG */
1955 };
1956
1957 /*
1958 * Query for Container Configuration Status
1959 */
1960
1961 #define CT_GET_CONTAINER_COUNT 4
1962 struct aac_get_container_count {
1963 __le32 command; /* VM_ContainerConfig */
1964 __le32 type; /* CT_GET_CONTAINER_COUNT */
1965 };
1966
1967 struct aac_get_container_count_resp {
1968 __le32 response; /* ST_OK */
1969 __le32 dummy0;
1970 __le32 MaxContainers;
1971 __le32 ContainerSwitchEntries;
1972 __le32 MaxPartitions;
1973 __le32 MaxSimpleVolumes;
1974 };
1975
1976
1977 /*
1978 * Query for "mountable" objects, ie, objects that are typically
1979 * associated with a drive letter on the client (host) side.
1980 */
1981
1982 struct aac_mntent {
1983 __le32 oid;
1984 u8 name[16]; /* if applicable */
1985 struct creation_info create_info; /* if applicable */
1986 __le32 capacity;
1987 __le32 vol; /* substrate structure */
1988 __le32 obj; /* FT_FILESYS, etc. */
1989 __le32 state; /* unready for mounting,
1990 readonly, etc. */
1991 union aac_contentinfo fileinfo; /* Info specific to content
1992 manager (eg, filesystem) */
1993 __le32 altoid; /* != oid <==> snapshot or
1994 broken mirror exists */
1995 __le32 capacityhigh;
1996 };
1997
1998 #define FSCS_NOTCLEAN 0x0001 /* fsck is necessary before mounting */
1999 #define FSCS_READONLY 0x0002 /* possible result of broken mirror */
2000 #define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */
2001 #define FSCS_NOT_READY 0x0008 /* Array spinning up to fulfil request */
2002
2003 struct aac_query_mount {
2004 __le32 command;
2005 __le32 type;
2006 __le32 count;
2007 };
2008
2009 struct aac_mount {
2010 __le32 status;
2011 __le32 type; /* should be same as that requested */
2012 __le32 count;
2013 struct aac_mntent mnt[1];
2014 };
2015
2016 #define CT_READ_NAME 130
2017 struct aac_get_name {
2018 __le32 command; /* VM_ContainerConfig */
2019 __le32 type; /* CT_READ_NAME */
2020 __le32 cid;
2021 __le32 parm1;
2022 __le32 parm2;
2023 __le32 parm3;
2024 __le32 parm4;
2025 __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */
2026 };
2027
2028 struct aac_get_name_resp {
2029 __le32 dummy0;
2030 __le32 dummy1;
2031 __le32 status; /* CT_OK */
2032 __le32 parm1;
2033 __le32 parm2;
2034 __le32 parm3;
2035 __le32 parm4;
2036 __le32 parm5;
2037 u8 data[16];
2038 };
2039
2040 #define CT_CID_TO_32BITS_UID 165
2041 struct aac_get_serial {
2042 __le32 command; /* VM_ContainerConfig */
2043 __le32 type; /* CT_CID_TO_32BITS_UID */
2044 __le32 cid;
2045 };
2046
2047 struct aac_get_serial_resp {
2048 __le32 dummy0;
2049 __le32 dummy1;
2050 __le32 status; /* CT_OK */
2051 __le32 uid;
2052 };
2053
2054 /*
2055 * The following command is sent to shut down each container.
2056 */
2057
2058 struct aac_close {
2059 __le32 command;
2060 __le32 cid;
2061 };
2062
2063 struct aac_query_disk
2064 {
2065 s32 cnum;
2066 s32 bus;
2067 s32 id;
2068 s32 lun;
2069 u32 valid;
2070 u32 locked;
2071 u32 deleted;
2072 s32 instance;
2073 s8 name[10];
2074 u32 unmapped;
2075 };
2076
2077 struct aac_delete_disk {
2078 u32 disknum;
2079 u32 cnum;
2080 };
2081
2082 struct fib_ioctl
2083 {
2084 u32 fibctx;
2085 s32 wait;
2086 char __user *fib;
2087 };
2088
2089 struct revision
2090 {
2091 u32 compat;
2092 __le32 version;
2093 __le32 build;
2094 };
2095
2096
2097 /*
2098 * Ugly - non Linux like ioctl coding for back compat.
2099 */
2100
2101 #define CTL_CODE(function, method) ( \
2102 (4<< 16) | ((function) << 2) | (method) \
2103 )
2104
2105 /*
2106 * Define the method codes for how buffers are passed for I/O and FS
2107 * controls
2108 */
2109
2110 #define METHOD_BUFFERED 0
2111 #define METHOD_NEITHER 3
2112
2113 /*
2114 * Filesystem ioctls
2115 */
2116
2117 #define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED)
2118 #define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED)
2119 #define FSACTL_DELETE_DISK 0x163
2120 #define FSACTL_QUERY_DISK 0x173
2121 #define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED)
2122 #define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED)
2123 #define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED)
2124 #define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED)
2125 #define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED)
2126 #define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER)
2127 #define FSACTL_GET_CONTAINERS 2131
2128 #define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED)
2129
2130
2131 struct aac_common
2132 {
2133 /*
2134 * If this value is set to 1 then interrupt moderation will occur
2135 * in the base commuication support.
2136 */
2137 u32 irq_mod;
2138 u32 peak_fibs;
2139 u32 zero_fibs;
2140 u32 fib_timeouts;
2141 /*
2142 * Statistical counters in debug mode
2143 */
2144 #ifdef DBG
2145 u32 FibsSent;
2146 u32 FibRecved;
2147 u32 NoResponseSent;
2148 u32 NoResponseRecved;
2149 u32 AsyncSent;
2150 u32 AsyncRecved;
2151 u32 NormalSent;
2152 u32 NormalRecved;
2153 #endif
2154 };
2155
2156 extern struct aac_common aac_config;
2157
2158
2159 /*
2160 * The following macro is used when sending and receiving FIBs. It is
2161 * only used for debugging.
2162 */
2163
2164 #ifdef DBG
2165 #define FIB_COUNTER_INCREMENT(counter) (counter)++
2166 #else
2167 #define FIB_COUNTER_INCREMENT(counter)
2168 #endif
2169
2170 /*
2171 * Adapter direct commands
2172 * Monitor/Kernel API
2173 */
2174
2175 #define BREAKPOINT_REQUEST 0x00000004
2176 #define INIT_STRUCT_BASE_ADDRESS 0x00000005
2177 #define READ_PERMANENT_PARAMETERS 0x0000000a
2178 #define WRITE_PERMANENT_PARAMETERS 0x0000000b
2179 #define HOST_CRASHING 0x0000000d
2180 #define SEND_SYNCHRONOUS_FIB 0x0000000c
2181 #define COMMAND_POST_RESULTS 0x00000014
2182 #define GET_ADAPTER_PROPERTIES 0x00000019
2183 #define GET_DRIVER_BUFFER_PROPERTIES 0x00000023
2184 #define RCV_TEMP_READINGS 0x00000025
2185 #define GET_COMM_PREFERRED_SETTINGS 0x00000026
2186 #define IOP_RESET 0x00001000
2187 #define IOP_RESET_ALWAYS 0x00001001
2188 #define RE_INIT_ADAPTER 0x000000ee
2189
2190 /*
2191 * Adapter Status Register
2192 *
2193 * Phase Staus mailbox is 32bits:
2194 * <31:16> = Phase Status
2195 * <15:0> = Phase
2196 *
2197 * The adapter reports is present state through the phase. Only
2198 * a single phase should be ever be set. Each phase can have multiple
2199 * phase status bits to provide more detailed information about the
2200 * state of the board. Care should be taken to ensure that any phase
2201 * status bits that are set when changing the phase are also valid
2202 * for the new phase or be cleared out. Adapter software (monitor,
2203 * iflash, kernel) is responsible for properly maintining the phase
2204 * status mailbox when it is running.
2205 *
2206 * MONKER_API Phases
2207 *
2208 * Phases are bit oriented. It is NOT valid to have multiple bits set
2209 */
2210
2211 #define SELF_TEST_FAILED 0x00000004
2212 #define MONITOR_PANIC 0x00000020
2213 #define KERNEL_UP_AND_RUNNING 0x00000080
2214 #define KERNEL_PANIC 0x00000100
2215 #define FLASH_UPD_PENDING 0x00002000
2216 #define FLASH_UPD_SUCCESS 0x00004000
2217 #define FLASH_UPD_FAILED 0x00008000
2218 #define FWUPD_TIMEOUT (5 * 60)
2219
2220 /*
2221 * Doorbell bit defines
2222 */
2223
2224 #define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */
2225 #define DoorBellPrintfDone (1<<5) /* Host -> Adapter */
2226 #define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */
2227 #define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */
2228 #define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */
2229 #define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */
2230 #define DoorBellPrintfReady (1<<5) /* Adapter -> Host */
2231 #define DoorBellAifPending (1<<6) /* Adapter -> Host */
2232
2233 /* PMC specific outbound doorbell bits */
2234 #define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */
2235
2236 /*
2237 * For FIB communication, we need all of the following things
2238 * to send back to the user.
2239 */
2240
2241 #define AifCmdEventNotify 1 /* Notify of event */
2242 #define AifEnConfigChange 3 /* Adapter configuration change */
2243 #define AifEnContainerChange 4 /* Container configuration change */
2244 #define AifEnDeviceFailure 5 /* SCSI device failed */
2245 #define AifEnEnclosureManagement 13 /* EM_DRIVE_* */
2246 #define EM_DRIVE_INSERTION 31
2247 #define EM_DRIVE_REMOVAL 32
2248 #define EM_SES_DRIVE_INSERTION 33
2249 #define EM_SES_DRIVE_REMOVAL 26
2250 #define AifEnBatteryEvent 14 /* Change in Battery State */
2251 #define AifEnAddContainer 15 /* A new array was created */
2252 #define AifEnDeleteContainer 16 /* A container was deleted */
2253 #define AifEnExpEvent 23 /* Firmware Event Log */
2254 #define AifExeFirmwarePanic 3 /* Firmware Event Panic */
2255 #define AifHighPriority 3 /* Highest Priority Event */
2256 #define AifEnAddJBOD 30 /* JBOD created */
2257 #define AifEnDeleteJBOD 31 /* JBOD deleted */
2258
2259 #define AifBuManagerEvent 42 /* Bu management*/
2260 #define AifBuCacheDataLoss 10
2261 #define AifBuCacheDataRecover 11
2262
2263 #define AifCmdJobProgress 2 /* Progress report */
2264 #define AifJobCtrZero 101 /* Array Zero progress */
2265 #define AifJobStsSuccess 1 /* Job completes */
2266 #define AifJobStsRunning 102 /* Job running */
2267 #define AifCmdAPIReport 3 /* Report from other user of API */
2268 #define AifCmdDriverNotify 4 /* Notify host driver of event */
2269 #define AifDenMorphComplete 200 /* A morph operation completed */
2270 #define AifDenVolumeExtendComplete 201 /* A volume extend completed */
2271 #define AifReqJobList 100 /* Gets back complete job list */
2272 #define AifReqJobsForCtr 101 /* Gets back jobs for specific container */
2273 #define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */
2274 #define AifReqJobReport 103 /* Gets back a specific job report or list of them */
2275 #define AifReqTerminateJob 104 /* Terminates job */
2276 #define AifReqSuspendJob 105 /* Suspends a job */
2277 #define AifReqResumeJob 106 /* Resumes a job */
2278 #define AifReqSendAPIReport 107 /* API generic report requests */
2279 #define AifReqAPIJobStart 108 /* Start a job from the API */
2280 #define AifReqAPIJobUpdate 109 /* Update a job report from the API */
2281 #define AifReqAPIJobFinish 110 /* Finish a job from the API */
2282
2283 /* PMC NEW COMM: Request the event data */
2284 #define AifReqEvent 200
2285
2286 /* RAW device deleted */
2287 #define AifRawDeviceRemove 203
2288
2289 /*
2290 * Adapter Initiated FIB command structures. Start with the adapter
2291 * initiated FIBs that really come from the adapter, and get responded
2292 * to by the host.
2293 */
2294
2295 struct aac_aifcmd {
2296 __le32 command; /* Tell host what type of notify this is */
2297 __le32 seqnum; /* To allow ordering of reports (if necessary) */
2298 u8 data[1]; /* Undefined length (from kernel viewpoint) */
2299 };
2300
2301 /**
2302 * Convert capacity to cylinders
2303 * accounting for the fact capacity could be a 64 bit value
2304 *
2305 */
2306 static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor)
2307 {
2308 sector_div(capacity, divisor);
2309 return capacity;
2310 }
2311
2312 /* SCp.phase values */
2313 #define AAC_OWNER_MIDLEVEL 0x101
2314 #define AAC_OWNER_LOWLEVEL 0x102
2315 #define AAC_OWNER_ERROR_HANDLER 0x103
2316 #define AAC_OWNER_FIRMWARE 0x106
2317
2318 int aac_acquire_irq(struct aac_dev *dev);
2319 void aac_free_irq(struct aac_dev *dev);
2320 int aac_report_phys_luns(struct aac_dev *dev, struct fib *fibptr);
2321 int aac_issue_bmic_identify(struct aac_dev *dev, u32 bus, u32 target);
2322 const char *aac_driverinfo(struct Scsi_Host *);
2323 void aac_fib_vector_assign(struct aac_dev *dev);
2324 struct fib *aac_fib_alloc(struct aac_dev *dev);
2325 struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd);
2326 int aac_fib_setup(struct aac_dev *dev);
2327 void aac_fib_map_free(struct aac_dev *dev);
2328 void aac_fib_free(struct fib * context);
2329 void aac_fib_init(struct fib * context);
2330 void aac_printf(struct aac_dev *dev, u32 val);
2331 int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt);
2332 int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry);
2333 void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum);
2334 int aac_fib_complete(struct fib * context);
2335 #define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data)
2336 struct aac_dev *aac_init_adapter(struct aac_dev *dev);
2337 void aac_src_access_devreg(struct aac_dev *dev, int mode);
2338 int aac_get_config_status(struct aac_dev *dev, int commit_flag);
2339 int aac_get_containers(struct aac_dev *dev);
2340 int aac_scsi_cmd(struct scsi_cmnd *cmd);
2341 int aac_dev_ioctl(struct aac_dev *dev, int cmd, void __user *arg);
2342 #ifndef shost_to_class
2343 #define shost_to_class(shost) &shost->shost_dev
2344 #endif
2345 ssize_t aac_get_serial_number(struct device *dev, char *buf);
2346 int aac_do_ioctl(struct aac_dev * dev, int cmd, void __user *arg);
2347 int aac_rx_init(struct aac_dev *dev);
2348 int aac_rkt_init(struct aac_dev *dev);
2349 int aac_nark_init(struct aac_dev *dev);
2350 int aac_sa_init(struct aac_dev *dev);
2351 int aac_src_init(struct aac_dev *dev);
2352 int aac_srcv_init(struct aac_dev *dev);
2353 int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify);
2354 void aac_define_int_mode(struct aac_dev *dev);
2355 unsigned int aac_response_normal(struct aac_queue * q);
2356 unsigned int aac_command_normal(struct aac_queue * q);
2357 unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index,
2358 int isAif, int isFastResponse,
2359 struct hw_fib *aif_fib);
2360 int aac_reset_adapter(struct aac_dev * dev, int forced);
2361 int aac_check_health(struct aac_dev * dev);
2362 int aac_command_thread(void *data);
2363 int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx);
2364 int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size);
2365 struct aac_driver_ident* aac_get_driver_ident(int devtype);
2366 int aac_get_adapter_info(struct aac_dev* dev);
2367 int aac_send_shutdown(struct aac_dev *dev);
2368 int aac_probe_container(struct aac_dev *dev, int cid);
2369 int _aac_rx_init(struct aac_dev *dev);
2370 int aac_rx_select_comm(struct aac_dev *dev, int comm);
2371 int aac_rx_deliver_producer(struct fib * fib);
2372 char * get_container_type(unsigned type);
2373 extern int numacb;
2374 extern char aac_driver_version[];
2375 extern int startup_timeout;
2376 extern int aif_timeout;
2377 extern int expose_physicals;
2378 extern int aac_reset_devices;
2379 extern int aac_msi;
2380 extern int aac_commit;
2381 extern int update_interval;
2382 extern int check_interval;
2383 extern int aac_check_reset;
2384 #endif
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