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scsi: aacraid: Skip IOP reset on controller panic(SMART Family)
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / aacraid / src.c
1 /*
2 * Adaptec AAC series RAID controller driver
3 * (c) Copyright 2001 Red Hat Inc.
4 *
5 * based on the old aacraid driver that is..
6 * Adaptec aacraid device driver for Linux.
7 *
8 * Copyright (c) 2000-2010 Adaptec, Inc.
9 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
10 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Module Name:
27 * src.c
28 *
29 * Abstract: Hardware Device Interface for PMC SRC based controllers
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/types.h>
36 #include <linux/pci.h>
37 #include <linux/spinlock.h>
38 #include <linux/slab.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/completion.h>
42 #include <linux/time.h>
43 #include <linux/interrupt.h>
44 #include <scsi/scsi_host.h>
45
46 #include "aacraid.h"
47
48 static int aac_src_get_sync_status(struct aac_dev *dev);
49
50 static irqreturn_t aac_src_intr_message(int irq, void *dev_id)
51 {
52 struct aac_msix_ctx *ctx;
53 struct aac_dev *dev;
54 unsigned long bellbits, bellbits_shifted;
55 int vector_no;
56 int isFastResponse, mode;
57 u32 index, handle;
58
59 ctx = (struct aac_msix_ctx *)dev_id;
60 dev = ctx->dev;
61 vector_no = ctx->vector_no;
62
63 if (dev->msi_enabled) {
64 mode = AAC_INT_MODE_MSI;
65 if (vector_no == 0) {
66 bellbits = src_readl(dev, MUnit.ODR_MSI);
67 if (bellbits & 0x40000)
68 mode |= AAC_INT_MODE_AIF;
69 if (bellbits & 0x1000)
70 mode |= AAC_INT_MODE_SYNC;
71 }
72 } else {
73 mode = AAC_INT_MODE_INTX;
74 bellbits = src_readl(dev, MUnit.ODR_R);
75 if (bellbits & PmDoorBellResponseSent) {
76 bellbits = PmDoorBellResponseSent;
77 src_writel(dev, MUnit.ODR_C, bellbits);
78 src_readl(dev, MUnit.ODR_C);
79 } else {
80 bellbits_shifted = (bellbits >> SRC_ODR_SHIFT);
81 src_writel(dev, MUnit.ODR_C, bellbits);
82 src_readl(dev, MUnit.ODR_C);
83
84 if (bellbits_shifted & DoorBellAifPending)
85 mode |= AAC_INT_MODE_AIF;
86 else if (bellbits_shifted & OUTBOUNDDOORBELL_0)
87 mode |= AAC_INT_MODE_SYNC;
88 }
89 }
90
91 if (mode & AAC_INT_MODE_SYNC) {
92 unsigned long sflags;
93 struct list_head *entry;
94 int send_it = 0;
95 extern int aac_sync_mode;
96
97 if (!aac_sync_mode && !dev->msi_enabled) {
98 src_writel(dev, MUnit.ODR_C, bellbits);
99 src_readl(dev, MUnit.ODR_C);
100 }
101
102 if (dev->sync_fib) {
103 if (dev->sync_fib->callback)
104 dev->sync_fib->callback(dev->sync_fib->callback_data,
105 dev->sync_fib);
106 spin_lock_irqsave(&dev->sync_fib->event_lock, sflags);
107 if (dev->sync_fib->flags & FIB_CONTEXT_FLAG_WAIT) {
108 dev->management_fib_count--;
109 up(&dev->sync_fib->event_wait);
110 }
111 spin_unlock_irqrestore(&dev->sync_fib->event_lock,
112 sflags);
113 spin_lock_irqsave(&dev->sync_lock, sflags);
114 if (!list_empty(&dev->sync_fib_list)) {
115 entry = dev->sync_fib_list.next;
116 dev->sync_fib = list_entry(entry,
117 struct fib,
118 fiblink);
119 list_del(entry);
120 send_it = 1;
121 } else {
122 dev->sync_fib = NULL;
123 }
124 spin_unlock_irqrestore(&dev->sync_lock, sflags);
125 if (send_it) {
126 aac_adapter_sync_cmd(dev, SEND_SYNCHRONOUS_FIB,
127 (u32)dev->sync_fib->hw_fib_pa,
128 0, 0, 0, 0, 0,
129 NULL, NULL, NULL, NULL, NULL);
130 }
131 }
132 if (!dev->msi_enabled)
133 mode = 0;
134
135 }
136
137 if (mode & AAC_INT_MODE_AIF) {
138 /* handle AIF */
139 if (dev->sa_firmware) {
140 u32 events = src_readl(dev, MUnit.SCR0);
141
142 aac_intr_normal(dev, events, 1, 0, NULL);
143 writel(events, &dev->IndexRegs->Mailbox[0]);
144 src_writel(dev, MUnit.IDR, 1 << 23);
145 } else {
146 if (dev->aif_thread && dev->fsa_dev)
147 aac_intr_normal(dev, 0, 2, 0, NULL);
148 }
149 if (dev->msi_enabled)
150 aac_src_access_devreg(dev, AAC_CLEAR_AIF_BIT);
151 mode = 0;
152 }
153
154 if (mode) {
155 index = dev->host_rrq_idx[vector_no];
156
157 for (;;) {
158 isFastResponse = 0;
159 /* remove toggle bit (31) */
160 handle = le32_to_cpu((dev->host_rrq[index])
161 & 0x7fffffff);
162 /* check fast response bits (30, 1) */
163 if (handle & 0x40000000)
164 isFastResponse = 1;
165 handle &= 0x0000ffff;
166 if (handle == 0)
167 break;
168 handle >>= 2;
169 if (dev->msi_enabled && dev->max_msix > 1)
170 atomic_dec(&dev->rrq_outstanding[vector_no]);
171 aac_intr_normal(dev, handle, 0, isFastResponse, NULL);
172 dev->host_rrq[index++] = 0;
173 if (index == (vector_no + 1) * dev->vector_cap)
174 index = vector_no * dev->vector_cap;
175 dev->host_rrq_idx[vector_no] = index;
176 }
177 mode = 0;
178 }
179
180 return IRQ_HANDLED;
181 }
182
183 /**
184 * aac_src_disable_interrupt - Disable interrupts
185 * @dev: Adapter
186 */
187
188 static void aac_src_disable_interrupt(struct aac_dev *dev)
189 {
190 src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff);
191 }
192
193 /**
194 * aac_src_enable_interrupt_message - Enable interrupts
195 * @dev: Adapter
196 */
197
198 static void aac_src_enable_interrupt_message(struct aac_dev *dev)
199 {
200 aac_src_access_devreg(dev, AAC_ENABLE_INTERRUPT);
201 }
202
203 /**
204 * src_sync_cmd - send a command and wait
205 * @dev: Adapter
206 * @command: Command to execute
207 * @p1: first parameter
208 * @ret: adapter status
209 *
210 * This routine will send a synchronous command to the adapter and wait
211 * for its completion.
212 */
213
214 static int src_sync_cmd(struct aac_dev *dev, u32 command,
215 u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6,
216 u32 *status, u32 * r1, u32 * r2, u32 * r3, u32 * r4)
217 {
218 unsigned long start;
219 unsigned long delay;
220 int ok;
221
222 /*
223 * Write the command into Mailbox 0
224 */
225 writel(command, &dev->IndexRegs->Mailbox[0]);
226 /*
227 * Write the parameters into Mailboxes 1 - 6
228 */
229 writel(p1, &dev->IndexRegs->Mailbox[1]);
230 writel(p2, &dev->IndexRegs->Mailbox[2]);
231 writel(p3, &dev->IndexRegs->Mailbox[3]);
232 writel(p4, &dev->IndexRegs->Mailbox[4]);
233
234 /*
235 * Clear the synch command doorbell to start on a clean slate.
236 */
237 if (!dev->msi_enabled)
238 src_writel(dev,
239 MUnit.ODR_C,
240 OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
241
242 /*
243 * Disable doorbell interrupts
244 */
245 src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff);
246
247 /*
248 * Force the completion of the mask register write before issuing
249 * the interrupt.
250 */
251 src_readl(dev, MUnit.OIMR);
252
253 /*
254 * Signal that there is a new synch command
255 */
256 src_writel(dev, MUnit.IDR, INBOUNDDOORBELL_0 << SRC_IDR_SHIFT);
257
258 if (!dev->sync_mode || command != SEND_SYNCHRONOUS_FIB) {
259 ok = 0;
260 start = jiffies;
261
262 if (command == IOP_RESET_ALWAYS) {
263 /* Wait up to 10 sec */
264 delay = 10*HZ;
265 } else {
266 /* Wait up to 5 minutes */
267 delay = 300*HZ;
268 }
269 while (time_before(jiffies, start+delay)) {
270 udelay(5); /* Delay 5 microseconds to let Mon960 get info. */
271 /*
272 * Mon960 will set doorbell0 bit when it has completed the command.
273 */
274 if (aac_src_get_sync_status(dev) & OUTBOUNDDOORBELL_0) {
275 /*
276 * Clear the doorbell.
277 */
278 if (dev->msi_enabled)
279 aac_src_access_devreg(dev,
280 AAC_CLEAR_SYNC_BIT);
281 else
282 src_writel(dev,
283 MUnit.ODR_C,
284 OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
285 ok = 1;
286 break;
287 }
288 /*
289 * Yield the processor in case we are slow
290 */
291 msleep(1);
292 }
293 if (unlikely(ok != 1)) {
294 /*
295 * Restore interrupt mask even though we timed out
296 */
297 aac_adapter_enable_int(dev);
298 return -ETIMEDOUT;
299 }
300 /*
301 * Pull the synch status from Mailbox 0.
302 */
303 if (status)
304 *status = readl(&dev->IndexRegs->Mailbox[0]);
305 if (r1)
306 *r1 = readl(&dev->IndexRegs->Mailbox[1]);
307 if (r2)
308 *r2 = readl(&dev->IndexRegs->Mailbox[2]);
309 if (r3)
310 *r3 = readl(&dev->IndexRegs->Mailbox[3]);
311 if (r4)
312 *r4 = readl(&dev->IndexRegs->Mailbox[4]);
313 if (command == GET_COMM_PREFERRED_SETTINGS)
314 dev->max_msix =
315 readl(&dev->IndexRegs->Mailbox[5]) & 0xFFFF;
316 /*
317 * Clear the synch command doorbell.
318 */
319 if (!dev->msi_enabled)
320 src_writel(dev,
321 MUnit.ODR_C,
322 OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
323 }
324
325 /*
326 * Restore interrupt mask
327 */
328 aac_adapter_enable_int(dev);
329 return 0;
330 }
331
332 /**
333 * aac_src_interrupt_adapter - interrupt adapter
334 * @dev: Adapter
335 *
336 * Send an interrupt to the i960 and breakpoint it.
337 */
338
339 static void aac_src_interrupt_adapter(struct aac_dev *dev)
340 {
341 src_sync_cmd(dev, BREAKPOINT_REQUEST,
342 0, 0, 0, 0, 0, 0,
343 NULL, NULL, NULL, NULL, NULL);
344 }
345
346 /**
347 * aac_src_notify_adapter - send an event to the adapter
348 * @dev: Adapter
349 * @event: Event to send
350 *
351 * Notify the i960 that something it probably cares about has
352 * happened.
353 */
354
355 static void aac_src_notify_adapter(struct aac_dev *dev, u32 event)
356 {
357 switch (event) {
358
359 case AdapNormCmdQue:
360 src_writel(dev, MUnit.ODR_C,
361 INBOUNDDOORBELL_1 << SRC_ODR_SHIFT);
362 break;
363 case HostNormRespNotFull:
364 src_writel(dev, MUnit.ODR_C,
365 INBOUNDDOORBELL_4 << SRC_ODR_SHIFT);
366 break;
367 case AdapNormRespQue:
368 src_writel(dev, MUnit.ODR_C,
369 INBOUNDDOORBELL_2 << SRC_ODR_SHIFT);
370 break;
371 case HostNormCmdNotFull:
372 src_writel(dev, MUnit.ODR_C,
373 INBOUNDDOORBELL_3 << SRC_ODR_SHIFT);
374 break;
375 case FastIo:
376 src_writel(dev, MUnit.ODR_C,
377 INBOUNDDOORBELL_6 << SRC_ODR_SHIFT);
378 break;
379 case AdapPrintfDone:
380 src_writel(dev, MUnit.ODR_C,
381 INBOUNDDOORBELL_5 << SRC_ODR_SHIFT);
382 break;
383 default:
384 BUG();
385 break;
386 }
387 }
388
389 /**
390 * aac_src_start_adapter - activate adapter
391 * @dev: Adapter
392 *
393 * Start up processing on an i960 based AAC adapter
394 */
395
396 static void aac_src_start_adapter(struct aac_dev *dev)
397 {
398 union aac_init *init;
399 int i;
400
401 /* reset host_rrq_idx first */
402 for (i = 0; i < dev->max_msix; i++) {
403 dev->host_rrq_idx[i] = i * dev->vector_cap;
404 atomic_set(&dev->rrq_outstanding[i], 0);
405 }
406 atomic_set(&dev->msix_counter, 0);
407 dev->fibs_pushed_no = 0;
408
409 init = dev->init;
410 if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE3) {
411 init->r8.host_elapsed_seconds = cpu_to_le32(get_seconds());
412 src_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS,
413 lower_32_bits(dev->init_pa),
414 upper_32_bits(dev->init_pa),
415 sizeof(struct _r8) +
416 (AAC_MAX_HRRQ - 1) * sizeof(struct _rrq),
417 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
418 } else {
419 init->r7.host_elapsed_seconds = cpu_to_le32(get_seconds());
420 // We can only use a 32 bit address here
421 src_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS,
422 (u32)(ulong)dev->init_pa, 0, 0, 0, 0, 0,
423 NULL, NULL, NULL, NULL, NULL);
424 }
425
426 }
427
428 /**
429 * aac_src_check_health
430 * @dev: device to check if healthy
431 *
432 * Will attempt to determine if the specified adapter is alive and
433 * capable of handling requests, returning 0 if alive.
434 */
435 static int aac_src_check_health(struct aac_dev *dev)
436 {
437 u32 status = src_readl(dev, MUnit.OMR);
438
439 /*
440 * Check to see if the board failed any self tests.
441 */
442 if (unlikely(status & SELF_TEST_FAILED))
443 return -1;
444
445 /*
446 * Check to see if the board panic'd.
447 */
448 if (unlikely(status & KERNEL_PANIC))
449 return (status >> 16) & 0xFF;
450 /*
451 * Wait for the adapter to be up and running.
452 */
453 if (unlikely(!(status & KERNEL_UP_AND_RUNNING)))
454 return -3;
455 /*
456 * Everything is OK
457 */
458 return 0;
459 }
460
461 static inline u32 aac_get_vector(struct aac_dev *dev)
462 {
463 return atomic_inc_return(&dev->msix_counter)%dev->max_msix;
464 }
465
466 /**
467 * aac_src_deliver_message
468 * @fib: fib to issue
469 *
470 * Will send a fib, returning 0 if successful.
471 */
472 static int aac_src_deliver_message(struct fib *fib)
473 {
474 struct aac_dev *dev = fib->dev;
475 struct aac_queue *q = &dev->queues->queue[AdapNormCmdQueue];
476 u32 fibsize;
477 dma_addr_t address;
478 struct aac_fib_xporthdr *pFibX;
479 int native_hba;
480 #if !defined(writeq)
481 unsigned long flags;
482 #endif
483
484 u16 vector_no;
485
486 atomic_inc(&q->numpending);
487
488 native_hba = (fib->flags & FIB_CONTEXT_FLAG_NATIVE_HBA) ? 1 : 0;
489
490
491 if (dev->msi_enabled && dev->max_msix > 1 &&
492 (native_hba || fib->hw_fib_va->header.Command != AifRequest)) {
493
494 if ((dev->comm_interface == AAC_COMM_MESSAGE_TYPE3)
495 && dev->sa_firmware)
496 vector_no = aac_get_vector(dev);
497 else
498 vector_no = fib->vector_no;
499
500 if (native_hba) {
501 if (fib->flags & FIB_CONTEXT_FLAG_NATIVE_HBA_TMF) {
502 struct aac_hba_tm_req *tm_req;
503
504 tm_req = (struct aac_hba_tm_req *)
505 fib->hw_fib_va;
506 if (tm_req->iu_type ==
507 HBA_IU_TYPE_SCSI_TM_REQ) {
508 ((struct aac_hba_tm_req *)
509 fib->hw_fib_va)->reply_qid
510 = vector_no;
511 ((struct aac_hba_tm_req *)
512 fib->hw_fib_va)->request_id
513 += (vector_no << 16);
514 } else {
515 ((struct aac_hba_reset_req *)
516 fib->hw_fib_va)->reply_qid
517 = vector_no;
518 ((struct aac_hba_reset_req *)
519 fib->hw_fib_va)->request_id
520 += (vector_no << 16);
521 }
522 } else {
523 ((struct aac_hba_cmd_req *)
524 fib->hw_fib_va)->reply_qid
525 = vector_no;
526 ((struct aac_hba_cmd_req *)
527 fib->hw_fib_va)->request_id
528 += (vector_no << 16);
529 }
530 } else {
531 fib->hw_fib_va->header.Handle += (vector_no << 16);
532 }
533 } else {
534 vector_no = 0;
535 }
536
537 atomic_inc(&dev->rrq_outstanding[vector_no]);
538
539 if (native_hba) {
540 address = fib->hw_fib_pa;
541 fibsize = (fib->hbacmd_size + 127) / 128 - 1;
542 if (fibsize > 31)
543 fibsize = 31;
544 address |= fibsize;
545 #if defined(writeq)
546 src_writeq(dev, MUnit.IQN_L, (u64)address);
547 #else
548 spin_lock_irqsave(&fib->dev->iq_lock, flags);
549 src_writel(dev, MUnit.IQN_H,
550 upper_32_bits(address) & 0xffffffff);
551 src_writel(dev, MUnit.IQN_L, address & 0xffffffff);
552 spin_unlock_irqrestore(&fib->dev->iq_lock, flags);
553 #endif
554 } else {
555 if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2 ||
556 dev->comm_interface == AAC_COMM_MESSAGE_TYPE3) {
557 /* Calculate the amount to the fibsize bits */
558 fibsize = (le16_to_cpu(fib->hw_fib_va->header.Size)
559 + 127) / 128 - 1;
560 /* New FIB header, 32-bit */
561 address = fib->hw_fib_pa;
562 fib->hw_fib_va->header.StructType = FIB_MAGIC2;
563 fib->hw_fib_va->header.SenderFibAddress =
564 cpu_to_le32((u32)address);
565 fib->hw_fib_va->header.u.TimeStamp = 0;
566 WARN_ON(upper_32_bits(address) != 0L);
567 } else {
568 /* Calculate the amount to the fibsize bits */
569 fibsize = (sizeof(struct aac_fib_xporthdr) +
570 le16_to_cpu(fib->hw_fib_va->header.Size)
571 + 127) / 128 - 1;
572 /* Fill XPORT header */
573 pFibX = (struct aac_fib_xporthdr *)
574 ((unsigned char *)fib->hw_fib_va -
575 sizeof(struct aac_fib_xporthdr));
576 pFibX->Handle = fib->hw_fib_va->header.Handle;
577 pFibX->HostAddress =
578 cpu_to_le64((u64)fib->hw_fib_pa);
579 pFibX->Size = cpu_to_le32(
580 le16_to_cpu(fib->hw_fib_va->header.Size));
581 address = fib->hw_fib_pa -
582 (u64)sizeof(struct aac_fib_xporthdr);
583 }
584 if (fibsize > 31)
585 fibsize = 31;
586 address |= fibsize;
587
588 #if defined(writeq)
589 src_writeq(dev, MUnit.IQ_L, (u64)address);
590 #else
591 spin_lock_irqsave(&fib->dev->iq_lock, flags);
592 src_writel(dev, MUnit.IQ_H,
593 upper_32_bits(address) & 0xffffffff);
594 src_writel(dev, MUnit.IQ_L, address & 0xffffffff);
595 spin_unlock_irqrestore(&fib->dev->iq_lock, flags);
596 #endif
597 }
598 return 0;
599 }
600
601 /**
602 * aac_src_ioremap
603 * @size: mapping resize request
604 *
605 */
606 static int aac_src_ioremap(struct aac_dev *dev, u32 size)
607 {
608 if (!size) {
609 iounmap(dev->regs.src.bar1);
610 dev->regs.src.bar1 = NULL;
611 iounmap(dev->regs.src.bar0);
612 dev->base = dev->regs.src.bar0 = NULL;
613 return 0;
614 }
615 dev->regs.src.bar1 = ioremap(pci_resource_start(dev->pdev, 2),
616 AAC_MIN_SRC_BAR1_SIZE);
617 dev->base = NULL;
618 if (dev->regs.src.bar1 == NULL)
619 return -1;
620 dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size);
621 if (dev->base == NULL) {
622 iounmap(dev->regs.src.bar1);
623 dev->regs.src.bar1 = NULL;
624 return -1;
625 }
626 dev->IndexRegs = &((struct src_registers __iomem *)
627 dev->base)->u.tupelo.IndexRegs;
628 return 0;
629 }
630
631 /**
632 * aac_srcv_ioremap
633 * @size: mapping resize request
634 *
635 */
636 static int aac_srcv_ioremap(struct aac_dev *dev, u32 size)
637 {
638 if (!size) {
639 iounmap(dev->regs.src.bar0);
640 dev->base = dev->regs.src.bar0 = NULL;
641 return 0;
642 }
643
644 dev->regs.src.bar1 =
645 ioremap(pci_resource_start(dev->pdev, 2), AAC_MIN_SRCV_BAR1_SIZE);
646 dev->base = NULL;
647 if (dev->regs.src.bar1 == NULL)
648 return -1;
649 dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size);
650 if (dev->base == NULL) {
651 iounmap(dev->regs.src.bar1);
652 dev->regs.src.bar1 = NULL;
653 return -1;
654 }
655 dev->IndexRegs = &((struct src_registers __iomem *)
656 dev->base)->u.denali.IndexRegs;
657 return 0;
658 }
659
660 void aac_set_intx_mode(struct aac_dev *dev)
661 {
662 if (dev->msi_enabled) {
663 aac_src_access_devreg(dev, AAC_ENABLE_INTX);
664 dev->msi_enabled = 0;
665 msleep(5000); /* Delay 5 seconds */
666 }
667 }
668
669 static void aac_send_iop_reset(struct aac_dev *dev, int bled)
670 {
671 u32 var, reset_mask;
672
673 bled = aac_adapter_sync_cmd(dev, IOP_RESET_ALWAYS,
674 0, 0, 0, 0, 0, 0, &var,
675 &reset_mask, NULL, NULL, NULL);
676
677 if ((bled || var != 0x00000001) && !dev->doorbell_mask)
678 bled = -EINVAL;
679 else if (dev->doorbell_mask) {
680 reset_mask = dev->doorbell_mask;
681 bled = 0;
682 var = 0x00000001;
683 }
684
685 aac_set_intx_mode(dev);
686
687 if (!bled && (dev->supplement_adapter_info.supported_options2 &
688 AAC_OPTION_DOORBELL_RESET)) {
689 src_writel(dev, MUnit.IDR, reset_mask);
690 } else {
691 src_writel(dev, MUnit.IDR, 0x100);
692 }
693 msleep(30000);
694 }
695
696 static void aac_send_hardware_soft_reset(struct aac_dev *dev)
697 {
698 u_int32_t val;
699
700 val = readl(((char *)(dev->base) + IBW_SWR_OFFSET));
701 val |= 0x01;
702 writel(val, ((char *)(dev->base) + IBW_SWR_OFFSET));
703 msleep_interruptible(20000);
704 }
705
706 static int aac_src_restart_adapter(struct aac_dev *dev, int bled, u8 reset_type)
707 {
708 unsigned long status, start;
709
710 if (bled < 0)
711 goto invalid_out;
712
713 if (bled)
714 pr_err("%s%d: adapter kernel panic'd %x.\n",
715 dev->name, dev->id, bled);
716
717 /*
718 * When there is a BlinkLED, IOP_RESET has not effect
719 */
720 if (bled >= 2 && dev->sa_firmware && reset_type & HW_IOP_RESET)
721 reset_type &= ~HW_IOP_RESET;
722
723 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
724
725 switch (reset_type) {
726 case IOP_HWSOFT_RESET:
727 aac_send_iop_reset(dev, bled);
728 /*
729 * Check to see if KERNEL_UP_AND_RUNNING
730 * Wait for the adapter to be up and running.
731 * If !KERNEL_UP_AND_RUNNING issue HW Soft Reset
732 */
733 status = src_readl(dev, MUnit.OMR);
734 if (dev->sa_firmware
735 && !(status & KERNEL_UP_AND_RUNNING)) {
736 start = jiffies;
737 do {
738 status = src_readl(dev, MUnit.OMR);
739 if (time_after(jiffies,
740 start+HZ*SOFT_RESET_TIME)) {
741 aac_send_hardware_soft_reset(dev);
742 start = jiffies;
743 }
744 } while (!(status & KERNEL_UP_AND_RUNNING));
745 }
746 break;
747 case HW_SOFT_RESET:
748 if (dev->sa_firmware) {
749 aac_send_hardware_soft_reset(dev);
750 aac_set_intx_mode(dev);
751 }
752 break;
753 default:
754 aac_send_iop_reset(dev, bled);
755 break;
756 }
757
758 invalid_out:
759
760 if (src_readl(dev, MUnit.OMR) & KERNEL_PANIC)
761 return -ENODEV;
762
763 if (startup_timeout < 300)
764 startup_timeout = 300;
765
766 return 0;
767 }
768
769 /**
770 * aac_src_select_comm - Select communications method
771 * @dev: Adapter
772 * @comm: communications method
773 */
774 static int aac_src_select_comm(struct aac_dev *dev, int comm)
775 {
776 switch (comm) {
777 case AAC_COMM_MESSAGE:
778 dev->a_ops.adapter_intr = aac_src_intr_message;
779 dev->a_ops.adapter_deliver = aac_src_deliver_message;
780 break;
781 default:
782 return 1;
783 }
784 return 0;
785 }
786
787 /**
788 * aac_src_init - initialize an Cardinal Frey Bar card
789 * @dev: device to configure
790 *
791 */
792
793 int aac_src_init(struct aac_dev *dev)
794 {
795 unsigned long start;
796 unsigned long status;
797 int restart = 0;
798 int instance = dev->id;
799 const char *name = dev->name;
800
801 dev->a_ops.adapter_ioremap = aac_src_ioremap;
802 dev->a_ops.adapter_comm = aac_src_select_comm;
803
804 dev->base_size = AAC_MIN_SRC_BAR0_SIZE;
805 if (aac_adapter_ioremap(dev, dev->base_size)) {
806 printk(KERN_WARNING "%s: unable to map adapter.\n", name);
807 goto error_iounmap;
808 }
809
810 /* Failure to reset here is an option ... */
811 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
812 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
813 if ((aac_reset_devices || reset_devices) &&
814 !aac_src_restart_adapter(dev, 0, IOP_HWSOFT_RESET))
815 ++restart;
816 /*
817 * Check to see if the board panic'd while booting.
818 */
819 status = src_readl(dev, MUnit.OMR);
820 if (status & KERNEL_PANIC) {
821 if (aac_src_restart_adapter(dev,
822 aac_src_check_health(dev), IOP_HWSOFT_RESET))
823 goto error_iounmap;
824 ++restart;
825 }
826 /*
827 * Check to see if the board failed any self tests.
828 */
829 status = src_readl(dev, MUnit.OMR);
830 if (status & SELF_TEST_FAILED) {
831 printk(KERN_ERR "%s%d: adapter self-test failed.\n",
832 dev->name, instance);
833 goto error_iounmap;
834 }
835 /*
836 * Check to see if the monitor panic'd while booting.
837 */
838 if (status & MONITOR_PANIC) {
839 printk(KERN_ERR "%s%d: adapter monitor panic.\n",
840 dev->name, instance);
841 goto error_iounmap;
842 }
843 start = jiffies;
844 /*
845 * Wait for the adapter to be up and running. Wait up to 3 minutes
846 */
847 while (!((status = src_readl(dev, MUnit.OMR)) &
848 KERNEL_UP_AND_RUNNING)) {
849 if ((restart &&
850 (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
851 time_after(jiffies, start+HZ*startup_timeout)) {
852 printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
853 dev->name, instance, status);
854 goto error_iounmap;
855 }
856 if (!restart &&
857 ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
858 time_after(jiffies, start + HZ *
859 ((startup_timeout > 60)
860 ? (startup_timeout - 60)
861 : (startup_timeout / 2))))) {
862 if (likely(!aac_src_restart_adapter(dev,
863 aac_src_check_health(dev), IOP_HWSOFT_RESET)))
864 start = jiffies;
865 ++restart;
866 }
867 msleep(1);
868 }
869 if (restart && aac_commit)
870 aac_commit = 1;
871 /*
872 * Fill in the common function dispatch table.
873 */
874 dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter;
875 dev->a_ops.adapter_disable_int = aac_src_disable_interrupt;
876 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
877 dev->a_ops.adapter_notify = aac_src_notify_adapter;
878 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
879 dev->a_ops.adapter_check_health = aac_src_check_health;
880 dev->a_ops.adapter_restart = aac_src_restart_adapter;
881 dev->a_ops.adapter_start = aac_src_start_adapter;
882
883 /*
884 * First clear out all interrupts. Then enable the one's that we
885 * can handle.
886 */
887 aac_adapter_comm(dev, AAC_COMM_MESSAGE);
888 aac_adapter_disable_int(dev);
889 src_writel(dev, MUnit.ODR_C, 0xffffffff);
890 aac_adapter_enable_int(dev);
891
892 if (aac_init_adapter(dev) == NULL)
893 goto error_iounmap;
894 if (dev->comm_interface != AAC_COMM_MESSAGE_TYPE1)
895 goto error_iounmap;
896
897 dev->msi = !pci_enable_msi(dev->pdev);
898
899 dev->aac_msix[0].vector_no = 0;
900 dev->aac_msix[0].dev = dev;
901
902 if (request_irq(dev->pdev->irq, dev->a_ops.adapter_intr,
903 IRQF_SHARED, "aacraid", &(dev->aac_msix[0])) < 0) {
904
905 if (dev->msi)
906 pci_disable_msi(dev->pdev);
907
908 printk(KERN_ERR "%s%d: Interrupt unavailable.\n",
909 name, instance);
910 goto error_iounmap;
911 }
912 dev->dbg_base = pci_resource_start(dev->pdev, 2);
913 dev->dbg_base_mapped = dev->regs.src.bar1;
914 dev->dbg_size = AAC_MIN_SRC_BAR1_SIZE;
915 dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message;
916
917 aac_adapter_enable_int(dev);
918
919 if (!dev->sync_mode) {
920 /*
921 * Tell the adapter that all is configured, and it can
922 * start accepting requests
923 */
924 aac_src_start_adapter(dev);
925 }
926 return 0;
927
928 error_iounmap:
929
930 return -1;
931 }
932
933 /**
934 * aac_srcv_init - initialize an SRCv card
935 * @dev: device to configure
936 *
937 */
938
939 int aac_srcv_init(struct aac_dev *dev)
940 {
941 unsigned long start;
942 unsigned long status;
943 int restart = 0;
944 int instance = dev->id;
945 const char *name = dev->name;
946
947 dev->a_ops.adapter_ioremap = aac_srcv_ioremap;
948 dev->a_ops.adapter_comm = aac_src_select_comm;
949
950 dev->base_size = AAC_MIN_SRCV_BAR0_SIZE;
951 if (aac_adapter_ioremap(dev, dev->base_size)) {
952 printk(KERN_WARNING "%s: unable to map adapter.\n", name);
953 goto error_iounmap;
954 }
955
956 /* Failure to reset here is an option ... */
957 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
958 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
959 if ((aac_reset_devices || reset_devices) &&
960 !aac_src_restart_adapter(dev, 0, IOP_HWSOFT_RESET))
961 ++restart;
962 /*
963 * Check to see if flash update is running.
964 * Wait for the adapter to be up and running. Wait up to 5 minutes
965 */
966 status = src_readl(dev, MUnit.OMR);
967 if (status & FLASH_UPD_PENDING) {
968 start = jiffies;
969 do {
970 status = src_readl(dev, MUnit.OMR);
971 if (time_after(jiffies, start+HZ*FWUPD_TIMEOUT)) {
972 printk(KERN_ERR "%s%d: adapter flash update failed.\n",
973 dev->name, instance);
974 goto error_iounmap;
975 }
976 } while (!(status & FLASH_UPD_SUCCESS) &&
977 !(status & FLASH_UPD_FAILED));
978 /* Delay 10 seconds.
979 * Because right now FW is doing a soft reset,
980 * do not read scratch pad register at this time
981 */
982 ssleep(10);
983 }
984 /*
985 * Check to see if the board panic'd while booting.
986 */
987 status = src_readl(dev, MUnit.OMR);
988 if (status & KERNEL_PANIC) {
989 if (aac_src_restart_adapter(dev,
990 aac_src_check_health(dev), IOP_HWSOFT_RESET))
991 goto error_iounmap;
992 ++restart;
993 }
994 /*
995 * Check to see if the board failed any self tests.
996 */
997 status = src_readl(dev, MUnit.OMR);
998 if (status & SELF_TEST_FAILED) {
999 printk(KERN_ERR "%s%d: adapter self-test failed.\n", dev->name, instance);
1000 goto error_iounmap;
1001 }
1002 /*
1003 * Check to see if the monitor panic'd while booting.
1004 */
1005 if (status & MONITOR_PANIC) {
1006 printk(KERN_ERR "%s%d: adapter monitor panic.\n", dev->name, instance);
1007 goto error_iounmap;
1008 }
1009 start = jiffies;
1010 /*
1011 * Wait for the adapter to be up and running. Wait up to 3 minutes
1012 */
1013 while (!((status = src_readl(dev, MUnit.OMR)) &
1014 KERNEL_UP_AND_RUNNING) ||
1015 status == 0xffffffff) {
1016 if ((restart &&
1017 (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
1018 time_after(jiffies, start+HZ*startup_timeout)) {
1019 printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
1020 dev->name, instance, status);
1021 goto error_iounmap;
1022 }
1023 if (!restart &&
1024 ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
1025 time_after(jiffies, start + HZ *
1026 ((startup_timeout > 60)
1027 ? (startup_timeout - 60)
1028 : (startup_timeout / 2))))) {
1029 if (likely(!aac_src_restart_adapter(dev,
1030 aac_src_check_health(dev), IOP_HWSOFT_RESET)))
1031 start = jiffies;
1032 ++restart;
1033 }
1034 msleep(1);
1035 }
1036 if (restart && aac_commit)
1037 aac_commit = 1;
1038 /*
1039 * Fill in the common function dispatch table.
1040 */
1041 dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter;
1042 dev->a_ops.adapter_disable_int = aac_src_disable_interrupt;
1043 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
1044 dev->a_ops.adapter_notify = aac_src_notify_adapter;
1045 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
1046 dev->a_ops.adapter_check_health = aac_src_check_health;
1047 dev->a_ops.adapter_restart = aac_src_restart_adapter;
1048 dev->a_ops.adapter_start = aac_src_start_adapter;
1049
1050 /*
1051 * First clear out all interrupts. Then enable the one's that we
1052 * can handle.
1053 */
1054 aac_adapter_comm(dev, AAC_COMM_MESSAGE);
1055 aac_adapter_disable_int(dev);
1056 src_writel(dev, MUnit.ODR_C, 0xffffffff);
1057 aac_adapter_enable_int(dev);
1058
1059 if (aac_init_adapter(dev) == NULL)
1060 goto error_iounmap;
1061 if ((dev->comm_interface != AAC_COMM_MESSAGE_TYPE2) &&
1062 (dev->comm_interface != AAC_COMM_MESSAGE_TYPE3))
1063 goto error_iounmap;
1064 if (dev->msi_enabled)
1065 aac_src_access_devreg(dev, AAC_ENABLE_MSIX);
1066
1067 if (aac_acquire_irq(dev))
1068 goto error_iounmap;
1069
1070 dev->dbg_base = pci_resource_start(dev->pdev, 2);
1071 dev->dbg_base_mapped = dev->regs.src.bar1;
1072 dev->dbg_size = AAC_MIN_SRCV_BAR1_SIZE;
1073 dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message;
1074
1075 aac_adapter_enable_int(dev);
1076
1077 if (!dev->sync_mode) {
1078 /*
1079 * Tell the adapter that all is configured, and it can
1080 * start accepting requests
1081 */
1082 aac_src_start_adapter(dev);
1083 }
1084 return 0;
1085
1086 error_iounmap:
1087
1088 return -1;
1089 }
1090
1091 void aac_src_access_devreg(struct aac_dev *dev, int mode)
1092 {
1093 u_int32_t val;
1094
1095 switch (mode) {
1096 case AAC_ENABLE_INTERRUPT:
1097 src_writel(dev,
1098 MUnit.OIMR,
1099 dev->OIMR = (dev->msi_enabled ?
1100 AAC_INT_ENABLE_TYPE1_MSIX :
1101 AAC_INT_ENABLE_TYPE1_INTX));
1102 break;
1103
1104 case AAC_DISABLE_INTERRUPT:
1105 src_writel(dev,
1106 MUnit.OIMR,
1107 dev->OIMR = AAC_INT_DISABLE_ALL);
1108 break;
1109
1110 case AAC_ENABLE_MSIX:
1111 /* set bit 6 */
1112 val = src_readl(dev, MUnit.IDR);
1113 val |= 0x40;
1114 src_writel(dev, MUnit.IDR, val);
1115 src_readl(dev, MUnit.IDR);
1116 /* unmask int. */
1117 val = PMC_ALL_INTERRUPT_BITS;
1118 src_writel(dev, MUnit.IOAR, val);
1119 val = src_readl(dev, MUnit.OIMR);
1120 src_writel(dev,
1121 MUnit.OIMR,
1122 val & (~(PMC_GLOBAL_INT_BIT2 | PMC_GLOBAL_INT_BIT0)));
1123 break;
1124
1125 case AAC_DISABLE_MSIX:
1126 /* reset bit 6 */
1127 val = src_readl(dev, MUnit.IDR);
1128 val &= ~0x40;
1129 src_writel(dev, MUnit.IDR, val);
1130 src_readl(dev, MUnit.IDR);
1131 break;
1132
1133 case AAC_CLEAR_AIF_BIT:
1134 /* set bit 5 */
1135 val = src_readl(dev, MUnit.IDR);
1136 val |= 0x20;
1137 src_writel(dev, MUnit.IDR, val);
1138 src_readl(dev, MUnit.IDR);
1139 break;
1140
1141 case AAC_CLEAR_SYNC_BIT:
1142 /* set bit 4 */
1143 val = src_readl(dev, MUnit.IDR);
1144 val |= 0x10;
1145 src_writel(dev, MUnit.IDR, val);
1146 src_readl(dev, MUnit.IDR);
1147 break;
1148
1149 case AAC_ENABLE_INTX:
1150 /* set bit 7 */
1151 val = src_readl(dev, MUnit.IDR);
1152 val |= 0x80;
1153 src_writel(dev, MUnit.IDR, val);
1154 src_readl(dev, MUnit.IDR);
1155 /* unmask int. */
1156 val = PMC_ALL_INTERRUPT_BITS;
1157 src_writel(dev, MUnit.IOAR, val);
1158 src_readl(dev, MUnit.IOAR);
1159 val = src_readl(dev, MUnit.OIMR);
1160 src_writel(dev, MUnit.OIMR,
1161 val & (~(PMC_GLOBAL_INT_BIT2)));
1162 break;
1163
1164 default:
1165 break;
1166 }
1167 }
1168
1169 static int aac_src_get_sync_status(struct aac_dev *dev)
1170 {
1171
1172 int val;
1173
1174 if (dev->msi_enabled)
1175 val = src_readl(dev, MUnit.ODR_MSI) & 0x1000 ? 1 : 0;
1176 else
1177 val = src_readl(dev, MUnit.ODR_R) >> SRC_ODR_SHIFT;
1178
1179 return val;
1180 }
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