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[PATCH] ahci: add HOST_CAP_NCQ constant
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include <asm/io.h>
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.3"
52
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_MAX_CMDS = 1,
60 AHCI_CMD_SZ = 32,
61 AHCI_CMD_SLOT_SZ = 32 * AHCI_CMD_SZ,
62 AHCI_RX_FIS_SZ = 256,
63 AHCI_CMD_TBL_CDB = 0x40,
64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_RX_FIS_SZ,
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
72 AHCI_CMD_PREFETCH = (1 << 7),
73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
75
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
78
79 board_ahci = 0,
80 board_ahci_vt8251 = 1,
81
82 /* global controller registers */
83 HOST_CAP = 0x00, /* host capabilities */
84 HOST_CTL = 0x04, /* global host control */
85 HOST_IRQ_STAT = 0x08, /* interrupt status */
86 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
87 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
88
89 /* HOST_CTL bits */
90 HOST_RESET = (1 << 0), /* reset controller; self-clear */
91 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
92 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
93
94 /* HOST_CAP bits */
95 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
96 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
97 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
98
99 /* registers for each SATA port */
100 PORT_LST_ADDR = 0x00, /* command list DMA addr */
101 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
102 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
103 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
104 PORT_IRQ_STAT = 0x10, /* interrupt status */
105 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
106 PORT_CMD = 0x18, /* port command */
107 PORT_TFDATA = 0x20, /* taskfile data */
108 PORT_SIG = 0x24, /* device TF signature */
109 PORT_CMD_ISSUE = 0x38, /* command issue */
110 PORT_SCR = 0x28, /* SATA phy register block */
111 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
112 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
113 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
114 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
115
116 /* PORT_IRQ_{STAT,MASK} bits */
117 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
118 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
119 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
120 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
121 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
122 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
123 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
124 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
125
126 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
127 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
128 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
129 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
130 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
131 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
132 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
133 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
134 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
135
136 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
137 PORT_IRQ_IF_ERR |
138 PORT_IRQ_CONNECT |
139 PORT_IRQ_UNK_FIS,
140 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
141 PORT_IRQ_TF_ERR |
142 PORT_IRQ_HBUS_DATA_ERR,
143 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
144 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
145 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
146
147 /* PORT_CMD bits */
148 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
149 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
150 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
151 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
152 PORT_CMD_CLO = (1 << 3), /* Command list override */
153 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
154 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
155 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
156
157 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
158 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
159 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
160
161 /* hpriv->flags bits */
162 AHCI_FLAG_MSI = (1 << 0),
163
164 /* ap->flags bits */
165 AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
166 };
167
168 struct ahci_cmd_hdr {
169 u32 opts;
170 u32 status;
171 u32 tbl_addr;
172 u32 tbl_addr_hi;
173 u32 reserved[4];
174 };
175
176 struct ahci_sg {
177 u32 addr;
178 u32 addr_hi;
179 u32 reserved;
180 u32 flags_size;
181 };
182
183 struct ahci_host_priv {
184 unsigned long flags;
185 u32 cap; /* cache of HOST_CAP register */
186 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
187 };
188
189 struct ahci_port_priv {
190 struct ahci_cmd_hdr *cmd_slot;
191 dma_addr_t cmd_slot_dma;
192 void *cmd_tbl;
193 dma_addr_t cmd_tbl_dma;
194 struct ahci_sg *cmd_tbl_sg;
195 void *rx_fis;
196 dma_addr_t rx_fis_dma;
197 };
198
199 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
200 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
201 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
202 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
203 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
204 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes);
205 static void ahci_irq_clear(struct ata_port *ap);
206 static int ahci_port_start(struct ata_port *ap);
207 static void ahci_port_stop(struct ata_port *ap);
208 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
209 static void ahci_qc_prep(struct ata_queued_cmd *qc);
210 static u8 ahci_check_status(struct ata_port *ap);
211 static void ahci_freeze(struct ata_port *ap);
212 static void ahci_thaw(struct ata_port *ap);
213 static void ahci_error_handler(struct ata_port *ap);
214 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
215 static void ahci_remove_one (struct pci_dev *pdev);
216
217 static struct scsi_host_template ahci_sht = {
218 .module = THIS_MODULE,
219 .name = DRV_NAME,
220 .ioctl = ata_scsi_ioctl,
221 .queuecommand = ata_scsi_queuecmd,
222 .can_queue = ATA_DEF_QUEUE,
223 .this_id = ATA_SHT_THIS_ID,
224 .sg_tablesize = AHCI_MAX_SG,
225 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
226 .emulated = ATA_SHT_EMULATED,
227 .use_clustering = AHCI_USE_CLUSTERING,
228 .proc_name = DRV_NAME,
229 .dma_boundary = AHCI_DMA_BOUNDARY,
230 .slave_configure = ata_scsi_slave_config,
231 .bios_param = ata_std_bios_param,
232 };
233
234 static const struct ata_port_operations ahci_ops = {
235 .port_disable = ata_port_disable,
236
237 .check_status = ahci_check_status,
238 .check_altstatus = ahci_check_status,
239 .dev_select = ata_noop_dev_select,
240
241 .tf_read = ahci_tf_read,
242
243 .probe_reset = ahci_probe_reset,
244
245 .qc_prep = ahci_qc_prep,
246 .qc_issue = ahci_qc_issue,
247
248 .irq_handler = ahci_interrupt,
249 .irq_clear = ahci_irq_clear,
250
251 .scr_read = ahci_scr_read,
252 .scr_write = ahci_scr_write,
253
254 .freeze = ahci_freeze,
255 .thaw = ahci_thaw,
256
257 .error_handler = ahci_error_handler,
258 .post_internal_cmd = ahci_post_internal_cmd,
259
260 .port_start = ahci_port_start,
261 .port_stop = ahci_port_stop,
262 };
263
264 static const struct ata_port_info ahci_port_info[] = {
265 /* board_ahci */
266 {
267 .sht = &ahci_sht,
268 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
269 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
270 .pio_mask = 0x1f, /* pio0-4 */
271 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
272 .port_ops = &ahci_ops,
273 },
274 /* board_ahci_vt8251 */
275 {
276 .sht = &ahci_sht,
277 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
278 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
279 AHCI_FLAG_RESET_NEEDS_CLO,
280 .pio_mask = 0x1f, /* pio0-4 */
281 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
282 .port_ops = &ahci_ops,
283 },
284 };
285
286 static const struct pci_device_id ahci_pci_tbl[] = {
287 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
288 board_ahci }, /* ICH6 */
289 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
290 board_ahci }, /* ICH6M */
291 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
292 board_ahci }, /* ICH7 */
293 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
294 board_ahci }, /* ICH7M */
295 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
296 board_ahci }, /* ICH7R */
297 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
298 board_ahci }, /* ULi M5288 */
299 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
300 board_ahci }, /* ESB2 */
301 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
302 board_ahci }, /* ESB2 */
303 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
304 board_ahci }, /* ESB2 */
305 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
306 board_ahci }, /* ICH7-M DH */
307 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
308 board_ahci }, /* ICH8 */
309 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
310 board_ahci }, /* ICH8 */
311 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
312 board_ahci }, /* ICH8 */
313 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
314 board_ahci }, /* ICH8M */
315 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
316 board_ahci }, /* ICH8M */
317 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
318 board_ahci }, /* JMicron JMB360 */
319 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
320 board_ahci }, /* JMicron JMB363 */
321 { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
322 board_ahci }, /* ATI SB600 non-raid */
323 { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
324 board_ahci }, /* ATI SB600 raid */
325 { PCI_VENDOR_ID_VIA, 0x3349, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
326 board_ahci_vt8251 }, /* VIA VT8251 */
327 { } /* terminate list */
328 };
329
330
331 static struct pci_driver ahci_pci_driver = {
332 .name = DRV_NAME,
333 .id_table = ahci_pci_tbl,
334 .probe = ahci_init_one,
335 .remove = ahci_remove_one,
336 };
337
338
339 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
340 {
341 return base + 0x100 + (port * 0x80);
342 }
343
344 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
345 {
346 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
347 }
348
349 static int ahci_port_start(struct ata_port *ap)
350 {
351 struct device *dev = ap->host_set->dev;
352 struct ahci_host_priv *hpriv = ap->host_set->private_data;
353 struct ahci_port_priv *pp;
354 void __iomem *mmio = ap->host_set->mmio_base;
355 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
356 void *mem;
357 dma_addr_t mem_dma;
358 int rc;
359
360 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
361 if (!pp)
362 return -ENOMEM;
363 memset(pp, 0, sizeof(*pp));
364
365 rc = ata_pad_alloc(ap, dev);
366 if (rc) {
367 kfree(pp);
368 return rc;
369 }
370
371 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
372 if (!mem) {
373 ata_pad_free(ap, dev);
374 kfree(pp);
375 return -ENOMEM;
376 }
377 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
378
379 /*
380 * First item in chunk of DMA memory: 32-slot command table,
381 * 32 bytes each in size
382 */
383 pp->cmd_slot = mem;
384 pp->cmd_slot_dma = mem_dma;
385
386 mem += AHCI_CMD_SLOT_SZ;
387 mem_dma += AHCI_CMD_SLOT_SZ;
388
389 /*
390 * Second item: Received-FIS area
391 */
392 pp->rx_fis = mem;
393 pp->rx_fis_dma = mem_dma;
394
395 mem += AHCI_RX_FIS_SZ;
396 mem_dma += AHCI_RX_FIS_SZ;
397
398 /*
399 * Third item: data area for storing a single command
400 * and its scatter-gather table
401 */
402 pp->cmd_tbl = mem;
403 pp->cmd_tbl_dma = mem_dma;
404
405 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR_SZ;
406
407 ap->private_data = pp;
408
409 if (hpriv->cap & HOST_CAP_64)
410 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
411 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
412 readl(port_mmio + PORT_LST_ADDR); /* flush */
413
414 if (hpriv->cap & HOST_CAP_64)
415 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
416 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
417 readl(port_mmio + PORT_FIS_ADDR); /* flush */
418
419 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
420 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
421 PORT_CMD_START, port_mmio + PORT_CMD);
422 readl(port_mmio + PORT_CMD); /* flush */
423
424 return 0;
425 }
426
427
428 static void ahci_port_stop(struct ata_port *ap)
429 {
430 struct device *dev = ap->host_set->dev;
431 struct ahci_port_priv *pp = ap->private_data;
432 void __iomem *mmio = ap->host_set->mmio_base;
433 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
434 u32 tmp;
435
436 tmp = readl(port_mmio + PORT_CMD);
437 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
438 writel(tmp, port_mmio + PORT_CMD);
439 readl(port_mmio + PORT_CMD); /* flush */
440
441 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
442 * this is slightly incorrect.
443 */
444 msleep(500);
445
446 ap->private_data = NULL;
447 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
448 pp->cmd_slot, pp->cmd_slot_dma);
449 ata_pad_free(ap, dev);
450 kfree(pp);
451 }
452
453 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
454 {
455 unsigned int sc_reg;
456
457 switch (sc_reg_in) {
458 case SCR_STATUS: sc_reg = 0; break;
459 case SCR_CONTROL: sc_reg = 1; break;
460 case SCR_ERROR: sc_reg = 2; break;
461 case SCR_ACTIVE: sc_reg = 3; break;
462 default:
463 return 0xffffffffU;
464 }
465
466 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
467 }
468
469
470 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
471 u32 val)
472 {
473 unsigned int sc_reg;
474
475 switch (sc_reg_in) {
476 case SCR_STATUS: sc_reg = 0; break;
477 case SCR_CONTROL: sc_reg = 1; break;
478 case SCR_ERROR: sc_reg = 2; break;
479 case SCR_ACTIVE: sc_reg = 3; break;
480 default:
481 return;
482 }
483
484 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
485 }
486
487 static int ahci_stop_engine(struct ata_port *ap)
488 {
489 void __iomem *mmio = ap->host_set->mmio_base;
490 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
491 int work;
492 u32 tmp;
493
494 tmp = readl(port_mmio + PORT_CMD);
495 tmp &= ~PORT_CMD_START;
496 writel(tmp, port_mmio + PORT_CMD);
497
498 /* wait for engine to stop. TODO: this could be
499 * as long as 500 msec
500 */
501 work = 1000;
502 while (work-- > 0) {
503 tmp = readl(port_mmio + PORT_CMD);
504 if ((tmp & PORT_CMD_LIST_ON) == 0)
505 return 0;
506 udelay(10);
507 }
508
509 return -EIO;
510 }
511
512 static void ahci_start_engine(struct ata_port *ap)
513 {
514 void __iomem *mmio = ap->host_set->mmio_base;
515 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
516 u32 tmp;
517
518 tmp = readl(port_mmio + PORT_CMD);
519 tmp |= PORT_CMD_START;
520 writel(tmp, port_mmio + PORT_CMD);
521 readl(port_mmio + PORT_CMD); /* flush */
522 }
523
524 static unsigned int ahci_dev_classify(struct ata_port *ap)
525 {
526 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
527 struct ata_taskfile tf;
528 u32 tmp;
529
530 tmp = readl(port_mmio + PORT_SIG);
531 tf.lbah = (tmp >> 24) & 0xff;
532 tf.lbam = (tmp >> 16) & 0xff;
533 tf.lbal = (tmp >> 8) & 0xff;
534 tf.nsect = (tmp) & 0xff;
535
536 return ata_dev_classify(&tf);
537 }
538
539 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts)
540 {
541 pp->cmd_slot[0].opts = cpu_to_le32(opts);
542 pp->cmd_slot[0].status = 0;
543 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
544 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
545 }
546
547 static int ahci_clo(struct ata_port *ap)
548 {
549 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
550 struct ahci_host_priv *hpriv = ap->host_set->private_data;
551 u32 tmp;
552
553 if (!(hpriv->cap & HOST_CAP_CLO))
554 return -EOPNOTSUPP;
555
556 tmp = readl(port_mmio + PORT_CMD);
557 tmp |= PORT_CMD_CLO;
558 writel(tmp, port_mmio + PORT_CMD);
559
560 tmp = ata_wait_register(port_mmio + PORT_CMD,
561 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
562 if (tmp & PORT_CMD_CLO)
563 return -EIO;
564
565 return 0;
566 }
567
568 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
569 {
570 struct ahci_port_priv *pp = ap->private_data;
571 void __iomem *mmio = ap->host_set->mmio_base;
572 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
573 const u32 cmd_fis_len = 5; /* five dwords */
574 const char *reason = NULL;
575 struct ata_taskfile tf;
576 u32 tmp;
577 u8 *fis;
578 int rc;
579
580 DPRINTK("ENTER\n");
581
582 if (ata_port_offline(ap)) {
583 DPRINTK("PHY reports no device\n");
584 *class = ATA_DEV_NONE;
585 return 0;
586 }
587
588 /* prepare for SRST (AHCI-1.1 10.4.1) */
589 rc = ahci_stop_engine(ap);
590 if (rc) {
591 reason = "failed to stop engine";
592 goto fail_restart;
593 }
594
595 /* check BUSY/DRQ, perform Command List Override if necessary */
596 ahci_tf_read(ap, &tf);
597 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
598 rc = ahci_clo(ap);
599
600 if (rc == -EOPNOTSUPP) {
601 reason = "port busy but CLO unavailable";
602 goto fail_restart;
603 } else if (rc) {
604 reason = "port busy but CLO failed";
605 goto fail_restart;
606 }
607 }
608
609 /* restart engine */
610 ahci_start_engine(ap);
611
612 ata_tf_init(ap->device, &tf);
613 fis = pp->cmd_tbl;
614
615 /* issue the first D2H Register FIS */
616 ahci_fill_cmd_slot(pp, cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
617
618 tf.ctl |= ATA_SRST;
619 ata_tf_to_fis(&tf, fis, 0);
620 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
621
622 writel(1, port_mmio + PORT_CMD_ISSUE);
623
624 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
625 if (tmp & 0x1) {
626 rc = -EIO;
627 reason = "1st FIS failed";
628 goto fail;
629 }
630
631 /* spec says at least 5us, but be generous and sleep for 1ms */
632 msleep(1);
633
634 /* issue the second D2H Register FIS */
635 ahci_fill_cmd_slot(pp, cmd_fis_len);
636
637 tf.ctl &= ~ATA_SRST;
638 ata_tf_to_fis(&tf, fis, 0);
639 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
640
641 writel(1, port_mmio + PORT_CMD_ISSUE);
642 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
643
644 /* spec mandates ">= 2ms" before checking status.
645 * We wait 150ms, because that was the magic delay used for
646 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
647 * between when the ATA command register is written, and then
648 * status is checked. Because waiting for "a while" before
649 * checking status is fine, post SRST, we perform this magic
650 * delay here as well.
651 */
652 msleep(150);
653
654 *class = ATA_DEV_NONE;
655 if (ata_port_online(ap)) {
656 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
657 rc = -EIO;
658 reason = "device not ready";
659 goto fail;
660 }
661 *class = ahci_dev_classify(ap);
662 }
663
664 DPRINTK("EXIT, class=%u\n", *class);
665 return 0;
666
667 fail_restart:
668 ahci_start_engine(ap);
669 fail:
670 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
671 return rc;
672 }
673
674 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
675 {
676 int rc;
677
678 DPRINTK("ENTER\n");
679
680 ahci_stop_engine(ap);
681 rc = sata_std_hardreset(ap, class);
682 ahci_start_engine(ap);
683
684 if (rc == 0 && ata_port_online(ap))
685 *class = ahci_dev_classify(ap);
686 if (*class == ATA_DEV_UNKNOWN)
687 *class = ATA_DEV_NONE;
688
689 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
690 return rc;
691 }
692
693 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
694 {
695 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
696 u32 new_tmp, tmp;
697
698 ata_std_postreset(ap, class);
699
700 /* Make sure port's ATAPI bit is set appropriately */
701 new_tmp = tmp = readl(port_mmio + PORT_CMD);
702 if (*class == ATA_DEV_ATAPI)
703 new_tmp |= PORT_CMD_ATAPI;
704 else
705 new_tmp &= ~PORT_CMD_ATAPI;
706 if (new_tmp != tmp) {
707 writel(new_tmp, port_mmio + PORT_CMD);
708 readl(port_mmio + PORT_CMD); /* flush */
709 }
710 }
711
712 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
713 {
714 if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) &&
715 (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) {
716 /* ATA_BUSY hasn't cleared, so send a CLO */
717 ahci_clo(ap);
718 }
719
720 return ata_drive_probe_reset(ap, ata_std_probeinit,
721 ahci_softreset, ahci_hardreset,
722 ahci_postreset, classes);
723 }
724
725 static u8 ahci_check_status(struct ata_port *ap)
726 {
727 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
728
729 return readl(mmio + PORT_TFDATA) & 0xFF;
730 }
731
732 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
733 {
734 struct ahci_port_priv *pp = ap->private_data;
735 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
736
737 ata_tf_from_fis(d2h_fis, tf);
738 }
739
740 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
741 {
742 struct ahci_port_priv *pp = qc->ap->private_data;
743 struct scatterlist *sg;
744 struct ahci_sg *ahci_sg;
745 unsigned int n_sg = 0;
746
747 VPRINTK("ENTER\n");
748
749 /*
750 * Next, the S/G list.
751 */
752 ahci_sg = pp->cmd_tbl_sg;
753 ata_for_each_sg(sg, qc) {
754 dma_addr_t addr = sg_dma_address(sg);
755 u32 sg_len = sg_dma_len(sg);
756
757 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
758 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
759 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
760
761 ahci_sg++;
762 n_sg++;
763 }
764
765 return n_sg;
766 }
767
768 static void ahci_qc_prep(struct ata_queued_cmd *qc)
769 {
770 struct ata_port *ap = qc->ap;
771 struct ahci_port_priv *pp = ap->private_data;
772 int is_atapi = is_atapi_taskfile(&qc->tf);
773 u32 opts;
774 const u32 cmd_fis_len = 5; /* five dwords */
775 unsigned int n_elem;
776
777 /*
778 * Fill in command table information. First, the header,
779 * a SATA Register - Host to Device command FIS.
780 */
781 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
782 if (is_atapi) {
783 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
784 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb,
785 qc->dev->cdb_len);
786 }
787
788 n_elem = 0;
789 if (qc->flags & ATA_QCFLAG_DMAMAP)
790 n_elem = ahci_fill_sg(qc);
791
792 /*
793 * Fill in command slot information.
794 */
795 opts = cmd_fis_len | n_elem << 16;
796 if (qc->tf.flags & ATA_TFLAG_WRITE)
797 opts |= AHCI_CMD_WRITE;
798 if (is_atapi)
799 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
800
801 ahci_fill_cmd_slot(pp, opts);
802 }
803
804 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
805 {
806 struct ahci_port_priv *pp = ap->private_data;
807 struct ata_eh_info *ehi = &ap->eh_info;
808 unsigned int err_mask = 0, action = 0;
809 struct ata_queued_cmd *qc;
810 u32 serror;
811
812 ata_ehi_clear_desc(ehi);
813
814 /* AHCI needs SError cleared; otherwise, it might lock up */
815 serror = ahci_scr_read(ap, SCR_ERROR);
816 ahci_scr_write(ap, SCR_ERROR, serror);
817
818 /* analyze @irq_stat */
819 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
820
821 if (irq_stat & PORT_IRQ_TF_ERR)
822 err_mask |= AC_ERR_DEV;
823
824 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
825 err_mask |= AC_ERR_HOST_BUS;
826 action |= ATA_EH_SOFTRESET;
827 }
828
829 if (irq_stat & PORT_IRQ_IF_ERR) {
830 err_mask |= AC_ERR_ATA_BUS;
831 action |= ATA_EH_SOFTRESET;
832 ata_ehi_push_desc(ehi, ", interface fatal error");
833 }
834
835 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
836 err_mask |= AC_ERR_ATA_BUS;
837 action |= ATA_EH_SOFTRESET;
838 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
839 "connection status changed" : "PHY RDY changed");
840 }
841
842 if (irq_stat & PORT_IRQ_UNK_FIS) {
843 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
844
845 err_mask |= AC_ERR_HSM;
846 action |= ATA_EH_SOFTRESET;
847 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
848 unk[0], unk[1], unk[2], unk[3]);
849 }
850
851 /* okay, let's hand over to EH */
852 ehi->serror |= serror;
853 ehi->action |= action;
854
855 qc = ata_qc_from_tag(ap, ap->active_tag);
856 if (qc)
857 qc->err_mask |= err_mask;
858 else
859 ehi->err_mask |= err_mask;
860
861 if (irq_stat & PORT_IRQ_FREEZE)
862 ata_port_freeze(ap);
863 else
864 ata_port_abort(ap);
865 }
866
867 static void ahci_host_intr(struct ata_port *ap)
868 {
869 void __iomem *mmio = ap->host_set->mmio_base;
870 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
871 struct ata_queued_cmd *qc;
872 u32 status, ci;
873
874 status = readl(port_mmio + PORT_IRQ_STAT);
875 writel(status, port_mmio + PORT_IRQ_STAT);
876
877 if (unlikely(status & PORT_IRQ_ERROR)) {
878 ahci_error_intr(ap, status);
879 return;
880 }
881
882 if ((qc = ata_qc_from_tag(ap, ap->active_tag))) {
883 ci = readl(port_mmio + PORT_CMD_ISSUE);
884 if ((ci & 0x1) == 0) {
885 ata_qc_complete(qc);
886 return;
887 }
888 }
889
890 /* hmmm... a spurious interupt */
891
892 /* ignore interim PIO setup fis interrupts */
893 if (ata_tag_valid(ap->active_tag)) {
894 struct ata_queued_cmd *qc =
895 ata_qc_from_tag(ap, ap->active_tag);
896
897 if (qc && qc->tf.protocol == ATA_PROT_PIO &&
898 (status & PORT_IRQ_PIOS_FIS))
899 return;
900 }
901
902 if (ata_ratelimit())
903 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
904 "(irq_stat 0x%x active_tag %d)\n",
905 status, ap->active_tag);
906 }
907
908 static void ahci_irq_clear(struct ata_port *ap)
909 {
910 /* TODO */
911 }
912
913 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
914 {
915 struct ata_host_set *host_set = dev_instance;
916 struct ahci_host_priv *hpriv;
917 unsigned int i, handled = 0;
918 void __iomem *mmio;
919 u32 irq_stat, irq_ack = 0;
920
921 VPRINTK("ENTER\n");
922
923 hpriv = host_set->private_data;
924 mmio = host_set->mmio_base;
925
926 /* sigh. 0xffffffff is a valid return from h/w */
927 irq_stat = readl(mmio + HOST_IRQ_STAT);
928 irq_stat &= hpriv->port_map;
929 if (!irq_stat)
930 return IRQ_NONE;
931
932 spin_lock(&host_set->lock);
933
934 for (i = 0; i < host_set->n_ports; i++) {
935 struct ata_port *ap;
936
937 if (!(irq_stat & (1 << i)))
938 continue;
939
940 ap = host_set->ports[i];
941 if (ap) {
942 ahci_host_intr(ap);
943 VPRINTK("port %u\n", i);
944 } else {
945 VPRINTK("port %u (no irq)\n", i);
946 if (ata_ratelimit())
947 dev_printk(KERN_WARNING, host_set->dev,
948 "interrupt on disabled port %u\n", i);
949 }
950
951 irq_ack |= (1 << i);
952 }
953
954 if (irq_ack) {
955 writel(irq_ack, mmio + HOST_IRQ_STAT);
956 handled = 1;
957 }
958
959 spin_unlock(&host_set->lock);
960
961 VPRINTK("EXIT\n");
962
963 return IRQ_RETVAL(handled);
964 }
965
966 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
967 {
968 struct ata_port *ap = qc->ap;
969 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
970
971 writel(1, port_mmio + PORT_CMD_ISSUE);
972 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
973
974 return 0;
975 }
976
977 static void ahci_freeze(struct ata_port *ap)
978 {
979 void __iomem *mmio = ap->host_set->mmio_base;
980 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
981
982 /* turn IRQ off */
983 writel(0, port_mmio + PORT_IRQ_MASK);
984 }
985
986 static void ahci_thaw(struct ata_port *ap)
987 {
988 void __iomem *mmio = ap->host_set->mmio_base;
989 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
990 u32 tmp;
991
992 /* clear IRQ */
993 tmp = readl(port_mmio + PORT_IRQ_STAT);
994 writel(tmp, port_mmio + PORT_IRQ_STAT);
995 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
996
997 /* turn IRQ back on */
998 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
999 }
1000
1001 static void ahci_error_handler(struct ata_port *ap)
1002 {
1003 if (!(ap->flags & ATA_FLAG_FROZEN)) {
1004 /* restart engine */
1005 ahci_stop_engine(ap);
1006 ahci_start_engine(ap);
1007 }
1008
1009 /* perform recovery */
1010 ata_do_eh(ap, ahci_softreset, ahci_hardreset, ahci_postreset);
1011 }
1012
1013 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1014 {
1015 struct ata_port *ap = qc->ap;
1016
1017 if (qc->flags & ATA_QCFLAG_FAILED)
1018 qc->err_mask |= AC_ERR_OTHER;
1019
1020 if (qc->err_mask) {
1021 /* make DMA engine forget about the failed command */
1022 ahci_stop_engine(ap);
1023 ahci_start_engine(ap);
1024 }
1025 }
1026
1027 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1028 unsigned int port_idx)
1029 {
1030 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1031 base = ahci_port_base_ul(base, port_idx);
1032 VPRINTK("base now==0x%lx\n", base);
1033
1034 port->cmd_addr = base;
1035 port->scr_addr = base + PORT_SCR;
1036
1037 VPRINTK("EXIT\n");
1038 }
1039
1040 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1041 {
1042 struct ahci_host_priv *hpriv = probe_ent->private_data;
1043 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1044 void __iomem *mmio = probe_ent->mmio_base;
1045 u32 tmp, cap_save;
1046 unsigned int i, j, using_dac;
1047 int rc;
1048 void __iomem *port_mmio;
1049
1050 cap_save = readl(mmio + HOST_CAP);
1051 cap_save &= ( (1<<28) | (1<<17) );
1052 cap_save |= (1 << 27);
1053
1054 /* global controller reset */
1055 tmp = readl(mmio + HOST_CTL);
1056 if ((tmp & HOST_RESET) == 0) {
1057 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1058 readl(mmio + HOST_CTL); /* flush */
1059 }
1060
1061 /* reset must complete within 1 second, or
1062 * the hardware should be considered fried.
1063 */
1064 ssleep(1);
1065
1066 tmp = readl(mmio + HOST_CTL);
1067 if (tmp & HOST_RESET) {
1068 dev_printk(KERN_ERR, &pdev->dev,
1069 "controller reset failed (0x%x)\n", tmp);
1070 return -EIO;
1071 }
1072
1073 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1074 (void) readl(mmio + HOST_CTL); /* flush */
1075 writel(cap_save, mmio + HOST_CAP);
1076 writel(0xf, mmio + HOST_PORTS_IMPL);
1077 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1078
1079 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1080 u16 tmp16;
1081
1082 pci_read_config_word(pdev, 0x92, &tmp16);
1083 tmp16 |= 0xf;
1084 pci_write_config_word(pdev, 0x92, tmp16);
1085 }
1086
1087 hpriv->cap = readl(mmio + HOST_CAP);
1088 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1089 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1090
1091 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1092 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1093
1094 using_dac = hpriv->cap & HOST_CAP_64;
1095 if (using_dac &&
1096 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1097 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1098 if (rc) {
1099 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1100 if (rc) {
1101 dev_printk(KERN_ERR, &pdev->dev,
1102 "64-bit DMA enable failed\n");
1103 return rc;
1104 }
1105 }
1106 } else {
1107 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1108 if (rc) {
1109 dev_printk(KERN_ERR, &pdev->dev,
1110 "32-bit DMA enable failed\n");
1111 return rc;
1112 }
1113 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1114 if (rc) {
1115 dev_printk(KERN_ERR, &pdev->dev,
1116 "32-bit consistent DMA enable failed\n");
1117 return rc;
1118 }
1119 }
1120
1121 for (i = 0; i < probe_ent->n_ports; i++) {
1122 #if 0 /* BIOSen initialize this incorrectly */
1123 if (!(hpriv->port_map & (1 << i)))
1124 continue;
1125 #endif
1126
1127 port_mmio = ahci_port_base(mmio, i);
1128 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
1129
1130 ahci_setup_port(&probe_ent->port[i],
1131 (unsigned long) mmio, i);
1132
1133 /* make sure port is not active */
1134 tmp = readl(port_mmio + PORT_CMD);
1135 VPRINTK("PORT_CMD 0x%x\n", tmp);
1136 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1137 PORT_CMD_FIS_RX | PORT_CMD_START)) {
1138 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1139 PORT_CMD_FIS_RX | PORT_CMD_START);
1140 writel(tmp, port_mmio + PORT_CMD);
1141 readl(port_mmio + PORT_CMD); /* flush */
1142
1143 /* spec says 500 msecs for each bit, so
1144 * this is slightly incorrect.
1145 */
1146 msleep(500);
1147 }
1148
1149 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
1150
1151 j = 0;
1152 while (j < 100) {
1153 msleep(10);
1154 tmp = readl(port_mmio + PORT_SCR_STAT);
1155 if ((tmp & 0xf) == 0x3)
1156 break;
1157 j++;
1158 }
1159
1160 tmp = readl(port_mmio + PORT_SCR_ERR);
1161 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1162 writel(tmp, port_mmio + PORT_SCR_ERR);
1163
1164 /* ack any pending irq events for this port */
1165 tmp = readl(port_mmio + PORT_IRQ_STAT);
1166 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1167 if (tmp)
1168 writel(tmp, port_mmio + PORT_IRQ_STAT);
1169
1170 writel(1 << i, mmio + HOST_IRQ_STAT);
1171 }
1172
1173 tmp = readl(mmio + HOST_CTL);
1174 VPRINTK("HOST_CTL 0x%x\n", tmp);
1175 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1176 tmp = readl(mmio + HOST_CTL);
1177 VPRINTK("HOST_CTL 0x%x\n", tmp);
1178
1179 pci_set_master(pdev);
1180
1181 return 0;
1182 }
1183
1184 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1185 {
1186 struct ahci_host_priv *hpriv = probe_ent->private_data;
1187 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1188 void __iomem *mmio = probe_ent->mmio_base;
1189 u32 vers, cap, impl, speed;
1190 const char *speed_s;
1191 u16 cc;
1192 const char *scc_s;
1193
1194 vers = readl(mmio + HOST_VERSION);
1195 cap = hpriv->cap;
1196 impl = hpriv->port_map;
1197
1198 speed = (cap >> 20) & 0xf;
1199 if (speed == 1)
1200 speed_s = "1.5";
1201 else if (speed == 2)
1202 speed_s = "3";
1203 else
1204 speed_s = "?";
1205
1206 pci_read_config_word(pdev, 0x0a, &cc);
1207 if (cc == 0x0101)
1208 scc_s = "IDE";
1209 else if (cc == 0x0106)
1210 scc_s = "SATA";
1211 else if (cc == 0x0104)
1212 scc_s = "RAID";
1213 else
1214 scc_s = "unknown";
1215
1216 dev_printk(KERN_INFO, &pdev->dev,
1217 "AHCI %02x%02x.%02x%02x "
1218 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1219 ,
1220
1221 (vers >> 24) & 0xff,
1222 (vers >> 16) & 0xff,
1223 (vers >> 8) & 0xff,
1224 vers & 0xff,
1225
1226 ((cap >> 8) & 0x1f) + 1,
1227 (cap & 0x1f) + 1,
1228 speed_s,
1229 impl,
1230 scc_s);
1231
1232 dev_printk(KERN_INFO, &pdev->dev,
1233 "flags: "
1234 "%s%s%s%s%s%s"
1235 "%s%s%s%s%s%s%s\n"
1236 ,
1237
1238 cap & (1 << 31) ? "64bit " : "",
1239 cap & (1 << 30) ? "ncq " : "",
1240 cap & (1 << 28) ? "ilck " : "",
1241 cap & (1 << 27) ? "stag " : "",
1242 cap & (1 << 26) ? "pm " : "",
1243 cap & (1 << 25) ? "led " : "",
1244
1245 cap & (1 << 24) ? "clo " : "",
1246 cap & (1 << 19) ? "nz " : "",
1247 cap & (1 << 18) ? "only " : "",
1248 cap & (1 << 17) ? "pmp " : "",
1249 cap & (1 << 15) ? "pio " : "",
1250 cap & (1 << 14) ? "slum " : "",
1251 cap & (1 << 13) ? "part " : ""
1252 );
1253 }
1254
1255 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1256 {
1257 static int printed_version;
1258 struct ata_probe_ent *probe_ent = NULL;
1259 struct ahci_host_priv *hpriv;
1260 unsigned long base;
1261 void __iomem *mmio_base;
1262 unsigned int board_idx = (unsigned int) ent->driver_data;
1263 int have_msi, pci_dev_busy = 0;
1264 int rc;
1265
1266 VPRINTK("ENTER\n");
1267
1268 if (!printed_version++)
1269 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1270
1271 rc = pci_enable_device(pdev);
1272 if (rc)
1273 return rc;
1274
1275 rc = pci_request_regions(pdev, DRV_NAME);
1276 if (rc) {
1277 pci_dev_busy = 1;
1278 goto err_out;
1279 }
1280
1281 if (pci_enable_msi(pdev) == 0)
1282 have_msi = 1;
1283 else {
1284 pci_intx(pdev, 1);
1285 have_msi = 0;
1286 }
1287
1288 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1289 if (probe_ent == NULL) {
1290 rc = -ENOMEM;
1291 goto err_out_msi;
1292 }
1293
1294 memset(probe_ent, 0, sizeof(*probe_ent));
1295 probe_ent->dev = pci_dev_to_dev(pdev);
1296 INIT_LIST_HEAD(&probe_ent->node);
1297
1298 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1299 if (mmio_base == NULL) {
1300 rc = -ENOMEM;
1301 goto err_out_free_ent;
1302 }
1303 base = (unsigned long) mmio_base;
1304
1305 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1306 if (!hpriv) {
1307 rc = -ENOMEM;
1308 goto err_out_iounmap;
1309 }
1310 memset(hpriv, 0, sizeof(*hpriv));
1311
1312 probe_ent->sht = ahci_port_info[board_idx].sht;
1313 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1314 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1315 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1316 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1317
1318 probe_ent->irq = pdev->irq;
1319 probe_ent->irq_flags = SA_SHIRQ;
1320 probe_ent->mmio_base = mmio_base;
1321 probe_ent->private_data = hpriv;
1322
1323 if (have_msi)
1324 hpriv->flags |= AHCI_FLAG_MSI;
1325
1326 /* JMicron-specific fixup: make sure we're in AHCI mode */
1327 if (pdev->vendor == 0x197b)
1328 pci_write_config_byte(pdev, 0x41, 0xa1);
1329
1330 /* initialize adapter */
1331 rc = ahci_host_init(probe_ent);
1332 if (rc)
1333 goto err_out_hpriv;
1334
1335 ahci_print_info(probe_ent);
1336
1337 /* FIXME: check ata_device_add return value */
1338 ata_device_add(probe_ent);
1339 kfree(probe_ent);
1340
1341 return 0;
1342
1343 err_out_hpriv:
1344 kfree(hpriv);
1345 err_out_iounmap:
1346 pci_iounmap(pdev, mmio_base);
1347 err_out_free_ent:
1348 kfree(probe_ent);
1349 err_out_msi:
1350 if (have_msi)
1351 pci_disable_msi(pdev);
1352 else
1353 pci_intx(pdev, 0);
1354 pci_release_regions(pdev);
1355 err_out:
1356 if (!pci_dev_busy)
1357 pci_disable_device(pdev);
1358 return rc;
1359 }
1360
1361 static void ahci_remove_one (struct pci_dev *pdev)
1362 {
1363 struct device *dev = pci_dev_to_dev(pdev);
1364 struct ata_host_set *host_set = dev_get_drvdata(dev);
1365 struct ahci_host_priv *hpriv = host_set->private_data;
1366 struct ata_port *ap;
1367 unsigned int i;
1368 int have_msi;
1369
1370 for (i = 0; i < host_set->n_ports; i++) {
1371 ap = host_set->ports[i];
1372
1373 scsi_remove_host(ap->host);
1374 }
1375
1376 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1377 free_irq(host_set->irq, host_set);
1378
1379 for (i = 0; i < host_set->n_ports; i++) {
1380 ap = host_set->ports[i];
1381
1382 ata_scsi_release(ap->host);
1383 scsi_host_put(ap->host);
1384 }
1385
1386 kfree(hpriv);
1387 pci_iounmap(pdev, host_set->mmio_base);
1388 kfree(host_set);
1389
1390 if (have_msi)
1391 pci_disable_msi(pdev);
1392 else
1393 pci_intx(pdev, 0);
1394 pci_release_regions(pdev);
1395 pci_disable_device(pdev);
1396 dev_set_drvdata(dev, NULL);
1397 }
1398
1399 static int __init ahci_init(void)
1400 {
1401 return pci_module_init(&ahci_pci_driver);
1402 }
1403
1404 static void __exit ahci_exit(void)
1405 {
1406 pci_unregister_driver(&ahci_pci_driver);
1407 }
1408
1409
1410 MODULE_AUTHOR("Jeff Garzik");
1411 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1412 MODULE_LICENSE("GPL");
1413 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1414 MODULE_VERSION(DRV_VERSION);
1415
1416 module_init(ahci_init);
1417 module_exit(ahci_exit);
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