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1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include <asm/io.h>
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.2"
52
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_RX_FIS_SZ = 256,
61 AHCI_CMD_TBL_HDR = 0x80,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_RX_FIS_SZ,
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
69
70 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
71
72 board_ahci = 0,
73
74 /* global controller registers */
75 HOST_CAP = 0x00, /* host capabilities */
76 HOST_CTL = 0x04, /* global host control */
77 HOST_IRQ_STAT = 0x08, /* interrupt status */
78 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
79 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
80
81 /* HOST_CTL bits */
82 HOST_RESET = (1 << 0), /* reset controller; self-clear */
83 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
84 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
85
86 /* HOST_CAP bits */
87 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
88
89 /* registers for each SATA port */
90 PORT_LST_ADDR = 0x00, /* command list DMA addr */
91 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
92 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
93 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
94 PORT_IRQ_STAT = 0x10, /* interrupt status */
95 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
96 PORT_CMD = 0x18, /* port command */
97 PORT_TFDATA = 0x20, /* taskfile data */
98 PORT_SIG = 0x24, /* device TF signature */
99 PORT_CMD_ISSUE = 0x38, /* command issue */
100 PORT_SCR = 0x28, /* SATA phy register block */
101 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
102 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
103 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
104 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
105
106 /* PORT_IRQ_{STAT,MASK} bits */
107 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
108 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
109 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
110 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
111 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
112 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
113 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
114 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
115
116 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
117 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
118 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
119 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
120 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
121 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
122 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
123 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
124 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
125
126 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
127 PORT_IRQ_HBUS_ERR |
128 PORT_IRQ_HBUS_DATA_ERR |
129 PORT_IRQ_IF_ERR,
130 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
131 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
132 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
133 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
134 PORT_IRQ_D2H_REG_FIS,
135
136 /* PORT_CMD bits */
137 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
138 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
139 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
140 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
141 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
142 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
143 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
144
145 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
146 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
147 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
148
149 /* hpriv->flags bits */
150 AHCI_FLAG_MSI = (1 << 0),
151 };
152
153 struct ahci_cmd_hdr {
154 u32 opts;
155 u32 status;
156 u32 tbl_addr;
157 u32 tbl_addr_hi;
158 u32 reserved[4];
159 };
160
161 struct ahci_sg {
162 u32 addr;
163 u32 addr_hi;
164 u32 reserved;
165 u32 flags_size;
166 };
167
168 struct ahci_host_priv {
169 unsigned long flags;
170 u32 cap; /* cache of HOST_CAP register */
171 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
172 };
173
174 struct ahci_port_priv {
175 struct ahci_cmd_hdr *cmd_slot;
176 dma_addr_t cmd_slot_dma;
177 void *cmd_tbl;
178 dma_addr_t cmd_tbl_dma;
179 struct ahci_sg *cmd_tbl_sg;
180 void *rx_fis;
181 dma_addr_t rx_fis_dma;
182 };
183
184 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
185 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
186 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
187 static int ahci_qc_issue(struct ata_queued_cmd *qc);
188 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
189 static void ahci_phy_reset(struct ata_port *ap);
190 static void ahci_irq_clear(struct ata_port *ap);
191 static void ahci_eng_timeout(struct ata_port *ap);
192 static int ahci_port_start(struct ata_port *ap);
193 static void ahci_port_stop(struct ata_port *ap);
194 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
195 static void ahci_qc_prep(struct ata_queued_cmd *qc);
196 static u8 ahci_check_status(struct ata_port *ap);
197 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
198 static void ahci_remove_one (struct pci_dev *pdev);
199
200 static struct scsi_host_template ahci_sht = {
201 .module = THIS_MODULE,
202 .name = DRV_NAME,
203 .ioctl = ata_scsi_ioctl,
204 .queuecommand = ata_scsi_queuecmd,
205 .eh_strategy_handler = ata_scsi_error,
206 .can_queue = ATA_DEF_QUEUE,
207 .this_id = ATA_SHT_THIS_ID,
208 .sg_tablesize = AHCI_MAX_SG,
209 .max_sectors = ATA_MAX_SECTORS,
210 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
211 .emulated = ATA_SHT_EMULATED,
212 .use_clustering = AHCI_USE_CLUSTERING,
213 .proc_name = DRV_NAME,
214 .dma_boundary = AHCI_DMA_BOUNDARY,
215 .slave_configure = ata_scsi_slave_config,
216 .bios_param = ata_std_bios_param,
217 };
218
219 static const struct ata_port_operations ahci_ops = {
220 .port_disable = ata_port_disable,
221
222 .check_status = ahci_check_status,
223 .check_altstatus = ahci_check_status,
224 .dev_select = ata_noop_dev_select,
225
226 .tf_read = ahci_tf_read,
227
228 .phy_reset = ahci_phy_reset,
229
230 .qc_prep = ahci_qc_prep,
231 .qc_issue = ahci_qc_issue,
232
233 .eng_timeout = ahci_eng_timeout,
234
235 .irq_handler = ahci_interrupt,
236 .irq_clear = ahci_irq_clear,
237
238 .scr_read = ahci_scr_read,
239 .scr_write = ahci_scr_write,
240
241 .port_start = ahci_port_start,
242 .port_stop = ahci_port_stop,
243 };
244
245 static const struct ata_port_info ahci_port_info[] = {
246 /* board_ahci */
247 {
248 .sht = &ahci_sht,
249 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
250 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
251 ATA_FLAG_PIO_DMA,
252 .pio_mask = 0x1f, /* pio0-4 */
253 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
254 .port_ops = &ahci_ops,
255 },
256 };
257
258 static const struct pci_device_id ahci_pci_tbl[] = {
259 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
260 board_ahci }, /* ICH6 */
261 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
262 board_ahci }, /* ICH6M */
263 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
264 board_ahci }, /* ICH7 */
265 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
266 board_ahci }, /* ICH7M */
267 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 board_ahci }, /* ICH7R */
269 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
270 board_ahci }, /* ULi M5288 */
271 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
272 board_ahci }, /* ESB2 */
273 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
274 board_ahci }, /* ESB2 */
275 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
276 board_ahci }, /* ESB2 */
277 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
278 board_ahci }, /* ICH7-M DH */
279 { } /* terminate list */
280 };
281
282
283 static struct pci_driver ahci_pci_driver = {
284 .name = DRV_NAME,
285 .id_table = ahci_pci_tbl,
286 .probe = ahci_init_one,
287 .remove = ahci_remove_one,
288 };
289
290
291 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
292 {
293 return base + 0x100 + (port * 0x80);
294 }
295
296 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
297 {
298 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
299 }
300
301 static int ahci_port_start(struct ata_port *ap)
302 {
303 struct device *dev = ap->host_set->dev;
304 struct ahci_host_priv *hpriv = ap->host_set->private_data;
305 struct ahci_port_priv *pp;
306 void __iomem *mmio = ap->host_set->mmio_base;
307 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
308 void *mem;
309 dma_addr_t mem_dma;
310 int rc;
311
312 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
313 if (!pp)
314 return -ENOMEM;
315 memset(pp, 0, sizeof(*pp));
316
317 rc = ata_pad_alloc(ap, dev);
318 if (rc) {
319 kfree(pp);
320 return rc;
321 }
322
323 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
324 if (!mem) {
325 ata_pad_free(ap, dev);
326 kfree(pp);
327 return -ENOMEM;
328 }
329 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
330
331 /*
332 * First item in chunk of DMA memory: 32-slot command table,
333 * 32 bytes each in size
334 */
335 pp->cmd_slot = mem;
336 pp->cmd_slot_dma = mem_dma;
337
338 mem += AHCI_CMD_SLOT_SZ;
339 mem_dma += AHCI_CMD_SLOT_SZ;
340
341 /*
342 * Second item: Received-FIS area
343 */
344 pp->rx_fis = mem;
345 pp->rx_fis_dma = mem_dma;
346
347 mem += AHCI_RX_FIS_SZ;
348 mem_dma += AHCI_RX_FIS_SZ;
349
350 /*
351 * Third item: data area for storing a single command
352 * and its scatter-gather table
353 */
354 pp->cmd_tbl = mem;
355 pp->cmd_tbl_dma = mem_dma;
356
357 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
358
359 ap->private_data = pp;
360
361 if (hpriv->cap & HOST_CAP_64)
362 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
363 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
364 readl(port_mmio + PORT_LST_ADDR); /* flush */
365
366 if (hpriv->cap & HOST_CAP_64)
367 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
368 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
369 readl(port_mmio + PORT_FIS_ADDR); /* flush */
370
371 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
372 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
373 PORT_CMD_START, port_mmio + PORT_CMD);
374 readl(port_mmio + PORT_CMD); /* flush */
375
376 return 0;
377 }
378
379
380 static void ahci_port_stop(struct ata_port *ap)
381 {
382 struct device *dev = ap->host_set->dev;
383 struct ahci_port_priv *pp = ap->private_data;
384 void __iomem *mmio = ap->host_set->mmio_base;
385 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
386 u32 tmp;
387
388 tmp = readl(port_mmio + PORT_CMD);
389 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
390 writel(tmp, port_mmio + PORT_CMD);
391 readl(port_mmio + PORT_CMD); /* flush */
392
393 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
394 * this is slightly incorrect.
395 */
396 msleep(500);
397
398 ap->private_data = NULL;
399 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
400 pp->cmd_slot, pp->cmd_slot_dma);
401 ata_pad_free(ap, dev);
402 kfree(pp);
403 }
404
405 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
406 {
407 unsigned int sc_reg;
408
409 switch (sc_reg_in) {
410 case SCR_STATUS: sc_reg = 0; break;
411 case SCR_CONTROL: sc_reg = 1; break;
412 case SCR_ERROR: sc_reg = 2; break;
413 case SCR_ACTIVE: sc_reg = 3; break;
414 default:
415 return 0xffffffffU;
416 }
417
418 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
419 }
420
421
422 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
423 u32 val)
424 {
425 unsigned int sc_reg;
426
427 switch (sc_reg_in) {
428 case SCR_STATUS: sc_reg = 0; break;
429 case SCR_CONTROL: sc_reg = 1; break;
430 case SCR_ERROR: sc_reg = 2; break;
431 case SCR_ACTIVE: sc_reg = 3; break;
432 default:
433 return;
434 }
435
436 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
437 }
438
439 static void ahci_phy_reset(struct ata_port *ap)
440 {
441 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
442 struct ata_taskfile tf;
443 struct ata_device *dev = &ap->device[0];
444 u32 new_tmp, tmp;
445
446 __sata_phy_reset(ap);
447
448 if (ap->flags & ATA_FLAG_PORT_DISABLED)
449 return;
450
451 tmp = readl(port_mmio + PORT_SIG);
452 tf.lbah = (tmp >> 24) & 0xff;
453 tf.lbam = (tmp >> 16) & 0xff;
454 tf.lbal = (tmp >> 8) & 0xff;
455 tf.nsect = (tmp) & 0xff;
456
457 dev->class = ata_dev_classify(&tf);
458 if (!ata_dev_present(dev)) {
459 ata_port_disable(ap);
460 return;
461 }
462
463 /* Make sure port's ATAPI bit is set appropriately */
464 new_tmp = tmp = readl(port_mmio + PORT_CMD);
465 if (dev->class == ATA_DEV_ATAPI)
466 new_tmp |= PORT_CMD_ATAPI;
467 else
468 new_tmp &= ~PORT_CMD_ATAPI;
469 if (new_tmp != tmp) {
470 writel(new_tmp, port_mmio + PORT_CMD);
471 readl(port_mmio + PORT_CMD); /* flush */
472 }
473 }
474
475 static u8 ahci_check_status(struct ata_port *ap)
476 {
477 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
478
479 return readl(mmio + PORT_TFDATA) & 0xFF;
480 }
481
482 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
483 {
484 struct ahci_port_priv *pp = ap->private_data;
485 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
486
487 ata_tf_from_fis(d2h_fis, tf);
488 }
489
490 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
491 {
492 struct ahci_port_priv *pp = qc->ap->private_data;
493 struct scatterlist *sg;
494 struct ahci_sg *ahci_sg;
495 unsigned int n_sg = 0;
496
497 VPRINTK("ENTER\n");
498
499 /*
500 * Next, the S/G list.
501 */
502 ahci_sg = pp->cmd_tbl_sg;
503 ata_for_each_sg(sg, qc) {
504 dma_addr_t addr = sg_dma_address(sg);
505 u32 sg_len = sg_dma_len(sg);
506
507 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
508 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
509 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
510
511 ahci_sg++;
512 n_sg++;
513 }
514
515 return n_sg;
516 }
517
518 static void ahci_qc_prep(struct ata_queued_cmd *qc)
519 {
520 struct ata_port *ap = qc->ap;
521 struct ahci_port_priv *pp = ap->private_data;
522 u32 opts;
523 const u32 cmd_fis_len = 5; /* five dwords */
524 unsigned int n_elem;
525
526 /*
527 * Fill in command slot information (currently only one slot,
528 * slot 0, is currently since we don't do queueing)
529 */
530
531 opts = cmd_fis_len;
532 if (qc->tf.flags & ATA_TFLAG_WRITE)
533 opts |= AHCI_CMD_WRITE;
534 if (is_atapi_taskfile(&qc->tf))
535 opts |= AHCI_CMD_ATAPI;
536
537 pp->cmd_slot[0].opts = cpu_to_le32(opts);
538 pp->cmd_slot[0].status = 0;
539 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
540 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
541
542 /*
543 * Fill in command table information. First, the header,
544 * a SATA Register - Host to Device command FIS.
545 */
546 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
547 if (opts & AHCI_CMD_ATAPI) {
548 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
549 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
550 }
551
552 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
553 return;
554
555 n_elem = ahci_fill_sg(qc);
556
557 pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16);
558 }
559
560 static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
561 {
562 void __iomem *mmio = ap->host_set->mmio_base;
563 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
564 u32 tmp;
565 int work;
566
567 if ((ap->device[0].class != ATA_DEV_ATAPI) ||
568 ((irq_stat & PORT_IRQ_TF_ERR) == 0))
569 printk(KERN_WARNING "ata%u: port reset, "
570 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
571 ap->id,
572 irq_stat,
573 readl(mmio + HOST_IRQ_STAT),
574 readl(port_mmio + PORT_IRQ_STAT),
575 readl(port_mmio + PORT_CMD),
576 readl(port_mmio + PORT_TFDATA),
577 readl(port_mmio + PORT_SCR_STAT),
578 readl(port_mmio + PORT_SCR_ERR));
579
580 /* stop DMA */
581 tmp = readl(port_mmio + PORT_CMD);
582 tmp &= ~PORT_CMD_START;
583 writel(tmp, port_mmio + PORT_CMD);
584
585 /* wait for engine to stop. TODO: this could be
586 * as long as 500 msec
587 */
588 work = 1000;
589 while (work-- > 0) {
590 tmp = readl(port_mmio + PORT_CMD);
591 if ((tmp & PORT_CMD_LIST_ON) == 0)
592 break;
593 udelay(10);
594 }
595
596 /* clear SATA phy error, if any */
597 tmp = readl(port_mmio + PORT_SCR_ERR);
598 writel(tmp, port_mmio + PORT_SCR_ERR);
599
600 /* if DRQ/BSY is set, device needs to be reset.
601 * if so, issue COMRESET
602 */
603 tmp = readl(port_mmio + PORT_TFDATA);
604 if (tmp & (ATA_BUSY | ATA_DRQ)) {
605 writel(0x301, port_mmio + PORT_SCR_CTL);
606 readl(port_mmio + PORT_SCR_CTL); /* flush */
607 udelay(10);
608 writel(0x300, port_mmio + PORT_SCR_CTL);
609 readl(port_mmio + PORT_SCR_CTL); /* flush */
610 }
611
612 /* re-start DMA */
613 tmp = readl(port_mmio + PORT_CMD);
614 tmp |= PORT_CMD_START;
615 writel(tmp, port_mmio + PORT_CMD);
616 readl(port_mmio + PORT_CMD); /* flush */
617 }
618
619 static void ahci_eng_timeout(struct ata_port *ap)
620 {
621 struct ata_host_set *host_set = ap->host_set;
622 void __iomem *mmio = host_set->mmio_base;
623 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
624 struct ata_queued_cmd *qc;
625 unsigned long flags;
626
627 printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id);
628
629 spin_lock_irqsave(&host_set->lock, flags);
630
631 qc = ata_qc_from_tag(ap, ap->active_tag);
632 if (!qc) {
633 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
634 ap->id);
635 } else {
636 ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT));
637
638 /* hack alert! We cannot use the supplied completion
639 * function from inside the ->eh_strategy_handler() thread.
640 * libata is the only user of ->eh_strategy_handler() in
641 * any kernel, so the default scsi_done() assumes it is
642 * not being called from the SCSI EH.
643 */
644 qc->scsidone = scsi_finish_command;
645 qc->err_mask |= AC_ERR_OTHER;
646 ata_qc_complete(qc);
647 }
648
649 spin_unlock_irqrestore(&host_set->lock, flags);
650 }
651
652 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
653 {
654 void __iomem *mmio = ap->host_set->mmio_base;
655 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
656 u32 status, serr, ci;
657
658 serr = readl(port_mmio + PORT_SCR_ERR);
659 writel(serr, port_mmio + PORT_SCR_ERR);
660
661 status = readl(port_mmio + PORT_IRQ_STAT);
662 writel(status, port_mmio + PORT_IRQ_STAT);
663
664 ci = readl(port_mmio + PORT_CMD_ISSUE);
665 if (likely((ci & 0x1) == 0)) {
666 if (qc) {
667 assert(qc->err_mask == 0);
668 ata_qc_complete(qc);
669 qc = NULL;
670 }
671 }
672
673 if (status & PORT_IRQ_FATAL) {
674 unsigned int err_mask;
675 if (status & PORT_IRQ_TF_ERR)
676 err_mask = AC_ERR_DEV;
677 else if (status & PORT_IRQ_IF_ERR)
678 err_mask = AC_ERR_ATA_BUS;
679 else
680 err_mask = AC_ERR_HOST_BUS;
681
682 /* command processing has stopped due to error; restart */
683 ahci_restart_port(ap, status);
684
685 if (qc) {
686 qc->err_mask |= AC_ERR_OTHER;
687 ata_qc_complete(qc);
688 }
689 }
690
691 return 1;
692 }
693
694 static void ahci_irq_clear(struct ata_port *ap)
695 {
696 /* TODO */
697 }
698
699 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
700 {
701 struct ata_host_set *host_set = dev_instance;
702 struct ahci_host_priv *hpriv;
703 unsigned int i, handled = 0;
704 void __iomem *mmio;
705 u32 irq_stat, irq_ack = 0;
706
707 VPRINTK("ENTER\n");
708
709 hpriv = host_set->private_data;
710 mmio = host_set->mmio_base;
711
712 /* sigh. 0xffffffff is a valid return from h/w */
713 irq_stat = readl(mmio + HOST_IRQ_STAT);
714 irq_stat &= hpriv->port_map;
715 if (!irq_stat)
716 return IRQ_NONE;
717
718 spin_lock(&host_set->lock);
719
720 for (i = 0; i < host_set->n_ports; i++) {
721 struct ata_port *ap;
722
723 if (!(irq_stat & (1 << i)))
724 continue;
725
726 ap = host_set->ports[i];
727 if (ap) {
728 struct ata_queued_cmd *qc;
729 qc = ata_qc_from_tag(ap, ap->active_tag);
730 if (!ahci_host_intr(ap, qc))
731 if (ata_ratelimit()) {
732 struct pci_dev *pdev =
733 to_pci_dev(ap->host_set->dev);
734 dev_printk(KERN_WARNING, &pdev->dev,
735 "unhandled interrupt on port %u\n",
736 i);
737 }
738
739 VPRINTK("port %u\n", i);
740 } else {
741 VPRINTK("port %u (no irq)\n", i);
742 if (ata_ratelimit()) {
743 struct pci_dev *pdev =
744 to_pci_dev(ap->host_set->dev);
745 dev_printk(KERN_WARNING, &pdev->dev,
746 "interrupt on disabled port %u\n", i);
747 }
748 }
749
750 irq_ack |= (1 << i);
751 }
752
753 if (irq_ack) {
754 writel(irq_ack, mmio + HOST_IRQ_STAT);
755 handled = 1;
756 }
757
758 spin_unlock(&host_set->lock);
759
760 VPRINTK("EXIT\n");
761
762 return IRQ_RETVAL(handled);
763 }
764
765 static int ahci_qc_issue(struct ata_queued_cmd *qc)
766 {
767 struct ata_port *ap = qc->ap;
768 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
769
770 writel(1, port_mmio + PORT_CMD_ISSUE);
771 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
772
773 return 0;
774 }
775
776 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
777 unsigned int port_idx)
778 {
779 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
780 base = ahci_port_base_ul(base, port_idx);
781 VPRINTK("base now==0x%lx\n", base);
782
783 port->cmd_addr = base;
784 port->scr_addr = base + PORT_SCR;
785
786 VPRINTK("EXIT\n");
787 }
788
789 static int ahci_host_init(struct ata_probe_ent *probe_ent)
790 {
791 struct ahci_host_priv *hpriv = probe_ent->private_data;
792 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
793 void __iomem *mmio = probe_ent->mmio_base;
794 u32 tmp, cap_save;
795 u16 tmp16;
796 unsigned int i, j, using_dac;
797 int rc;
798 void __iomem *port_mmio;
799
800 cap_save = readl(mmio + HOST_CAP);
801 cap_save &= ( (1<<28) | (1<<17) );
802 cap_save |= (1 << 27);
803
804 /* global controller reset */
805 tmp = readl(mmio + HOST_CTL);
806 if ((tmp & HOST_RESET) == 0) {
807 writel(tmp | HOST_RESET, mmio + HOST_CTL);
808 readl(mmio + HOST_CTL); /* flush */
809 }
810
811 /* reset must complete within 1 second, or
812 * the hardware should be considered fried.
813 */
814 ssleep(1);
815
816 tmp = readl(mmio + HOST_CTL);
817 if (tmp & HOST_RESET) {
818 dev_printk(KERN_ERR, &pdev->dev,
819 "controller reset failed (0x%x)\n", tmp);
820 return -EIO;
821 }
822
823 writel(HOST_AHCI_EN, mmio + HOST_CTL);
824 (void) readl(mmio + HOST_CTL); /* flush */
825 writel(cap_save, mmio + HOST_CAP);
826 writel(0xf, mmio + HOST_PORTS_IMPL);
827 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
828
829 pci_read_config_word(pdev, 0x92, &tmp16);
830 tmp16 |= 0xf;
831 pci_write_config_word(pdev, 0x92, tmp16);
832
833 hpriv->cap = readl(mmio + HOST_CAP);
834 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
835 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
836
837 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
838 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
839
840 using_dac = hpriv->cap & HOST_CAP_64;
841 if (using_dac &&
842 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
843 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
844 if (rc) {
845 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
846 if (rc) {
847 dev_printk(KERN_ERR, &pdev->dev,
848 "64-bit DMA enable failed\n");
849 return rc;
850 }
851 }
852 } else {
853 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
854 if (rc) {
855 dev_printk(KERN_ERR, &pdev->dev,
856 "32-bit DMA enable failed\n");
857 return rc;
858 }
859 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
860 if (rc) {
861 dev_printk(KERN_ERR, &pdev->dev,
862 "32-bit consistent DMA enable failed\n");
863 return rc;
864 }
865 }
866
867 for (i = 0; i < probe_ent->n_ports; i++) {
868 #if 0 /* BIOSen initialize this incorrectly */
869 if (!(hpriv->port_map & (1 << i)))
870 continue;
871 #endif
872
873 port_mmio = ahci_port_base(mmio, i);
874 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
875
876 ahci_setup_port(&probe_ent->port[i],
877 (unsigned long) mmio, i);
878
879 /* make sure port is not active */
880 tmp = readl(port_mmio + PORT_CMD);
881 VPRINTK("PORT_CMD 0x%x\n", tmp);
882 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
883 PORT_CMD_FIS_RX | PORT_CMD_START)) {
884 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
885 PORT_CMD_FIS_RX | PORT_CMD_START);
886 writel(tmp, port_mmio + PORT_CMD);
887 readl(port_mmio + PORT_CMD); /* flush */
888
889 /* spec says 500 msecs for each bit, so
890 * this is slightly incorrect.
891 */
892 msleep(500);
893 }
894
895 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
896
897 j = 0;
898 while (j < 100) {
899 msleep(10);
900 tmp = readl(port_mmio + PORT_SCR_STAT);
901 if ((tmp & 0xf) == 0x3)
902 break;
903 j++;
904 }
905
906 tmp = readl(port_mmio + PORT_SCR_ERR);
907 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
908 writel(tmp, port_mmio + PORT_SCR_ERR);
909
910 /* ack any pending irq events for this port */
911 tmp = readl(port_mmio + PORT_IRQ_STAT);
912 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
913 if (tmp)
914 writel(tmp, port_mmio + PORT_IRQ_STAT);
915
916 writel(1 << i, mmio + HOST_IRQ_STAT);
917
918 /* set irq mask (enables interrupts) */
919 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
920 }
921
922 tmp = readl(mmio + HOST_CTL);
923 VPRINTK("HOST_CTL 0x%x\n", tmp);
924 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
925 tmp = readl(mmio + HOST_CTL);
926 VPRINTK("HOST_CTL 0x%x\n", tmp);
927
928 pci_set_master(pdev);
929
930 return 0;
931 }
932
933 static void ahci_print_info(struct ata_probe_ent *probe_ent)
934 {
935 struct ahci_host_priv *hpriv = probe_ent->private_data;
936 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
937 void __iomem *mmio = probe_ent->mmio_base;
938 u32 vers, cap, impl, speed;
939 const char *speed_s;
940 u16 cc;
941 const char *scc_s;
942
943 vers = readl(mmio + HOST_VERSION);
944 cap = hpriv->cap;
945 impl = hpriv->port_map;
946
947 speed = (cap >> 20) & 0xf;
948 if (speed == 1)
949 speed_s = "1.5";
950 else if (speed == 2)
951 speed_s = "3";
952 else
953 speed_s = "?";
954
955 pci_read_config_word(pdev, 0x0a, &cc);
956 if (cc == 0x0101)
957 scc_s = "IDE";
958 else if (cc == 0x0106)
959 scc_s = "SATA";
960 else if (cc == 0x0104)
961 scc_s = "RAID";
962 else
963 scc_s = "unknown";
964
965 dev_printk(KERN_INFO, &pdev->dev,
966 "AHCI %02x%02x.%02x%02x "
967 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
968 ,
969
970 (vers >> 24) & 0xff,
971 (vers >> 16) & 0xff,
972 (vers >> 8) & 0xff,
973 vers & 0xff,
974
975 ((cap >> 8) & 0x1f) + 1,
976 (cap & 0x1f) + 1,
977 speed_s,
978 impl,
979 scc_s);
980
981 dev_printk(KERN_INFO, &pdev->dev,
982 "flags: "
983 "%s%s%s%s%s%s"
984 "%s%s%s%s%s%s%s\n"
985 ,
986
987 cap & (1 << 31) ? "64bit " : "",
988 cap & (1 << 30) ? "ncq " : "",
989 cap & (1 << 28) ? "ilck " : "",
990 cap & (1 << 27) ? "stag " : "",
991 cap & (1 << 26) ? "pm " : "",
992 cap & (1 << 25) ? "led " : "",
993
994 cap & (1 << 24) ? "clo " : "",
995 cap & (1 << 19) ? "nz " : "",
996 cap & (1 << 18) ? "only " : "",
997 cap & (1 << 17) ? "pmp " : "",
998 cap & (1 << 15) ? "pio " : "",
999 cap & (1 << 14) ? "slum " : "",
1000 cap & (1 << 13) ? "part " : ""
1001 );
1002 }
1003
1004 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1005 {
1006 static int printed_version;
1007 struct ata_probe_ent *probe_ent = NULL;
1008 struct ahci_host_priv *hpriv;
1009 unsigned long base;
1010 void __iomem *mmio_base;
1011 unsigned int board_idx = (unsigned int) ent->driver_data;
1012 int have_msi, pci_dev_busy = 0;
1013 int rc;
1014
1015 VPRINTK("ENTER\n");
1016
1017 if (!printed_version++)
1018 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1019
1020 rc = pci_enable_device(pdev);
1021 if (rc)
1022 return rc;
1023
1024 rc = pci_request_regions(pdev, DRV_NAME);
1025 if (rc) {
1026 pci_dev_busy = 1;
1027 goto err_out;
1028 }
1029
1030 if (pci_enable_msi(pdev) == 0)
1031 have_msi = 1;
1032 else {
1033 pci_intx(pdev, 1);
1034 have_msi = 0;
1035 }
1036
1037 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1038 if (probe_ent == NULL) {
1039 rc = -ENOMEM;
1040 goto err_out_msi;
1041 }
1042
1043 memset(probe_ent, 0, sizeof(*probe_ent));
1044 probe_ent->dev = pci_dev_to_dev(pdev);
1045 INIT_LIST_HEAD(&probe_ent->node);
1046
1047 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1048 if (mmio_base == NULL) {
1049 rc = -ENOMEM;
1050 goto err_out_free_ent;
1051 }
1052 base = (unsigned long) mmio_base;
1053
1054 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1055 if (!hpriv) {
1056 rc = -ENOMEM;
1057 goto err_out_iounmap;
1058 }
1059 memset(hpriv, 0, sizeof(*hpriv));
1060
1061 probe_ent->sht = ahci_port_info[board_idx].sht;
1062 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1063 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1064 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1065 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1066
1067 probe_ent->irq = pdev->irq;
1068 probe_ent->irq_flags = SA_SHIRQ;
1069 probe_ent->mmio_base = mmio_base;
1070 probe_ent->private_data = hpriv;
1071
1072 if (have_msi)
1073 hpriv->flags |= AHCI_FLAG_MSI;
1074
1075 /* initialize adapter */
1076 rc = ahci_host_init(probe_ent);
1077 if (rc)
1078 goto err_out_hpriv;
1079
1080 ahci_print_info(probe_ent);
1081
1082 /* FIXME: check ata_device_add return value */
1083 ata_device_add(probe_ent);
1084 kfree(probe_ent);
1085
1086 return 0;
1087
1088 err_out_hpriv:
1089 kfree(hpriv);
1090 err_out_iounmap:
1091 pci_iounmap(pdev, mmio_base);
1092 err_out_free_ent:
1093 kfree(probe_ent);
1094 err_out_msi:
1095 if (have_msi)
1096 pci_disable_msi(pdev);
1097 else
1098 pci_intx(pdev, 0);
1099 pci_release_regions(pdev);
1100 err_out:
1101 if (!pci_dev_busy)
1102 pci_disable_device(pdev);
1103 return rc;
1104 }
1105
1106 static void ahci_remove_one (struct pci_dev *pdev)
1107 {
1108 struct device *dev = pci_dev_to_dev(pdev);
1109 struct ata_host_set *host_set = dev_get_drvdata(dev);
1110 struct ahci_host_priv *hpriv = host_set->private_data;
1111 struct ata_port *ap;
1112 unsigned int i;
1113 int have_msi;
1114
1115 for (i = 0; i < host_set->n_ports; i++) {
1116 ap = host_set->ports[i];
1117
1118 scsi_remove_host(ap->host);
1119 }
1120
1121 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1122 free_irq(host_set->irq, host_set);
1123
1124 for (i = 0; i < host_set->n_ports; i++) {
1125 ap = host_set->ports[i];
1126
1127 ata_scsi_release(ap->host);
1128 scsi_host_put(ap->host);
1129 }
1130
1131 kfree(hpriv);
1132 pci_iounmap(pdev, host_set->mmio_base);
1133 kfree(host_set);
1134
1135 if (have_msi)
1136 pci_disable_msi(pdev);
1137 else
1138 pci_intx(pdev, 0);
1139 pci_release_regions(pdev);
1140 pci_disable_device(pdev);
1141 dev_set_drvdata(dev, NULL);
1142 }
1143
1144 static int __init ahci_init(void)
1145 {
1146 return pci_module_init(&ahci_pci_driver);
1147 }
1148
1149 static void __exit ahci_exit(void)
1150 {
1151 pci_unregister_driver(&ahci_pci_driver);
1152 }
1153
1154
1155 MODULE_AUTHOR("Jeff Garzik");
1156 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1157 MODULE_LICENSE("GPL");
1158 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1159 MODULE_VERSION(DRV_VERSION);
1160
1161 module_init(ahci_init);
1162 module_exit(ahci_exit);