drivers/scsi/arm/fas216.h

   1 /*
   2  *  linux/drivers/acorn/scsi/fas216.h
   3  *
   4  *  Copyright (C) 1997-2000 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  FAS216 generic driver
  11  */
  12 #ifndef FAS216_H
  13 #define FAS216_H
  14
  15 #ifndef NO_IRQ
  16 #define NO_IRQ 255
  17 #endif
  18
  19 #include <scsi/scsi_eh.h>
  20
  21 #include "queue.h"
  22 #include "msgqueue.h"
  23
  24 /* FAS register definitions */
  25
  26 /* transfer count low */
  27 #define REG_CTCL                (0)
  28 #define REG_STCL                (0)
  29
  30 /* transfer count medium */
  31 #define REG_CTCM                (1)
  32 #define REG_STCM                (1)
  33
  34 /* fifo data */
  35 #define REG_FF                  (2)
  36
  37 /* command */
  38 #define REG_CMD                 (3)
  39 #define CMD_NOP                 0x00
  40 #define CMD_FLUSHFIFO           0x01
  41 #define CMD_RESETCHIP           0x02
  42 #define CMD_RESETSCSI           0x03
  43
  44 #define CMD_TRANSFERINFO        0x10
  45 #define CMD_INITCMDCOMPLETE     0x11
  46 #define CMD_MSGACCEPTED         0x12
  47 #define CMD_PADBYTES            0x18
  48 #define CMD_SETATN              0x1a
  49 #define CMD_RSETATN             0x1b
  50
  51 #define CMD_SELECTWOATN         0x41
  52 #define CMD_SELECTATN           0x42
  53 #define CMD_SELECTATNSTOP       0x43
  54 #define CMD_ENABLESEL           0x44
  55 #define CMD_DISABLESEL          0x45
  56 #define CMD_SELECTATN3          0x46
  57 #define CMD_RESEL3              0x47
  58
  59 #define CMD_WITHDMA             0x80
  60
  61 /* status register (read) */
  62 #define REG_STAT                (4)
  63 #define STAT_IO                 (1 << 0)                        /* IO phase             */
  64 #define STAT_CD                 (1 << 1)                        /* CD phase             */
  65 #define STAT_MSG                (1 << 2)                        /* MSG phase            */
  66 #define STAT_TRANSFERDONE       (1 << 3)                        /* Transfer completed   */
  67 #define STAT_TRANSFERCNTZ       (1 << 4)                        /* Transfer counter is zero */
  68 #define STAT_PARITYERROR        (1 << 5)                        /* Parity error         */
  69 #define STAT_REALBAD            (1 << 6)                        /* Something bad        */
  70 #define STAT_INT                (1 << 7)                        /* Interrupt            */
  71
  72 #define STAT_BUSMASK            (STAT_MSG|STAT_CD|STAT_IO)
  73 #define STAT_DATAOUT            (0)                             /* Data out             */
  74 #define STAT_DATAIN             (STAT_IO)                       /* Data in              */
  75 #define STAT_COMMAND            (STAT_CD)                       /* Command out          */
  76 #define STAT_STATUS             (STAT_CD|STAT_IO)               /* Status In            */
  77 #define STAT_MESGOUT            (STAT_MSG|STAT_CD)              /* Message out          */
  78 #define STAT_MESGIN             (STAT_MSG|STAT_CD|STAT_IO)      /* Message In           */
  79
  80 /* bus ID for select / reselect */
  81 #define REG_SDID                (4)
  82 #define BUSID(target)           ((target) & 7)
  83
  84 /* Interrupt status register (read) */
  85 #define REG_INST                (5)
  86 #define INST_SELWOATN           (1 << 0)                        /* Select w/o ATN       */
  87 #define INST_SELATN             (1 << 1)                        /* Select w/ATN         */
  88 #define INST_RESELECTED         (1 << 2)                        /* Reselected           */
  89 #define INST_FUNCDONE           (1 << 3)                        /* Function done        */
  90 #define INST_BUSSERVICE         (1 << 4)                        /* Bus service          */
  91 #define INST_DISCONNECT         (1 << 5)                        /* Disconnect           */
  92 #define INST_ILLEGALCMD         (1 << 6)                        /* Illegal command      */
  93 #define INST_BUSRESET           (1 << 7)                        /* SCSI Bus reset       */
  94
  95 /* Timeout register (write) */
  96 #define REG_STIM                (5)
  97
  98 /* Sequence step register (read) */
  99 #define REG_IS                  (6)
 100 #define IS_BITS                 0x07
 101 #define IS_SELARB               0x00                            /* Select & Arb ok      */
 102 #define IS_MSGBYTESENT          0x01                            /* One byte message sent*/
 103 #define IS_NOTCOMMAND           0x02                            /* Not in command state */
 104 #define IS_EARLYPHASE           0x03                            /* Early phase change   */
 105 #define IS_COMPLETE             0x04                            /* Command ok           */
 106 #define IS_SOF                  0x08                            /* Sync off flag        */
 107
 108 /* Transfer period step (write) */
 109 #define REG_STP                 (6)
 110
 111 /* Synchronous Offset (write) */
 112 #define REG_SOF                 (7)
 113
 114 /* Fifo state register (read) */
 115 #define REG_CFIS                (7)
 116 #define CFIS_CF                 0x1f                            /* Num bytes in FIFO    */
 117 #define CFIS_IS                 0xe0                            /* Step                 */
 118
 119 /* config register 1 */
 120 #define REG_CNTL1               (8)
 121 #define CNTL1_CID               (7 << 0)                        /* Chip ID                      */
 122 #define CNTL1_STE               (1 << 3)                        /* Self test enable             */
 123 #define CNTL1_PERE              (1 << 4)                        /* Parity enable reporting en.  */
 124 #define CNTL1_PTE               (1 << 5)                        /* Parity test enable           */
 125 #define CNTL1_DISR              (1 << 6)                        /* Disable Irq on SCSI reset    */
 126 #define CNTL1_ETM               (1 << 7)                        /* Extended Timing Mode         */
 127
 128 /* Clock conversion factor (read) */
 129 #define REG_CLKF                (9)
 130 #define CLKF_F37MHZ             0x00                            /* 35.01 - 40 MHz               */
 131 #define CLKF_F10MHZ             0x02                            /* 10 MHz                       */
 132 #define CLKF_F12MHZ             0x03                            /* 10.01 - 15 MHz               */
 133 #define CLKF_F17MHZ             0x04                            /* 15.01 - 20 MHz               */
 134 #define CLKF_F22MHZ             0x05                            /* 20.01 - 25 MHz               */
 135 #define CLKF_F27MHZ             0x06                            /* 25.01 - 30 MHz               */
 136 #define CLKF_F32MHZ             0x07                            /* 30.01 - 35 MHz               */
 137
 138 /* Chip test register (write) */
 139 #define REG_FTM                 (10)
 140 #define TEST_FTM                0x01                            /* Force target mode            */
 141 #define TEST_FIM                0x02                            /* Force initiator mode         */
 142 #define TEST_FHI                0x04                            /* Force high impedance mode    */
 143
 144 /* Configuration register 2 (read/write) */
 145 #define REG_CNTL2               (11)
 146 #define CNTL2_PGDP              (1 << 0)                        /* Pass Th/Generate Data Parity */
 147 #define CNTL2_PGRP              (1 << 1)                        /* Pass Th/Generate Reg Parity  */
 148 #define CNTL2_ACDPE             (1 << 2)                        /* Abort on Cmd/Data Parity Err */
 149 #define CNTL2_S2FE              (1 << 3)                        /* SCSI2 Features Enable        */
 150 #define CNTL2_TSDR              (1 << 4)                        /* Tristate DREQ                */
 151 #define CNTL2_SBO               (1 << 5)                        /* Select Byte Order            */
 152 #define CNTL2_ENF               (1 << 6)                        /* Enable features              */
 153 #define CNTL2_DAE               (1 << 7)                        /* Data Alignment Enable        */
 154
 155 /* Configuration register 3 (read/write) */
 156 #define REG_CNTL3               (12)
 157 #define CNTL3_BS8               (1 << 0)                        /* Burst size 8                 */
 158 #define CNTL3_MDM               (1 << 1)                        /* Modify DMA mode              */
 159 #define CNTL3_LBTM              (1 << 2)                        /* Last Byte Transfer mode      */
 160 #define CNTL3_FASTCLK           (1 << 3)                        /* Fast SCSI clocking           */
 161 #define CNTL3_FASTSCSI          (1 << 4)                        /* Fast SCSI                    */
 162 #define CNTL3_G2CB              (1 << 5)                        /* Group2 SCSI support          */
 163 #define CNTL3_QTAG              (1 << 6)                        /* Enable 3 byte msgs           */
 164 #define CNTL3_ADIDCHK           (1 << 7)                        /* Additional ID check          */
 165
 166 /* High transfer count (read/write) */
 167 #define REG_CTCH                (14)
 168 #define REG_STCH                (14)
 169
 170 /* ID register (read only) */
 171 #define REG_ID                  (14)
 172
 173 /* Data alignment */
 174 #define REG_DAL                 (15)
 175
 176 typedef enum {
 177         PHASE_IDLE,                                     /* we're not planning on doing anything */
 178         PHASE_SELECTION,                                /* selecting a device                   */
 179         PHASE_SELSTEPS,                                 /* selection with command steps         */
 180         PHASE_COMMAND,                                  /* command sent                         */
 181         PHASE_MESSAGESENT,                              /* selected, and we're sending cmd      */
 182         PHASE_DATAOUT,                                  /* data out to device                   */
 183         PHASE_DATAIN,                                   /* data in from device                  */
 184         PHASE_MSGIN,                                    /* message in from device               */
 185         PHASE_MSGIN_DISCONNECT,                         /* disconnecting from bus               */
 186         PHASE_MSGOUT,                                   /* after message out phase              */
 187         PHASE_MSGOUT_EXPECT,                            /* expecting message out                */
 188         PHASE_STATUS,                                   /* status from device                   */
 189         PHASE_DONE                                      /* Command complete                     */
 190 } phase_t;
 191
 192 typedef enum {
 193         DMA_OUT,                                        /* DMA from memory to chip              */
 194         DMA_IN                                          /* DMA from chip to memory              */
 195 } fasdmadir_t;
 196
 197 typedef enum {
 198         fasdma_none,                                    /* No dma                               */
 199         fasdma_pio,                                     /* PIO mode                             */
 200         fasdma_pseudo,                                  /* Pseudo DMA                           */
 201         fasdma_real_block,                              /* Real DMA, on block by block basis    */
 202         fasdma_real_all                                 /* Real DMA, on request by request      */
 203 } fasdmatype_t;
 204
 205 typedef enum {
 206         neg_wait,                                       /* Negotiate with device                */
 207         neg_inprogress,                                 /* Negotiation sent                     */
 208         neg_complete,                                   /* Negotiation complete                 */
 209         neg_targcomplete,                               /* Target completed negotiation         */
 210         neg_invalid                                     /* Negotiation not supported            */
 211 } neg_t;
 212
 213 #define MAGIC   0x441296bdUL
 214 #define NR_MSGS 8
 215
 216 #define FASCAP_DMA              (1 << 0)
 217 #define FASCAP_PSEUDODMA        (1 << 1)
 218
 219 typedef struct {
 220         unsigned long           magic_start;
 221         spinlock_t              host_lock;
 222         struct Scsi_Host        *host;                  /* host                                 */
 223         struct scsi_cmnd        *SCpnt;                 /* currently processing command         */
 224         struct scsi_cmnd        *origSCpnt;             /* original connecting command          */
 225         struct scsi_cmnd        *reqSCpnt;              /* request sense command                */
 226         struct scsi_cmnd        *rstSCpnt;              /* reset command                        */
 227         struct scsi_cmnd        *pending_SCpnt[8];      /* per-device pending commands          */
 228         int                     next_pending;           /* next pending device                  */
 229
 230         /*
 231          * Error recovery
 232          */
 233         wait_queue_head_t       eh_wait;
 234         struct timer_list       eh_timer;
 235         unsigned int            rst_dev_status;
 236         unsigned int            rst_bus_status;
 237
 238         /* driver information */
 239         struct {
 240                 phase_t         phase;                  /* current phase                        */
 241                 void __iomem    *io_base;               /* iomem base of FAS216                 */
 242                 unsigned int    io_shift;               /* shift to adjust reg offsets by       */
 243                 unsigned char   cfg[4];                 /* configuration registers              */
 244                 const char      *type;                  /* chip type                            */
 245                 unsigned int    irq;                    /* interrupt                            */
 246                 int             dma;                    /* dma channel                          */
 247
 248                 struct scsi_pointer     SCp;                    /* current commands data pointer        */
 249
 250                 MsgQueue_t      msgs;                   /* message queue for connected device   */
 251
 252                 unsigned int    async_stp;              /* Async transfer STP value             */
 253                 unsigned char   msgin_fifo;             /* bytes in fifo at time of message in  */
 254                 unsigned char   message[256];           /* last message received from device    */
 255
 256                 unsigned char   disconnectable:1;       /* this command can be disconnected     */
 257                 unsigned char   aborting:1;             /* aborting command                     */
 258         } scsi;
 259
 260         /* statistics information */
 261         struct {
 262                 unsigned int    queues;
 263                 unsigned int    removes;
 264                 unsigned int    fins;
 265                 unsigned int    reads;
 266                 unsigned int    writes;
 267                 unsigned int    miscs;
 268                 unsigned int    disconnects;
 269                 unsigned int    aborts;
 270                 unsigned int    bus_resets;
 271                 unsigned int    host_resets;
 272         } stats;
 273
 274         /* configuration information */
 275         struct {
 276                 unsigned char   clockrate;              /* clock rate of FAS device (MHz)       */
 277                 unsigned char   select_timeout;         /* timeout (R5)                         */
 278                 unsigned char   sync_max_depth;         /* Synchronous xfer max fifo depth      */
 279                 unsigned char   wide_max_size;          /* Maximum wide transfer size           */
 280                 unsigned char   cntl3;                  /* Control Reg 3                        */
 281                 unsigned int    asyncperiod;            /* Async transfer period (ns)           */
 282                 unsigned int    capabilities;           /* driver capabilities                  */
 283                 unsigned int    disconnect_ok:1;        /* Disconnects allowed?                 */
 284         } ifcfg;
 285
 286         /* queue handling */
 287         struct {
 288                 Queue_t         issue;                  /* issue queue                          */
 289                 Queue_t         disconnected;           /* disconnected command queue           */
 290         } queues;
 291
 292         /* per-device info */
 293         struct fas216_device {
 294                 unsigned char   disconnect_ok:1;        /* device can disconnect                */
 295                 unsigned char   parity_enabled:1;       /* parity checking enabled              */
 296                 unsigned char   parity_check:1;         /* need to check parity checking        */
 297                 unsigned char   period;                 /* sync xfer period in (*4ns)           */
 298                 unsigned char   stp;                    /* synchronous transfer period          */
 299                 unsigned char   sof;                    /* synchronous offset register          */
 300                 unsigned char   wide_xfer;              /* currently negociated wide transfer   */
 301                 neg_t           sync_state;             /* synchronous transfer mode            */
 302                 neg_t           wide_state;             /* wide transfer mode                   */
 303         } device[8];
 304         unsigned long   busyluns[64/sizeof(unsigned long)];/* array of bits indicating LUNs busy        */
 305
 306         /* dma */
 307         struct {
 308                 fasdmatype_t    transfer_type;          /* current type of DMA transfer         */
 309                 fasdmatype_t    (*setup) (struct Scsi_Host *host, struct scsi_pointer *SCp, fasdmadir_t direction, fasdmatype_t min_dma);
 310                 void            (*pseudo)(struct Scsi_Host *host, struct scsi_pointer *SCp, fasdmadir_t direction, int transfer);
 311                 void            (*stop)  (struct Scsi_Host *host, struct scsi_pointer *SCp);
 312         } dma;
 313
 314         /* miscellaneous */
 315         int                     internal_done;          /* flag to indicate request done */
 316         struct scsi_eh_save     ses;            /* holds request sense restore info */
 317         unsigned long           magic_end;
 318 } FAS216_Info;
 319
 320 /* Function: int fas216_init (struct Scsi_Host *instance)
 321  * Purpose : initialise FAS/NCR/AMD SCSI structures.
 322  * Params  : instance - a driver-specific filled-out structure
 323  * Returns : 0 on success
 324  */
 325 extern int fas216_init (struct Scsi_Host *instance);
 326
 327 /* Function: int fas216_add (struct Scsi_Host *instance, struct device *dev)
 328  * Purpose : initialise FAS/NCR/AMD SCSI ic.
 329  * Params  : instance - a driver-specific filled-out structure
 330  * Returns : 0 on success
 331  */
 332 extern int fas216_add (struct Scsi_Host *instance, struct device *dev);
 333
 334 /* Function: int fas216_queue_command(struct Scsi_Host *h, struct scsi_cmnd *SCpnt)
 335  * Purpose : queue a command for adapter to process.
 336  * Params  : h - host adapter
 337  *         : SCpnt - Command to queue
 338  * Returns : 0 - success, else error
 339  */
 340 extern int fas216_queue_command(struct Scsi_Host *h, struct scsi_cmnd *SCpnt);
 341
 342 /* Function: int fas216_noqueue_command(struct Scsi_Host *h, struct scsi_cmnd *SCpnt)
 343  * Purpose : queue a command for adapter to process, and process it to completion.
 344  * Params  : h - host adapter
 345  *         : SCpnt - Command to queue
 346  * Returns : 0 - success, else error
 347  */
 348 extern int fas216_noqueue_command(struct Scsi_Host *, struct scsi_cmnd *);
 349
 350 /* Function: irqreturn_t fas216_intr (FAS216_Info *info)
 351  * Purpose : handle interrupts from the interface to progress a command
 352  * Params  : info - interface to service
 353  */
 354 extern irqreturn_t fas216_intr (FAS216_Info *info);
 355
 356 extern void fas216_remove (struct Scsi_Host *instance);
 357
 358 /* Function: void fas216_release (struct Scsi_Host *instance)
 359  * Purpose : release all resources and put everything to bed for FAS/NCR/AMD SCSI ic.
 360  * Params  : instance - a driver-specific filled-out structure
 361  * Returns : 0 on success
 362  */
 363 extern void fas216_release (struct Scsi_Host *instance);
 364
 365 extern int fas216_print_host(FAS216_Info *info, char *buffer);
 366 extern int fas216_print_stats(FAS216_Info *info, char *buffer);
 367 extern int fas216_print_devices(FAS216_Info *info, char *buffer);
 368
 369 /* Function: int fas216_eh_abort(struct scsi_cmnd *SCpnt)
 370  * Purpose : abort this command
 371  * Params  : SCpnt - command to abort
 372  * Returns : FAILED if unable to abort
 373  */
 374 extern int fas216_eh_abort(struct scsi_cmnd *SCpnt);
 375
 376 /* Function: int fas216_eh_device_reset(struct scsi_cmnd *SCpnt)
 377  * Purpose : Reset the device associated with this command
 378  * Params  : SCpnt - command specifing device to reset
 379  * Returns : FAILED if unable to reset
 380  */
 381 extern int fas216_eh_device_reset(struct scsi_cmnd *SCpnt);
 382
 383 /* Function: int fas216_eh_bus_reset(struct scsi_cmnd *SCpnt)
 384  * Purpose : Reset the complete bus associated with this command
 385  * Params  : SCpnt - command specifing bus to reset
 386  * Returns : FAILED if unable to reset
 387  */
 388 extern int fas216_eh_bus_reset(struct scsi_cmnd *SCpnt);
 389
 390 /* Function: int fas216_eh_host_reset(struct scsi_cmnd *SCpnt)
 391  * Purpose : Reset the host associated with this command
 392  * Params  : SCpnt - command specifing host to reset
 393  * Returns : FAILED if unable to reset
 394  */
 395 extern int fas216_eh_host_reset(struct scsi_cmnd *SCpnt);
 396
 397 #endif /* FAS216_H */