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1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "2.00"
97
98 enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
103
104 PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108 PIIX_FLAG_COMBINED = (1 << 29), /* combined mode possible */
109 /* ICH6/7 use different scheme for map value */
110 PIIX_FLAG_COMBINED_ICH6 = PIIX_FLAG_COMBINED | (1 << 30),
111
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
121 /* controller IDs */
122 piix4_pata = 0,
123 ich5_pata = 1,
124 ich5_sata = 2,
125 esb_sata = 3,
126 ich6_sata = 4,
127 ich6_sata_ahci = 5,
128 ich6m_sata_ahci = 6,
129
130 /* constants for mapping table */
131 P0 = 0, /* port 0 */
132 P1 = 1, /* port 1 */
133 P2 = 2, /* port 2 */
134 P3 = 3, /* port 3 */
135 IDE = -1, /* IDE */
136 NA = -2, /* not avaliable */
137 RV = -3, /* reserved */
138
139 PIIX_AHCI_DEVICE = 6,
140 };
141
142 struct piix_map_db {
143 const u32 mask;
144 const u32 port_enable;
145 const int map[][4];
146 };
147
148 struct piix_host_priv {
149 const int *map;
150 };
151
152 static int piix_init_one (struct pci_dev *pdev,
153 const struct pci_device_id *ent);
154 static void piix_host_stop(struct ata_host_set *host_set);
155 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
156 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
157 static void piix_pata_error_handler(struct ata_port *ap);
158 static void piix_sata_error_handler(struct ata_port *ap);
159
160 static unsigned int in_module_init = 1;
161
162 static const struct pci_device_id piix_pci_tbl[] = {
163 #ifdef ATA_ENABLE_PATA
164 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
165 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
166 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
167 { 0x8086, 0x27df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
168 #endif
169
170 /* NOTE: The following PCI ids must be kept in sync with the
171 * list in drivers/pci/quirks.c.
172 */
173
174 /* 82801EB (ICH5) */
175 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
176 /* 82801EB (ICH5) */
177 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
178 /* 6300ESB (ICH5 variant with broken PCS present bits) */
179 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
180 /* 6300ESB pretending RAID */
181 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
182 /* 82801FB/FW (ICH6/ICH6W) */
183 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
184 /* 82801FR/FRW (ICH6R/ICH6RW) */
185 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
186 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
187 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
188 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
189 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
190 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
191 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
192 /* Enterprise Southbridge 2 (where's the datasheet?) */
193 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
194 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
195 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
196 /* SATA Controller 2 IDE (ICH8, ditto) */
197 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
198 /* Mobile SATA Controller IDE (ICH8M, ditto) */
199 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
200
201 { } /* terminate list */
202 };
203
204 static struct pci_driver piix_pci_driver = {
205 .name = DRV_NAME,
206 .id_table = piix_pci_tbl,
207 .probe = piix_init_one,
208 .remove = ata_pci_remove_one,
209 .suspend = ata_pci_device_suspend,
210 .resume = ata_pci_device_resume,
211 };
212
213 static struct scsi_host_template piix_sht = {
214 .module = THIS_MODULE,
215 .name = DRV_NAME,
216 .ioctl = ata_scsi_ioctl,
217 .queuecommand = ata_scsi_queuecmd,
218 .can_queue = ATA_DEF_QUEUE,
219 .this_id = ATA_SHT_THIS_ID,
220 .sg_tablesize = LIBATA_MAX_PRD,
221 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
222 .emulated = ATA_SHT_EMULATED,
223 .use_clustering = ATA_SHT_USE_CLUSTERING,
224 .proc_name = DRV_NAME,
225 .dma_boundary = ATA_DMA_BOUNDARY,
226 .slave_configure = ata_scsi_slave_config,
227 .slave_destroy = ata_scsi_slave_destroy,
228 .bios_param = ata_std_bios_param,
229 .resume = ata_scsi_device_resume,
230 .suspend = ata_scsi_device_suspend,
231 };
232
233 static const struct ata_port_operations piix_pata_ops = {
234 .port_disable = ata_port_disable,
235 .set_piomode = piix_set_piomode,
236 .set_dmamode = piix_set_dmamode,
237 .mode_filter = ata_pci_default_filter,
238
239 .tf_load = ata_tf_load,
240 .tf_read = ata_tf_read,
241 .check_status = ata_check_status,
242 .exec_command = ata_exec_command,
243 .dev_select = ata_std_dev_select,
244
245 .bmdma_setup = ata_bmdma_setup,
246 .bmdma_start = ata_bmdma_start,
247 .bmdma_stop = ata_bmdma_stop,
248 .bmdma_status = ata_bmdma_status,
249 .qc_prep = ata_qc_prep,
250 .qc_issue = ata_qc_issue_prot,
251 .data_xfer = ata_pio_data_xfer,
252
253 .freeze = ata_bmdma_freeze,
254 .thaw = ata_bmdma_thaw,
255 .error_handler = piix_pata_error_handler,
256 .post_internal_cmd = ata_bmdma_post_internal_cmd,
257
258 .irq_handler = ata_interrupt,
259 .irq_clear = ata_bmdma_irq_clear,
260
261 .port_start = ata_port_start,
262 .port_stop = ata_port_stop,
263 .host_stop = piix_host_stop,
264 };
265
266 static const struct ata_port_operations piix_sata_ops = {
267 .port_disable = ata_port_disable,
268
269 .tf_load = ata_tf_load,
270 .tf_read = ata_tf_read,
271 .check_status = ata_check_status,
272 .exec_command = ata_exec_command,
273 .dev_select = ata_std_dev_select,
274
275 .bmdma_setup = ata_bmdma_setup,
276 .bmdma_start = ata_bmdma_start,
277 .bmdma_stop = ata_bmdma_stop,
278 .bmdma_status = ata_bmdma_status,
279 .qc_prep = ata_qc_prep,
280 .qc_issue = ata_qc_issue_prot,
281 .data_xfer = ata_pio_data_xfer,
282
283 .freeze = ata_bmdma_freeze,
284 .thaw = ata_bmdma_thaw,
285 .error_handler = piix_sata_error_handler,
286 .post_internal_cmd = ata_bmdma_post_internal_cmd,
287
288 .irq_handler = ata_interrupt,
289 .irq_clear = ata_bmdma_irq_clear,
290
291 .port_start = ata_port_start,
292 .port_stop = ata_port_stop,
293 .host_stop = piix_host_stop,
294 };
295
296 static const struct piix_map_db ich5_map_db = {
297 .mask = 0x7,
298 .port_enable = 0x3,
299 .map = {
300 /* PM PS SM SS MAP */
301 { P0, NA, P1, NA }, /* 000b */
302 { P1, NA, P0, NA }, /* 001b */
303 { RV, RV, RV, RV },
304 { RV, RV, RV, RV },
305 { P0, P1, IDE, IDE }, /* 100b */
306 { P1, P0, IDE, IDE }, /* 101b */
307 { IDE, IDE, P0, P1 }, /* 110b */
308 { IDE, IDE, P1, P0 }, /* 111b */
309 },
310 };
311
312 static const struct piix_map_db ich6_map_db = {
313 .mask = 0x3,
314 .port_enable = 0xf,
315 .map = {
316 /* PM PS SM SS MAP */
317 { P0, P2, P1, P3 }, /* 00b */
318 { IDE, IDE, P1, P3 }, /* 01b */
319 { P0, P2, IDE, IDE }, /* 10b */
320 { RV, RV, RV, RV },
321 },
322 };
323
324 static const struct piix_map_db ich6m_map_db = {
325 .mask = 0x3,
326 .port_enable = 0x5,
327 .map = {
328 /* PM PS SM SS MAP */
329 { P0, P2, RV, RV }, /* 00b */
330 { RV, RV, RV, RV },
331 { P0, P2, IDE, IDE }, /* 10b */
332 { RV, RV, RV, RV },
333 },
334 };
335
336 static const struct piix_map_db *piix_map_db_table[] = {
337 [ich5_sata] = &ich5_map_db,
338 [esb_sata] = &ich5_map_db,
339 [ich6_sata] = &ich6_map_db,
340 [ich6_sata_ahci] = &ich6_map_db,
341 [ich6m_sata_ahci] = &ich6m_map_db,
342 };
343
344 static struct ata_port_info piix_port_info[] = {
345 /* piix4_pata */
346 {
347 .sht = &piix_sht,
348 .host_flags = ATA_FLAG_SLAVE_POSS,
349 .pio_mask = 0x1f, /* pio0-4 */
350 #if 0
351 .mwdma_mask = 0x06, /* mwdma1-2 */
352 #else
353 .mwdma_mask = 0x00, /* mwdma broken */
354 #endif
355 .udma_mask = ATA_UDMA_MASK_40C,
356 .port_ops = &piix_pata_ops,
357 },
358
359 /* ich5_pata */
360 {
361 .sht = &piix_sht,
362 .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
363 .pio_mask = 0x1f, /* pio0-4 */
364 #if 0
365 .mwdma_mask = 0x06, /* mwdma1-2 */
366 #else
367 .mwdma_mask = 0x00, /* mwdma broken */
368 #endif
369 .udma_mask = 0x3f, /* udma0-5 */
370 .port_ops = &piix_pata_ops,
371 },
372
373 /* ich5_sata */
374 {
375 .sht = &piix_sht,
376 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
377 PIIX_FLAG_CHECKINTR,
378 .pio_mask = 0x1f, /* pio0-4 */
379 .mwdma_mask = 0x07, /* mwdma0-2 */
380 .udma_mask = 0x7f, /* udma0-6 */
381 .port_ops = &piix_sata_ops,
382 },
383
384 /* i6300esb_sata */
385 {
386 .sht = &piix_sht,
387 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
388 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS,
389 .pio_mask = 0x1f, /* pio0-4 */
390 .mwdma_mask = 0x07, /* mwdma0-2 */
391 .udma_mask = 0x7f, /* udma0-6 */
392 .port_ops = &piix_sata_ops,
393 },
394
395 /* ich6_sata */
396 {
397 .sht = &piix_sht,
398 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
399 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR,
400 .pio_mask = 0x1f, /* pio0-4 */
401 .mwdma_mask = 0x07, /* mwdma0-2 */
402 .udma_mask = 0x7f, /* udma0-6 */
403 .port_ops = &piix_sata_ops,
404 },
405
406 /* ich6_sata_ahci */
407 {
408 .sht = &piix_sht,
409 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
410 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
411 PIIX_FLAG_AHCI,
412 .pio_mask = 0x1f, /* pio0-4 */
413 .mwdma_mask = 0x07, /* mwdma0-2 */
414 .udma_mask = 0x7f, /* udma0-6 */
415 .port_ops = &piix_sata_ops,
416 },
417
418 /* ich6m_sata_ahci */
419 {
420 .sht = &piix_sht,
421 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
422 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
423 PIIX_FLAG_AHCI,
424 .pio_mask = 0x1f, /* pio0-4 */
425 .mwdma_mask = 0x07, /* mwdma0-2 */
426 .udma_mask = 0x7f, /* udma0-6 */
427 .port_ops = &piix_sata_ops,
428 },
429 };
430
431 static struct pci_bits piix_enable_bits[] = {
432 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
433 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
434 };
435
436 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
437 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
438 MODULE_LICENSE("GPL");
439 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
440 MODULE_VERSION(DRV_VERSION);
441
442 /**
443 * piix_pata_cbl_detect - Probe host controller cable detect info
444 * @ap: Port for which cable detect info is desired
445 *
446 * Read 80c cable indicator from ATA PCI device's PCI config
447 * register. This register is normally set by firmware (BIOS).
448 *
449 * LOCKING:
450 * None (inherited from caller).
451 */
452 static void piix_pata_cbl_detect(struct ata_port *ap)
453 {
454 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
455 u8 tmp, mask;
456
457 /* no 80c support in host controller? */
458 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
459 goto cbl40;
460
461 /* check BIOS cable detect results */
462 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
463 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
464 if ((tmp & mask) == 0)
465 goto cbl40;
466
467 ap->cbl = ATA_CBL_PATA80;
468 return;
469
470 cbl40:
471 ap->cbl = ATA_CBL_PATA40;
472 ap->udma_mask &= ATA_UDMA_MASK_40C;
473 }
474
475 /**
476 * piix_pata_prereset - prereset for PATA host controller
477 * @ap: Target port
478 *
479 * Prereset including cable detection.
480 *
481 * LOCKING:
482 * None (inherited from caller).
483 */
484 static int piix_pata_prereset(struct ata_port *ap)
485 {
486 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
487
488 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
489 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
490 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
491 return 0;
492 }
493
494 piix_pata_cbl_detect(ap);
495
496 return ata_std_prereset(ap);
497 }
498
499 static void piix_pata_error_handler(struct ata_port *ap)
500 {
501 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
502 ata_std_postreset);
503 }
504
505 /**
506 * piix_sata_prereset - prereset for SATA host controller
507 * @ap: Target port
508 *
509 * Reads and configures SATA PCI device's PCI config register
510 * Port Configuration and Status (PCS) to determine port and
511 * device availability. Return -ENODEV to skip reset if no
512 * device is present.
513 *
514 * LOCKING:
515 * None (inherited from caller).
516 *
517 * RETURNS:
518 * 0 if device is present, -ENODEV otherwise.
519 */
520 static int piix_sata_prereset(struct ata_port *ap)
521 {
522 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
523 struct piix_host_priv *hpriv = ap->host_set->private_data;
524 const unsigned int *map = hpriv->map;
525 int base = 2 * ap->hard_port_no;
526 unsigned int present = 0;
527 int port, i;
528 u16 pcs;
529
530 pci_read_config_word(pdev, ICH5_PCS, &pcs);
531 DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base);
532
533 for (i = 0; i < 2; i++) {
534 port = map[base + i];
535 if (port < 0)
536 continue;
537 if (ap->flags & PIIX_FLAG_IGNORE_PCS || pcs & 1 << (4 + port))
538 present = 1;
539 }
540
541 DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n",
542 ap->id, pcs, present_mask);
543
544 if (!present) {
545 ata_port_printk(ap, KERN_INFO, "SATA port has no device.\n");
546 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
547 return 0;
548 }
549
550 return ata_std_prereset(ap);
551 }
552
553 static void piix_sata_error_handler(struct ata_port *ap)
554 {
555 ata_bmdma_drive_eh(ap, piix_sata_prereset, ata_std_softreset, NULL,
556 ata_std_postreset);
557 }
558
559 /**
560 * piix_set_piomode - Initialize host controller PATA PIO timings
561 * @ap: Port whose timings we are configuring
562 * @adev: um
563 *
564 * Set PIO mode for device, in host controller PCI config space.
565 *
566 * LOCKING:
567 * None (inherited from caller).
568 */
569
570 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
571 {
572 unsigned int pio = adev->pio_mode - XFER_PIO_0;
573 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
574 unsigned int is_slave = (adev->devno != 0);
575 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
576 unsigned int slave_port = 0x44;
577 u16 master_data;
578 u8 slave_data;
579
580 static const /* ISP RTC */
581 u8 timings[][2] = { { 0, 0 },
582 { 0, 0 },
583 { 1, 0 },
584 { 2, 1 },
585 { 2, 3 }, };
586
587 pci_read_config_word(dev, master_port, &master_data);
588 if (is_slave) {
589 master_data |= 0x4000;
590 /* enable PPE, IE and TIME */
591 master_data |= 0x0070;
592 pci_read_config_byte(dev, slave_port, &slave_data);
593 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
594 slave_data |=
595 (timings[pio][0] << 2) |
596 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
597 } else {
598 master_data &= 0xccf8;
599 /* enable PPE, IE and TIME */
600 master_data |= 0x0007;
601 master_data |=
602 (timings[pio][0] << 12) |
603 (timings[pio][1] << 8);
604 }
605 pci_write_config_word(dev, master_port, master_data);
606 if (is_slave)
607 pci_write_config_byte(dev, slave_port, slave_data);
608 }
609
610 /**
611 * piix_set_dmamode - Initialize host controller PATA PIO timings
612 * @ap: Port whose timings we are configuring
613 * @adev: um
614 * @udma: udma mode, 0 - 6
615 *
616 * Set UDMA mode for device, in host controller PCI config space.
617 *
618 * LOCKING:
619 * None (inherited from caller).
620 */
621
622 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
623 {
624 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
625 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
626 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
627 u8 speed = udma;
628 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
629 int a_speed = 3 << (drive_dn * 4);
630 int u_flag = 1 << drive_dn;
631 int v_flag = 0x01 << drive_dn;
632 int w_flag = 0x10 << drive_dn;
633 int u_speed = 0;
634 int sitre;
635 u16 reg4042, reg4a;
636 u8 reg48, reg54, reg55;
637
638 pci_read_config_word(dev, maslave, &reg4042);
639 DPRINTK("reg4042 = 0x%04x\n", reg4042);
640 sitre = (reg4042 & 0x4000) ? 1 : 0;
641 pci_read_config_byte(dev, 0x48, &reg48);
642 pci_read_config_word(dev, 0x4a, &reg4a);
643 pci_read_config_byte(dev, 0x54, &reg54);
644 pci_read_config_byte(dev, 0x55, &reg55);
645
646 switch(speed) {
647 case XFER_UDMA_4:
648 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
649 case XFER_UDMA_6:
650 case XFER_UDMA_5:
651 case XFER_UDMA_3:
652 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
653 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
654 case XFER_MW_DMA_2:
655 case XFER_MW_DMA_1: break;
656 default:
657 BUG();
658 return;
659 }
660
661 if (speed >= XFER_UDMA_0) {
662 if (!(reg48 & u_flag))
663 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
664 if (speed == XFER_UDMA_5) {
665 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
666 } else {
667 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
668 }
669 if ((reg4a & a_speed) != u_speed)
670 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
671 if (speed > XFER_UDMA_2) {
672 if (!(reg54 & v_flag))
673 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
674 } else
675 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
676 } else {
677 if (reg48 & u_flag)
678 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
679 if (reg4a & a_speed)
680 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
681 if (reg54 & v_flag)
682 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
683 if (reg55 & w_flag)
684 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
685 }
686 }
687
688 #define AHCI_PCI_BAR 5
689 #define AHCI_GLOBAL_CTL 0x04
690 #define AHCI_ENABLE (1 << 31)
691 static int piix_disable_ahci(struct pci_dev *pdev)
692 {
693 void __iomem *mmio;
694 u32 tmp;
695 int rc = 0;
696
697 /* BUG: pci_enable_device has not yet been called. This
698 * works because this device is usually set up by BIOS.
699 */
700
701 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
702 !pci_resource_len(pdev, AHCI_PCI_BAR))
703 return 0;
704
705 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
706 if (!mmio)
707 return -ENOMEM;
708
709 tmp = readl(mmio + AHCI_GLOBAL_CTL);
710 if (tmp & AHCI_ENABLE) {
711 tmp &= ~AHCI_ENABLE;
712 writel(tmp, mmio + AHCI_GLOBAL_CTL);
713
714 tmp = readl(mmio + AHCI_GLOBAL_CTL);
715 if (tmp & AHCI_ENABLE)
716 rc = -EIO;
717 }
718
719 pci_iounmap(pdev, mmio);
720 return rc;
721 }
722
723 /**
724 * piix_check_450nx_errata - Check for problem 450NX setup
725 * @ata_dev: the PCI device to check
726 *
727 * Check for the present of 450NX errata #19 and errata #25. If
728 * they are found return an error code so we can turn off DMA
729 */
730
731 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
732 {
733 struct pci_dev *pdev = NULL;
734 u16 cfg;
735 u8 rev;
736 int no_piix_dma = 0;
737
738 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
739 {
740 /* Look for 450NX PXB. Check for problem configurations
741 A PCI quirk checks bit 6 already */
742 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
743 pci_read_config_word(pdev, 0x41, &cfg);
744 /* Only on the original revision: IDE DMA can hang */
745 if (rev == 0x00)
746 no_piix_dma = 1;
747 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
748 else if (cfg & (1<<14) && rev < 5)
749 no_piix_dma = 2;
750 }
751 if (no_piix_dma)
752 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
753 if (no_piix_dma == 2)
754 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
755 return no_piix_dma;
756 }
757
758 static void __devinit piix_init_pcs(struct pci_dev *pdev,
759 const struct piix_map_db *map_db)
760 {
761 u16 pcs, new_pcs;
762
763 pci_read_config_word(pdev, ICH5_PCS, &pcs);
764
765 new_pcs = pcs | map_db->port_enable;
766
767 if (new_pcs != pcs) {
768 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
769 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
770 msleep(150);
771 }
772 }
773
774 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
775 struct ata_port_info *pinfo,
776 const struct piix_map_db *map_db)
777 {
778 struct piix_host_priv *hpriv = pinfo[0].private_data;
779 const unsigned int *map;
780 int i, invalid_map = 0;
781 u8 map_value;
782
783 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
784
785 map = map_db->map[map_value & map_db->mask];
786
787 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
788 for (i = 0; i < 4; i++) {
789 switch (map[i]) {
790 case RV:
791 invalid_map = 1;
792 printk(" XX");
793 break;
794
795 case NA:
796 printk(" --");
797 break;
798
799 case IDE:
800 WARN_ON((i & 1) || map[i + 1] != IDE);
801 pinfo[i / 2] = piix_port_info[ich5_pata];
802 i++;
803 printk(" IDE IDE");
804 break;
805
806 default:
807 printk(" P%d", map[i]);
808 if (i & 1)
809 pinfo[i / 2].host_flags |= ATA_FLAG_SLAVE_POSS;
810 break;
811 }
812 }
813 printk(" ]\n");
814
815 if (invalid_map)
816 dev_printk(KERN_ERR, &pdev->dev,
817 "invalid MAP value %u\n", map_value);
818
819 hpriv->map = map;
820 }
821
822 /**
823 * piix_init_one - Register PIIX ATA PCI device with kernel services
824 * @pdev: PCI device to register
825 * @ent: Entry in piix_pci_tbl matching with @pdev
826 *
827 * Called from kernel PCI layer. We probe for combined mode (sigh),
828 * and then hand over control to libata, for it to do the rest.
829 *
830 * LOCKING:
831 * Inherited from PCI layer (may sleep).
832 *
833 * RETURNS:
834 * Zero on success, or -ERRNO value.
835 */
836
837 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
838 {
839 static int printed_version;
840 struct ata_port_info port_info[2];
841 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
842 struct piix_host_priv *hpriv;
843 unsigned long host_flags;
844
845 if (!printed_version++)
846 dev_printk(KERN_DEBUG, &pdev->dev,
847 "version " DRV_VERSION "\n");
848
849 /* no hotplugging support (FIXME) */
850 if (!in_module_init)
851 return -ENODEV;
852
853 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
854 if (!hpriv)
855 return -ENOMEM;
856
857 port_info[0] = piix_port_info[ent->driver_data];
858 port_info[1] = piix_port_info[ent->driver_data];
859 port_info[0].private_data = hpriv;
860 port_info[1].private_data = hpriv;
861
862 host_flags = port_info[0].host_flags;
863
864 if (host_flags & PIIX_FLAG_AHCI) {
865 u8 tmp;
866 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
867 if (tmp == PIIX_AHCI_DEVICE) {
868 int rc = piix_disable_ahci(pdev);
869 if (rc)
870 return rc;
871 }
872 }
873
874 /* Initialize SATA map */
875 if (host_flags & ATA_FLAG_SATA) {
876 piix_init_sata_map(pdev, port_info,
877 piix_map_db_table[ent->driver_data]);
878 piix_init_pcs(pdev, piix_map_db_table[ent->driver_data]);
879 }
880
881 /* On ICH5, some BIOSen disable the interrupt using the
882 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
883 * On ICH6, this bit has the same effect, but only when
884 * MSI is disabled (and it is disabled, as we don't use
885 * message-signalled interrupts currently).
886 */
887 if (host_flags & PIIX_FLAG_CHECKINTR)
888 pci_intx(pdev, 1);
889
890 if (piix_check_450nx_errata(pdev)) {
891 /* This writes into the master table but it does not
892 really matter for this errata as we will apply it to
893 all the PIIX devices on the board */
894 port_info[0].mwdma_mask = 0;
895 port_info[0].udma_mask = 0;
896 port_info[1].mwdma_mask = 0;
897 port_info[1].udma_mask = 0;
898 }
899 return ata_pci_init_one(pdev, ppinfo, 2);
900 }
901
902 static void piix_host_stop(struct ata_host_set *host_set)
903 {
904 if (host_set->next == NULL)
905 kfree(host_set->private_data);
906 ata_host_stop(host_set);
907 }
908
909 static int __init piix_init(void)
910 {
911 int rc;
912
913 DPRINTK("pci_module_init\n");
914 rc = pci_module_init(&piix_pci_driver);
915 if (rc)
916 return rc;
917
918 in_module_init = 0;
919
920 DPRINTK("done\n");
921 return 0;
922 }
923
924 static void __exit piix_exit(void)
925 {
926 pci_unregister_driver(&piix_pci_driver);
927 }
928
929 module_init(piix_init);
930 module_exit(piix_exit);
931
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