]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - drivers/scsi/ata_piix.c
projects / mirror_ubuntu-jammy-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[libata] ata_piix: attempt to fix ICH8 support
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / ata_piix.c
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "2.00"
97
98 enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
103
104 PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108 PIIX_FLAG_COMBINED = (1 << 29), /* combined mode possible */
109 /* ICH6/7 use different scheme for map value */
110 PIIX_FLAG_COMBINED_ICH6 = PIIX_FLAG_COMBINED | (1 << 30),
111
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
121 /* controller IDs */
122 piix4_pata = 0,
123 ich5_pata = 1,
124 ich5_sata = 2,
125 esb_sata = 3,
126 ich6_sata = 4,
127 ich6_sata_ahci = 5,
128 ich6m_sata_ahci = 6,
129 ich8_sata_ahci = 7,
130
131 /* constants for mapping table */
132 P0 = 0, /* port 0 */
133 P1 = 1, /* port 1 */
134 P2 = 2, /* port 2 */
135 P3 = 3, /* port 3 */
136 IDE = -1, /* IDE */
137 NA = -2, /* not avaliable */
138 RV = -3, /* reserved */
139
140 PIIX_AHCI_DEVICE = 6,
141 };
142
143 struct piix_map_db {
144 const u32 mask;
145 const u32 port_enable;
146 const int present_shift;
147 const int map[][4];
148 };
149
150 struct piix_host_priv {
151 const int *map;
152 const struct piix_map_db *map_db;
153 };
154
155 static int piix_init_one (struct pci_dev *pdev,
156 const struct pci_device_id *ent);
157 static void piix_host_stop(struct ata_host_set *host_set);
158 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
159 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
160 static void piix_pata_error_handler(struct ata_port *ap);
161 static void piix_sata_error_handler(struct ata_port *ap);
162
163 static unsigned int in_module_init = 1;
164
165 static const struct pci_device_id piix_pci_tbl[] = {
166 #ifdef ATA_ENABLE_PATA
167 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
168 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
169 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
170 { 0x8086, 0x27df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
171 #endif
172
173 /* NOTE: The following PCI ids must be kept in sync with the
174 * list in drivers/pci/quirks.c.
175 */
176
177 /* 82801EB (ICH5) */
178 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
179 /* 82801EB (ICH5) */
180 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
181 /* 6300ESB (ICH5 variant with broken PCS present bits) */
182 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
183 /* 6300ESB pretending RAID */
184 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
185 /* 82801FB/FW (ICH6/ICH6W) */
186 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
187 /* 82801FR/FRW (ICH6R/ICH6RW) */
188 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
189 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
190 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
191 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
192 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
193 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
194 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
195 /* Enterprise Southbridge 2 (where's the datasheet?) */
196 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
197 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
198 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
199 /* SATA Controller 2 IDE (ICH8, ditto) */
200 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
201 /* Mobile SATA Controller IDE (ICH8M, ditto) */
202 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
203
204 { } /* terminate list */
205 };
206
207 static struct pci_driver piix_pci_driver = {
208 .name = DRV_NAME,
209 .id_table = piix_pci_tbl,
210 .probe = piix_init_one,
211 .remove = ata_pci_remove_one,
212 .suspend = ata_pci_device_suspend,
213 .resume = ata_pci_device_resume,
214 };
215
216 static struct scsi_host_template piix_sht = {
217 .module = THIS_MODULE,
218 .name = DRV_NAME,
219 .ioctl = ata_scsi_ioctl,
220 .queuecommand = ata_scsi_queuecmd,
221 .can_queue = ATA_DEF_QUEUE,
222 .this_id = ATA_SHT_THIS_ID,
223 .sg_tablesize = LIBATA_MAX_PRD,
224 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
225 .emulated = ATA_SHT_EMULATED,
226 .use_clustering = ATA_SHT_USE_CLUSTERING,
227 .proc_name = DRV_NAME,
228 .dma_boundary = ATA_DMA_BOUNDARY,
229 .slave_configure = ata_scsi_slave_config,
230 .slave_destroy = ata_scsi_slave_destroy,
231 .bios_param = ata_std_bios_param,
232 .resume = ata_scsi_device_resume,
233 .suspend = ata_scsi_device_suspend,
234 };
235
236 static const struct ata_port_operations piix_pata_ops = {
237 .port_disable = ata_port_disable,
238 .set_piomode = piix_set_piomode,
239 .set_dmamode = piix_set_dmamode,
240 .mode_filter = ata_pci_default_filter,
241
242 .tf_load = ata_tf_load,
243 .tf_read = ata_tf_read,
244 .check_status = ata_check_status,
245 .exec_command = ata_exec_command,
246 .dev_select = ata_std_dev_select,
247
248 .bmdma_setup = ata_bmdma_setup,
249 .bmdma_start = ata_bmdma_start,
250 .bmdma_stop = ata_bmdma_stop,
251 .bmdma_status = ata_bmdma_status,
252 .qc_prep = ata_qc_prep,
253 .qc_issue = ata_qc_issue_prot,
254 .data_xfer = ata_pio_data_xfer,
255
256 .freeze = ata_bmdma_freeze,
257 .thaw = ata_bmdma_thaw,
258 .error_handler = piix_pata_error_handler,
259 .post_internal_cmd = ata_bmdma_post_internal_cmd,
260
261 .irq_handler = ata_interrupt,
262 .irq_clear = ata_bmdma_irq_clear,
263
264 .port_start = ata_port_start,
265 .port_stop = ata_port_stop,
266 .host_stop = piix_host_stop,
267 };
268
269 static const struct ata_port_operations piix_sata_ops = {
270 .port_disable = ata_port_disable,
271
272 .tf_load = ata_tf_load,
273 .tf_read = ata_tf_read,
274 .check_status = ata_check_status,
275 .exec_command = ata_exec_command,
276 .dev_select = ata_std_dev_select,
277
278 .bmdma_setup = ata_bmdma_setup,
279 .bmdma_start = ata_bmdma_start,
280 .bmdma_stop = ata_bmdma_stop,
281 .bmdma_status = ata_bmdma_status,
282 .qc_prep = ata_qc_prep,
283 .qc_issue = ata_qc_issue_prot,
284 .data_xfer = ata_pio_data_xfer,
285
286 .freeze = ata_bmdma_freeze,
287 .thaw = ata_bmdma_thaw,
288 .error_handler = piix_sata_error_handler,
289 .post_internal_cmd = ata_bmdma_post_internal_cmd,
290
291 .irq_handler = ata_interrupt,
292 .irq_clear = ata_bmdma_irq_clear,
293
294 .port_start = ata_port_start,
295 .port_stop = ata_port_stop,
296 .host_stop = piix_host_stop,
297 };
298
299 static const struct piix_map_db ich5_map_db = {
300 .mask = 0x7,
301 .port_enable = 0x3,
302 .present_shift = 4,
303 .map = {
304 /* PM PS SM SS MAP */
305 { P0, NA, P1, NA }, /* 000b */
306 { P1, NA, P0, NA }, /* 001b */
307 { RV, RV, RV, RV },
308 { RV, RV, RV, RV },
309 { P0, P1, IDE, IDE }, /* 100b */
310 { P1, P0, IDE, IDE }, /* 101b */
311 { IDE, IDE, P0, P1 }, /* 110b */
312 { IDE, IDE, P1, P0 }, /* 111b */
313 },
314 };
315
316 static const struct piix_map_db ich6_map_db = {
317 .mask = 0x3,
318 .port_enable = 0xf,
319 .present_shift = 4,
320 .map = {
321 /* PM PS SM SS MAP */
322 { P0, P2, P1, P3 }, /* 00b */
323 { IDE, IDE, P1, P3 }, /* 01b */
324 { P0, P2, IDE, IDE }, /* 10b */
325 { RV, RV, RV, RV },
326 },
327 };
328
329 static const struct piix_map_db ich6m_map_db = {
330 .mask = 0x3,
331 .port_enable = 0x5,
332 .present_shift = 4,
333 .map = {
334 /* PM PS SM SS MAP */
335 { P0, P2, RV, RV }, /* 00b */
336 { RV, RV, RV, RV },
337 { P0, P2, IDE, IDE }, /* 10b */
338 { RV, RV, RV, RV },
339 },
340 };
341
342 static const struct piix_map_db ich8_map_db = {
343 .mask = 0x3,
344 .port_enable = 0x3,
345 .present_shift = 8,
346 .map = {
347 /* PM PS SM SS MAP */
348 { P0, RV, P1, RV }, /* 00b (hardwired) */
349 { RV, RV, RV, RV },
350 { RV, RV, RV, RV }, /* 10b (never) */
351 { RV, RV, RV, RV },
352 },
353 };
354
355 static const struct piix_map_db *piix_map_db_table[] = {
356 [ich5_sata] = &ich5_map_db,
357 [esb_sata] = &ich5_map_db,
358 [ich6_sata] = &ich6_map_db,
359 [ich6_sata_ahci] = &ich6_map_db,
360 [ich6m_sata_ahci] = &ich6m_map_db,
361 [ich8_sata_ahci] = &ich8_map_db,
362 };
363
364 static struct ata_port_info piix_port_info[] = {
365 /* piix4_pata */
366 {
367 .sht = &piix_sht,
368 .host_flags = ATA_FLAG_SLAVE_POSS,
369 .pio_mask = 0x1f, /* pio0-4 */
370 #if 0
371 .mwdma_mask = 0x06, /* mwdma1-2 */
372 #else
373 .mwdma_mask = 0x00, /* mwdma broken */
374 #endif
375 .udma_mask = ATA_UDMA_MASK_40C,
376 .port_ops = &piix_pata_ops,
377 },
378
379 /* ich5_pata */
380 {
381 .sht = &piix_sht,
382 .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
383 .pio_mask = 0x1f, /* pio0-4 */
384 #if 0
385 .mwdma_mask = 0x06, /* mwdma1-2 */
386 #else
387 .mwdma_mask = 0x00, /* mwdma broken */
388 #endif
389 .udma_mask = 0x3f, /* udma0-5 */
390 .port_ops = &piix_pata_ops,
391 },
392
393 /* ich5_sata */
394 {
395 .sht = &piix_sht,
396 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
397 PIIX_FLAG_CHECKINTR,
398 .pio_mask = 0x1f, /* pio0-4 */
399 .mwdma_mask = 0x07, /* mwdma0-2 */
400 .udma_mask = 0x7f, /* udma0-6 */
401 .port_ops = &piix_sata_ops,
402 },
403
404 /* i6300esb_sata */
405 {
406 .sht = &piix_sht,
407 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
408 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS,
409 .pio_mask = 0x1f, /* pio0-4 */
410 .mwdma_mask = 0x07, /* mwdma0-2 */
411 .udma_mask = 0x7f, /* udma0-6 */
412 .port_ops = &piix_sata_ops,
413 },
414
415 /* ich6_sata */
416 {
417 .sht = &piix_sht,
418 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
419 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR,
420 .pio_mask = 0x1f, /* pio0-4 */
421 .mwdma_mask = 0x07, /* mwdma0-2 */
422 .udma_mask = 0x7f, /* udma0-6 */
423 .port_ops = &piix_sata_ops,
424 },
425
426 /* ich6_sata_ahci */
427 {
428 .sht = &piix_sht,
429 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
430 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
431 PIIX_FLAG_AHCI,
432 .pio_mask = 0x1f, /* pio0-4 */
433 .mwdma_mask = 0x07, /* mwdma0-2 */
434 .udma_mask = 0x7f, /* udma0-6 */
435 .port_ops = &piix_sata_ops,
436 },
437
438 /* ich6m_sata_ahci */
439 {
440 .sht = &piix_sht,
441 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
442 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
443 PIIX_FLAG_AHCI,
444 .pio_mask = 0x1f, /* pio0-4 */
445 .mwdma_mask = 0x07, /* mwdma0-2 */
446 .udma_mask = 0x7f, /* udma0-6 */
447 .port_ops = &piix_sata_ops,
448 },
449
450 /* ich8_sata_ahci */
451 {
452 .sht = &piix_sht,
453 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
454 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
455 PIIX_FLAG_AHCI,
456 .pio_mask = 0x1f, /* pio0-4 */
457 .mwdma_mask = 0x07, /* mwdma0-2 */
458 .udma_mask = 0x7f, /* udma0-6 */
459 .port_ops = &piix_sata_ops,
460 },
461 };
462
463 static struct pci_bits piix_enable_bits[] = {
464 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
465 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
466 };
467
468 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
469 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
470 MODULE_LICENSE("GPL");
471 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
472 MODULE_VERSION(DRV_VERSION);
473
474 /**
475 * piix_pata_cbl_detect - Probe host controller cable detect info
476 * @ap: Port for which cable detect info is desired
477 *
478 * Read 80c cable indicator from ATA PCI device's PCI config
479 * register. This register is normally set by firmware (BIOS).
480 *
481 * LOCKING:
482 * None (inherited from caller).
483 */
484 static void piix_pata_cbl_detect(struct ata_port *ap)
485 {
486 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
487 u8 tmp, mask;
488
489 /* no 80c support in host controller? */
490 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
491 goto cbl40;
492
493 /* check BIOS cable detect results */
494 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
495 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
496 if ((tmp & mask) == 0)
497 goto cbl40;
498
499 ap->cbl = ATA_CBL_PATA80;
500 return;
501
502 cbl40:
503 ap->cbl = ATA_CBL_PATA40;
504 ap->udma_mask &= ATA_UDMA_MASK_40C;
505 }
506
507 /**
508 * piix_pata_prereset - prereset for PATA host controller
509 * @ap: Target port
510 *
511 * Prereset including cable detection.
512 *
513 * LOCKING:
514 * None (inherited from caller).
515 */
516 static int piix_pata_prereset(struct ata_port *ap)
517 {
518 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
519
520 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
521 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
522 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
523 return 0;
524 }
525
526 piix_pata_cbl_detect(ap);
527
528 return ata_std_prereset(ap);
529 }
530
531 static void piix_pata_error_handler(struct ata_port *ap)
532 {
533 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
534 ata_std_postreset);
535 }
536
537 /**
538 * piix_sata_prereset - prereset for SATA host controller
539 * @ap: Target port
540 *
541 * Reads and configures SATA PCI device's PCI config register
542 * Port Configuration and Status (PCS) to determine port and
543 * device availability. Return -ENODEV to skip reset if no
544 * device is present.
545 *
546 * LOCKING:
547 * None (inherited from caller).
548 *
549 * RETURNS:
550 * 0 if device is present, -ENODEV otherwise.
551 */
552 static int piix_sata_prereset(struct ata_port *ap)
553 {
554 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
555 struct piix_host_priv *hpriv = ap->host_set->private_data;
556 const unsigned int *map = hpriv->map;
557 int base = 2 * ap->hard_port_no;
558 unsigned int present = 0;
559 int port, i;
560 u16 pcs;
561
562 pci_read_config_word(pdev, ICH5_PCS, &pcs);
563 DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base);
564
565 for (i = 0; i < 2; i++) {
566 port = map[base + i];
567 if (port < 0)
568 continue;
569 if ((ap->flags & PIIX_FLAG_IGNORE_PCS) ||
570 (pcs & 1 << (hpriv->map_db->present_shift + port)))
571 present = 1;
572 }
573
574 DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n",
575 ap->id, pcs, present_mask);
576
577 if (!present) {
578 ata_port_printk(ap, KERN_INFO, "SATA port has no device.\n");
579 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
580 return 0;
581 }
582
583 return ata_std_prereset(ap);
584 }
585
586 static void piix_sata_error_handler(struct ata_port *ap)
587 {
588 ata_bmdma_drive_eh(ap, piix_sata_prereset, ata_std_softreset, NULL,
589 ata_std_postreset);
590 }
591
592 /**
593 * piix_set_piomode - Initialize host controller PATA PIO timings
594 * @ap: Port whose timings we are configuring
595 * @adev: um
596 *
597 * Set PIO mode for device, in host controller PCI config space.
598 *
599 * LOCKING:
600 * None (inherited from caller).
601 */
602
603 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
604 {
605 unsigned int pio = adev->pio_mode - XFER_PIO_0;
606 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
607 unsigned int is_slave = (adev->devno != 0);
608 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
609 unsigned int slave_port = 0x44;
610 u16 master_data;
611 u8 slave_data;
612
613 static const /* ISP RTC */
614 u8 timings[][2] = { { 0, 0 },
615 { 0, 0 },
616 { 1, 0 },
617 { 2, 1 },
618 { 2, 3 }, };
619
620 pci_read_config_word(dev, master_port, &master_data);
621 if (is_slave) {
622 master_data |= 0x4000;
623 /* enable PPE, IE and TIME */
624 master_data |= 0x0070;
625 pci_read_config_byte(dev, slave_port, &slave_data);
626 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
627 slave_data |=
628 (timings[pio][0] << 2) |
629 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
630 } else {
631 master_data &= 0xccf8;
632 /* enable PPE, IE and TIME */
633 master_data |= 0x0007;
634 master_data |=
635 (timings[pio][0] << 12) |
636 (timings[pio][1] << 8);
637 }
638 pci_write_config_word(dev, master_port, master_data);
639 if (is_slave)
640 pci_write_config_byte(dev, slave_port, slave_data);
641 }
642
643 /**
644 * piix_set_dmamode - Initialize host controller PATA PIO timings
645 * @ap: Port whose timings we are configuring
646 * @adev: um
647 * @udma: udma mode, 0 - 6
648 *
649 * Set UDMA mode for device, in host controller PCI config space.
650 *
651 * LOCKING:
652 * None (inherited from caller).
653 */
654
655 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
656 {
657 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
658 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
659 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
660 u8 speed = udma;
661 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
662 int a_speed = 3 << (drive_dn * 4);
663 int u_flag = 1 << drive_dn;
664 int v_flag = 0x01 << drive_dn;
665 int w_flag = 0x10 << drive_dn;
666 int u_speed = 0;
667 int sitre;
668 u16 reg4042, reg4a;
669 u8 reg48, reg54, reg55;
670
671 pci_read_config_word(dev, maslave, &reg4042);
672 DPRINTK("reg4042 = 0x%04x\n", reg4042);
673 sitre = (reg4042 & 0x4000) ? 1 : 0;
674 pci_read_config_byte(dev, 0x48, &reg48);
675 pci_read_config_word(dev, 0x4a, &reg4a);
676 pci_read_config_byte(dev, 0x54, &reg54);
677 pci_read_config_byte(dev, 0x55, &reg55);
678
679 switch(speed) {
680 case XFER_UDMA_4:
681 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
682 case XFER_UDMA_6:
683 case XFER_UDMA_5:
684 case XFER_UDMA_3:
685 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
686 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
687 case XFER_MW_DMA_2:
688 case XFER_MW_DMA_1: break;
689 default:
690 BUG();
691 return;
692 }
693
694 if (speed >= XFER_UDMA_0) {
695 if (!(reg48 & u_flag))
696 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
697 if (speed == XFER_UDMA_5) {
698 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
699 } else {
700 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
701 }
702 if ((reg4a & a_speed) != u_speed)
703 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
704 if (speed > XFER_UDMA_2) {
705 if (!(reg54 & v_flag))
706 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
707 } else
708 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
709 } else {
710 if (reg48 & u_flag)
711 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
712 if (reg4a & a_speed)
713 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
714 if (reg54 & v_flag)
715 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
716 if (reg55 & w_flag)
717 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
718 }
719 }
720
721 #define AHCI_PCI_BAR 5
722 #define AHCI_GLOBAL_CTL 0x04
723 #define AHCI_ENABLE (1 << 31)
724 static int piix_disable_ahci(struct pci_dev *pdev)
725 {
726 void __iomem *mmio;
727 u32 tmp;
728 int rc = 0;
729
730 /* BUG: pci_enable_device has not yet been called. This
731 * works because this device is usually set up by BIOS.
732 */
733
734 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
735 !pci_resource_len(pdev, AHCI_PCI_BAR))
736 return 0;
737
738 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
739 if (!mmio)
740 return -ENOMEM;
741
742 tmp = readl(mmio + AHCI_GLOBAL_CTL);
743 if (tmp & AHCI_ENABLE) {
744 tmp &= ~AHCI_ENABLE;
745 writel(tmp, mmio + AHCI_GLOBAL_CTL);
746
747 tmp = readl(mmio + AHCI_GLOBAL_CTL);
748 if (tmp & AHCI_ENABLE)
749 rc = -EIO;
750 }
751
752 pci_iounmap(pdev, mmio);
753 return rc;
754 }
755
756 /**
757 * piix_check_450nx_errata - Check for problem 450NX setup
758 * @ata_dev: the PCI device to check
759 *
760 * Check for the present of 450NX errata #19 and errata #25. If
761 * they are found return an error code so we can turn off DMA
762 */
763
764 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
765 {
766 struct pci_dev *pdev = NULL;
767 u16 cfg;
768 u8 rev;
769 int no_piix_dma = 0;
770
771 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
772 {
773 /* Look for 450NX PXB. Check for problem configurations
774 A PCI quirk checks bit 6 already */
775 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
776 pci_read_config_word(pdev, 0x41, &cfg);
777 /* Only on the original revision: IDE DMA can hang */
778 if (rev == 0x00)
779 no_piix_dma = 1;
780 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
781 else if (cfg & (1<<14) && rev < 5)
782 no_piix_dma = 2;
783 }
784 if (no_piix_dma)
785 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
786 if (no_piix_dma == 2)
787 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
788 return no_piix_dma;
789 }
790
791 static void __devinit piix_init_pcs(struct pci_dev *pdev,
792 const struct piix_map_db *map_db)
793 {
794 u16 pcs, new_pcs;
795
796 pci_read_config_word(pdev, ICH5_PCS, &pcs);
797
798 new_pcs = pcs | map_db->port_enable;
799
800 if (new_pcs != pcs) {
801 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
802 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
803 msleep(150);
804 }
805 }
806
807 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
808 struct ata_port_info *pinfo,
809 const struct piix_map_db *map_db)
810 {
811 struct piix_host_priv *hpriv = pinfo[0].private_data;
812 const unsigned int *map;
813 int i, invalid_map = 0;
814 u8 map_value;
815
816 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
817
818 map = map_db->map[map_value & map_db->mask];
819
820 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
821 for (i = 0; i < 4; i++) {
822 switch (map[i]) {
823 case RV:
824 invalid_map = 1;
825 printk(" XX");
826 break;
827
828 case NA:
829 printk(" --");
830 break;
831
832 case IDE:
833 WARN_ON((i & 1) || map[i + 1] != IDE);
834 pinfo[i / 2] = piix_port_info[ich5_pata];
835 i++;
836 printk(" IDE IDE");
837 break;
838
839 default:
840 printk(" P%d", map[i]);
841 if (i & 1)
842 pinfo[i / 2].host_flags |= ATA_FLAG_SLAVE_POSS;
843 break;
844 }
845 }
846 printk(" ]\n");
847
848 if (invalid_map)
849 dev_printk(KERN_ERR, &pdev->dev,
850 "invalid MAP value %u\n", map_value);
851
852 hpriv->map = map;
853 hpriv->map_db = map_db;
854 }
855
856 /**
857 * piix_init_one - Register PIIX ATA PCI device with kernel services
858 * @pdev: PCI device to register
859 * @ent: Entry in piix_pci_tbl matching with @pdev
860 *
861 * Called from kernel PCI layer. We probe for combined mode (sigh),
862 * and then hand over control to libata, for it to do the rest.
863 *
864 * LOCKING:
865 * Inherited from PCI layer (may sleep).
866 *
867 * RETURNS:
868 * Zero on success, or -ERRNO value.
869 */
870
871 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
872 {
873 static int printed_version;
874 struct ata_port_info port_info[2];
875 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
876 struct piix_host_priv *hpriv;
877 unsigned long host_flags;
878
879 if (!printed_version++)
880 dev_printk(KERN_DEBUG, &pdev->dev,
881 "version " DRV_VERSION "\n");
882
883 /* no hotplugging support (FIXME) */
884 if (!in_module_init)
885 return -ENODEV;
886
887 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
888 if (!hpriv)
889 return -ENOMEM;
890
891 port_info[0] = piix_port_info[ent->driver_data];
892 port_info[1] = piix_port_info[ent->driver_data];
893 port_info[0].private_data = hpriv;
894 port_info[1].private_data = hpriv;
895
896 host_flags = port_info[0].host_flags;
897
898 if (host_flags & PIIX_FLAG_AHCI) {
899 u8 tmp;
900 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
901 if (tmp == PIIX_AHCI_DEVICE) {
902 int rc = piix_disable_ahci(pdev);
903 if (rc)
904 return rc;
905 }
906 }
907
908 /* Initialize SATA map */
909 if (host_flags & ATA_FLAG_SATA) {
910 piix_init_sata_map(pdev, port_info,
911 piix_map_db_table[ent->driver_data]);
912 piix_init_pcs(pdev, piix_map_db_table[ent->driver_data]);
913 }
914
915 /* On ICH5, some BIOSen disable the interrupt using the
916 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
917 * On ICH6, this bit has the same effect, but only when
918 * MSI is disabled (and it is disabled, as we don't use
919 * message-signalled interrupts currently).
920 */
921 if (host_flags & PIIX_FLAG_CHECKINTR)
922 pci_intx(pdev, 1);
923
924 if (piix_check_450nx_errata(pdev)) {
925 /* This writes into the master table but it does not
926 really matter for this errata as we will apply it to
927 all the PIIX devices on the board */
928 port_info[0].mwdma_mask = 0;
929 port_info[0].udma_mask = 0;
930 port_info[1].mwdma_mask = 0;
931 port_info[1].udma_mask = 0;
932 }
933 return ata_pci_init_one(pdev, ppinfo, 2);
934 }
935
936 static void piix_host_stop(struct ata_host_set *host_set)
937 {
938 if (host_set->next == NULL)
939 kfree(host_set->private_data);
940 ata_host_stop(host_set);
941 }
942
943 static int __init piix_init(void)
944 {
945 int rc;
946
947 DPRINTK("pci_module_init\n");
948 rc = pci_module_init(&piix_pci_driver);
949 if (rc)
950 return rc;
951
952 in_module_init = 0;
953
954 DPRINTK("done\n");
955 return 0;
956 }
957
958 static void __exit piix_exit(void)
959 {
960 pci_unregister_driver(&piix_pci_driver);
961 }
962
963 module_init(piix_init);
964 module_exit(piix_exit);
965
Ubuntu Jammy Linux kernel mirror