drivers/scsi/be2iscsi/be_main.h

   1 /**
   2  * Copyright (C) 2005 - 2016 Broadcom
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Written by: Jayamohan Kallickal (jayamohan.kallickal@broadcom.com)
  11  *
  12  * Contact Information:
  13  * linux-drivers@broadcom.com
  14  *
  15  * Emulex
  16  * 3333 Susan Street
  17  * Costa Mesa, CA 92626
  18  */
  19
  20 #ifndef _BEISCSI_MAIN_
  21 #define _BEISCSI_MAIN_
  22
  23 #include <linux/kernel.h>
  24 #include <linux/pci.h>
  25 #include <linux/if_ether.h>
  26 #include <linux/in.h>
  27 #include <linux/ctype.h>
  28 #include <linux/module.h>
  29 #include <linux/aer.h>
  30 #include <scsi/scsi.h>
  31 #include <scsi/scsi_cmnd.h>
  32 #include <scsi/scsi_device.h>
  33 #include <scsi/scsi_host.h>
  34 #include <scsi/iscsi_proto.h>
  35 #include <scsi/libiscsi.h>
  36 #include <scsi/scsi_transport_iscsi.h>
  37
  38 #define DRV_NAME                "be2iscsi"
  39 #define BUILD_STR               "11.2.1.0"
  40 #define BE_NAME                 "Emulex OneConnect" \
  41                                 "Open-iSCSI Driver version" BUILD_STR
  42 #define DRV_DESC                BE_NAME " " "Driver"
  43
  44 #define BE_VENDOR_ID            0x19A2
  45 #define ELX_VENDOR_ID           0x10DF
  46 /* DEVICE ID's for BE2 */
  47 #define BE_DEVICE_ID1           0x212
  48 #define OC_DEVICE_ID1           0x702
  49 #define OC_DEVICE_ID2           0x703
  50
  51 /* DEVICE ID's for BE3 */
  52 #define BE_DEVICE_ID2           0x222
  53 #define OC_DEVICE_ID3           0x712
  54
  55 /* DEVICE ID for SKH */
  56 #define OC_SKH_ID1              0x722
  57
  58 #define BE2_IO_DEPTH            1024
  59 #define BE2_MAX_SESSIONS        256
  60 #define BE2_TMFS                16
  61 #define BE2_NOPOUT_REQ          16
  62 #define BE2_SGE                 32
  63 #define BE2_DEFPDU_HDR_SZ       64
  64 #define BE2_DEFPDU_DATA_SZ      8192
  65 #define BE2_MAX_NUM_CQ_PROC     512
  66
  67 #define MAX_CPUS                64
  68 #define BEISCSI_MAX_NUM_CPUS    7
  69
  70 #define BEISCSI_VER_STRLEN 32
  71
  72 #define BEISCSI_SGLIST_ELEMENTS 30
  73
  74 /**
  75  * BE_INVLDT_CMD_TBL_SZ is 128 which is total number commands that can
  76  * be invalidated at a time, consider it before changing the value of
  77  * BEISCSI_CMD_PER_LUN.
  78  */
  79 #define BEISCSI_CMD_PER_LUN     128     /* scsi_host->cmd_per_lun */
  80 #define BEISCSI_MAX_SECTORS     1024    /* scsi_host->max_sectors */
  81 #define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
  82
  83 #define BEISCSI_MAX_CMD_LEN     16      /* scsi_host->max_cmd_len */
  84 #define BEISCSI_NUM_MAX_LUN     256     /* scsi_host->max_lun */
  85 #define BEISCSI_NUM_DEVICES_SUPPORTED   0x01
  86 #define BEISCSI_MAX_FRAGS_INIT  192
  87 #define BE_NUM_MSIX_ENTRIES     1
  88
  89 #define BE_SENSE_INFO_SIZE              258
  90 #define BE_ISCSI_PDU_HEADER_SIZE        64
  91 #define BE_MIN_MEM_SIZE                 16384
  92 #define MAX_CMD_SZ                      65536
  93 #define IIOC_SCSI_DATA                  0x05    /* Write Operation */
  94
  95 /**
  96  * hardware needs the async PDU buffers to be posted in multiples of 8
  97  * So have atleast 8 of them by default
  98  */
  99
 100 #define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num)    \
 101         (phwi->phwi_ctxt->pasync_ctx[ulp_num])
 102
 103 /********* Memory BAR register ************/
 104 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET      0xfc
 105 /**
 106  * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
 107  * Disable" may still globally block interrupts in addition to individual
 108  * interrupt masks; a mechanism for the device driver to block all interrupts
 109  * atomically without having to arbitrate for the PCI Interrupt Disable bit
 110  * with the OS.
 111  */
 112 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK      (1 << 29)       /* bit 29 */
 113
 114 /********* ISR0 Register offset **********/
 115 #define CEV_ISR0_OFFSET                         0xC18
 116 #define CEV_ISR_SIZE                            4
 117
 118 /**
 119  * Macros for reading/writing a protection domain or CSR registers
 120  * in BladeEngine.
 121  */
 122
 123 #define DB_TXULP0_OFFSET 0x40
 124 #define DB_RXULP0_OFFSET 0xA0
 125 /********* Event Q door bell *************/
 126 #define DB_EQ_OFFSET                    DB_CQ_OFFSET
 127 #define DB_EQ_RING_ID_LOW_MASK          0x1FF   /* bits 0 - 8 */
 128 /* Clear the interrupt for this eq */
 129 #define DB_EQ_CLR_SHIFT                 (9)     /* bit 9 */
 130 /* Must be 1 */
 131 #define DB_EQ_EVNT_SHIFT                (10)    /* bit 10 */
 132 /* Higher Order EQ_ID bit */
 133 #define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
 134 #define DB_EQ_HIGH_SET_SHIFT    11
 135 #define DB_EQ_HIGH_FEILD_SHIFT  9
 136 /* Number of event entries processed */
 137 #define DB_EQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 138 /* Rearm bit */
 139 #define DB_EQ_REARM_SHIFT               (29)    /* bit 29 */
 140
 141 /********* Compl Q door bell *************/
 142 #define DB_CQ_OFFSET                    0x120
 143 #define DB_CQ_RING_ID_LOW_MASK          0x3FF   /* bits 0 - 9 */
 144 /* Higher Order CQ_ID bit */
 145 #define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
 146 #define DB_CQ_HIGH_SET_SHIFT    11
 147 #define DB_CQ_HIGH_FEILD_SHIFT  10
 148
 149 /* Number of event entries processed */
 150 #define DB_CQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 151 /* Rearm bit */
 152 #define DB_CQ_REARM_SHIFT               (29)    /* bit 29 */
 153
 154 #define GET_HWI_CONTROLLER_WS(pc)       (pc->phwi_ctrlr)
 155 #define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
 156                 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
 157 #define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
 158                 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
 159
 160 #define PAGES_REQUIRED(x) \
 161         ((x < PAGE_SIZE) ? 1 :  ((x + PAGE_SIZE - 1) / PAGE_SIZE))
 162
 163 #define BEISCSI_MSI_NAME 20 /* size of msi_name string */
 164
 165 #define MEM_DESCR_OFFSET 8
 166 #define BEISCSI_DEFQ_HDR 1
 167 #define BEISCSI_DEFQ_DATA 0
 168 enum be_mem_enum {
 169         HWI_MEM_ADDN_CONTEXT,
 170         HWI_MEM_WRB,
 171         HWI_MEM_WRBH,
 172         HWI_MEM_SGLH,
 173         HWI_MEM_SGE,
 174         HWI_MEM_TEMPLATE_HDR_ULP0,
 175         HWI_MEM_ASYNC_HEADER_BUF_ULP0,  /* 6 */
 176         HWI_MEM_ASYNC_DATA_BUF_ULP0,
 177         HWI_MEM_ASYNC_HEADER_RING_ULP0,
 178         HWI_MEM_ASYNC_DATA_RING_ULP0,
 179         HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
 180         HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
 181         HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
 182         HWI_MEM_TEMPLATE_HDR_ULP1,
 183         HWI_MEM_ASYNC_HEADER_BUF_ULP1,  /* 14 */
 184         HWI_MEM_ASYNC_DATA_BUF_ULP1,
 185         HWI_MEM_ASYNC_HEADER_RING_ULP1,
 186         HWI_MEM_ASYNC_DATA_RING_ULP1,
 187         HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
 188         HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
 189         HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
 190         ISCSI_MEM_GLOBAL_HEADER,
 191         SE_MEM_MAX
 192 };
 193
 194 struct be_bus_address32 {
 195         unsigned int address_lo;
 196         unsigned int address_hi;
 197 };
 198
 199 struct be_bus_address64 {
 200         unsigned long long address;
 201 };
 202
 203 struct be_bus_address {
 204         union {
 205                 struct be_bus_address32 a32;
 206                 struct be_bus_address64 a64;
 207         } u;
 208 };
 209
 210 struct mem_array {
 211         struct be_bus_address bus_address;      /* Bus address of location */
 212         void *virtual_address;          /* virtual address to the location */
 213         unsigned int size;              /* Size required by memory block */
 214 };
 215
 216 struct be_mem_descriptor {
 217         unsigned int index;     /* Index of this memory parameter */
 218         unsigned int category;  /* type indicates cached/non-cached */
 219         unsigned int num_elements;      /* number of elements in this
 220                                          * descriptor
 221                                          */
 222         unsigned int alignment_mask;    /* Alignment mask for this block */
 223         unsigned int size_in_bytes;     /* Size required by memory block */
 224         struct mem_array *mem_array;
 225 };
 226
 227 struct sgl_handle {
 228         unsigned int sgl_index;
 229         unsigned int type;
 230         unsigned int cid;
 231         struct iscsi_task *task;
 232         struct iscsi_sge *pfrag;
 233 };
 234
 235 struct hba_parameters {
 236         unsigned int ios_per_ctrl;
 237         unsigned int cxns_per_ctrl;
 238         unsigned int asyncpdus_per_ctrl;
 239         unsigned int icds_per_ctrl;
 240         unsigned int num_sge_per_io;
 241         unsigned int defpdu_hdr_sz;
 242         unsigned int defpdu_data_sz;
 243         unsigned int num_cq_entries;
 244         unsigned int num_eq_entries;
 245         unsigned int wrbs_per_cxn;
 246         unsigned int hwi_ws_sz;
 247         /**
 248          * These are calculated from other params. They're here
 249          * for debug purposes
 250          */
 251         unsigned int num_mcc_pages;
 252         unsigned int num_mcc_cq_pages;
 253         unsigned int num_cq_pages;
 254         unsigned int num_eq_pages;
 255
 256         unsigned int num_async_pdu_buf_pages;
 257         unsigned int num_async_pdu_buf_sgl_pages;
 258         unsigned int num_async_pdu_buf_cq_pages;
 259
 260         unsigned int num_async_pdu_hdr_pages;
 261         unsigned int num_async_pdu_hdr_sgl_pages;
 262         unsigned int num_async_pdu_hdr_cq_pages;
 263
 264         unsigned int num_sge;
 265 };
 266
 267 #define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
 268         (phwi_ctrlr->wrb_context[cri].ulp_num)
 269 struct hwi_wrb_context {
 270         spinlock_t wrb_lock;
 271         struct list_head wrb_handle_list;
 272         struct list_head wrb_handle_drvr_list;
 273         struct wrb_handle **pwrb_handle_base;
 274         struct wrb_handle **pwrb_handle_basestd;
 275         struct iscsi_wrb *plast_wrb;
 276         unsigned short alloc_index;
 277         unsigned short free_index;
 278         unsigned short wrb_handles_available;
 279         unsigned short cid;
 280         uint8_t ulp_num;        /* ULP to which CID binded */
 281         uint16_t register_set;
 282         uint16_t doorbell_format;
 283         uint32_t doorbell_offset;
 284 };
 285
 286 struct ulp_cid_info {
 287         unsigned short *cid_array;
 288         unsigned short avlbl_cids;
 289         unsigned short cid_alloc;
 290         unsigned short cid_free;
 291 };
 292
 293 #include "be.h"
 294 #define chip_be2(phba)      (phba->generation == BE_GEN2)
 295 #define chip_be3_r(phba)    (phba->generation == BE_GEN3)
 296 #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
 297
 298 #define BEISCSI_ULP0    0
 299 #define BEISCSI_ULP1    1
 300 #define BEISCSI_ULP_COUNT   2
 301 #define BEISCSI_ULP0_LOADED 0x01
 302 #define BEISCSI_ULP1_LOADED 0x02
 303
 304 #define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
 305         (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
 306 #define BEISCSI_ULP0_AVLBL_CID(phba) \
 307         BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
 308 #define BEISCSI_ULP1_AVLBL_CID(phba) \
 309         BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
 310
 311 struct beiscsi_hba {
 312         struct hba_parameters params;
 313         struct hwi_controller *phwi_ctrlr;
 314         unsigned int mem_req[SE_MEM_MAX];
 315         /* PCI BAR mapped addresses */
 316         u8 __iomem *csr_va;     /* CSR */
 317         u8 __iomem *db_va;      /* Door  Bell  */
 318         u8 __iomem *pci_va;     /* PCI Config */
 319         struct be_bus_address csr_pa;   /* CSR */
 320         struct be_bus_address db_pa;    /* CSR */
 321         struct be_bus_address pci_pa;   /* CSR */
 322         /* PCI representation of our HBA */
 323         struct pci_dev *pcidev;
 324         unsigned int num_cpus;
 325         unsigned int nxt_cqid;
 326         struct msix_entry msix_entries[MAX_CPUS];
 327         char *msi_name[MAX_CPUS];
 328         bool msix_enabled;
 329         struct be_mem_descriptor *init_mem;
 330
 331         unsigned short io_sgl_alloc_index;
 332         unsigned short io_sgl_free_index;
 333         unsigned short io_sgl_hndl_avbl;
 334         struct sgl_handle **io_sgl_hndl_base;
 335         struct sgl_handle **sgl_hndl_array;
 336
 337         unsigned short eh_sgl_alloc_index;
 338         unsigned short eh_sgl_free_index;
 339         unsigned short eh_sgl_hndl_avbl;
 340         struct sgl_handle **eh_sgl_hndl_base;
 341         spinlock_t io_sgl_lock;
 342         spinlock_t mgmt_sgl_lock;
 343         spinlock_t async_pdu_lock;
 344         struct list_head hba_queue;
 345 #define BE_MAX_SESSION 2048
 346 #define BE_INVALID_CID 0xffff
 347 #define BE_SET_CID_TO_CRI(cri_index, cid) \
 348                           (phba->cid_to_cri_map[cid] = cri_index)
 349 #define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
 350         unsigned short cid_to_cri_map[BE_MAX_SESSION];
 351         struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
 352         struct iscsi_endpoint **ep_array;
 353         struct beiscsi_conn **conn_table;
 354         struct Scsi_Host *shost;
 355         struct iscsi_iface *ipv4_iface;
 356         struct iscsi_iface *ipv6_iface;
 357         struct {
 358                 /**
 359                  * group together since they are used most frequently
 360                  * for cid to cri conversion
 361                  */
 362 #define BEISCSI_PHYS_PORT_MAX   4
 363                 unsigned int phys_port;
 364                 /* valid values of phys_port id are 0, 1, 2, 3 */
 365                 unsigned int eqid_count;
 366                 unsigned int cqid_count;
 367                 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
 368 #define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
 369                 (phba->fw_config.iscsi_cid_count[ulp_num])
 370                 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
 371                 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
 372                 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
 373                 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
 374                 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
 375
 376                 unsigned short iscsi_features;
 377                 uint16_t dual_ulp_aware;
 378                 unsigned long ulp_supported;
 379         } fw_config;
 380
 381         unsigned long state;
 382 #define BEISCSI_HBA_ONLINE      0
 383 #define BEISCSI_HBA_LINK_UP     1
 384 #define BEISCSI_HBA_BOOT_FOUND  2
 385 #define BEISCSI_HBA_BOOT_WORK   3
 386 #define BEISCSI_HBA_UER_SUPP    4
 387 #define BEISCSI_HBA_PCI_ERR     5
 388 #define BEISCSI_HBA_FW_TIMEOUT  6
 389 #define BEISCSI_HBA_IN_UE       7
 390 #define BEISCSI_HBA_IN_TPE      8
 391
 392 /* error bits */
 393 #define BEISCSI_HBA_IN_ERR      ((1 << BEISCSI_HBA_PCI_ERR) | \
 394                                  (1 << BEISCSI_HBA_FW_TIMEOUT) | \
 395                                  (1 << BEISCSI_HBA_IN_UE) | \
 396                                  (1 << BEISCSI_HBA_IN_TPE))
 397
 398         u8 optic_state;
 399         struct delayed_work eqd_update;
 400         /* update EQ delay timer every 1000ms */
 401 #define BEISCSI_EQD_UPDATE_INTERVAL     1000
 402         struct timer_list hw_check;
 403         /* check for UE every 1000ms */
 404 #define BEISCSI_UE_DETECT_INTERVAL      1000
 405         u32 ue2rp;
 406         struct delayed_work recover_port;
 407         struct work_struct sess_work;
 408
 409         bool mac_addr_set;
 410         u8 mac_address[ETH_ALEN];
 411         u8 port_name;
 412         u8 port_speed;
 413         char fw_ver_str[BEISCSI_VER_STRLEN];
 414         struct workqueue_struct *wq;    /* The actuak work queue */
 415         struct be_ctrl_info ctrl;
 416         unsigned int generation;
 417         unsigned int interface_handle;
 418
 419         struct be_aic_obj aic_obj[MAX_CPUS];
 420         unsigned int attr_log_enable;
 421         int (*iotask_fn)(struct iscsi_task *,
 422                         struct scatterlist *sg,
 423                         uint32_t num_sg, uint32_t xferlen,
 424                         uint32_t writedir);
 425         struct boot_struct {
 426                 int retry;
 427                 unsigned int tag;
 428                 unsigned int s_handle;
 429                 struct be_dma_mem nonemb_cmd;
 430                 enum {
 431                         BEISCSI_BOOT_REOPEN_SESS = 1,
 432                         BEISCSI_BOOT_GET_SHANDLE,
 433                         BEISCSI_BOOT_GET_SINFO,
 434                         BEISCSI_BOOT_LOGOUT_SESS,
 435                         BEISCSI_BOOT_CREATE_KSET,
 436                 } action;
 437                 struct mgmt_session_info boot_sess;
 438                 struct iscsi_boot_kset *boot_kset;
 439         } boot_struct;
 440         struct work_struct boot_work;
 441 };
 442
 443 #define beiscsi_hba_in_error(phba) ((phba)->state & BEISCSI_HBA_IN_ERR)
 444 #define beiscsi_hba_is_online(phba) \
 445         (!beiscsi_hba_in_error((phba)) && \
 446          test_bit(BEISCSI_HBA_ONLINE, &phba->state))
 447
 448 struct beiscsi_session {
 449         struct pci_pool *bhs_pool;
 450 };
 451
 452 /**
 453  * struct beiscsi_conn - iscsi connection structure
 454  */
 455 struct beiscsi_conn {
 456         struct iscsi_conn *conn;
 457         struct beiscsi_hba *phba;
 458         u32 exp_statsn;
 459         u32 doorbell_offset;
 460         u32 beiscsi_conn_cid;
 461         struct beiscsi_endpoint *ep;
 462         unsigned short login_in_progress;
 463         struct wrb_handle *plogin_wrb_handle;
 464         struct sgl_handle *plogin_sgl_handle;
 465         struct beiscsi_session *beiscsi_sess;
 466         struct iscsi_task *task;
 467 };
 468
 469 /* This structure is used by the chip */
 470 struct pdu_data_out {
 471         u32 dw[12];
 472 };
 473 /**
 474  * Pseudo amap definition in which each bit of the actual structure is defined
 475  * as a byte: used to calculate offset/shift/mask of each field
 476  */
 477 struct amap_pdu_data_out {
 478         u8 opcode[6];           /* opcode */
 479         u8 rsvd0[2];            /* should be 0 */
 480         u8 rsvd1[7];
 481         u8 final_bit;           /* F bit */
 482         u8 rsvd2[16];
 483         u8 ahs_length[8];       /* no AHS */
 484         u8 data_len_hi[8];
 485         u8 data_len_lo[16];     /* DataSegmentLength */
 486         u8 lun[64];
 487         u8 itt[32];             /* ITT; initiator task tag */
 488         u8 ttt[32];             /* TTT; valid for R2T or 0xffffffff */
 489         u8 rsvd3[32];
 490         u8 exp_stat_sn[32];
 491         u8 rsvd4[32];
 492         u8 data_sn[32];
 493         u8 buffer_offset[32];
 494         u8 rsvd5[32];
 495 };
 496
 497 struct be_cmd_bhs {
 498         struct iscsi_scsi_req iscsi_hdr;
 499         unsigned char pad1[16];
 500         struct pdu_data_out iscsi_data_pdu;
 501         unsigned char pad2[BE_SENSE_INFO_SIZE -
 502                         sizeof(struct pdu_data_out)];
 503 };
 504
 505 struct beiscsi_io_task {
 506         struct wrb_handle *pwrb_handle;
 507         struct sgl_handle *psgl_handle;
 508         struct beiscsi_conn *conn;
 509         struct scsi_cmnd *scsi_cmnd;
 510         int num_sg;
 511         struct hwi_wrb_context *pwrb_context;
 512         itt_t libiscsi_itt;
 513         struct be_cmd_bhs *cmd_bhs;
 514         struct be_bus_address bhs_pa;
 515         unsigned short bhs_len;
 516         dma_addr_t mtask_addr;
 517         uint32_t mtask_data_count;
 518         uint8_t wrb_type;
 519 };
 520
 521 struct be_nonio_bhs {
 522         struct iscsi_hdr iscsi_hdr;
 523         unsigned char pad1[16];
 524         struct pdu_data_out iscsi_data_pdu;
 525         unsigned char pad2[BE_SENSE_INFO_SIZE -
 526                         sizeof(struct pdu_data_out)];
 527 };
 528
 529 struct be_status_bhs {
 530         struct iscsi_scsi_req iscsi_hdr;
 531         unsigned char pad1[16];
 532         /**
 533          * The plus 2 below is to hold the sense info length that gets
 534          * DMA'ed by RxULP
 535          */
 536         unsigned char sense_info[BE_SENSE_INFO_SIZE];
 537 };
 538
 539 struct iscsi_sge {
 540         u32 dw[4];
 541 };
 542
 543 /**
 544  * Pseudo amap definition in which each bit of the actual structure is defined
 545  * as a byte: used to calculate offset/shift/mask of each field
 546  */
 547 struct amap_iscsi_sge {
 548         u8 addr_hi[32];
 549         u8 addr_lo[32];
 550         u8 sge_offset[22];      /* DWORD 2 */
 551         u8 rsvd0[9];            /* DWORD 2 */
 552         u8 last_sge;            /* DWORD 2 */
 553         u8 len[17];             /* DWORD 3 */
 554         u8 rsvd1[15];           /* DWORD 3 */
 555 };
 556
 557 struct beiscsi_offload_params {
 558         u32 dw[6];
 559 };
 560
 561 #define OFFLD_PARAMS_ERL        0x00000003
 562 #define OFFLD_PARAMS_DDE        0x00000004
 563 #define OFFLD_PARAMS_HDE        0x00000008
 564 #define OFFLD_PARAMS_IR2T       0x00000010
 565 #define OFFLD_PARAMS_IMD        0x00000020
 566 #define OFFLD_PARAMS_DATA_SEQ_INORDER   0x00000040
 567 #define OFFLD_PARAMS_PDU_SEQ_INORDER    0x00000080
 568 #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
 569
 570 /**
 571  * Pseudo amap definition in which each bit of the actual structure is defined
 572  * as a byte: used to calculate offset/shift/mask of each field
 573  */
 574 struct amap_beiscsi_offload_params {
 575         u8 max_burst_length[32];
 576         u8 max_send_data_segment_length[32];
 577         u8 first_burst_length[32];
 578         u8 erl[2];
 579         u8 dde[1];
 580         u8 hde[1];
 581         u8 ir2t[1];
 582         u8 imd[1];
 583         u8 data_seq_inorder[1];
 584         u8 pdu_seq_inorder[1];
 585         u8 max_r2t[16];
 586         u8 pad[8];
 587         u8 exp_statsn[32];
 588         u8 max_recv_data_segment_length[32];
 589 };
 590
 591 struct hd_async_handle {
 592         struct list_head link;
 593         struct be_bus_address pa;
 594         void *pbuffer;
 595         u32 buffer_len;
 596         u16 index;
 597         u16 cri;
 598         u8 is_header;
 599         u8 is_final;
 600 };
 601
 602 /**
 603  * This has list of async PDUs that are waiting to be processed.
 604  * Buffers live in this list for a brief duration before they get
 605  * processed and posted back to hardware.
 606  * Note that we don't really need one cri_wait_queue per async_entry.
 607  * We need one cri_wait_queue per CRI. Its easier to manage if this
 608  * is tagged along with the async_entry.
 609  */
 610 struct hd_async_entry {
 611         struct cri_wait_queue {
 612                 unsigned short hdr_len;
 613                 unsigned int bytes_received;
 614                 unsigned int bytes_needed;
 615                 struct list_head list;
 616         } wq;
 617         /* handles posted to FW resides here */
 618         struct hd_async_handle *header;
 619         struct hd_async_handle *data;
 620 };
 621
 622 struct hd_async_buf_context {
 623         struct be_bus_address pa_base;
 624         void *va_base;
 625         void *ring_base;
 626         struct hd_async_handle *handle_base;
 627         u16 free_entries;
 628         u32 buffer_size;
 629         /**
 630          * Once iSCSI layer finishes processing an async PDU, the
 631          * handles used for the PDU are added to this list.
 632          * They are posted back to FW in groups of 8.
 633          */
 634         struct list_head free_list;
 635 };
 636
 637 /**
 638  * hd_async_context is declared for each ULP supporting iSCSI function.
 639  */
 640 struct hd_async_context {
 641         struct hd_async_buf_context async_header;
 642         struct hd_async_buf_context async_data;
 643         u16 num_entries;
 644         /**
 645          * When unsol PDU is in, it needs to be chained till all the bytes are
 646          * received and then processing is done. hd_async_entry is created
 647          * based on the cid_count for each ULP. When unsol PDU comes in based
 648          * on the conn_id it needs to be added to the correct async_entry wq.
 649          * Below defined cid_to_async_cri_map is used to reterive the
 650          * async_cri_map for a particular connection.
 651          *
 652          * This array is initialized after beiscsi_create_wrb_rings returns.
 653          *
 654          * - this method takes more memory space, fixed to 2K
 655          * - any support for connections greater than this the array size needs
 656          * to be incremented
 657          */
 658 #define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
 659         unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
 660         /**
 661          * This is a variable size array. Don`t add anything after this field!!
 662          */
 663         struct hd_async_entry *async_entry;
 664 };
 665
 666 struct i_t_dpdu_cqe {
 667         u32 dw[4];
 668 } __packed;
 669
 670 /**
 671  * Pseudo amap definition in which each bit of the actual structure is defined
 672  * as a byte: used to calculate offset/shift/mask of each field
 673  */
 674 struct amap_i_t_dpdu_cqe {
 675         u8 db_addr_hi[32];
 676         u8 db_addr_lo[32];
 677         u8 code[6];
 678         u8 cid[10];
 679         u8 dpl[16];
 680         u8 index[16];
 681         u8 num_cons[10];
 682         u8 rsvd0[4];
 683         u8 final;
 684         u8 valid;
 685 } __packed;
 686
 687 struct amap_i_t_dpdu_cqe_v2 {
 688         u8 db_addr_hi[32];  /* DWORD 0 */
 689         u8 db_addr_lo[32];  /* DWORD 1 */
 690         u8 code[6]; /* DWORD 2 */
 691         u8 num_cons; /* DWORD 2*/
 692         u8 rsvd0[8]; /* DWORD 2 */
 693         u8 dpl[17]; /* DWORD 2 */
 694         u8 index[16]; /* DWORD 3 */
 695         u8 cid[13]; /* DWORD 3 */
 696         u8 rsvd1; /* DWORD 3 */
 697         u8 final; /* DWORD 3 */
 698         u8 valid; /* DWORD 3 */
 699 } __packed;
 700
 701 #define CQE_VALID_MASK  0x80000000
 702 #define CQE_CODE_MASK   0x0000003F
 703 #define CQE_CID_MASK    0x0000FFC0
 704
 705 #define EQE_VALID_MASK          0x00000001
 706 #define EQE_MAJORCODE_MASK      0x0000000E
 707 #define EQE_RESID_MASK          0xFFFF0000
 708
 709 struct be_eq_entry {
 710         u32 dw[1];
 711 } __packed;
 712
 713 /**
 714  * Pseudo amap definition in which each bit of the actual structure is defined
 715  * as a byte: used to calculate offset/shift/mask of each field
 716  */
 717 struct amap_eq_entry {
 718         u8 valid;               /* DWORD 0 */
 719         u8 major_code[3];       /* DWORD 0 */
 720         u8 minor_code[12];      /* DWORD 0 */
 721         u8 resource_id[16];     /* DWORD 0 */
 722
 723 } __packed;
 724
 725 struct cq_db {
 726         u32 dw[1];
 727 } __packed;
 728
 729 /**
 730  * Pseudo amap definition in which each bit of the actual structure is defined
 731  * as a byte: used to calculate offset/shift/mask of each field
 732  */
 733 struct amap_cq_db {
 734         u8 qid[10];
 735         u8 event[1];
 736         u8 rsvd0[5];
 737         u8 num_popped[13];
 738         u8 rearm[1];
 739         u8 rsvd1[2];
 740 } __packed;
 741
 742 void beiscsi_process_eq(struct beiscsi_hba *phba);
 743
 744 struct iscsi_wrb {
 745         u32 dw[16];
 746 } __packed;
 747
 748 #define WRB_TYPE_MASK 0xF0000000
 749 #define SKH_WRB_TYPE_OFFSET 27
 750 #define BE_WRB_TYPE_OFFSET  28
 751
 752 #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
 753                 (pwrb->dw[0] |= (wrb_type << type_offset))
 754
 755 /**
 756  * Pseudo amap definition in which each bit of the actual structure is defined
 757  * as a byte: used to calculate offset/shift/mask of each field
 758  */
 759 struct amap_iscsi_wrb {
 760         u8 lun[14];             /* DWORD 0 */
 761         u8 lt;                  /* DWORD 0 */
 762         u8 invld;               /* DWORD 0 */
 763         u8 wrb_idx[8];          /* DWORD 0 */
 764         u8 dsp;                 /* DWORD 0 */
 765         u8 dmsg;                /* DWORD 0 */
 766         u8 undr_run;            /* DWORD 0 */
 767         u8 over_run;            /* DWORD 0 */
 768         u8 type[4];             /* DWORD 0 */
 769         u8 ptr2nextwrb[8];      /* DWORD 1 */
 770         u8 r2t_exp_dtl[24];     /* DWORD 1 */
 771         u8 sgl_icd_idx[12];     /* DWORD 2 */
 772         u8 rsvd0[20];           /* DWORD 2 */
 773         u8 exp_data_sn[32];     /* DWORD 3 */
 774         u8 iscsi_bhs_addr_hi[32];       /* DWORD 4 */
 775         u8 iscsi_bhs_addr_lo[32];       /* DWORD 5 */
 776         u8 cmdsn_itt[32];       /* DWORD 6 */
 777         u8 dif_ref_tag[32];     /* DWORD 7 */
 778         u8 sge0_addr_hi[32];    /* DWORD 8 */
 779         u8 sge0_addr_lo[32];    /* DWORD 9  */
 780         u8 sge0_offset[22];     /* DWORD 10 */
 781         u8 pbs;                 /* DWORD 10 */
 782         u8 dif_mode[2];         /* DWORD 10 */
 783         u8 rsvd1[6];            /* DWORD 10 */
 784         u8 sge0_last;           /* DWORD 10 */
 785         u8 sge0_len[17];        /* DWORD 11 */
 786         u8 dif_meta_tag[14];    /* DWORD 11 */
 787         u8 sge0_in_ddr;         /* DWORD 11 */
 788         u8 sge1_addr_hi[32];    /* DWORD 12 */
 789         u8 sge1_addr_lo[32];    /* DWORD 13 */
 790         u8 sge1_r2t_offset[22]; /* DWORD 14 */
 791         u8 rsvd2[9];            /* DWORD 14 */
 792         u8 sge1_last;           /* DWORD 14 */
 793         u8 sge1_len[17];        /* DWORD 15 */
 794         u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
 795         u8 rsvd3[2];            /* DWORD 15 */
 796         u8 sge1_in_ddr;         /* DWORD 15 */
 797
 798 } __packed;
 799
 800 struct amap_iscsi_wrb_v2 {
 801         u8 r2t_exp_dtl[25]; /* DWORD 0 */
 802         u8 rsvd0[2];    /* DWORD 0*/
 803         u8 type[5];     /* DWORD 0 */
 804         u8 ptr2nextwrb[8];  /* DWORD 1 */
 805         u8 wrb_idx[8];      /* DWORD 1 */
 806         u8 lun[16];     /* DWORD 1 */
 807         u8 sgl_idx[16]; /* DWORD 2 */
 808         u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
 809         u8 exp_data_sn[32]; /* DWORD 3 */
 810         u8 iscsi_bhs_addr_hi[32];   /* DWORD 4 */
 811         u8 iscsi_bhs_addr_lo[32];   /* DWORD 5 */
 812         u8 cq_id[16];   /* DWORD 6 */
 813         u8 rsvd1[16];   /* DWORD 6 */
 814         u8 cmdsn_itt[32];   /* DWORD 7 */
 815         u8 sge0_addr_hi[32];    /* DWORD 8 */
 816         u8 sge0_addr_lo[32];    /* DWORD 9 */
 817         u8 sge0_offset[24]; /* DWORD 10 */
 818         u8 rsvd2[7];    /* DWORD 10 */
 819         u8 sge0_last;   /* DWORD 10 */
 820         u8 sge0_len[17];    /* DWORD 11 */
 821         u8 rsvd3[7];    /* DWORD 11 */
 822         u8 diff_enbl;   /* DWORD 11 */
 823         u8 u_run;       /* DWORD 11 */
 824         u8 o_run;       /* DWORD 11 */
 825         u8 invld;     /* DWORD 11 */
 826         u8 dsp;         /* DWORD 11 */
 827         u8 dmsg;        /* DWORD 11 */
 828         u8 rsvd4;       /* DWORD 11 */
 829         u8 lt;          /* DWORD 11 */
 830         u8 sge1_addr_hi[32];    /* DWORD 12 */
 831         u8 sge1_addr_lo[32];    /* DWORD 13 */
 832         u8 sge1_r2t_offset[24]; /* DWORD 14 */
 833         u8 rsvd5[7];    /* DWORD 14 */
 834         u8 sge1_last;   /* DWORD 14 */
 835         u8 sge1_len[17];    /* DWORD 15 */
 836         u8 rsvd6[15];   /* DWORD 15 */
 837 } __packed;
 838
 839
 840 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
 841                                      struct hwi_wrb_context **pcontext);
 842 void
 843 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
 844
 845 void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
 846                                      struct iscsi_task *task);
 847
 848 void hwi_ring_cq_db(struct beiscsi_hba *phba,
 849                      unsigned int id, unsigned int num_processed,
 850                      unsigned char rearm);
 851
 852 unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget);
 853 void beiscsi_process_mcc_cq(struct beiscsi_hba *phba);
 854
 855 struct pdu_nop_out {
 856         u32 dw[12];
 857 };
 858
 859 /**
 860  * Pseudo amap definition in which each bit of the actual structure is defined
 861  * as a byte: used to calculate offset/shift/mask of each field
 862  */
 863 struct amap_pdu_nop_out {
 864         u8 opcode[6];           /* opcode 0x00 */
 865         u8 i_bit;               /* I Bit */
 866         u8 x_bit;               /* reserved; should be 0 */
 867         u8 fp_bit_filler1[7];
 868         u8 f_bit;               /* always 1 */
 869         u8 reserved1[16];
 870         u8 ahs_length[8];       /* no AHS */
 871         u8 data_len_hi[8];
 872         u8 data_len_lo[16];     /* DataSegmentLength */
 873         u8 lun[64];
 874         u8 itt[32];             /* initiator id for ping or 0xffffffff */
 875         u8 ttt[32];             /* target id for ping or 0xffffffff */
 876         u8 cmd_sn[32];
 877         u8 exp_stat_sn[32];
 878         u8 reserved5[128];
 879 };
 880
 881 #define PDUBASE_OPCODE_MASK     0x0000003F
 882 #define PDUBASE_DATALENHI_MASK  0x0000FF00
 883 #define PDUBASE_DATALENLO_MASK  0xFFFF0000
 884
 885 struct pdu_base {
 886         u32 dw[16];
 887 } __packed;
 888
 889 /**
 890  * Pseudo amap definition in which each bit of the actual structure is defined
 891  * as a byte: used to calculate offset/shift/mask of each field
 892  */
 893 struct amap_pdu_base {
 894         u8 opcode[6];
 895         u8 i_bit;               /* immediate bit */
 896         u8 x_bit;               /* reserved, always 0 */
 897         u8 reserved1[24];       /* opcode-specific fields */
 898         u8 ahs_length[8];       /* length units is 4 byte words */
 899         u8 data_len_hi[8];
 900         u8 data_len_lo[16];     /* DatasegmentLength */
 901         u8 lun[64];             /* lun or opcode-specific fields */
 902         u8 itt[32];             /* initiator task tag */
 903         u8 reserved4[224];
 904 };
 905
 906 struct iscsi_target_context_update_wrb {
 907         u32 dw[16];
 908 } __packed;
 909
 910 /**
 911  * Pseudo amap definition in which each bit of the actual structure is defined
 912  * as a byte: used to calculate offset/shift/mask of each field
 913  */
 914 #define BE_TGT_CTX_UPDT_CMD 0x07
 915 struct amap_iscsi_target_context_update_wrb {
 916         u8 lun[14];             /* DWORD 0 */
 917         u8 lt;                  /* DWORD 0 */
 918         u8 invld;               /* DWORD 0 */
 919         u8 wrb_idx[8];          /* DWORD 0 */
 920         u8 dsp;                 /* DWORD 0 */
 921         u8 dmsg;                /* DWORD 0 */
 922         u8 undr_run;            /* DWORD 0 */
 923         u8 over_run;            /* DWORD 0 */
 924         u8 type[4];             /* DWORD 0 */
 925         u8 ptr2nextwrb[8];      /* DWORD 1 */
 926         u8 max_burst_length[19];        /* DWORD 1 */
 927         u8 rsvd0[5];            /* DWORD 1 */
 928         u8 rsvd1[15];           /* DWORD 2 */
 929         u8 max_send_data_segment_length[17];    /* DWORD 2 */
 930         u8 first_burst_length[14];      /* DWORD 3 */
 931         u8 rsvd2[2];            /* DWORD 3 */
 932         u8 tx_wrbindex_drv_msg[8];      /* DWORD 3 */
 933         u8 rsvd3[5];            /* DWORD 3 */
 934         u8 session_state[3];    /* DWORD 3 */
 935         u8 rsvd4[16];           /* DWORD 4 */
 936         u8 tx_jumbo;            /* DWORD 4 */
 937         u8 hde;                 /* DWORD 4 */
 938         u8 dde;                 /* DWORD 4 */
 939         u8 erl[2];              /* DWORD 4 */
 940         u8 domain_id[5];                /* DWORD 4 */
 941         u8 mode;                /* DWORD 4 */
 942         u8 imd;                 /* DWORD 4 */
 943         u8 ir2t;                /* DWORD 4 */
 944         u8 notpredblq[2];       /* DWORD 4 */
 945         u8 compltonack;         /* DWORD 4 */
 946         u8 stat_sn[32];         /* DWORD 5 */
 947         u8 pad_buffer_addr_hi[32];      /* DWORD 6 */
 948         u8 pad_buffer_addr_lo[32];      /* DWORD 7 */
 949         u8 pad_addr_hi[32];     /* DWORD 8 */
 950         u8 pad_addr_lo[32];     /* DWORD 9 */
 951         u8 rsvd5[32];           /* DWORD 10 */
 952         u8 rsvd6[32];           /* DWORD 11 */
 953         u8 rsvd7[32];           /* DWORD 12 */
 954         u8 rsvd8[32];           /* DWORD 13 */
 955         u8 rsvd9[32];           /* DWORD 14 */
 956         u8 rsvd10[32];          /* DWORD 15 */
 957
 958 } __packed;
 959
 960 #define BEISCSI_MAX_RECV_DATASEG_LEN    (64 * 1024)
 961 #define BEISCSI_MAX_CXNS    1
 962 struct amap_iscsi_target_context_update_wrb_v2 {
 963         u8 max_burst_length[24];    /* DWORD 0 */
 964         u8 rsvd0[3];    /* DWORD 0 */
 965         u8 type[5];     /* DWORD 0 */
 966         u8 ptr2nextwrb[8];  /* DWORD 1 */
 967         u8 wrb_idx[8];      /* DWORD 1 */
 968         u8 rsvd1[16];       /* DWORD 1 */
 969         u8 max_send_data_segment_length[24];    /* DWORD 2 */
 970         u8 rsvd2[8];    /* DWORD 2 */
 971         u8 first_burst_length[24]; /* DWORD 3 */
 972         u8 rsvd3[8]; /* DOWRD 3 */
 973         u8 max_r2t[16]; /* DWORD 4 */
 974         u8 rsvd4;       /* DWORD 4 */
 975         u8 hde;         /* DWORD 4 */
 976         u8 dde;         /* DWORD 4 */
 977         u8 erl[2];      /* DWORD 4 */
 978         u8 rsvd5[6];    /* DWORD 4 */
 979         u8 imd;         /* DWORD 4 */
 980         u8 ir2t;        /* DWORD 4 */
 981         u8 rsvd6[3];    /* DWORD 4 */
 982         u8 stat_sn[32];     /* DWORD 5 */
 983         u8 rsvd7[32];   /* DWORD 6 */
 984         u8 rsvd8[32];   /* DWORD 7 */
 985         u8 max_recv_dataseg_len[24];    /* DWORD 8 */
 986         u8 rsvd9[8]; /* DWORD 8 */
 987         u8 rsvd10[32];   /* DWORD 9 */
 988         u8 rsvd11[32];   /* DWORD 10 */
 989         u8 max_cxns[16]; /* DWORD 11 */
 990         u8 rsvd12[11]; /* DWORD  11*/
 991         u8 invld; /* DWORD 11 */
 992         u8 rsvd13;/* DWORD 11*/
 993         u8 dmsg; /* DWORD 11 */
 994         u8 data_seq_inorder; /* DWORD 11 */
 995         u8 pdu_seq_inorder; /* DWORD 11 */
 996         u8 rsvd14[32]; /*DWORD 12 */
 997         u8 rsvd15[32]; /* DWORD 13 */
 998         u8 rsvd16[32]; /* DWORD 14 */
 999         u8 rsvd17[32]; /* DWORD 15 */
1000 } __packed;
1001
1002
1003 struct be_ring {
1004         u32 pages;              /* queue size in pages */
1005         u32 id;                 /* queue id assigned by beklib */
1006         u32 num;                /* number of elements in queue */
1007         u32 cidx;               /* consumer index */
1008         u32 pidx;               /* producer index -- not used by most rings */
1009         u32 item_size;          /* size in bytes of one object */
1010         u8 ulp_num;     /* ULP to which CID binded */
1011         u16 register_set;
1012         u16 doorbell_format;
1013         u32 doorbell_offset;
1014
1015         void *va;               /* The virtual address of the ring.  This
1016                                  * should be last to allow 32 & 64 bit debugger
1017                                  * extensions to work.
1018                                  */
1019 };
1020
1021 struct hwi_controller {
1022         struct list_head io_sgl_list;
1023         struct list_head eh_sgl_list;
1024         struct sgl_handle *psgl_handle_base;
1025
1026         struct hwi_wrb_context *wrb_context;
1027         struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
1028         struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
1029         struct hwi_context_memory *phwi_ctxt;
1030 };
1031
1032 enum hwh_type_enum {
1033         HWH_TYPE_IO = 1,
1034         HWH_TYPE_LOGOUT = 2,
1035         HWH_TYPE_TMF = 3,
1036         HWH_TYPE_NOP = 4,
1037         HWH_TYPE_IO_RD = 5,
1038         HWH_TYPE_LOGIN = 11,
1039         HWH_TYPE_INVALID = 0xFFFFFFFF
1040 };
1041
1042 struct wrb_handle {
1043         unsigned short wrb_index;
1044         struct iscsi_task *pio_handle;
1045         struct iscsi_wrb *pwrb;
1046 };
1047
1048 struct hwi_context_memory {
1049         /* Adaptive interrupt coalescing (AIC) info */
1050         u16 min_eqd;            /* in usecs */
1051         u16 max_eqd;            /* in usecs */
1052         u16 cur_eqd;            /* in usecs */
1053         struct be_eq_obj be_eq[MAX_CPUS];
1054         struct be_queue_info be_cq[MAX_CPUS - 1];
1055
1056         struct be_queue_info *be_wrbq;
1057         /**
1058          * Create array of ULP number for below entries as DEFQ
1059          * will be created for both ULP if iSCSI Protocol is
1060          * loaded on both ULP.
1061          */
1062         struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1063         struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1064         struct hd_async_context *pasync_ctx[BEISCSI_ULP_COUNT];
1065 };
1066
1067 void beiscsi_start_boot_work(struct beiscsi_hba *phba, unsigned int s_handle);
1068
1069 /* Logging related definitions */
1070 #define BEISCSI_LOG_INIT        0x0001  /* Initialization events */
1071 #define BEISCSI_LOG_MBOX        0x0002  /* Mailbox Events */
1072 #define BEISCSI_LOG_MISC        0x0004  /* Miscllaneous Events */
1073 #define BEISCSI_LOG_EH          0x0008  /* Error Handler */
1074 #define BEISCSI_LOG_IO          0x0010  /* IO Code Path */
1075 #define BEISCSI_LOG_CONFIG      0x0020  /* CONFIG Code Path */
1076 #define BEISCSI_LOG_ISCSI       0x0040  /* SCSI/iSCSI Protocol related Logs */
1077
1078 #define __beiscsi_log(phba, level, fmt, arg...) \
1079         shost_printk(level, phba->shost, fmt, __LINE__, ##arg)
1080
1081 #define beiscsi_log(phba, level, mask, fmt, arg...) \
1082 do { \
1083         uint32_t log_value = phba->attr_log_enable; \
1084                 if (((mask) & log_value) || (level[1] <= '3')) \
1085                         __beiscsi_log(phba, level, fmt, ##arg); \
1086 } while (0);
1087
1088 #endif