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Merge tag 'edac_updates_for_5.9_pt2' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / bnx2fc / bnx2fc_hwi.c
1 /* bnx2fc_hwi.c: QLogic Linux FCoE offload driver.
2 * This file contains the code that low level functions that interact
3 * with 57712 FCoE firmware.
4 *
5 * Copyright (c) 2008-2013 Broadcom Corporation
6 * Copyright (c) 2014-2016 QLogic Corporation
7 * Copyright (c) 2016-2017 Cavium Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation.
12 *
13 * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com)
14 */
15
16 #include "bnx2fc.h"
17
18 DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu);
19
20 static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
21 struct fcoe_kcqe *new_cqe_kcqe);
22 static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
23 struct fcoe_kcqe *ofld_kcqe);
24 static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
25 struct fcoe_kcqe *ofld_kcqe);
26 static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code);
27 static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
28 struct fcoe_kcqe *destroy_kcqe);
29
30 int bnx2fc_send_stat_req(struct bnx2fc_hba *hba)
31 {
32 struct fcoe_kwqe_stat stat_req;
33 struct kwqe *kwqe_arr[2];
34 int num_kwqes = 1;
35 int rc = 0;
36
37 memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat));
38 stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT;
39 stat_req.hdr.flags =
40 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
41
42 stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma;
43 stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32);
44
45 kwqe_arr[0] = (struct kwqe *) &stat_req;
46
47 if (hba->cnic && hba->cnic->submit_kwqes)
48 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
49
50 return rc;
51 }
52
53 /**
54 * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w
55 *
56 * @hba: adapter structure pointer
57 *
58 * Send down FCoE firmware init KWQEs which initiates the initial handshake
59 * with the f/w.
60 *
61 */
62 int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
63 {
64 struct fcoe_kwqe_init1 fcoe_init1;
65 struct fcoe_kwqe_init2 fcoe_init2;
66 struct fcoe_kwqe_init3 fcoe_init3;
67 struct kwqe *kwqe_arr[3];
68 int num_kwqes = 3;
69 int rc = 0;
70
71 if (!hba->cnic) {
72 printk(KERN_ERR PFX "hba->cnic NULL during fcoe fw init\n");
73 return -ENODEV;
74 }
75
76 /* fill init1 KWQE */
77 memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1));
78 fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1;
79 fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
80 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
81
82 fcoe_init1.num_tasks = hba->max_tasks;
83 fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX;
84 fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX;
85 fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ;
86 fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX;
87 fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma;
88 fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32);
89 fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma;
90 fcoe_init1.task_list_pbl_addr_hi =
91 (u32) ((u64) hba->task_ctx_bd_dma >> 32);
92 fcoe_init1.mtu = BNX2FC_MINI_JUMBO_MTU;
93
94 fcoe_init1.flags = (PAGE_SHIFT <<
95 FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT);
96
97 fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG;
98
99 /* fill init2 KWQE */
100 memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2));
101 fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2;
102 fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
103 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
104
105 fcoe_init2.hsi_major_version = FCOE_HSI_MAJOR_VERSION;
106 fcoe_init2.hsi_minor_version = FCOE_HSI_MINOR_VERSION;
107
108
109 fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma;
110 fcoe_init2.hash_tbl_pbl_addr_hi = (u32)
111 ((u64) hba->hash_tbl_pbl_dma >> 32);
112
113 fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma;
114 fcoe_init2.t2_hash_tbl_addr_hi = (u32)
115 ((u64) hba->t2_hash_tbl_dma >> 32);
116
117 fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma;
118 fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32)
119 ((u64) hba->t2_hash_tbl_ptr_dma >> 32);
120
121 fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS;
122
123 /* fill init3 KWQE */
124 memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3));
125 fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3;
126 fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
127 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
128 fcoe_init3.error_bit_map_lo = 0xffffffff;
129 fcoe_init3.error_bit_map_hi = 0xffffffff;
130
131 /*
132 * enable both cached connection and cached tasks
133 * 0 = none, 1 = cached connection, 2 = cached tasks, 3 = both
134 */
135 fcoe_init3.perf_config = 3;
136
137 kwqe_arr[0] = (struct kwqe *) &fcoe_init1;
138 kwqe_arr[1] = (struct kwqe *) &fcoe_init2;
139 kwqe_arr[2] = (struct kwqe *) &fcoe_init3;
140
141 if (hba->cnic && hba->cnic->submit_kwqes)
142 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
143
144 return rc;
145 }
146 int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba)
147 {
148 struct fcoe_kwqe_destroy fcoe_destroy;
149 struct kwqe *kwqe_arr[2];
150 int num_kwqes = 1;
151 int rc = -1;
152
153 /* fill destroy KWQE */
154 memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy));
155 fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY;
156 fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
157 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
158 kwqe_arr[0] = (struct kwqe *) &fcoe_destroy;
159
160 if (hba->cnic && hba->cnic->submit_kwqes)
161 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
162 return rc;
163 }
164
165 /**
166 * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process
167 *
168 * @port: port structure pointer
169 * @tgt: bnx2fc_rport structure pointer
170 */
171 int bnx2fc_send_session_ofld_req(struct fcoe_port *port,
172 struct bnx2fc_rport *tgt)
173 {
174 struct fc_lport *lport = port->lport;
175 struct bnx2fc_interface *interface = port->priv;
176 struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
177 struct bnx2fc_hba *hba = interface->hba;
178 struct kwqe *kwqe_arr[4];
179 struct fcoe_kwqe_conn_offload1 ofld_req1;
180 struct fcoe_kwqe_conn_offload2 ofld_req2;
181 struct fcoe_kwqe_conn_offload3 ofld_req3;
182 struct fcoe_kwqe_conn_offload4 ofld_req4;
183 struct fc_rport_priv *rdata = tgt->rdata;
184 struct fc_rport *rport = tgt->rport;
185 int num_kwqes = 4;
186 u32 port_id;
187 int rc = 0;
188 u16 conn_id;
189
190 /* Initialize offload request 1 structure */
191 memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1));
192
193 ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1;
194 ofld_req1.hdr.flags =
195 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
196
197
198 conn_id = (u16)tgt->fcoe_conn_id;
199 ofld_req1.fcoe_conn_id = conn_id;
200
201
202 ofld_req1.sq_addr_lo = (u32) tgt->sq_dma;
203 ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32);
204
205 ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma;
206 ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32);
207
208 ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma;
209 ofld_req1.rq_first_pbe_addr_hi =
210 (u32)((u64) tgt->rq_dma >> 32);
211
212 ofld_req1.rq_prod = 0x8000;
213
214 /* Initialize offload request 2 structure */
215 memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2));
216
217 ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2;
218 ofld_req2.hdr.flags =
219 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
220
221 ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size;
222
223 ofld_req2.cq_addr_lo = (u32) tgt->cq_dma;
224 ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32);
225
226 ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma;
227 ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32);
228
229 ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma;
230 ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32);
231
232 /* Initialize offload request 3 structure */
233 memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3));
234
235 ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3;
236 ofld_req3.hdr.flags =
237 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
238
239 ofld_req3.vlan_tag = interface->vlan_id <<
240 FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT;
241 ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT;
242
243 port_id = fc_host_port_id(lport->host);
244 if (port_id == 0) {
245 BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n");
246 return -EINVAL;
247 }
248
249 /*
250 * Store s_id of the initiator for further reference. This will
251 * be used during disable/destroy during linkdown processing as
252 * when the lport is reset, the port_id also is reset to 0
253 */
254 tgt->sid = port_id;
255 ofld_req3.s_id[0] = (port_id & 0x000000FF);
256 ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8;
257 ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16;
258
259 port_id = rport->port_id;
260 ofld_req3.d_id[0] = (port_id & 0x000000FF);
261 ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8;
262 ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16;
263
264 ofld_req3.tx_total_conc_seqs = rdata->max_seq;
265
266 ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq;
267 ofld_req3.rx_max_fc_pay_len = lport->mfs;
268
269 ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS;
270 ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS;
271 ofld_req3.rx_open_seqs_exch_c3 = 1;
272
273 ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma;
274 ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32);
275
276 /* set mul_n_port_ids supported flag to 0, until it is supported */
277 ofld_req3.flags = 0;
278 /*
279 ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) <<
280 FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT);
281 */
282 /* Info from PLOGI response */
283 ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) <<
284 FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT);
285
286 ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) <<
287 FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT);
288
289 /*
290 * Info from PRLI response, this info is used for sequence level error
291 * recovery support
292 */
293 if (tgt->dev_type == TYPE_TAPE) {
294 ofld_req3.flags |= 1 <<
295 FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT;
296 ofld_req3.flags |= (((rdata->flags & FC_RP_FLAGS_REC_SUPPORTED)
297 ? 1 : 0) <<
298 FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT);
299 }
300
301 /* vlan flag */
302 ofld_req3.flags |= (interface->vlan_enabled <<
303 FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT);
304
305 /* C2_VALID and ACK flags are not set as they are not supported */
306
307
308 /* Initialize offload request 4 structure */
309 memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4));
310 ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4;
311 ofld_req4.hdr.flags =
312 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
313
314 ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20;
315
316
317 ofld_req4.src_mac_addr_lo[0] = port->data_src_addr[5];
318 /* local mac */
319 ofld_req4.src_mac_addr_lo[1] = port->data_src_addr[4];
320 ofld_req4.src_mac_addr_mid[0] = port->data_src_addr[3];
321 ofld_req4.src_mac_addr_mid[1] = port->data_src_addr[2];
322 ofld_req4.src_mac_addr_hi[0] = port->data_src_addr[1];
323 ofld_req4.src_mac_addr_hi[1] = port->data_src_addr[0];
324 ofld_req4.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
325 /* fcf mac */
326 ofld_req4.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
327 ofld_req4.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
328 ofld_req4.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
329 ofld_req4.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
330 ofld_req4.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
331
332 ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma;
333 ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32);
334
335 ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma;
336 ofld_req4.confq_pbl_base_addr_hi =
337 (u32)((u64) tgt->confq_pbl_dma >> 32);
338
339 kwqe_arr[0] = (struct kwqe *) &ofld_req1;
340 kwqe_arr[1] = (struct kwqe *) &ofld_req2;
341 kwqe_arr[2] = (struct kwqe *) &ofld_req3;
342 kwqe_arr[3] = (struct kwqe *) &ofld_req4;
343
344 if (hba->cnic && hba->cnic->submit_kwqes)
345 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
346
347 return rc;
348 }
349
350 /**
351 * bnx2fc_send_session_enable_req - initiates FCoE Session enablement
352 *
353 * @port: port structure pointer
354 * @tgt: bnx2fc_rport structure pointer
355 */
356 int bnx2fc_send_session_enable_req(struct fcoe_port *port,
357 struct bnx2fc_rport *tgt)
358 {
359 struct kwqe *kwqe_arr[2];
360 struct bnx2fc_interface *interface = port->priv;
361 struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
362 struct bnx2fc_hba *hba = interface->hba;
363 struct fcoe_kwqe_conn_enable_disable enbl_req;
364 struct fc_lport *lport = port->lport;
365 struct fc_rport *rport = tgt->rport;
366 int num_kwqes = 1;
367 int rc = 0;
368 u32 port_id;
369
370 memset(&enbl_req, 0x00,
371 sizeof(struct fcoe_kwqe_conn_enable_disable));
372 enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN;
373 enbl_req.hdr.flags =
374 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
375
376 enbl_req.src_mac_addr_lo[0] = port->data_src_addr[5];
377 /* local mac */
378 enbl_req.src_mac_addr_lo[1] = port->data_src_addr[4];
379 enbl_req.src_mac_addr_mid[0] = port->data_src_addr[3];
380 enbl_req.src_mac_addr_mid[1] = port->data_src_addr[2];
381 enbl_req.src_mac_addr_hi[0] = port->data_src_addr[1];
382 enbl_req.src_mac_addr_hi[1] = port->data_src_addr[0];
383 memcpy(tgt->src_addr, port->data_src_addr, ETH_ALEN);
384
385 enbl_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
386 enbl_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
387 enbl_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
388 enbl_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
389 enbl_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
390 enbl_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
391
392 port_id = fc_host_port_id(lport->host);
393 if (port_id != tgt->sid) {
394 printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x,"
395 "sid = 0x%x\n", port_id, tgt->sid);
396 port_id = tgt->sid;
397 }
398 enbl_req.s_id[0] = (port_id & 0x000000FF);
399 enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
400 enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
401
402 port_id = rport->port_id;
403 enbl_req.d_id[0] = (port_id & 0x000000FF);
404 enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
405 enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
406 enbl_req.vlan_tag = interface->vlan_id <<
407 FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
408 enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
409 enbl_req.vlan_flag = interface->vlan_enabled;
410 enbl_req.context_id = tgt->context_id;
411 enbl_req.conn_id = tgt->fcoe_conn_id;
412
413 kwqe_arr[0] = (struct kwqe *) &enbl_req;
414
415 if (hba->cnic && hba->cnic->submit_kwqes)
416 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
417 return rc;
418 }
419
420 /**
421 * bnx2fc_send_session_disable_req - initiates FCoE Session disable
422 *
423 * @port: port structure pointer
424 * @tgt: bnx2fc_rport structure pointer
425 */
426 int bnx2fc_send_session_disable_req(struct fcoe_port *port,
427 struct bnx2fc_rport *tgt)
428 {
429 struct bnx2fc_interface *interface = port->priv;
430 struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
431 struct bnx2fc_hba *hba = interface->hba;
432 struct fcoe_kwqe_conn_enable_disable disable_req;
433 struct kwqe *kwqe_arr[2];
434 struct fc_rport *rport = tgt->rport;
435 int num_kwqes = 1;
436 int rc = 0;
437 u32 port_id;
438
439 memset(&disable_req, 0x00,
440 sizeof(struct fcoe_kwqe_conn_enable_disable));
441 disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN;
442 disable_req.hdr.flags =
443 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
444
445 disable_req.src_mac_addr_lo[0] = tgt->src_addr[5];
446 disable_req.src_mac_addr_lo[1] = tgt->src_addr[4];
447 disable_req.src_mac_addr_mid[0] = tgt->src_addr[3];
448 disable_req.src_mac_addr_mid[1] = tgt->src_addr[2];
449 disable_req.src_mac_addr_hi[0] = tgt->src_addr[1];
450 disable_req.src_mac_addr_hi[1] = tgt->src_addr[0];
451
452 disable_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
453 disable_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
454 disable_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
455 disable_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
456 disable_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
457 disable_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
458
459 port_id = tgt->sid;
460 disable_req.s_id[0] = (port_id & 0x000000FF);
461 disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
462 disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
463
464
465 port_id = rport->port_id;
466 disable_req.d_id[0] = (port_id & 0x000000FF);
467 disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
468 disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
469 disable_req.context_id = tgt->context_id;
470 disable_req.conn_id = tgt->fcoe_conn_id;
471 disable_req.vlan_tag = interface->vlan_id <<
472 FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
473 disable_req.vlan_tag |=
474 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
475 disable_req.vlan_flag = interface->vlan_enabled;
476
477 kwqe_arr[0] = (struct kwqe *) &disable_req;
478
479 if (hba->cnic && hba->cnic->submit_kwqes)
480 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
481
482 return rc;
483 }
484
485 /**
486 * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy
487 *
488 * @hba: adapter structure pointer
489 * @tgt: bnx2fc_rport structure pointer
490 */
491 int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba,
492 struct bnx2fc_rport *tgt)
493 {
494 struct fcoe_kwqe_conn_destroy destroy_req;
495 struct kwqe *kwqe_arr[2];
496 int num_kwqes = 1;
497 int rc = 0;
498
499 memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy));
500 destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN;
501 destroy_req.hdr.flags =
502 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
503
504 destroy_req.context_id = tgt->context_id;
505 destroy_req.conn_id = tgt->fcoe_conn_id;
506
507 kwqe_arr[0] = (struct kwqe *) &destroy_req;
508
509 if (hba->cnic && hba->cnic->submit_kwqes)
510 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
511
512 return rc;
513 }
514
515 static bool is_valid_lport(struct bnx2fc_hba *hba, struct fc_lport *lport)
516 {
517 struct bnx2fc_lport *blport;
518
519 spin_lock_bh(&hba->hba_lock);
520 list_for_each_entry(blport, &hba->vports, list) {
521 if (blport->lport == lport) {
522 spin_unlock_bh(&hba->hba_lock);
523 return true;
524 }
525 }
526 spin_unlock_bh(&hba->hba_lock);
527 return false;
528
529 }
530
531
532 static void bnx2fc_unsol_els_work(struct work_struct *work)
533 {
534 struct bnx2fc_unsol_els *unsol_els;
535 struct fc_lport *lport;
536 struct bnx2fc_hba *hba;
537 struct fc_frame *fp;
538
539 unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work);
540 lport = unsol_els->lport;
541 fp = unsol_els->fp;
542 hba = unsol_els->hba;
543 if (is_valid_lport(hba, lport))
544 fc_exch_recv(lport, fp);
545 kfree(unsol_els);
546 }
547
548 void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt,
549 unsigned char *buf,
550 u32 frame_len, u16 l2_oxid)
551 {
552 struct fcoe_port *port = tgt->port;
553 struct fc_lport *lport = port->lport;
554 struct bnx2fc_interface *interface = port->priv;
555 struct bnx2fc_unsol_els *unsol_els;
556 struct fc_frame_header *fh;
557 struct fc_frame *fp;
558 struct sk_buff *skb;
559 u32 payload_len;
560 u32 crc;
561 u8 op;
562
563
564 unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC);
565 if (!unsol_els) {
566 BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n");
567 return;
568 }
569
570 BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n",
571 l2_oxid, frame_len);
572
573 payload_len = frame_len - sizeof(struct fc_frame_header);
574
575 fp = fc_frame_alloc(lport, payload_len);
576 if (!fp) {
577 printk(KERN_ERR PFX "fc_frame_alloc failure\n");
578 kfree(unsol_els);
579 return;
580 }
581
582 fh = (struct fc_frame_header *) fc_frame_header_get(fp);
583 /* Copy FC Frame header and payload into the frame */
584 memcpy(fh, buf, frame_len);
585
586 if (l2_oxid != FC_XID_UNKNOWN)
587 fh->fh_ox_id = htons(l2_oxid);
588
589 skb = fp_skb(fp);
590
591 if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) ||
592 (fh->fh_r_ctl == FC_RCTL_ELS_REP)) {
593
594 if (fh->fh_type == FC_TYPE_ELS) {
595 op = fc_frame_payload_op(fp);
596 if ((op == ELS_TEST) || (op == ELS_ESTC) ||
597 (op == ELS_FAN) || (op == ELS_CSU)) {
598 /*
599 * No need to reply for these
600 * ELS requests
601 */
602 printk(KERN_ERR PFX "dropping ELS 0x%x\n", op);
603 kfree_skb(skb);
604 kfree(unsol_els);
605 return;
606 }
607 }
608 crc = fcoe_fc_crc(fp);
609 fc_frame_init(fp);
610 fr_dev(fp) = lport;
611 fr_sof(fp) = FC_SOF_I3;
612 fr_eof(fp) = FC_EOF_T;
613 fr_crc(fp) = cpu_to_le32(~crc);
614 unsol_els->lport = lport;
615 unsol_els->hba = interface->hba;
616 unsol_els->fp = fp;
617 INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work);
618 queue_work(bnx2fc_wq, &unsol_els->unsol_els_work);
619 } else {
620 BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl);
621 kfree_skb(skb);
622 kfree(unsol_els);
623 }
624 }
625
626 static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
627 {
628 u8 num_rq;
629 struct fcoe_err_report_entry *err_entry;
630 unsigned char *rq_data;
631 unsigned char *buf = NULL, *buf1;
632 int i;
633 u16 xid;
634 u32 frame_len, len;
635 struct bnx2fc_cmd *io_req = NULL;
636 struct bnx2fc_interface *interface = tgt->port->priv;
637 struct bnx2fc_hba *hba = interface->hba;
638 int rc = 0;
639 u64 err_warn_bit_map;
640 u8 err_warn = 0xff;
641
642
643 BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe);
644 switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) {
645 case FCOE_UNSOLICITED_FRAME_CQE_TYPE:
646 frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >>
647 FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT;
648
649 num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ;
650
651 spin_lock_bh(&tgt->tgt_lock);
652 rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq);
653 spin_unlock_bh(&tgt->tgt_lock);
654
655 if (rq_data) {
656 buf = rq_data;
657 } else {
658 buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ),
659 GFP_ATOMIC);
660
661 if (!buf1) {
662 BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n");
663 break;
664 }
665
666 for (i = 0; i < num_rq; i++) {
667 spin_lock_bh(&tgt->tgt_lock);
668 rq_data = (unsigned char *)
669 bnx2fc_get_next_rqe(tgt, 1);
670 spin_unlock_bh(&tgt->tgt_lock);
671 len = BNX2FC_RQ_BUF_SZ;
672 memcpy(buf1, rq_data, len);
673 buf1 += len;
674 }
675 }
676 bnx2fc_process_l2_frame_compl(tgt, buf, frame_len,
677 FC_XID_UNKNOWN);
678
679 if (buf != rq_data)
680 kfree(buf);
681 spin_lock_bh(&tgt->tgt_lock);
682 bnx2fc_return_rqe(tgt, num_rq);
683 spin_unlock_bh(&tgt->tgt_lock);
684 break;
685
686 case FCOE_ERROR_DETECTION_CQE_TYPE:
687 /*
688 * In case of error reporting CQE a single RQ entry
689 * is consumed.
690 */
691 spin_lock_bh(&tgt->tgt_lock);
692 num_rq = 1;
693 err_entry = (struct fcoe_err_report_entry *)
694 bnx2fc_get_next_rqe(tgt, 1);
695 xid = err_entry->fc_hdr.ox_id;
696 BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid);
697 BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n",
698 err_entry->data.err_warn_bitmap_hi,
699 err_entry->data.err_warn_bitmap_lo);
700 BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n",
701 err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
702
703 if (xid > hba->max_xid) {
704 BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n",
705 xid);
706 goto ret_err_rqe;
707 }
708
709
710 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
711 if (!io_req)
712 goto ret_err_rqe;
713
714 if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
715 printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
716 goto ret_err_rqe;
717 }
718
719 if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP,
720 &io_req->req_flags)) {
721 BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in "
722 "progress.. ignore unsol err\n");
723 goto ret_err_rqe;
724 }
725
726 err_warn_bit_map = (u64)
727 ((u64)err_entry->data.err_warn_bitmap_hi << 32) |
728 (u64)err_entry->data.err_warn_bitmap_lo;
729 for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) {
730 if (err_warn_bit_map & (u64)((u64)1 << i)) {
731 err_warn = i;
732 break;
733 }
734 }
735
736 /*
737 * If ABTS is already in progress, and FW error is
738 * received after that, do not cancel the timeout_work
739 * and let the error recovery continue by explicitly
740 * logging out the target, when the ABTS eventually
741 * times out.
742 */
743 if (test_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags)) {
744 printk(KERN_ERR PFX "err_warn: io_req (0x%x) already "
745 "in ABTS processing\n", xid);
746 goto ret_err_rqe;
747 }
748 BNX2FC_TGT_DBG(tgt, "err = 0x%x\n", err_warn);
749 if (tgt->dev_type != TYPE_TAPE)
750 goto skip_rec;
751 switch (err_warn) {
752 case FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION:
753 case FCOE_ERROR_CODE_DATA_OOO_RO:
754 case FCOE_ERROR_CODE_COMMON_INCORRECT_SEQ_CNT:
755 case FCOE_ERROR_CODE_DATA_SOFI3_SEQ_ACTIVE_SET:
756 case FCOE_ERROR_CODE_FCP_RSP_OPENED_SEQ:
757 case FCOE_ERROR_CODE_DATA_SOFN_SEQ_ACTIVE_RESET:
758 BNX2FC_TGT_DBG(tgt, "REC TOV popped for xid - 0x%x\n",
759 xid);
760 memcpy(&io_req->err_entry, err_entry,
761 sizeof(struct fcoe_err_report_entry));
762 if (!test_bit(BNX2FC_FLAG_SRR_SENT,
763 &io_req->req_flags)) {
764 spin_unlock_bh(&tgt->tgt_lock);
765 rc = bnx2fc_send_rec(io_req);
766 spin_lock_bh(&tgt->tgt_lock);
767
768 if (rc)
769 goto skip_rec;
770 } else
771 printk(KERN_ERR PFX "SRR in progress\n");
772 goto ret_err_rqe;
773 break;
774 default:
775 break;
776 }
777
778 skip_rec:
779 set_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags);
780 /*
781 * Cancel the timeout_work, as we received IO
782 * completion with FW error.
783 */
784 if (cancel_delayed_work(&io_req->timeout_work))
785 kref_put(&io_req->refcount, bnx2fc_cmd_release);
786
787 rc = bnx2fc_initiate_abts(io_req);
788 if (rc != SUCCESS) {
789 printk(KERN_ERR PFX "err_warn: initiate_abts "
790 "failed xid = 0x%x. issue cleanup\n",
791 io_req->xid);
792 bnx2fc_initiate_cleanup(io_req);
793 }
794 ret_err_rqe:
795 bnx2fc_return_rqe(tgt, 1);
796 spin_unlock_bh(&tgt->tgt_lock);
797 break;
798
799 case FCOE_WARNING_DETECTION_CQE_TYPE:
800 /*
801 *In case of warning reporting CQE a single RQ entry
802 * is consumes.
803 */
804 spin_lock_bh(&tgt->tgt_lock);
805 num_rq = 1;
806 err_entry = (struct fcoe_err_report_entry *)
807 bnx2fc_get_next_rqe(tgt, 1);
808 xid = cpu_to_be16(err_entry->fc_hdr.ox_id);
809 BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid);
810 BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x",
811 err_entry->data.err_warn_bitmap_hi,
812 err_entry->data.err_warn_bitmap_lo);
813 BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x",
814 err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
815
816 if (xid > hba->max_xid) {
817 BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n", xid);
818 goto ret_warn_rqe;
819 }
820
821 err_warn_bit_map = (u64)
822 ((u64)err_entry->data.err_warn_bitmap_hi << 32) |
823 (u64)err_entry->data.err_warn_bitmap_lo;
824 for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) {
825 if (err_warn_bit_map & ((u64)1 << i)) {
826 err_warn = i;
827 break;
828 }
829 }
830 BNX2FC_TGT_DBG(tgt, "warn = 0x%x\n", err_warn);
831
832 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
833 if (!io_req)
834 goto ret_warn_rqe;
835
836 if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
837 printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
838 goto ret_warn_rqe;
839 }
840
841 memcpy(&io_req->err_entry, err_entry,
842 sizeof(struct fcoe_err_report_entry));
843
844 if (err_warn == FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION)
845 /* REC_TOV is not a warning code */
846 BUG_ON(1);
847 else
848 BNX2FC_TGT_DBG(tgt, "Unsolicited warning\n");
849 ret_warn_rqe:
850 bnx2fc_return_rqe(tgt, 1);
851 spin_unlock_bh(&tgt->tgt_lock);
852 break;
853
854 default:
855 printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n");
856 break;
857 }
858 }
859
860 void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe,
861 unsigned char *rq_data, u8 num_rq,
862 struct fcoe_task_ctx_entry *task)
863 {
864 struct fcoe_port *port = tgt->port;
865 struct bnx2fc_interface *interface = port->priv;
866 struct bnx2fc_hba *hba = interface->hba;
867 struct bnx2fc_cmd *io_req;
868
869 u16 xid;
870 u8 cmd_type;
871 u8 rx_state = 0;
872
873 spin_lock_bh(&tgt->tgt_lock);
874
875 xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
876 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
877
878 if (io_req == NULL) {
879 printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n");
880 spin_unlock_bh(&tgt->tgt_lock);
881 return;
882 }
883
884 /* Timestamp IO completion time */
885 cmd_type = io_req->cmd_type;
886
887 rx_state = ((task->rxwr_txrd.var_ctx.rx_flags &
888 FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE) >>
889 FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT);
890
891 /* Process other IO completion types */
892 switch (cmd_type) {
893 case BNX2FC_SCSI_CMD:
894 if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
895 bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq,
896 rq_data);
897 spin_unlock_bh(&tgt->tgt_lock);
898 return;
899 }
900
901 if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
902 bnx2fc_process_abts_compl(io_req, task, num_rq);
903 else if (rx_state ==
904 FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
905 bnx2fc_process_cleanup_compl(io_req, task, num_rq);
906 else
907 printk(KERN_ERR PFX "Invalid rx state - %d\n",
908 rx_state);
909 break;
910
911 case BNX2FC_TASK_MGMT_CMD:
912 BNX2FC_IO_DBG(io_req, "Processing TM complete\n");
913 bnx2fc_process_tm_compl(io_req, task, num_rq, rq_data);
914 break;
915
916 case BNX2FC_ABTS:
917 /*
918 * ABTS request received by firmware. ABTS response
919 * will be delivered to the task belonging to the IO
920 * that was aborted
921 */
922 BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n");
923 kref_put(&io_req->refcount, bnx2fc_cmd_release);
924 break;
925
926 case BNX2FC_ELS:
927 if (rx_state == FCOE_TASK_RX_STATE_COMPLETED)
928 bnx2fc_process_els_compl(io_req, task, num_rq);
929 else if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
930 bnx2fc_process_abts_compl(io_req, task, num_rq);
931 else if (rx_state ==
932 FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
933 bnx2fc_process_cleanup_compl(io_req, task, num_rq);
934 else
935 printk(KERN_ERR PFX "Invalid rx state = %d\n",
936 rx_state);
937 break;
938
939 case BNX2FC_CLEANUP:
940 BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n");
941 kref_put(&io_req->refcount, bnx2fc_cmd_release);
942 break;
943
944 case BNX2FC_SEQ_CLEANUP:
945 BNX2FC_IO_DBG(io_req, "cq_compl(0x%x) - seq cleanup resp\n",
946 io_req->xid);
947 bnx2fc_process_seq_cleanup_compl(io_req, task, rx_state);
948 kref_put(&io_req->refcount, bnx2fc_cmd_release);
949 break;
950
951 default:
952 printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type);
953 break;
954 }
955 spin_unlock_bh(&tgt->tgt_lock);
956 }
957
958 void bnx2fc_arm_cq(struct bnx2fc_rport *tgt)
959 {
960 struct b577xx_fcoe_rx_doorbell *rx_db = &tgt->rx_db;
961 u32 msg;
962
963 wmb();
964 rx_db->doorbell_cq_cons = tgt->cq_cons_idx | (tgt->cq_curr_toggle_bit <<
965 FCOE_CQE_TOGGLE_BIT_SHIFT);
966 msg = *((u32 *)rx_db);
967 writel(cpu_to_le32(msg), tgt->ctx_base);
968
969 }
970
971 static struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe,
972 unsigned char *rq_data, u8 num_rq,
973 struct fcoe_task_ctx_entry *task)
974 {
975 struct bnx2fc_work *work;
976 work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC);
977 if (!work)
978 return NULL;
979
980 INIT_LIST_HEAD(&work->list);
981 work->tgt = tgt;
982 work->wqe = wqe;
983 work->num_rq = num_rq;
984 work->task = task;
985 if (rq_data)
986 memcpy(work->rq_data, rq_data, BNX2FC_RQ_BUF_SZ);
987
988 return work;
989 }
990
991 /* Pending work request completion */
992 static bool bnx2fc_pending_work(struct bnx2fc_rport *tgt, unsigned int wqe)
993 {
994 unsigned int cpu = wqe % num_possible_cpus();
995 struct bnx2fc_percpu_s *fps;
996 struct bnx2fc_work *work;
997 struct fcoe_task_ctx_entry *task;
998 struct fcoe_task_ctx_entry *task_page;
999 struct fcoe_port *port = tgt->port;
1000 struct bnx2fc_interface *interface = port->priv;
1001 struct bnx2fc_hba *hba = interface->hba;
1002 unsigned char *rq_data = NULL;
1003 unsigned char rq_data_buff[BNX2FC_RQ_BUF_SZ];
1004 int task_idx, index;
1005 u16 xid;
1006 u8 num_rq;
1007 int i;
1008
1009 xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
1010 if (xid >= hba->max_tasks) {
1011 pr_err(PFX "ERROR:xid out of range\n");
1012 return false;
1013 }
1014
1015 task_idx = xid / BNX2FC_TASKS_PER_PAGE;
1016 index = xid % BNX2FC_TASKS_PER_PAGE;
1017 task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx];
1018 task = &task_page[index];
1019
1020 num_rq = ((task->rxwr_txrd.var_ctx.rx_flags &
1021 FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE) >>
1022 FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT);
1023
1024 memset(rq_data_buff, 0, BNX2FC_RQ_BUF_SZ);
1025
1026 if (!num_rq)
1027 goto num_rq_zero;
1028
1029 rq_data = bnx2fc_get_next_rqe(tgt, 1);
1030
1031 if (num_rq > 1) {
1032 /* We do not need extra sense data */
1033 for (i = 1; i < num_rq; i++)
1034 bnx2fc_get_next_rqe(tgt, 1);
1035 }
1036
1037 if (rq_data)
1038 memcpy(rq_data_buff, rq_data, BNX2FC_RQ_BUF_SZ);
1039
1040 /* return RQ entries */
1041 for (i = 0; i < num_rq; i++)
1042 bnx2fc_return_rqe(tgt, 1);
1043
1044 num_rq_zero:
1045
1046 fps = &per_cpu(bnx2fc_percpu, cpu);
1047 spin_lock_bh(&fps->fp_work_lock);
1048 if (fps->iothread) {
1049 work = bnx2fc_alloc_work(tgt, wqe, rq_data_buff,
1050 num_rq, task);
1051 if (work) {
1052 list_add_tail(&work->list, &fps->work_list);
1053 wake_up_process(fps->iothread);
1054 spin_unlock_bh(&fps->fp_work_lock);
1055 return true;
1056 }
1057 }
1058 spin_unlock_bh(&fps->fp_work_lock);
1059 bnx2fc_process_cq_compl(tgt, wqe,
1060 rq_data_buff, num_rq, task);
1061
1062 return true;
1063 }
1064
1065 int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
1066 {
1067 struct fcoe_cqe *cq;
1068 u32 cq_cons;
1069 struct fcoe_cqe *cqe;
1070 u32 num_free_sqes = 0;
1071 u32 num_cqes = 0;
1072 u16 wqe;
1073
1074 /*
1075 * cq_lock is a low contention lock used to protect
1076 * the CQ data structure from being freed up during
1077 * the upload operation
1078 */
1079 spin_lock_bh(&tgt->cq_lock);
1080
1081 if (!tgt->cq) {
1082 printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n");
1083 spin_unlock_bh(&tgt->cq_lock);
1084 return 0;
1085 }
1086 cq = tgt->cq;
1087 cq_cons = tgt->cq_cons_idx;
1088 cqe = &cq[cq_cons];
1089
1090 while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
1091 (tgt->cq_curr_toggle_bit <<
1092 FCOE_CQE_TOGGLE_BIT_SHIFT)) {
1093
1094 /* new entry on the cq */
1095 if (wqe & FCOE_CQE_CQE_TYPE) {
1096 /* Unsolicited event notification */
1097 bnx2fc_process_unsol_compl(tgt, wqe);
1098 } else {
1099 if (bnx2fc_pending_work(tgt, wqe))
1100 num_free_sqes++;
1101 }
1102 cqe++;
1103 tgt->cq_cons_idx++;
1104 num_cqes++;
1105
1106 if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
1107 tgt->cq_cons_idx = 0;
1108 cqe = cq;
1109 tgt->cq_curr_toggle_bit =
1110 1 - tgt->cq_curr_toggle_bit;
1111 }
1112 }
1113 if (num_cqes) {
1114 /* Arm CQ only if doorbell is mapped */
1115 if (tgt->ctx_base)
1116 bnx2fc_arm_cq(tgt);
1117 atomic_add(num_free_sqes, &tgt->free_sqes);
1118 }
1119 spin_unlock_bh(&tgt->cq_lock);
1120 return 0;
1121 }
1122
1123 /**
1124 * bnx2fc_fastpath_notification - process global event queue (KCQ)
1125 *
1126 * @hba: adapter structure pointer
1127 * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry
1128 *
1129 * Fast path event notification handler
1130 */
1131 static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
1132 struct fcoe_kcqe *new_cqe_kcqe)
1133 {
1134 u32 conn_id = new_cqe_kcqe->fcoe_conn_id;
1135 struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id];
1136
1137 if (!tgt) {
1138 printk(KERN_ERR PFX "conn_id 0x%x not valid\n", conn_id);
1139 return;
1140 }
1141
1142 bnx2fc_process_new_cqes(tgt);
1143 }
1144
1145 /**
1146 * bnx2fc_process_ofld_cmpl - process FCoE session offload completion
1147 *
1148 * @hba: adapter structure pointer
1149 * @ofld_kcqe: connection offload kcqe pointer
1150 *
1151 * handle session offload completion, enable the session if offload is
1152 * successful.
1153 */
1154 static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
1155 struct fcoe_kcqe *ofld_kcqe)
1156 {
1157 struct bnx2fc_rport *tgt;
1158 struct bnx2fc_interface *interface;
1159 u32 conn_id;
1160 u32 context_id;
1161
1162 conn_id = ofld_kcqe->fcoe_conn_id;
1163 context_id = ofld_kcqe->fcoe_conn_context_id;
1164 tgt = hba->tgt_ofld_list[conn_id];
1165 if (!tgt) {
1166 printk(KERN_ALERT PFX "ERROR:ofld_cmpl: No pending ofld req\n");
1167 return;
1168 }
1169 BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n",
1170 ofld_kcqe->fcoe_conn_context_id);
1171 interface = tgt->port->priv;
1172 if (hba != interface->hba) {
1173 printk(KERN_ERR PFX "ERROR:ofld_cmpl: HBA mis-match\n");
1174 goto ofld_cmpl_err;
1175 }
1176 /*
1177 * cnic has allocated a context_id for this session; use this
1178 * while enabling the session.
1179 */
1180 tgt->context_id = context_id;
1181 if (ofld_kcqe->completion_status) {
1182 if (ofld_kcqe->completion_status ==
1183 FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) {
1184 printk(KERN_ERR PFX "unable to allocate FCoE context "
1185 "resources\n");
1186 set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags);
1187 }
1188 } else {
1189 /* FW offload request successfully completed */
1190 set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
1191 }
1192 ofld_cmpl_err:
1193 set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
1194 wake_up_interruptible(&tgt->ofld_wait);
1195 }
1196
1197 /**
1198 * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion
1199 *
1200 * @hba: adapter structure pointer
1201 * @ofld_kcqe: connection offload kcqe pointer
1202 *
1203 * handle session enable completion, mark the rport as ready
1204 */
1205
1206 static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
1207 struct fcoe_kcqe *ofld_kcqe)
1208 {
1209 struct bnx2fc_rport *tgt;
1210 struct bnx2fc_interface *interface;
1211 u32 conn_id;
1212 u32 context_id;
1213
1214 context_id = ofld_kcqe->fcoe_conn_context_id;
1215 conn_id = ofld_kcqe->fcoe_conn_id;
1216 tgt = hba->tgt_ofld_list[conn_id];
1217 if (!tgt) {
1218 printk(KERN_ERR PFX "ERROR:enbl_cmpl: No pending ofld req\n");
1219 return;
1220 }
1221
1222 BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n",
1223 ofld_kcqe->fcoe_conn_context_id);
1224
1225 /*
1226 * context_id should be the same for this target during offload
1227 * and enable
1228 */
1229 if (tgt->context_id != context_id) {
1230 printk(KERN_ERR PFX "context id mis-match\n");
1231 return;
1232 }
1233 interface = tgt->port->priv;
1234 if (hba != interface->hba) {
1235 printk(KERN_ERR PFX "bnx2fc-enbl_cmpl: HBA mis-match\n");
1236 goto enbl_cmpl_err;
1237 }
1238 if (!ofld_kcqe->completion_status)
1239 /* enable successful - rport ready for issuing IOs */
1240 set_bit(BNX2FC_FLAG_ENABLED, &tgt->flags);
1241
1242 enbl_cmpl_err:
1243 set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
1244 wake_up_interruptible(&tgt->ofld_wait);
1245 }
1246
1247 static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba,
1248 struct fcoe_kcqe *disable_kcqe)
1249 {
1250
1251 struct bnx2fc_rport *tgt;
1252 u32 conn_id;
1253
1254 conn_id = disable_kcqe->fcoe_conn_id;
1255 tgt = hba->tgt_ofld_list[conn_id];
1256 if (!tgt) {
1257 printk(KERN_ERR PFX "ERROR: disable_cmpl: No disable req\n");
1258 return;
1259 }
1260
1261 BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id);
1262
1263 if (disable_kcqe->completion_status) {
1264 printk(KERN_ERR PFX "Disable failed with cmpl status %d\n",
1265 disable_kcqe->completion_status);
1266 set_bit(BNX2FC_FLAG_DISABLE_FAILED, &tgt->flags);
1267 set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
1268 wake_up_interruptible(&tgt->upld_wait);
1269 } else {
1270 /* disable successful */
1271 BNX2FC_TGT_DBG(tgt, "disable successful\n");
1272 clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
1273 clear_bit(BNX2FC_FLAG_ENABLED, &tgt->flags);
1274 set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
1275 set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
1276 wake_up_interruptible(&tgt->upld_wait);
1277 }
1278 }
1279
1280 static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
1281 struct fcoe_kcqe *destroy_kcqe)
1282 {
1283 struct bnx2fc_rport *tgt;
1284 u32 conn_id;
1285
1286 conn_id = destroy_kcqe->fcoe_conn_id;
1287 tgt = hba->tgt_ofld_list[conn_id];
1288 if (!tgt) {
1289 printk(KERN_ERR PFX "destroy_cmpl: No destroy req\n");
1290 return;
1291 }
1292
1293 BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id);
1294
1295 if (destroy_kcqe->completion_status) {
1296 printk(KERN_ERR PFX "Destroy conn failed, cmpl status %d\n",
1297 destroy_kcqe->completion_status);
1298 return;
1299 } else {
1300 /* destroy successful */
1301 BNX2FC_TGT_DBG(tgt, "upload successful\n");
1302 clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
1303 set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags);
1304 set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
1305 wake_up_interruptible(&tgt->upld_wait);
1306 }
1307 }
1308
1309 static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code)
1310 {
1311 switch (err_code) {
1312 case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE:
1313 printk(KERN_ERR PFX "init_failure due to invalid opcode\n");
1314 break;
1315
1316 case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE:
1317 printk(KERN_ERR PFX "init failed due to ctx alloc failure\n");
1318 break;
1319
1320 case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR:
1321 printk(KERN_ERR PFX "init_failure due to NIC error\n");
1322 break;
1323 case FCOE_KCQE_COMPLETION_STATUS_ERROR:
1324 printk(KERN_ERR PFX "init failure due to compl status err\n");
1325 break;
1326 case FCOE_KCQE_COMPLETION_STATUS_WRONG_HSI_VERSION:
1327 printk(KERN_ERR PFX "init failure due to HSI mismatch\n");
1328 break;
1329 default:
1330 printk(KERN_ERR PFX "Unknown Error code %d\n", err_code);
1331 }
1332 }
1333
1334 /**
1335 * bnx2fc_indicae_kcqe - process KCQE
1336 *
1337 * @context: adapter structure pointer
1338 * @kcq: kcqe pointer
1339 * @num_cqe: Number of completion queue elements
1340 *
1341 * Generic KCQ event handler
1342 */
1343 void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[],
1344 u32 num_cqe)
1345 {
1346 struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context;
1347 int i = 0;
1348 struct fcoe_kcqe *kcqe = NULL;
1349
1350 while (i < num_cqe) {
1351 kcqe = (struct fcoe_kcqe *) kcq[i++];
1352
1353 switch (kcqe->op_code) {
1354 case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION:
1355 bnx2fc_fastpath_notification(hba, kcqe);
1356 break;
1357
1358 case FCOE_KCQE_OPCODE_OFFLOAD_CONN:
1359 bnx2fc_process_ofld_cmpl(hba, kcqe);
1360 break;
1361
1362 case FCOE_KCQE_OPCODE_ENABLE_CONN:
1363 bnx2fc_process_enable_conn_cmpl(hba, kcqe);
1364 break;
1365
1366 case FCOE_KCQE_OPCODE_INIT_FUNC:
1367 if (kcqe->completion_status !=
1368 FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
1369 bnx2fc_init_failure(hba,
1370 kcqe->completion_status);
1371 } else {
1372 set_bit(ADAPTER_STATE_UP, &hba->adapter_state);
1373 bnx2fc_get_link_state(hba);
1374 printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n",
1375 (u8)hba->pcidev->bus->number);
1376 }
1377 break;
1378
1379 case FCOE_KCQE_OPCODE_DESTROY_FUNC:
1380 if (kcqe->completion_status !=
1381 FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
1382
1383 printk(KERN_ERR PFX "DESTROY failed\n");
1384 } else {
1385 printk(KERN_ERR PFX "DESTROY success\n");
1386 }
1387 set_bit(BNX2FC_FLAG_DESTROY_CMPL, &hba->flags);
1388 wake_up_interruptible(&hba->destroy_wait);
1389 break;
1390
1391 case FCOE_KCQE_OPCODE_DISABLE_CONN:
1392 bnx2fc_process_conn_disable_cmpl(hba, kcqe);
1393 break;
1394
1395 case FCOE_KCQE_OPCODE_DESTROY_CONN:
1396 bnx2fc_process_conn_destroy_cmpl(hba, kcqe);
1397 break;
1398
1399 case FCOE_KCQE_OPCODE_STAT_FUNC:
1400 if (kcqe->completion_status !=
1401 FCOE_KCQE_COMPLETION_STATUS_SUCCESS)
1402 printk(KERN_ERR PFX "STAT failed\n");
1403 complete(&hba->stat_req_done);
1404 break;
1405
1406 case FCOE_KCQE_OPCODE_FCOE_ERROR:
1407 /* fall thru */
1408 default:
1409 printk(KERN_ERR PFX "unknown opcode 0x%x\n",
1410 kcqe->op_code);
1411 }
1412 }
1413 }
1414
1415 void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid)
1416 {
1417 struct fcoe_sqe *sqe;
1418
1419 sqe = &tgt->sq[tgt->sq_prod_idx];
1420
1421 /* Fill SQ WQE */
1422 sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT;
1423 sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT;
1424
1425 /* Advance SQ Prod Idx */
1426 if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) {
1427 tgt->sq_prod_idx = 0;
1428 tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit;
1429 }
1430 }
1431
1432 void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt)
1433 {
1434 struct b577xx_doorbell_set_prod *sq_db = &tgt->sq_db;
1435 u32 msg;
1436
1437 wmb();
1438 sq_db->prod = tgt->sq_prod_idx |
1439 (tgt->sq_curr_toggle_bit << 15);
1440 msg = *((u32 *)sq_db);
1441 writel(cpu_to_le32(msg), tgt->ctx_base);
1442
1443 }
1444
1445 int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt)
1446 {
1447 u32 context_id = tgt->context_id;
1448 struct fcoe_port *port = tgt->port;
1449 u32 reg_off;
1450 resource_size_t reg_base;
1451 struct bnx2fc_interface *interface = port->priv;
1452 struct bnx2fc_hba *hba = interface->hba;
1453
1454 reg_base = pci_resource_start(hba->pcidev,
1455 BNX2X_DOORBELL_PCI_BAR);
1456 reg_off = (1 << BNX2X_DB_SHIFT) * (context_id & 0x1FFFF);
1457 tgt->ctx_base = ioremap(reg_base + reg_off, 4);
1458 if (!tgt->ctx_base)
1459 return -ENOMEM;
1460 return 0;
1461 }
1462
1463 char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items)
1464 {
1465 char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ);
1466
1467 if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX)
1468 return NULL;
1469
1470 tgt->rq_cons_idx += num_items;
1471
1472 if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX)
1473 tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX;
1474
1475 return buf;
1476 }
1477
1478 void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items)
1479 {
1480 /* return the rq buffer */
1481 u32 next_prod_idx = tgt->rq_prod_idx + num_items;
1482 if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) {
1483 /* Wrap around RQ */
1484 next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX;
1485 }
1486 tgt->rq_prod_idx = next_prod_idx;
1487 tgt->conn_db->rq_prod = tgt->rq_prod_idx;
1488 }
1489
1490 void bnx2fc_init_seq_cleanup_task(struct bnx2fc_cmd *seq_clnp_req,
1491 struct fcoe_task_ctx_entry *task,
1492 struct bnx2fc_cmd *orig_io_req,
1493 u32 offset)
1494 {
1495 struct scsi_cmnd *sc_cmd = orig_io_req->sc_cmd;
1496 struct bnx2fc_rport *tgt = seq_clnp_req->tgt;
1497 struct fcoe_bd_ctx *bd = orig_io_req->bd_tbl->bd_tbl;
1498 struct fcoe_ext_mul_sges_ctx *sgl;
1499 u8 task_type = FCOE_TASK_TYPE_SEQUENCE_CLEANUP;
1500 u8 orig_task_type;
1501 u16 orig_xid = orig_io_req->xid;
1502 u32 context_id = tgt->context_id;
1503 u64 phys_addr = (u64)orig_io_req->bd_tbl->bd_tbl_dma;
1504 u32 orig_offset = offset;
1505 int bd_count;
1506 int i;
1507
1508 memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
1509
1510 if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
1511 orig_task_type = FCOE_TASK_TYPE_WRITE;
1512 else
1513 orig_task_type = FCOE_TASK_TYPE_READ;
1514
1515 /* Tx flags */
1516 task->txwr_rxrd.const_ctx.tx_flags =
1517 FCOE_TASK_TX_STATE_SEQUENCE_CLEANUP <<
1518 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
1519 /* init flags */
1520 task->txwr_rxrd.const_ctx.init_flags = task_type <<
1521 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
1522 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
1523 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
1524 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1525 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1526 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1527 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1528
1529 task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
1530
1531 task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_seq_cnt = 0;
1532 task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_data_offset = offset;
1533
1534 bd_count = orig_io_req->bd_tbl->bd_valid;
1535
1536 /* obtain the appropriate bd entry from relative offset */
1537 for (i = 0; i < bd_count; i++) {
1538 if (offset < bd[i].buf_len)
1539 break;
1540 offset -= bd[i].buf_len;
1541 }
1542 phys_addr += (i * sizeof(struct fcoe_bd_ctx));
1543
1544 if (orig_task_type == FCOE_TASK_TYPE_WRITE) {
1545 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
1546 (u32)phys_addr;
1547 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
1548 (u32)((u64)phys_addr >> 32);
1549 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
1550 bd_count;
1551 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_off =
1552 offset; /* adjusted offset */
1553 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_idx = i;
1554 } else {
1555
1556 /* Multiple SGEs were used for this IO */
1557 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
1558 sgl->mul_sgl.cur_sge_addr.lo = (u32)phys_addr;
1559 sgl->mul_sgl.cur_sge_addr.hi = (u32)((u64)phys_addr >> 32);
1560 sgl->mul_sgl.sgl_size = bd_count;
1561 sgl->mul_sgl.cur_sge_off = offset; /*adjusted offset */
1562 sgl->mul_sgl.cur_sge_idx = i;
1563
1564 memset(&task->rxwr_only.rx_seq_ctx, 0,
1565 sizeof(struct fcoe_rx_seq_ctx));
1566 task->rxwr_only.rx_seq_ctx.low_exp_ro = orig_offset;
1567 task->rxwr_only.rx_seq_ctx.high_exp_ro = orig_offset;
1568 }
1569 }
1570 void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req,
1571 struct fcoe_task_ctx_entry *task,
1572 u16 orig_xid)
1573 {
1574 u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP;
1575 struct bnx2fc_rport *tgt = io_req->tgt;
1576 u32 context_id = tgt->context_id;
1577
1578 memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
1579
1580 /* Tx Write Rx Read */
1581 /* init flags */
1582 task->txwr_rxrd.const_ctx.init_flags = task_type <<
1583 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
1584 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
1585 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
1586 if (tgt->dev_type == TYPE_TAPE)
1587 task->txwr_rxrd.const_ctx.init_flags |=
1588 FCOE_TASK_DEV_TYPE_TAPE <<
1589 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1590 else
1591 task->txwr_rxrd.const_ctx.init_flags |=
1592 FCOE_TASK_DEV_TYPE_DISK <<
1593 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1594 task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
1595
1596 /* Tx flags */
1597 task->txwr_rxrd.const_ctx.tx_flags =
1598 FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP <<
1599 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
1600
1601 /* Rx Read Tx Write */
1602 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1603 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1604 task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
1605 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
1606 }
1607
1608 void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
1609 struct fcoe_task_ctx_entry *task)
1610 {
1611 struct bnx2fc_mp_req *mp_req = &(io_req->mp_req);
1612 struct bnx2fc_rport *tgt = io_req->tgt;
1613 struct fc_frame_header *fc_hdr;
1614 struct fcoe_ext_mul_sges_ctx *sgl;
1615 u8 task_type = 0;
1616 u64 *hdr;
1617 u64 temp_hdr[3];
1618 u32 context_id;
1619
1620
1621 /* Obtain task_type */
1622 if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) ||
1623 (io_req->cmd_type == BNX2FC_ELS)) {
1624 task_type = FCOE_TASK_TYPE_MIDPATH;
1625 } else if (io_req->cmd_type == BNX2FC_ABTS) {
1626 task_type = FCOE_TASK_TYPE_ABTS;
1627 }
1628
1629 memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
1630
1631 /* Setup the task from io_req for easy reference */
1632 io_req->task = task;
1633
1634 BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n",
1635 io_req->cmd_type, task_type);
1636
1637 /* Tx only */
1638 if ((task_type == FCOE_TASK_TYPE_MIDPATH) ||
1639 (task_type == FCOE_TASK_TYPE_UNSOLICITED)) {
1640 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
1641 (u32)mp_req->mp_req_bd_dma;
1642 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
1643 (u32)((u64)mp_req->mp_req_bd_dma >> 32);
1644 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1;
1645 }
1646
1647 /* Tx Write Rx Read */
1648 /* init flags */
1649 task->txwr_rxrd.const_ctx.init_flags = task_type <<
1650 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
1651 if (tgt->dev_type == TYPE_TAPE)
1652 task->txwr_rxrd.const_ctx.init_flags |=
1653 FCOE_TASK_DEV_TYPE_TAPE <<
1654 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1655 else
1656 task->txwr_rxrd.const_ctx.init_flags |=
1657 FCOE_TASK_DEV_TYPE_DISK <<
1658 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1659 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
1660 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
1661
1662 /* tx flags */
1663 task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_INIT <<
1664 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
1665
1666 /* Rx Write Tx Read */
1667 task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
1668
1669 /* rx flags */
1670 task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
1671 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
1672
1673 context_id = tgt->context_id;
1674 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1675 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1676
1677 fc_hdr = &(mp_req->req_fc_hdr);
1678 if (task_type == FCOE_TASK_TYPE_MIDPATH) {
1679 fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid);
1680 fc_hdr->fh_rx_id = htons(0xffff);
1681 task->rxwr_txrd.var_ctx.rx_id = 0xffff;
1682 } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) {
1683 fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid);
1684 }
1685
1686 /* Fill FC Header into middle path buffer */
1687 hdr = (u64 *) &task->txwr_rxrd.union_ctx.tx_frame.fc_hdr;
1688 memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr));
1689 hdr[0] = cpu_to_be64(temp_hdr[0]);
1690 hdr[1] = cpu_to_be64(temp_hdr[1]);
1691 hdr[2] = cpu_to_be64(temp_hdr[2]);
1692
1693 /* Rx Only */
1694 if (task_type == FCOE_TASK_TYPE_MIDPATH) {
1695 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
1696
1697 sgl->mul_sgl.cur_sge_addr.lo = (u32)mp_req->mp_resp_bd_dma;
1698 sgl->mul_sgl.cur_sge_addr.hi =
1699 (u32)((u64)mp_req->mp_resp_bd_dma >> 32);
1700 sgl->mul_sgl.sgl_size = 1;
1701 }
1702 }
1703
1704 void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
1705 struct fcoe_task_ctx_entry *task)
1706 {
1707 u8 task_type;
1708 struct scsi_cmnd *sc_cmd = io_req->sc_cmd;
1709 struct io_bdt *bd_tbl = io_req->bd_tbl;
1710 struct bnx2fc_rport *tgt = io_req->tgt;
1711 struct fcoe_cached_sge_ctx *cached_sge;
1712 struct fcoe_ext_mul_sges_ctx *sgl;
1713 int dev_type = tgt->dev_type;
1714 u64 *fcp_cmnd;
1715 u64 tmp_fcp_cmnd[4];
1716 u32 context_id;
1717 int cnt, i;
1718 int bd_count;
1719
1720 memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
1721
1722 /* Setup the task from io_req for easy reference */
1723 io_req->task = task;
1724
1725 if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
1726 task_type = FCOE_TASK_TYPE_WRITE;
1727 else
1728 task_type = FCOE_TASK_TYPE_READ;
1729
1730 /* Tx only */
1731 bd_count = bd_tbl->bd_valid;
1732 cached_sge = &task->rxwr_only.union_ctx.read_info.sgl_ctx.cached_sge;
1733 if (task_type == FCOE_TASK_TYPE_WRITE) {
1734 if ((dev_type == TYPE_DISK) && (bd_count == 1)) {
1735 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
1736
1737 task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.lo =
1738 cached_sge->cur_buf_addr.lo =
1739 fcoe_bd_tbl->buf_addr_lo;
1740 task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.hi =
1741 cached_sge->cur_buf_addr.hi =
1742 fcoe_bd_tbl->buf_addr_hi;
1743 task->txwr_only.sgl_ctx.cached_sge.cur_buf_rem =
1744 cached_sge->cur_buf_rem =
1745 fcoe_bd_tbl->buf_len;
1746
1747 task->txwr_rxrd.const_ctx.init_flags |= 1 <<
1748 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
1749 } else {
1750 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
1751 (u32)bd_tbl->bd_tbl_dma;
1752 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
1753 (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
1754 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
1755 bd_tbl->bd_valid;
1756 }
1757 }
1758
1759 /*Tx Write Rx Read */
1760 /* Init state to NORMAL */
1761 task->txwr_rxrd.const_ctx.init_flags |= task_type <<
1762 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
1763 if (dev_type == TYPE_TAPE) {
1764 task->txwr_rxrd.const_ctx.init_flags |=
1765 FCOE_TASK_DEV_TYPE_TAPE <<
1766 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1767 io_req->rec_retry = 0;
1768 io_req->rec_retry = 0;
1769 } else
1770 task->txwr_rxrd.const_ctx.init_flags |=
1771 FCOE_TASK_DEV_TYPE_DISK <<
1772 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1773 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
1774 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
1775 /* tx flags */
1776 task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_NORMAL <<
1777 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
1778
1779 /* Set initial seq counter */
1780 task->txwr_rxrd.union_ctx.tx_seq.ctx.seq_cnt = 1;
1781
1782 /* Fill FCP_CMND IU */
1783 fcp_cmnd = (u64 *)
1784 task->txwr_rxrd.union_ctx.fcp_cmd.opaque;
1785 bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd);
1786
1787 /* swap fcp_cmnd */
1788 cnt = sizeof(struct fcp_cmnd) / sizeof(u64);
1789
1790 for (i = 0; i < cnt; i++) {
1791 *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]);
1792 fcp_cmnd++;
1793 }
1794
1795 /* Rx Write Tx Read */
1796 task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
1797
1798 context_id = tgt->context_id;
1799 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1800 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1801
1802 /* rx flags */
1803 /* Set state to "waiting for the first packet" */
1804 task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
1805 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
1806
1807 task->rxwr_txrd.var_ctx.rx_id = 0xffff;
1808
1809 /* Rx Only */
1810 if (task_type != FCOE_TASK_TYPE_READ)
1811 return;
1812
1813 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
1814 bd_count = bd_tbl->bd_valid;
1815
1816 if (dev_type == TYPE_DISK) {
1817 if (bd_count == 1) {
1818
1819 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
1820
1821 cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
1822 cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
1823 cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
1824 task->txwr_rxrd.const_ctx.init_flags |= 1 <<
1825 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
1826 } else if (bd_count == 2) {
1827 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
1828
1829 cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
1830 cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
1831 cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
1832
1833 fcoe_bd_tbl++;
1834 cached_sge->second_buf_addr.lo =
1835 fcoe_bd_tbl->buf_addr_lo;
1836 cached_sge->second_buf_addr.hi =
1837 fcoe_bd_tbl->buf_addr_hi;
1838 cached_sge->second_buf_rem = fcoe_bd_tbl->buf_len;
1839 task->txwr_rxrd.const_ctx.init_flags |= 1 <<
1840 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
1841 } else {
1842
1843 sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
1844 sgl->mul_sgl.cur_sge_addr.hi =
1845 (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
1846 sgl->mul_sgl.sgl_size = bd_count;
1847 }
1848 } else {
1849 sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
1850 sgl->mul_sgl.cur_sge_addr.hi =
1851 (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
1852 sgl->mul_sgl.sgl_size = bd_count;
1853 }
1854 }
1855
1856 /**
1857 * bnx2fc_setup_task_ctx - allocate and map task context
1858 *
1859 * @hba: pointer to adapter structure
1860 *
1861 * allocate memory for task context, and associated BD table to be used
1862 * by firmware
1863 *
1864 */
1865 int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba)
1866 {
1867 int rc = 0;
1868 struct regpair *task_ctx_bdt;
1869 dma_addr_t addr;
1870 int task_ctx_arr_sz;
1871 int i;
1872
1873 /*
1874 * Allocate task context bd table. A page size of bd table
1875 * can map 256 buffers. Each buffer contains 32 task context
1876 * entries. Hence the limit with one page is 8192 task context
1877 * entries.
1878 */
1879 hba->task_ctx_bd_tbl = dma_alloc_coherent(&hba->pcidev->dev,
1880 PAGE_SIZE,
1881 &hba->task_ctx_bd_dma,
1882 GFP_KERNEL);
1883 if (!hba->task_ctx_bd_tbl) {
1884 printk(KERN_ERR PFX "unable to allocate task context BDT\n");
1885 rc = -1;
1886 goto out;
1887 }
1888
1889 /*
1890 * Allocate task_ctx which is an array of pointers pointing to
1891 * a page containing 32 task contexts
1892 */
1893 task_ctx_arr_sz = (hba->max_tasks / BNX2FC_TASKS_PER_PAGE);
1894 hba->task_ctx = kzalloc((task_ctx_arr_sz * sizeof(void *)),
1895 GFP_KERNEL);
1896 if (!hba->task_ctx) {
1897 printk(KERN_ERR PFX "unable to allocate task context array\n");
1898 rc = -1;
1899 goto out1;
1900 }
1901
1902 /*
1903 * Allocate task_ctx_dma which is an array of dma addresses
1904 */
1905 hba->task_ctx_dma = kmalloc((task_ctx_arr_sz *
1906 sizeof(dma_addr_t)), GFP_KERNEL);
1907 if (!hba->task_ctx_dma) {
1908 printk(KERN_ERR PFX "unable to alloc context mapping array\n");
1909 rc = -1;
1910 goto out2;
1911 }
1912
1913 task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl;
1914 for (i = 0; i < task_ctx_arr_sz; i++) {
1915
1916 hba->task_ctx[i] = dma_alloc_coherent(&hba->pcidev->dev,
1917 PAGE_SIZE,
1918 &hba->task_ctx_dma[i],
1919 GFP_KERNEL);
1920 if (!hba->task_ctx[i]) {
1921 printk(KERN_ERR PFX "unable to alloc task context\n");
1922 rc = -1;
1923 goto out3;
1924 }
1925 addr = (u64)hba->task_ctx_dma[i];
1926 task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32);
1927 task_ctx_bdt->lo = cpu_to_le32((u32)addr);
1928 task_ctx_bdt++;
1929 }
1930 return 0;
1931
1932 out3:
1933 for (i = 0; i < task_ctx_arr_sz; i++) {
1934 if (hba->task_ctx[i]) {
1935
1936 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1937 hba->task_ctx[i], hba->task_ctx_dma[i]);
1938 hba->task_ctx[i] = NULL;
1939 }
1940 }
1941
1942 kfree(hba->task_ctx_dma);
1943 hba->task_ctx_dma = NULL;
1944 out2:
1945 kfree(hba->task_ctx);
1946 hba->task_ctx = NULL;
1947 out1:
1948 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1949 hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma);
1950 hba->task_ctx_bd_tbl = NULL;
1951 out:
1952 return rc;
1953 }
1954
1955 void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba)
1956 {
1957 int task_ctx_arr_sz;
1958 int i;
1959
1960 if (hba->task_ctx_bd_tbl) {
1961 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1962 hba->task_ctx_bd_tbl,
1963 hba->task_ctx_bd_dma);
1964 hba->task_ctx_bd_tbl = NULL;
1965 }
1966
1967 task_ctx_arr_sz = (hba->max_tasks / BNX2FC_TASKS_PER_PAGE);
1968 if (hba->task_ctx) {
1969 for (i = 0; i < task_ctx_arr_sz; i++) {
1970 if (hba->task_ctx[i]) {
1971 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1972 hba->task_ctx[i],
1973 hba->task_ctx_dma[i]);
1974 hba->task_ctx[i] = NULL;
1975 }
1976 }
1977 kfree(hba->task_ctx);
1978 hba->task_ctx = NULL;
1979 }
1980
1981 kfree(hba->task_ctx_dma);
1982 hba->task_ctx_dma = NULL;
1983 }
1984
1985 static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba)
1986 {
1987 int i;
1988 int segment_count;
1989 u32 *pbl;
1990
1991 if (hba->hash_tbl_segments) {
1992
1993 pbl = hba->hash_tbl_pbl;
1994 if (pbl) {
1995 segment_count = hba->hash_tbl_segment_count;
1996 for (i = 0; i < segment_count; ++i) {
1997 dma_addr_t dma_address;
1998
1999 dma_address = le32_to_cpu(*pbl);
2000 ++pbl;
2001 dma_address += ((u64)le32_to_cpu(*pbl)) << 32;
2002 ++pbl;
2003 dma_free_coherent(&hba->pcidev->dev,
2004 BNX2FC_HASH_TBL_CHUNK_SIZE,
2005 hba->hash_tbl_segments[i],
2006 dma_address);
2007 }
2008 }
2009
2010 kfree(hba->hash_tbl_segments);
2011 hba->hash_tbl_segments = NULL;
2012 }
2013
2014 if (hba->hash_tbl_pbl) {
2015 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
2016 hba->hash_tbl_pbl,
2017 hba->hash_tbl_pbl_dma);
2018 hba->hash_tbl_pbl = NULL;
2019 }
2020 }
2021
2022 static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba)
2023 {
2024 int i;
2025 int hash_table_size;
2026 int segment_count;
2027 int segment_array_size;
2028 int dma_segment_array_size;
2029 dma_addr_t *dma_segment_array;
2030 u32 *pbl;
2031
2032 hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
2033 sizeof(struct fcoe_hash_table_entry);
2034
2035 segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1;
2036 segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE;
2037 hba->hash_tbl_segment_count = segment_count;
2038
2039 segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments);
2040 hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL);
2041 if (!hba->hash_tbl_segments) {
2042 printk(KERN_ERR PFX "hash table pointers alloc failed\n");
2043 return -ENOMEM;
2044 }
2045 dma_segment_array_size = segment_count * sizeof(*dma_segment_array);
2046 dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL);
2047 if (!dma_segment_array) {
2048 printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n");
2049 goto cleanup_ht;
2050 }
2051
2052 for (i = 0; i < segment_count; ++i) {
2053 hba->hash_tbl_segments[i] = dma_alloc_coherent(&hba->pcidev->dev,
2054 BNX2FC_HASH_TBL_CHUNK_SIZE,
2055 &dma_segment_array[i],
2056 GFP_KERNEL);
2057 if (!hba->hash_tbl_segments[i]) {
2058 printk(KERN_ERR PFX "hash segment alloc failed\n");
2059 goto cleanup_dma;
2060 }
2061 }
2062
2063 hba->hash_tbl_pbl = dma_alloc_coherent(&hba->pcidev->dev, PAGE_SIZE,
2064 &hba->hash_tbl_pbl_dma,
2065 GFP_KERNEL);
2066 if (!hba->hash_tbl_pbl) {
2067 printk(KERN_ERR PFX "hash table pbl alloc failed\n");
2068 goto cleanup_dma;
2069 }
2070
2071 pbl = hba->hash_tbl_pbl;
2072 for (i = 0; i < segment_count; ++i) {
2073 u64 paddr = dma_segment_array[i];
2074 *pbl = cpu_to_le32((u32) paddr);
2075 ++pbl;
2076 *pbl = cpu_to_le32((u32) (paddr >> 32));
2077 ++pbl;
2078 }
2079 pbl = hba->hash_tbl_pbl;
2080 i = 0;
2081 while (*pbl && *(pbl + 1)) {
2082 ++pbl;
2083 ++pbl;
2084 ++i;
2085 }
2086 kfree(dma_segment_array);
2087 return 0;
2088
2089 cleanup_dma:
2090 for (i = 0; i < segment_count; ++i) {
2091 if (hba->hash_tbl_segments[i])
2092 dma_free_coherent(&hba->pcidev->dev,
2093 BNX2FC_HASH_TBL_CHUNK_SIZE,
2094 hba->hash_tbl_segments[i],
2095 dma_segment_array[i]);
2096 }
2097
2098 kfree(dma_segment_array);
2099
2100 cleanup_ht:
2101 kfree(hba->hash_tbl_segments);
2102 hba->hash_tbl_segments = NULL;
2103 return -ENOMEM;
2104 }
2105
2106 /**
2107 * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer
2108 *
2109 * @hba: Pointer to adapter structure
2110 *
2111 */
2112 int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba)
2113 {
2114 u64 addr;
2115 u32 mem_size;
2116 int i;
2117
2118 if (bnx2fc_allocate_hash_table(hba))
2119 return -ENOMEM;
2120
2121 mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
2122 hba->t2_hash_tbl_ptr = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
2123 &hba->t2_hash_tbl_ptr_dma,
2124 GFP_KERNEL);
2125 if (!hba->t2_hash_tbl_ptr) {
2126 printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n");
2127 bnx2fc_free_fw_resc(hba);
2128 return -ENOMEM;
2129 }
2130
2131 mem_size = BNX2FC_NUM_MAX_SESS *
2132 sizeof(struct fcoe_t2_hash_table_entry);
2133 hba->t2_hash_tbl = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
2134 &hba->t2_hash_tbl_dma,
2135 GFP_KERNEL);
2136 if (!hba->t2_hash_tbl) {
2137 printk(KERN_ERR PFX "unable to allocate t2 hash table\n");
2138 bnx2fc_free_fw_resc(hba);
2139 return -ENOMEM;
2140 }
2141 for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) {
2142 addr = (unsigned long) hba->t2_hash_tbl_dma +
2143 ((i+1) * sizeof(struct fcoe_t2_hash_table_entry));
2144 hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff;
2145 hba->t2_hash_tbl[i].next.hi = addr >> 32;
2146 }
2147
2148 hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev,
2149 PAGE_SIZE, &hba->dummy_buf_dma,
2150 GFP_KERNEL);
2151 if (!hba->dummy_buffer) {
2152 printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n");
2153 bnx2fc_free_fw_resc(hba);
2154 return -ENOMEM;
2155 }
2156
2157 hba->stats_buffer = dma_alloc_coherent(&hba->pcidev->dev, PAGE_SIZE,
2158 &hba->stats_buf_dma,
2159 GFP_KERNEL);
2160 if (!hba->stats_buffer) {
2161 printk(KERN_ERR PFX "unable to alloc Stats Buffer\n");
2162 bnx2fc_free_fw_resc(hba);
2163 return -ENOMEM;
2164 }
2165
2166 return 0;
2167 }
2168
2169 void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba)
2170 {
2171 u32 mem_size;
2172
2173 if (hba->stats_buffer) {
2174 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
2175 hba->stats_buffer, hba->stats_buf_dma);
2176 hba->stats_buffer = NULL;
2177 }
2178
2179 if (hba->dummy_buffer) {
2180 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
2181 hba->dummy_buffer, hba->dummy_buf_dma);
2182 hba->dummy_buffer = NULL;
2183 }
2184
2185 if (hba->t2_hash_tbl_ptr) {
2186 mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
2187 dma_free_coherent(&hba->pcidev->dev, mem_size,
2188 hba->t2_hash_tbl_ptr,
2189 hba->t2_hash_tbl_ptr_dma);
2190 hba->t2_hash_tbl_ptr = NULL;
2191 }
2192
2193 if (hba->t2_hash_tbl) {
2194 mem_size = BNX2FC_NUM_MAX_SESS *
2195 sizeof(struct fcoe_t2_hash_table_entry);
2196 dma_free_coherent(&hba->pcidev->dev, mem_size,
2197 hba->t2_hash_tbl, hba->t2_hash_tbl_dma);
2198 hba->t2_hash_tbl = NULL;
2199 }
2200 bnx2fc_free_hash_table(hba);
2201 }
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